On Mon, Dec 03, 2018 at 08:58:56PM +0100, Jernej Skrabec wrote:
> Cedrus driver wants to set VE clock higher than it's possible without
> changing parent rate.
>
> In order to correct that, allow changing parent rate for VE clock.
>
> Signed-off-by: Jernej Skrabec
Applied, thanks!
Maxime
--
M
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.
In order to correct that, allow changing parent rate for VE clock.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Mon, Dec 03, 2018 at 03:45:44PM +0530, Jagan Teki wrote:
> vcc-supply property is need for some Goodix CTP controller like GT5663
> where 3.3V external pull-up regulator connected via controller VCC pin.
>
> So, enable the regulator for those it attached the vcc-supply.
>
> Signed-off-by: Jaga
On 18/12/03 09:55, Maxime Ripard wrote:
> On Sun, Dec 02, 2018 at 11:23:47PM +0300, Mesih Kilinc wrote:
> > diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> > b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> > new file mode 100644
> > index 000..ea335a6
> > --- /dev/null
> > +++ b/drivers/c
Dne ponedeljek, 05. november 2018 ob 10:43:41 CET je Maxime Ripard napisal(a):
> On Sun, Nov 04, 2018 at 07:26:37PM +0100, Jernej Skrabec wrote:
> > This series adds support for Display Engine 3.0 and HDMI 2.0a, which
> > can be found on H6 SoC.
> >
> > Display Engine 3.0 in comparison to 2.0 most
On Mon, Dec 03, 2018 at 11:40:58PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This small series renames the csi0 and ts0 pin function names to csi and
> ts. This makes the names match the datasheet. As there are only one of
> each type of controller, having a numeral suffix doesn't make sense.
Hi everyone,
This small series renames the csi0 and ts0 pin function names to csi and
ts. This makes the names match the datasheet. As there are only one of
each type of controller, having a numeral suffix doesn't make sense.
I'd like to do the rename now while we don't have users nor support for
The A64 only has one CSI (camera sensor interface) controller. The
datasheet also lists the function as CSI_XXX instead of CSI0_XXX.
Rename the function names now before any there are any users.
Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: Chen-Yu Tsai
The A64 only has one TS (transport stream) controller. The datasheet
also lists the function as TS_XXX instead of TS0_XXX.
Rename the function names now before any there are any users.
Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: Chen-Yu Tsai
---
dri
While doing Bluetooth enablement for various boards based on various
Allwinner SoCs, minor differences in the RTC modules were found. These
include a lack of an external clock output (A31), different internal
oscillator frequencies (H3/H5/A64/V3/V3s), different regulator voltage
settings (H5/H6), a
The RTC module on the A23 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The A33's RTC is the same as the A23.
This patch fixes the compatible string
Experiments showed that on at least the H3/H5/A64 the RTC's internal
oscillator also feeds the CPUS mux in the PRCM.
Export this clock through the device tree, instead of having to use
a dummy fixed-clock device node, for the PRCM to consume. This will
properly describe the relationship between th
The R40 has an RTC hardware block, which has additional registers
that are not related to RTC or clock functions, and is otherwise
compatible with the H3's RTC.
Add a device node for it, and fix up any references to the LOSC.
Acked-by: Maxime Ripard
Tested-by: Corentin Labbe
Signed-off-by: Chen
The R40 datasheet specifies a tolerance range for the external
oscillators used. Add them to the device tree as the clock accuracy.
Acked-by: Maxime Ripard
Tested-by: Corentin Labbe
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff -
The clock output section for this binding describes the two outputs in
the descriptions for both the #clock-cells and clock-output-names
properties.
Instead of overlapping information that is hard to read, rewrite the
clock outputs as a list of indices and descriptions. The properies
can reference
The bindings have been updated to expose the RTC's internal oscillator,
for some SoCs that have it directly feeding the PRCM block. The changes
include the index 2 for the clock outputs, as well as the clock output
names.
This patch adds the internal oscillator to the list of clocks exposed
throug
The RTC's main clock, used internally and exported to the rest of the
SoC, is called "LOSC" (low speed oscillator) through the hardware
documentation.
This patch adds a default name for this clock, in case the device tree
does not provide one. This shouldn't happen, but lets play it safe.
Acked-b
The RTC module on the A64 was claimed to be the same as on the A31, when
in fact it is not. It is actually compatible to the H3's RTC. The A64's
RTC has some extra crypto-related registers which the H3's does not, but
the exact function of these is not clear.
This patch fixes the compatible string
There are different variants to the RTC hardware first seen on sun6i
(A31). The differences we care about in this driver are the clock rate
for the internal oscillator, prescalers, and the presence of an external
clock output.
This patch adds support for all the known pre-H6 base compatibles using
The A31 does not have an external clock output directly from the RTC.
Instead, it has four muxable clock outputs: three (A, B, C) are
controlled from the CCU, and the last (D) is controlled from the PRCM.
Deprecate the usage of the external clock output for the A31 compatible.
Acked-by: Maxime Ri
The RTC module on the H3 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The H5's RTC has some extra crypto-related registers compared to
the H3. Their
Hi everyone,
This is v2 of my rtc-sun6i clean-up series.
Changes since v1:
- Collected tags
- Dropped patch "clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC
output"; already merged
- Removed H6 compatible CLK_OF_DECLARE_DRIVER entry that wasn't
overlooked
- Only export IOSC clo
The H3 datasheet specifies a tolerance range for the external
oscillators used. Add them to the device tree as the clock accuracy.
The internal oscillator is left unchanged, as it will be removed later.
Acked-by: Maxime Ripard
Tested-by: Corentin Labbe
Signed-off-by: Chen-Yu Tsai
---
arch/arm/
Amongst the Allwinner SoCs that have seen some kind of coverage by the
linux-sunxi community, whether it be mainline Linux or U-boot support,
or just available datasheets, most newer chips use the RTC design first
seen in the A31 (sun6i).
Overall there have been some minor differences. This patch
I don't know if somebody has to sign this off, but here it goes...
sun8i-r40.dtsi add spi nodes, add spidev to sun8i-r40-bananapi-m2-ultra.dts
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index c39b9169ea64..3cad93230237 1
On Mon, Dec 03, 2018 at 01:25:21PM +0100, Heiko Stuebner wrote:
> > - reg : Physical base address of the device and length of the register
> > area.
> >
> > @@ -44,6 +45,18 @@ Optional properties:
> >for details.
> >
> >
> > +Vendor-specific bindings
> > +
> > +
Am Dienstag, 27. November 2018, 08:42:49 CET schrieb Icenowy Zheng:
> Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the
> Midgard GPU product line.
>
> Add binding for the H6 Mali Midgard GPU.
>
> Signed-off-by: Icenowy Zheng
> ---
> .../devicetree/bindings/gpu/arm,mali-mid
On Mon, Dec 03, 2018 at 12:23:11AM +0300, Mesih Kilinc wrote:
> DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4
> DDMA channels and endpoints are different. Also F1C100s has reset bit
> for DMA in CCU. Add support for it.
>
> Signed-off-by: Mesih Kilinc
> ---
> drivers/dma/K
On Mon, Dec 03, 2018 at 12:23:11AM +0300, Mesih Kilinc wrote:
> DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4
> DDMA channels and endpoints are different. Also F1C100s has reset bit
> for DMA in CCU. Add support for it.
>
> Signed-off-by: Mesih Kilinc
> ---
> drivers/dma/K
Hi,
(you don't really need the RFC tag. RFC tags are usually meant to ask
comments on the general approach, not the implementation).
On Mon, Dec 03, 2018 at 12:23:08AM +0300, Mesih Kilinc wrote:
> Allwinner suniv F1C100s has similar DMA engine to sun4i. Several
> registers has different addresses
On Mon, Dec 3, 2018 at 6:16 PM Jagan Teki wrote:
>
> vcc-supply property is need for some Goodix CTP controller like GT5663
> where 3.3V external pull-up regulator connected via controller VCC pin.
"External pull-up regulator" sounds fishy. Chips have power supply
pins, either combined, or separa
Hi,
On Sat, Dec 01, 2018 at 11:23:40PM +0800, Hao Zhang wrote:
> > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > > index 504d252..6105ac8 100644
> > > --- a/drivers/pwm/Kconfig
> > > +++ b/drivers/pwm/Kconfig
> > > @@ -426,7 +426,7 @@ config PWM_STMPE
> > > expanders.
> > >
On Mon, Dec 3, 2018 at 6:16 PM Jagan Teki wrote:
>
> AXP803 PMIC has two GPIO's which is similar to the one in
> AXP813 PMIC.
>
> Add a compatible string for it with AXP813 fallback compatible string, in
> this case the AXP813 driver can be used.
>
> Signed-off-by: Jagan Teki
First of all, pleas
GPIO0, GPIO1 can be used as LDO like ldo_io0, ldo_io1 in
AXP803.
So, attach the LDO GPIO pins along with pinctrl properties.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/
GT5663 is capacitive touch controller with customized smart wakeup gestures,
the existing goodix driver will work by phandle vcc-supply regulator.
So, document compatible and example node for the same.
Signed-off-by: Jagan Teki
---
.../bindings/input/touchscreen/goodix.txt | 13 ++
vcc-supply property is need for some Goodix CTP controller like GT5663
where 3.3V external pull-up regulator connected via controller VCC pin.
So, enable the regulator for those it attached the vcc-supply.
Signed-off-by: Jagan Teki
---
drivers/input/touchscreen/goodix.c | 39 +++
GT5663 is capacitive touch controller with customized smart wakeup gestures,
the existing goodix driver will work by phandle vcc-supply regulator.
So, add compatible for the same.
Signed-off-by: Jagan Teki
---
drivers/input/touchscreen/goodix.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Add GPIO/pinctrl support for AXP803.
This will reuse the similar compatible to that of AXP813,
since both PMIC GPIO's are same.
Signed-off-by: Jagan Teki
---
drivers/mfd/axp20x.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
Add Goodix GT5663 capacitive touch controller node on
Amarula A64-Relic board.
The CTP connected to board with,
- SDA, SCK from i2c1
- GPIO-LD0 as vcc supply
- PH4 gpio as interrupt pin
- PH8 gpio as reset pin
- X and Y axis are inverted
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64-am
Add GPIO/pinctrl node for AXP803 PMIC.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi
b/arch/arm64/boot/dts/allwinner/axp803.dtsi
index e5eae8bafc42..c6b95980d476 100644
AXP803 PMIC has two GPIO's which is similar to the one in
AXP813 PMIC.
Add a compatible string for it with AXP813 fallback compatible string, in
this case the AXP813 driver can be used.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/gpio/gpio-axp209.txt | 1 +
1 file changed, 1
vcc-supply property is need for some Goodix CTP controller like GT5663
where 3.3V external pull-up regulator connected via controller VCC pin.
So, document the same as optional property.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/input/touchscreen/goodix.txt | 1 +
1 file c
Hello,
On Mon, Nov 26, 2018 at 10:31:58PM +0100, Uwe Kleine-König wrote:
> > +static int sun8i_pwm_config(struct sun8i_pwm_chip *sun8i_pwm, u8 ch,
> > + struct pwm_state *state)
> > +{
> > +[...]
> > + clk_rate = clk_get_rate(clk);
> > + val = state->perio
Hi!
(Please keep all the recipiens in Cc)
On Sun, Dec 02, 2018 at 12:13:21AM +0800, Hao Zhang wrote:
> Maxime Ripard 于2018年11月27日周二 下午6:33写道：
> >
> > On Tue, Nov 27, 2018 at 09:35:23AM +0100, Uwe Kleine-König wrote:
> > > Hello,
> > >
> > > On Tue, Nov 27, 2018 at 08:52:26AM +0100, Maxime Ripard
On Wed, Nov 28, 2018 at 07:18:26PM +0800, Chen-Yu Tsai wrote:
> On Wed, Nov 28, 2018 at 6:33 PM Maxime Ripard
> wrote:
> >
> > On Wed, Nov 28, 2018 at 05:30:01PM +0800, Chen-Yu Tsai wrote:
> > > Experiments showed that on at least the H3/H5/A64 the RTC's internal
> > > oscillator also feeds the C
On Sun, Dec 02, 2018 at 11:23:51PM +0300, Mesih Kilinc wrote:
> Lichee Pi Nano is a F1C100s board by Lichee Pi.
>
> Add initial device tree for it.
>
> Signed-off-by: Mesih Kilinc
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
--
On Sun, Dec 02, 2018 at 11:23:50PM +0300, Mesih Kilinc wrote:
> F1C100s is one product with the suniv die, which has a 32MiB co-packaged
> DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now,
> add a
> initial DTSI for it.
>
> Signed-off-by: Mesih Kilinc
Applied, thanks!
On Sun, Dec 02, 2018 at 11:23:49PM +0300, Mesih Kilinc wrote:
> Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31.
> Add definition for it.
>
> Signed-off-by: Mesih Kilinc
> Reviewed-by: Rob Herring
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engi
On Sun, Dec 02, 2018 at 11:23:48PM +0300, Mesih Kilinc wrote:
> The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10.
> Add compatible string for it.
>
> Signed-off-by: Mesih Kilinc
> Reviewed-by: Rob Herring
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux an
On Sun, Dec 02, 2018 at 11:23:35PM +0300, Mesih Kilinc wrote:
> Allwinner also has some ARMv5 SoCs.
>
> In order to add support for them, check ARM_MULTI_V7 before enabling
> ARMv7 SoC's. Add help text for ARCH_SUNXI menuconfig.
>
> Signed-off-by: Mesih Kilinc
Applied, thanks!
Maxime
--
Maxim
On Sun, Dec 02, 2018 at 11:23:36PM +0300, Mesih Kilinc wrote:
> Add new Allwinner ARMv5 F1C100s SoC's compatible string
>
> Signed-off-by: Mesih Kilinc
> Acked-by: Maxime Ripard
> Reviewed-by: Rob Herring
Applie,d thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
On Sun, Dec 02, 2018 at 11:23:47PM +0300, Mesih Kilinc wrote:
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> new file mode 100644
> index 000..ea335a6
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> @@ -0,0 +1,541 @@
>
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