The VBUS current limit value macros have VBUS typed as VBUC, while
the bitmask macro is named correctly. Fix it.
Fixes: 69fb4dcada77 ("power: Add an axp20x-usb-power driver")
Signed-off-by: Chen-Yu Tsai
---
drivers/power/supply/axp20x_usb_power.c | 16
1 file changed, 8
The Bananapi M3 and Cubietruck Plus both have USB OTG ports wired to the
SoC and PMIC in the same way, with the N_VBUSEN pin on the PMIC
controlling VBUS output, the PMIC's VBUS input for sensing VBUS, and
PH11 on the SoC for sensing the ID pin.
Enable OTG on both boards.
Signed-off-by: Chen-Yu
From: Quentin Schulz
This adds support for AXP813 PMIC. It is almost the same as AXP22X but
has a different current limit.
Signed-off-by: Quentin Schulz
Signed-off-by: Chen-Yu Tsai
---
drivers/power/supply/axp20x_usb_power.c | 66 -
1 file changed, 65 insertions(+), 1
Hi everyone,
This series enables USB OTG on the A83T boards. The AXP813/AXP818 PMICs
used with the A83T have the same behavior as the AXP221 and AXP223,
where if the N_VBUSEN pin is driven high, the VBUS sensing interrupts
stop working. In the past Hans made a polling workaround in the USB PHY
On AXP221 and later AXP PMICs that have the N_VBUSEN pin, when this pin
is high, either due to the PMIC driving it high or as an input, the VBUS
detection related interrupt mechanisms are disabled.
Previously this was worked around in the phy-sun4i-usb driver, which
needed to sense VBUS changes
From: Quentin Schulz
To prepare for a new PMIC, factor out the code responsible of returning
the maximum current to axp20x_get_current_max.
Signed-off-by: Quentin Schulz
Signed-off-by: Chen-Yu Tsai
---
drivers/power/supply/axp20x_usb_power.c | 52 ++---
1 file changed, 30
The AXP PMICs allow the user to disable current limiting on the VBUS
input. While read-out of this setting was already supported by the
driver, it did not allow the user to configure the PMIC to disable
current limiting.
Add support for this.
Signed-off-by: Chen-Yu Tsai
---
From: Quentin Schulz
The AXP813/818 has a VBUS power input. Add a device node for it, now
that we support it.
Signed-off-by: Quentin Schulz
[w...@csie.org: Add commit message]
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/axp81x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git
This adds the "x-powers,axp813-usb-power-supply" to the list of
compatibles for AXP20X VBUS power supply driver.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/power/supply/axp20x_usb_power.txt| 1 +
1 file changed, 1 insertion(+)
diff --git
From: Quentin Schulz
The AXP813 has a VBUS power input. Now that the axp20x_usb_power driver
supports this variant, we can add an mfd cell for it to use it.
Signed-off-by: Quentin Schulz
[w...@csie.org: add commit message]
Signed-off-by: Chen-Yu Tsai
---
drivers/mfd/axp20x.c | 11 +++
On 06/02/2019 12:46, Philipp Tomsich wrote:
> On 11.01.2019, at 01:31, Andre Przywara wrote:
Hi,
>>
>> The normal MMIO accessor macros (readX/writeX) guarantee a strong ordering,
>> even with normal memory accesses [1].
>> For some MMIO operations (framebuffers being a prominent example) this
On Tue, 5 Feb 2019 at 16:42, Chen-Yu Tsai wrote:
>
> Some H5 boards seem to not have proper trace lengths for eMMC to be able
> to use the default setting for the delay chains under HS-DDR mode. These
> include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre
> Computer ALL-H3-CC-H5
On Tue, 5 Feb 2019 at 16:42, Chen-Yu Tsai wrote:
>
> The MMC device tree bindings include properties used to signal various
> signalling speed modes. Until now the sunxi driver was accepting them
> without any further filtering, while the sunxi device trees were not
> actually using them.
>
>
On Tue, Feb 05, 2019 at 11:42:25PM +0800, Chen-Yu Tsai wrote:
> The Libre Computer ALL-H3-CC H5 is one of the few boards that can have
> its eMMC run at HS-DDR speed mode. Mark it as such.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and
On Tue, Feb 05, 2019 at 11:42:24PM +0800, Chen-Yu Tsai wrote:
> The MMC device tree bindings include properties used to signal various
> signalling speed modes. Until now the sunxi driver was accepting them
> without any further filtering, while the sunxi device trees were not
> actually using
On Tue, Feb 05, 2019 at 11:00:40PM +0800, Chen-Yu Tsai wrote:
> On these A64 devices, the DC input jacks are wired to the ACIN pins of
> the PMIC, which is represented by the AC power supply. With the
> exception of the Nanopi A64, all devices include LiPo batteries or have
> connectors for them,
On Wed, Feb 06, 2019 at 11:32:31AM +0800, Chen-Yu Tsai wrote:
> The A80 SoC has configuration registers for I/O bias voltage. Incorrect
> settings would make the affected peripherals inoperable in some cases,
> such as Ethernet RGMII signals biased at 2.5V with the settings still
> at 3.3V.
On Wed, Feb 06, 2019 at 11:32:30AM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> On the Allwinner A80, the PIO pin controller includes configuration
> registers to set the I/O voltage. These must match the actual voltage
> provided externally. A mismatch results in signals not being passed
>
On Wed, Feb 06, 2019 at 10:16:08AM +0100, Maxime Ripard wrote:
> On Tue, Feb 05, 2019 at 09:49:17AM -0800, Vasily Khoruzhick wrote:
> > On Tue, Feb 5, 2019 at 7:42 AM Maxime Ripard
> > wrote:
> > >
> > > On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote:
> > > > On Mon, Feb 4,
On Wed, Feb 6, 2019 at 4:14 PM Linus Walleij wrote:
>
> On Wed, Feb 6, 2019 at 4:32 AM Chen-Yu Tsai wrote:
>
> > The A80 SoC has configuration registers for I/O bias voltage. Incorrect
> > settings would make the affected peripherals inoperable in some cases,
> > such as Ethernet RGMII signals
On Tue, Feb 05, 2019 at 09:49:17AM -0800, Vasily Khoruzhick wrote:
> On Tue, Feb 5, 2019 at 7:42 AM Maxime Ripard
> wrote:
> >
> > On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote:
> > > On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng wrote:
> > > > >> IIRC, from the previous
On Wed, Feb 6, 2019 at 4:32 AM Chen-Yu Tsai wrote:
> The A80 SoC has configuration registers for I/O bias voltage. Incorrect
> settings would make the affected peripherals inoperable in some cases,
> such as Ethernet RGMII signals biased at 2.5V with the settings still
> at 3.3V. However low
22 matches
Mail list logo
