[linux-sunxi] Re: [PATCH 1/3] clk: sunxi: Add a driver for the CCU

On Thu, 30 Jun 2016 23:16:35 +0200 Maxime Ripard wrote: > > - in case a driver requests a reset, this last one should exist. > > But, this reset may point to a void one (reg = null) when the real > > reset has been moved to the prepare/unprepare of the

[linux-sunxi] Re: [PATCH 1/3] clk: sunxi: Add a driver for the CCU

On Thu, 30 Jun 2016 23:16:35 +0200 Maxime Ripard wrote: > > - some fixed_factor clocks may have a gate. > > Which ones? I know only the "osc12M" in the A83T. It is used by the ehci1. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef

[linux-sunxi] Re: [PATCH 1/3] clk: sunxi: Add a driver for the CCU

On Tue, 28 Jun 2016 22:45:02 +0200 Maxime Ripard <maxime.rip...@free-electrons.com> wrote: > On Tue, Jun 28, 2016 at 05:37:35PM +0200, Jean-Francois Moine wrote: > > +/* --- prepare / enable --- */ > > +int ccu_prepare(struct clk_hw *hw) > > +{ > >

[linux-sunxi] [PATCH 3/3] dt: sun8i: Define the clocks of the A83T

Change the clock definition using the CCU. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- Documentation/devicetree/bindings/clock/sunxi.txt | 7 --- arch/arm/boot/dts/sun8i-a83t.dtsi | 16 2 files changed, 16 insertions(+), 7 deletions(-)

[linux-sunxi] [PATCH 1/3] clk: sunxi: Add a driver for the CCU

, - and the resets. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/clk/sunxi/Makefile | 2 + drivers/clk/sunxi/ccu.c| 980 + drivers/clk/sunxi/ccu.h| 153 +++ 3 files changed, 1135 insertions(+) create mode 100644 d

[linux-sunxi] [PATCH 2/3] clk: sunxi: Add the A83T clocks

Define the CCU clocks of the Allwinner's A83T Soc. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/ccu-sun8i-a83t.c | 858 + include/dt-bindings/clock/sun8i-a83t.h | 97 i

[linux-sunxi] [PATCH 0/3] clk: sunxi: Simpler driver for Allwinner's clocks

preventing audio to be enabled) - not working: MMC1 (wifi), MMC2 (eMMC) (sorry, Maxime, but I think that my implementation is easier to extend than yours) Jean-Francois Moine (3): clk: sunxi: Add a driver for the CCU clk: sunxi: Add the A83T clocks dt: sun8i

[linux-sunxi] [PATCH v2 3/3] dt: sun8i: Define the clocks of the A83T

The clocks are defined by the CCU binding. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83

[linux-sunxi] [PATCH v2 0/3] clk: sunxi-ng: Add the A83T clocks

ths uart0 usb0 - not working: mmc1 (wifi/bt) video (machine freeze on reading/writing the DE I/O memory) - not yet tested audio prcm Jean-Francois Moine (3): clk: sunxi-ng: Add N-D-M-P-factor clock support clk: sunxi-ng: Add the A83T clocks

[linux-sunxi] [PATCH v2 1/3] clk: sunxi-ng: Add N-D-M-P-factor clock support

Introduce support for the PLL clocks of the A83T and A80 SoCs which are set from N, D1, D2, M and P factors. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu_common.h | 1 + drivers/clk/sunxi-ng/ccu_ndmp.c

[linux-sunxi] Re: [PATCH] mmc: sunxi: Add support to the Allwinner A83T

On Sun, 5 Jun 2016 20:58:42 +0800 Chen-Yu Tsai wrote: > > +static const struct sunxi_mmc_clk_delay sun8i_a83t_mmc_clk_delays[] = { > > + [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, > > + [SDXC_CLK_25M] = { .output = 180, .sample = 50 }, > > +

[linux-sunxi] [PATCH] mmc: sunxi: Add support to the Allwinner A83T

The A83T has different clock delays. The values have been adapted from the Banana Pi M3 driver. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 3 ++- drivers/mmc/host/sunxi-mmc.c| 12 +++- 2

[linux-sunxi] Re: [PATCH RFC 1/2] clk: sunxi-ng: Add the A83T and A80 PLL clocks

Hi Wens, Thanks for the review. On Fri, 3 Jun 2016 14:53:24 +0800 Chen-Yu Tsai <w...@csie.org> wrote: > On Tue, May 31, 2016 at 3:26 PM, Jean-Francois Moine <moin...@free.fr> wrote: > > The A83T and A80 SoCs have unique settings of their PLL clocks. > > > > S

[linux-sunxi] [PATCH RFC 2/2] clk: sunxi-ng: Add the A83T clocks

Add the clocks and resets found in the A83T CCU. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 755 + include/dt-bindings/clock/sun8i-a83t.h | 150 +++ include/dt-bindings/reset/sun8i-a83t.h | 96 ++

[linux-sunxi] [PATCH RFC 0/2] clk: sunxi-ng: Add the A83T clocks

This patch series is a proposal to add the clocks of the sunxi A83T in the "modern" clock framework proposed by Maxime Ripard. It is currently being tested on a Banana Pi M3. Jean-Francois Moine (2): clk: sunxi: Add the PLL clocks of the A83T and A80 SoCs clk: sunxi-ng: Add the A

[linux-sunxi] [PATCH RFC 1/2] clk: sunxi-ng: Add the A83T and A80 PLL clocks

The A83T and A80 SoCs have unique settings of their PLL clocks. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/clk/sunxi-ng/ccu_ndmp.c | 247 drivers/clk/sunxi-ng/ccu_ndmp.h | 45 2 files changed, 292 insertions(+) creat

[linux-sunxi] Re: [PATCH v2] clk: sunxi: predivider handling for factors clock

On Mon, 30 May 2016 20:45:32 +0200 Maxime Ripard wrote: > I went over all the A83T clocks, and most of them could be > covered. The issue only lies in the PLLs and their additional 1-bit > dividers. > > If we just choos to ignore (one of) them, it should be

[linux-sunxi] [PATCH v6 1/3] dmaengine: sun6i: Set default maxburst size and bus width

Some DMA clients, as audio, don't set the maxburst size and bus width on the memory side when starting DMA transfers. This patch prevents such transfers to be aborted by providing system default values to the lacking ones. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drive

[linux-sunxi] [PATCH v6 2/3] dmaengine: sun6i: Remove useless check

The transfer direction is now checked in set_config. There is no need to check it twice. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/dma/sun6i-dma.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index c

[linux-sunxi] [PATCH v6 0/3] dmaengine: sun6i: Upgrade for audio transfers

value '4' (Maxime Ripard) - remove the driver fixes v2 (comments from Vinod Koul and Sergei Shtylyov - thanks) - typo fixes - change some comments - better handling of burst and bus width - remove useless code in the cyclic capability patch Jean-Francois Moine (3): dmaengine: sun6i: Set

[linux-sunxi] [PATCH v5 3/3] dmaengine: sun6i: Add cyclic capability

DMA cyclic transfers are required by audio streaming. Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/dma/sun6i-dma.c | 129 +--- 1 file changed, 122 insertions(+),

[linux-sunxi] [PATCH v5 2/3] dmaengine: sun6i: Set default maxburst size and bus width

Some DMA clients, as audio, don't set the maxburst size and bus width on the memory side when starting DMA transfers. This patch prevents such transfers to be aborted by providing system default values to the lacking ones. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drive

[linux-sunxi] [PATCH v5 1/3] dmaengine: sun6i: Simplify lli setting

Checking the DMA config before setting the lli list avoids to do tests inside the setting loop. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/dma/sun6i-dma.c | 102 ++-- 1 file changed, 47 insertions(+), 55 deletions(-) diff

[linux-sunxi] [PATCH v5 0/3] dmaengine: sun6i: Upgrade for audio transfers

handling of burst and bus width - remove useless code in the cyclic capability patch Jean-Francois Moine (3): dmaengine: sun6i: Simplify lli setting dmaengine: sun6i: Set default maxburst size and bus width dmaengine: sun6i: Add cyclic capability drivers/dma/sun6i-dma.c | 246

[linux-sunxi] [PATCH RESEND v3 1/2] dmaengine: sun6i: Fix the access of the IRQ register

The IRQ register number is computed, but this number was not used and the register was the one indexed by the channel index instead. Then, only the first DMA channel was working. Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Signed-off-by: Jean-Francois Moine <moin..

[linux-sunxi] [PATCH RESEND v3 0/2] dmaengine: sun6i: Fixes

and Sergei Shtylyov - thanks) - typo fixes - change some comments - better handling of burst and bus width - remove useless code in the cyclic capability patch Jean-Francois Moine (2): dmaengine: sun6i: Fix the access of the IRQ register dmaengine: sun6i: Fix impossible settings of burst and bus

[linux-sunxi] [PATCH RESEND v3 2/2] dmaengine: sun6i: Fix impossible settings of burst and bus width

the burst or buswidth had values different from 1, as 8 for the burst or 4 for the bus width. Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/dma/sun6i-dma.c | 10 +- 1 file changed, 5 insertions(+), 5 de

[linux-sunxi] [PATCH v4 3/3] dmaengine: sun6i: Add cyclic capability

DMA cyclic transfers are required by audio streaming. Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/dma/sun6i-dma.c | 129 +--- 1 file changed, 122 insertions(+),

[linux-sunxi] [PATCH v4 2/3] dmaengine: sun6i: Set default maxburst size and bus width

Some DMA clients, as audio, don't set the maxburst size and bus width on the memory side when starting DMA transfers. This patch prevents such transfers to be aborted by providing system default values to the lacking ones. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drive

[linux-sunxi] [PATCH v4 1/3] dmaengine: sun6i: Simplify lli setting

Checking the DMA config before setting the lli list avoids to do tests inside the setting loop. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- drivers/dma/sun6i-dma.c | 102 ++-- 1 file changed, 47 insertions(+), 55 deletions(-) diff

[linux-sunxi] [PATCH v4 0/3] dmaengine: sun6i: Upgrade for audio transfers

- remove useless code in the cyclic capability patch Jean-Francois Moine (3): dmaengine: sun6i: Simplify lli setting dmaengine: sun6i: Set default maxburst size and bus width dmaengine: sun6i: Add cyclic capability drivers/dma/sun6i-dma.c | 246 1

[linux-sunxi] Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

On Fri, 5 Feb 2016 12:11:52 +0100 Maxime Ripard wrote: > However, I'd like to keep per-soc and per-clocks compatibles in the > DT, in case we need to protect a clock in the future. What do you mean by "protect a clock"? -- Ken ar c'hentañ | **

[linux-sunxi] Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

On Thu, 4 Feb 2016 00:33:46 +0100 Krzysztof Adamski wrote: > This patch adds support for APB0 in H3. It seems to be compatible with > earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, > etc). > > Signed-off-by: Krzysztof Adamski > --- >

[linux-sunxi] Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver

clk/sunxi/clk-multi-gates.c [snip] Glad to see that things are moving to the right way. Thanks. Acked-by: Jean-Francois Moine <moin...@free.fr> -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ -- You receiv

Re: [linux-sunxi] Problem with Allwinner H3 clocks

On Thu, 28 Jan 2016 20:29:31 +0100 Maxime Ripard wrote: > > You are right, I had these lines in my DT. Thanks. > > And even though you had these lines, it was still not working? Or is > it working now? I'm confused. It was not working with these lines because

Re: [linux-sunxi] Problem with Allwinner H3 clocks

On Thu, 28 Jan 2016 09:15:57 +0100 Hans de Goede wrote: > p.s. > > Did I understand correctly that you are working on a kms (or fbdev) driver > for the H3? A fellow Dutch hacker (Jelle van der Waa, added to the Cc) is > looking into adding H3 video console support to

Re: [linux-sunxi] Problem with Allwinner H3 clocks

On Thu, 28 Jan 2016 14:16:26 +0100 Jens Kuske wrote: > after figuring out how to boot a devicetree kernel with allwinner's > u-boot I only had to add the mandatory > > clock-frequency = <2400>; > arm,cpu-registers-not-fw-configured; > > to the timer

Re: [linux-sunxi] Problem with Allwinner H3 clocks

On Wed, 27 Jan 2016 15:36:21 +0100 Jens Kuske wrote: > That sounds strange, 4.5-rc1 is working perfectly fine for me too. > > I doubt the patch you linked is responsible for making it work, it only > removes the hardcoded output-names. If your DT isn't messed up this >

Re: [linux-sunxi] Problem with Allwinner H3 clocks

On Wed, 27 Jan 2016 19:16:42 +0100 Hans de Goede wrote: > > To be sure, I generated a pure 4.5-rc1 kernel. Same result: no UART. > > Maybe... one more information: I am using Allwinner's u-boot. > > Could be that that is the culprit, why are you not using upstream u-boot? >

Re: [linux-sunxi] Problem with Allwinner H3 clocks

On Wed, 27 Jan 2016 16:18:53 +0800 Chen-Yu Tsai <w...@csie.org> wrote: > Hi, Hi ChenYu, > On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine <moin...@free.fr> wrote: > > Hi Jens, > > > > My H3 machine (OPI2) cannot boot with the PLL6 (periph0)

[linux-sunxi] Problem with Allwinner H3 clocks

Hi Jens, My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined in the kernel 4.5-rc1. As there is no UART, I don't know what is wrong. But, applying your old patch [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

[linux-sunxi] Re: [PATCH] clk: sunxi: Extend the simple gates and handle the Allwinner H3

On Tue, 8 Dec 2015 08:53:54 +0100 Maxime Ripard wrote: > Look, we all agreed on a solution that raised all objections, but > yours. > > I'm going to take Jens patch. OK. Good luck for the next SoCs! -- Ken ar c'hentañ | ** Breizh ha Linux atav!

[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Mon, 7 Dec 2015 19:44:30 +0100 Jens Kuske wrote: > >> + "bus_lcd0", "bus_lcd1", > >> "bus_deint", > > > "bus_tcon0", "bus_tcon1", "bus_deint", > > > > (the tcon1 clock is used by both lcd0 and lcd1, while > > the tcon0 clock

[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Tue, 8 Dec 2015 09:32:24 +0100 Maxime Ripard wrote: > If the H3 display block is done the same way than the A10 (and later) > one on this aspect, then the TCON has two channels with two different > streaming (or functional, you pick the name) clocks. The

[linux-sunxi] Re: [PATCH] clk: sunxi: Extend the simple gates and handle the Allwinner H3

On Mon, 7 Dec 2015 08:31:02 -0600 Rob Herring <r...@kernel.org> wrote: > On Sun, Dec 06, 2015 at 10:04:12AM +0100, Jean-Francois Moine wrote: > > The H3 has a clock gate definition similar to the other Allwinner SoCs, > > but with a different parent clock for each single

[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Fri, 4 Dec 2015 22:24:42 +0100 Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 497 >

[linux-sunxi] [PATCH] clk: sunxi: Extend the simple gates and handle the Allwinner H3

. Signed-off-by: Jean-Francois Moine <moin...@free.fr> --- This patch replaces a part of Jens Kuske's patch [PATCH v5 1/4] clk: sunxi: Add H3 clocks support --- Documentation/devicetree/bindings/clock/sunxi.txt | 25 +++ drivers/clk/sunxi/clk-simple-g

[linux-sunxi] Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

On Wed, 4 Nov 2015 08:30:14 -0800 Maxime Ripard wrote: > Hi Arnd, > > On Fri, Oct 30, 2015 at 09:27:03AM +0100, Arnd Bergmann wrote: > > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote: > > > > > > +static int sun8i_h3_bus_reset_xlate(struct

[linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Tue, 27 Oct 2015 17:50:25 +0100 Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 482 >

[linux-sunxi] Re: [PATCH v4 0/6] ARM: sunxi: Introduce Allwinner H3 support

On Tue, 27 Oct 2015 17:50:20 +0100 Jens Kuske wrote: > Changes since v3: > - add a clock driver specific to the bus gates instead of listing parents in > the DTSI > - skip the holes in the reset controller with of_xlate() Hi, Maxime, there we are :(. The H3 description is

[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Fri, 23 Oct 2015 20:14:06 +0200 Maxime Ripard wrote: > On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > > + bus_gates: clk@01c20060 { > > + #clock-cells = <1>; > > + compatible =

[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Wed, 21 Oct 2015 18:20:27 +0200 Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 499 >

[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Thu, 22 Oct 2015 10:05:08 +0200 Maxime Ripard wrote: > > + uart0: serial@01c28000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28000 0x400>; > > + interrupts = ; > > +

[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Thu, 22 Oct 2015 10:47:35 +0200 Maxime Ripard wrote: > Not really. The uart0 reset is the bit 16, in the reset register 4. > > 4 * 32 + 16 = 44. > > Not 112, but still not 208 either. The registers are numbered 1..5, then (4 - 1) * 32 + 16 = 112 -- Ken

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