Hi,
This year for fosdem sunxi visitors, we are doing the dinner with
other embedded people here:
https://elinux.org/FOSDEM
Please register here ASAP:
https://doodle.com/poll/6rxc94nsbgqxnfun
If there is not enough space, I have an alternative nice location
which has a larger room available.
Hi,
This year for fosdem sunxi visitors, we are doing the dinner with
other embedded people here:
https://elinux.org/FOSDEM
Please register here ASAP:
https://doodle.com/poll/6rxc94nsbgqxnfun
If there is not enough space, I have an alternative nice location
which has a larger room available.
Hi,
This year for fosdem sunxi visitors, we are doing the dinner with
other embedded people here:
https://elinux.org/FOSDEM
Please register here ASAP:
https://doodle.com/poll/6rxc94nsbgqxnfun
If there is not enough space, I have an alternative nice location
which has a larger room available.
On Fri, 25 Jan 2019 13:54:50 +0530
Jagan Teki wrote:
> From: Andre Przywara
>
> Add the MMC clock gates and reset bits for all the Allwinner SoCs.
> This allows them to be used by the MMC driver.
>
> We don't advertise the mod clock yet, as this is still handled by the
> MMC driver.
>
>
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wrote:
>
> On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki wrote:
> >
> > On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wrote:
> > >
> > > On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki
> > > wrote:
> > > >
> > > > Compared to previous version changes[1]
On Fri, Jan 25, 2019 at 7:37 PM Andre Przywara wrote:
>
> On Fri, 25 Jan 2019 19:01:12 +0800
> Chen-Yu Tsai wrote:
>
> Hi,
>
> > On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> > wrote:
> > >
> > > On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai
> > > wrote:
> > > >
> > > > On Fri, Jan 25, 2019 at
Hi,
On Thu, Jan 24, 2019 at 02:10:25PM +0100, Paul Kocialkowski wrote:
> On Tue, 2018-11-27 at 09:21 +0100, Maxime Ripard wrote:
> > Hi!
> >
> > On Fri, Nov 23, 2018 at 02:02:09PM +0100, Paul Kocialkowski wrote:
> > > This introduces support for HEVC/H.265 to the Cedrus VPU driver, with
> > >
On Fri, Jan 25, 2019 at 5:07 PM Andre Przywara wrote:
>
> On Fri, 25 Jan 2019 19:01:12 +0800
> Chen-Yu Tsai wrote:
>
> Hi,
>
> > On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> > wrote:
> > >
> > > On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai
> > > wrote:
> > > >
> > > > On Fri, Jan 25, 2019 at
Environment and fastboot mmc devices are configured based on the number
of mmc slots defined on particular board configs, MMC_SUNXI_SLOT_EXTRA.
If MMC_SUNXI_SLOT_EXTRA is more than 1, the default env and fastboot
mmc devices is mmc1 by assuming mmc0 is SD and mmc1 is emmc device.
But with DM_MMC
On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki wrote:
>
> On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wrote:
> >
> > On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki
> > wrote:
> > >
> > > Compared to previous version changes[1] this version do manage
> > > ahb clocks/resets via CLK framework.
> > >
>
On Fri, 25 Jan 2019 19:01:12 +0800
Chen-Yu Tsai wrote:
Hi,
> On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> wrote:
> >
> > On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai
> > wrote:
> > >
> > > On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki
> > > wrote:
> > > >
> > > > On Tue, Jan 22, 2019 at
From: Andre Przywara
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the
MMC driver.
Signed-off-by: Andre Przywara
[jagan: add V3S, A80 gates/resets]
On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wrote:
>
> On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki wrote:
> >
> > Compared to previous version changes[1] this version do manage
> > ahb clocks/resets via CLK framework.
> >
> > This version created changes along with Andre patches to support
> >
On Fri, 25 Jan 2019 12:46:38 +0530
Jagan Teki wrote:
> On Sat, Jan 19, 2019 at 7:03 AM Andre Przywara
> wrote:
> >
> > If a board DT describes a cd-gpios property, but also marks the
> > storage as non-removable, we must ignore the GPIO (as Linux does).
> >
> > Teach the DM_MMC part of the
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki wrote:
>
> On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wrote:
> >
> > On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wrote:
> > > >
> > > > On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki
On Fri, 25 Jan 2019 19:42:22 +0800
Chen-Yu Tsai wrote:
> On Fri, Jan 25, 2019 at 7:37 PM Andre Przywara
> wrote:
> >
> > On Fri, 25 Jan 2019 19:01:12 +0800
> > Chen-Yu Tsai wrote:
> >
> > Hi,
> >
> > > On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> > > wrote:
> > > >
> > > > On Fri, Jan 25,
On Thu, Jan 24, 2019 at 10:37:23PM +0800, Ayaka wrote:
> > +#define V4L2_H264_DPB_ENTRY_FLAG_VALID0x01
> > +#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE0x02
> > +#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM0x04
> > +
> > +struct v4l2_h264_dpb_entry {
> > +
On Thu, Jan 24, 2019 at 11:37:32PM +0530, Jagan Teki wrote:
> Allwinner A64 CSI is a single channel time-multiplexed BT.656
> protocol interface.
>
> Add separate compatible string for A64 since it require explicit
> change in sun6i_csi driver to update default CSI_SCLK rate.
>
> Reviewed-by:
On Fri, Jan 25, 2019 at 01:28:50AM +0530, Jagan Teki wrote:
> Most of the Allwinner MIPI DSI controllers are supply with
> VCC-DSI pin. which need to supply for some of the boards to
> trigger the power.
>
> So, document the supply property so-that the required board
> can eable it via device
On Fri, Jan 25, 2019 at 01:28:52AM +0530, Jagan Teki wrote:
> The MIPI DSI controller in Allwinner A64 is similar to A33.
>
> But unlike A33, A64 doesn't have DSI_SCLK gating which eventually
> set the mod clock rate for the controller.
>
> So, use the DSI_DPHY gating for the similar purpose of
On Fri, Jan 25, 2019 at 01:28:53AM +0530, Jagan Teki wrote:
> The MIPI DSI PHY controller on Allwinner A64 is similar
> on the one on A31.
>
> Add A64 compatible and append A31 compatible as fallback.
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Rob Herring
> ---
>
On Thu, Jan 24, 2019 at 11:37:33PM +0530, Jagan Teki wrote:
> CSI block in Allwinner A64 has similar features as like in H3,
> but the default CSI_SCLK rate cannot work properly to drive the
> connected sensor interface.
>
> The tested mod cock rate is 300 MHz and BSP vfe media driver is also
>
On Thu, Jan 24, 2019 at 11:37:34PM +0530, Jagan Teki wrote:
> Add dts node details for Allwinner A64 CSI controller.
>
> A64 CSI has similar features as like in H3, but the CSI_SCLK
> need to update it to 300MHz than default clock rate.
>
> Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
On Fri, Jan 25, 2019 at 10:49:58AM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 25, 2019 at 2:57 AM Jernej Škrabec
> wrote:
> >
> > Dne ponedeljek, 21. januar 2019 ob 10:57:57 CET je Chen-Yu Tsai napisal(a):
> > > On Mon, Jan 21, 2019 at 5:50 PM Maxime Ripard
> > wrote:
> > > > Hi,
> > > >
> > > >
On Fri, Jan 25, 2019 at 01:28:54AM +0530, Jagan Teki wrote:
> The A64 has a MIPI-DSI block which is similar to A31.
>
> Add dsi, dphy nodes with A31 fallback compatible and finally
> connect the dsi node to tcon0 node to make proper DSI pipeline.
>
> Signed-off-by: Jagan Teki
> ---
>
On Fri, Jan 25, 2019 at 01:28:49AM +0530, Jagan Teki wrote:
> Minimum PLL used for MIPI is 500MHz, as per manual, but
> lowering the min rate by 300MHz can result proper working
> nkms divider with the help of desired dclock rate from
> panel driver.
>
> Signed-off-by: Jagan Teki
> Acked-by:
On Tue, Jan 22, 2019 at 05:21:08PM +0530, Jagan Teki wrote:
> On Tue, Jan 22, 2019 at 4:41 PM Maxime Ripard
> wrote:
> >
> > On Fri, Jan 18, 2019 at 09:14:19PM +0530, Jagan Teki wrote:
> > > On Thu, Jan 17, 2019 at 10:02 AM Jagan Teki
> > > wrote:
> > > >
> > > > On Thu, Jan 17, 2019 at 12:48
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