[linux-sunxi] Re: [PATCH v8 3/6] pwm: sun4i: Add an optional probe for bus clock
Hi Uwe,
On Thu, 21 Nov 2019 at 22:06, Uwe Kleine-König
wrote:
>
> On Thu, Nov 21, 2019 at 08:58:59PM +0100, Clément Péron wrote:
> > From: Jernej Skrabec
> >
> > H6 PWM core needs bus clock to be enabled in order to work.
> >
> > Add an optional probe for it.
> >
> > Signed-off-by: Jernej Skrabec
> > Signed-off-by: Clément Péron
> > ---
> > drivers/pwm/pwm-sun4i.c | 23 +++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index 369990ae7d09..66befd8d6f9c 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> > @@ -78,6 +78,7 @@ struct sun4i_pwm_data {
> >
> > struct sun4i_pwm_chip {
> > struct pwm_chip chip;
> > + struct clk *bus_clk;
> > struct clk *clk;
> > struct reset_control *rst;
> > void __iomem *base;
> > @@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device
> > *pdev)
> > }
> > }
> >
> > + pwm->bus_clk = devm_clk_get_optional(>dev, "bus");
> > + if (IS_ERR(pwm->bus_clk)) {
> > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> > + dev_err(>dev, "get bus clock failed %pe\n",
> > + pwm->bus_clk);
> > + return PTR_ERR(pwm->bus_clk);
> > + }
> > +
> > pwm->rst = devm_reset_control_get_optional_shared(>dev, NULL);
> > if (IS_ERR(pwm->rst)) {
> > if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> > @@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device
> > *pdev)
> > return ret;
> > }
> >
> > + /*
> > + * We're keeping the bus clock on for the sake of simplicity.
> > + * Actually it only needs to be on for hardware register accesses.
> > + */
> > + ret = clk_prepare_enable(pwm->bus_clk);
> > + if (ret) {
> > + dev_err(>dev, "Cannot prepare and enable bus_clk %d\n",
> > + ret);
>
> nitpick: other error messages in this driver start with a lower case
> letter.
>
> Until there is an equivalent for %pe that consumes an int, I suggest to
> use
>
> dev_err(>dev, "Cannot prepare and enable bus_clk: %pe\n",
> ERR_PTR(ret));
>
> to benefit from a symbolic error name instead of an error constant.
Ok i will fix both
Thanks,
Clement
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K. | Uwe Kleine-König|
> Industrial Linux Solutions | https://www.pengutronix.de/ |
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[linux-sunxi] Re: [PATCH v8 5/6] pwm: sun4i: Add support to output source clock directly
Hi Uwe,
On Thu, 21 Nov 2019 at 22:16, Uwe Kleine-König
wrote:
>
> On Thu, Nov 21, 2019 at 08:59:01PM +0100, Clément Péron wrote:
> > From: Jernej Skrabec
> >
> > PWM core has an option to bypass whole logic and output unchanged source
> > clock as PWM output. This is achieved by enabling bypass bit.
> >
> > Note that when bypass is enabled, no other setting has any meaning, not
> > even enable bit.
> >
> > This mode of operation is needed to achieve high enough frequency to
> > serve as clock source for AC200 chip which is integrated into same
> > package as H6 SoC.
> >
> > Signed-off-by: Jernej Skrabec
> > Signed-off-by: Clément Péron
> > ---
> > drivers/pwm/pwm-sun4i.c | 48 +++--
> > 1 file changed, 46 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index 1fa2057419fb..0fe9c680d6d0 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> > @@ -3,6 +3,10 @@
> > * Driver for Allwinner sun4i Pulse Width Modulation Controller
> > *
> > * Copyright (C) 2014 Alexandre Belloni
> >
> > + *
> > + * Limitations:
> > + * - When outputing the source clock directly, the PWM logic will be
> > bypassed
> > + * and the currently running period is not guaranteed to be completed
> > */
> >
> > #include
> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
> >
> > struct sun4i_pwm_data {
> > bool has_prescaler_bypass;
> > + bool has_direct_mod_clk_output;
> > unsigned int npwm;
> > };
> >
> > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > + /*
> > + * PWM chapter in H6 manual has a diagram which explains that if
> > bypass
> > + * bit is set, no other setting has any meaning. Even more, experiment
> > + * proved that also enable bit is ignored in this case.
> > + */
> > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> > + sun4i_pwm->data->has_direct_mod_clk_output) {
> > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
> > + state->polarity = PWM_POLARITY_NORMAL;
> > + state->enabled = true;
> > + return;
> > + }
> > +
> > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
> > sun4i_pwm->data->has_prescaler_bypass)
> > prescaler = 1;
> > @@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> > static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
> > const struct pwm_state *state,
> > -u32 *dty, u32 *prd, unsigned int *prsclr)
> > +u32 *dty, u32 *prd, unsigned int *prsclr,
> > +bool *bypass)
> > {
> > u64 clk_rate, div = 0;
> > unsigned int pval, prescaler = 0;
> >
> > clk_rate = clk_get_rate(sun4i_pwm->clk);
> >
> > + *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
> > + state->enabled &&
> > + (state->period * clk_rate >= NSEC_PER_SEC) &&
> > + (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
> > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
> > +
> > + /* Skip calculation of other parameters if we bypass them */
> > + if (*bypass)
> > + return 0;
> > +
> > if (sun4i_pwm->data->has_prescaler_bypass) {
> > /* First, test without any prescaler when available */
> > prescaler = PWM_PRESCAL_MASK;
> > @@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip,
> > struct pwm_device *pwm,
> > int ret;
> > unsigned int delay_us, prescaler;
> > unsigned long now;
> > + bool bypass;
> >
> > pwm_get_state(pwm, );
> >
> > @@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip,
> > struct pwm_device *pwm,
> > spin_lock(_pwm->ctrl_lock);
> > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > - ret = sun4i_pwm_calculate(sun4i_pwm, state, , ,
> > );
> > + ret = sun4i_pwm_calculate(sun4i_pwm, state, , ,
> > ,
> > + );
> > if (ret) {
> > dev_err(chip->dev, "period exceeds the maximum value\n");
> > spin_unlock(_pwm->ctrl_lock);
> > @@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip,
> > struct pwm_device *pwm,
> > return ret;
> > }
> >
> > + if (sun4i_pwm->data->has_direct_mod_clk_output) {
> > + if (bypass) {
> > + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> > + /* We can skip other parameter */
> > + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
> > + spin_unlock(_pwm->ctrl_lock);
> > +
[linux-sunxi] Re: [PATCH v8 5/6] pwm: sun4i: Add support to output source clock directly
On Thu, Nov 21, 2019 at 08:59:01PM +0100, Clément Péron wrote:
> From: Jernej Skrabec
>
> PWM core has an option to bypass whole logic and output unchanged source
> clock as PWM output. This is achieved by enabling bypass bit.
>
> Note that when bypass is enabled, no other setting has any meaning, not
> even enable bit.
>
> This mode of operation is needed to achieve high enough frequency to
> serve as clock source for AC200 chip which is integrated into same
> package as H6 SoC.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Clément Péron
> ---
> drivers/pwm/pwm-sun4i.c | 48 +++--
> 1 file changed, 46 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 1fa2057419fb..0fe9c680d6d0 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -3,6 +3,10 @@
> * Driver for Allwinner sun4i Pulse Width Modulation Controller
> *
> * Copyright (C) 2014 Alexandre Belloni
>
> + *
> + * Limitations:
> + * - When outputing the source clock directly, the PWM logic will be bypassed
> + * and the currently running period is not guaranteed to be completed
> */
>
> #include
> @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
>
> struct sun4i_pwm_data {
> bool has_prescaler_bypass;
> + bool has_direct_mod_clk_output;
> unsigned int npwm;
> };
>
> @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>
> val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>
> + /*
> + * PWM chapter in H6 manual has a diagram which explains that if bypass
> + * bit is set, no other setting has any meaning. Even more, experiment
> + * proved that also enable bit is ignored in this case.
> + */
> + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> + sun4i_pwm->data->has_direct_mod_clk_output) {
> + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
> + state->polarity = PWM_POLARITY_NORMAL;
> + state->enabled = true;
> + return;
> + }
> +
> if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
> sun4i_pwm->data->has_prescaler_bypass)
> prescaler = 1;
> @@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>
> static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
> const struct pwm_state *state,
> -u32 *dty, u32 *prd, unsigned int *prsclr)
> +u32 *dty, u32 *prd, unsigned int *prsclr,
> +bool *bypass)
> {
> u64 clk_rate, div = 0;
> unsigned int pval, prescaler = 0;
>
> clk_rate = clk_get_rate(sun4i_pwm->clk);
>
> + *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
> + state->enabled &&
> + (state->period * clk_rate >= NSEC_PER_SEC) &&
> + (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
> + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
> +
> + /* Skip calculation of other parameters if we bypass them */
> + if (*bypass)
> + return 0;
> +
> if (sun4i_pwm->data->has_prescaler_bypass) {
> /* First, test without any prescaler when available */
> prescaler = PWM_PRESCAL_MASK;
> @@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
> pwm_device *pwm,
> int ret;
> unsigned int delay_us, prescaler;
> unsigned long now;
> + bool bypass;
>
> pwm_get_state(pwm, );
>
> @@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
> pwm_device *pwm,
> spin_lock(_pwm->ctrl_lock);
> ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>
> - ret = sun4i_pwm_calculate(sun4i_pwm, state, , , );
> + ret = sun4i_pwm_calculate(sun4i_pwm, state, , , ,
> + );
> if (ret) {
> dev_err(chip->dev, "period exceeds the maximum value\n");
> spin_unlock(_pwm->ctrl_lock);
> @@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
> pwm_device *pwm,
> return ret;
> }
>
> + if (sun4i_pwm->data->has_direct_mod_clk_output) {
> + if (bypass) {
> + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> + /* We can skip other parameter */
> + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
> + spin_unlock(_pwm->ctrl_lock);
> + return 0;
> + } else {
> + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
> + }
> + }
This could be simplified to:
if (bypass) {
ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
/*
* Other
[linux-sunxi] Re: [PATCH v8 4/6] pwm: sun4i: Always calculate params when applying new parameters
On Thu, Nov 21, 2019 at 08:59:00PM +0100, Clément Péron wrote: > Bypass mode will require to be re-calculated when the pwm state > is changed. > > Remove the condition so pwm_sun4i_calculate is always called. > > Signed-off-by: Clément Péron When applying this patch and looking at it using git show -b it is obvious the patch does exactly what is promised here. (Apart from the introduced empty line in the last hunk which is ok in my book.) Reviewed-by: Uwe Kleine-König Thanks Uwe -- Pengutronix e.K. | Uwe Kleine-König| Industrial Linux Solutions | https://www.pengutronix.de/ | -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191121211142.kuhcxpxudt3tod4p%40pengutronix.de.
[linux-sunxi] Re: [PATCH v8 3/6] pwm: sun4i: Add an optional probe for bus clock
On Thu, Nov 21, 2019 at 08:58:59PM +0100, Clément Péron wrote:
> From: Jernej Skrabec
>
> H6 PWM core needs bus clock to be enabled in order to work.
>
> Add an optional probe for it.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Clément Péron
> ---
> drivers/pwm/pwm-sun4i.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 369990ae7d09..66befd8d6f9c 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -78,6 +78,7 @@ struct sun4i_pwm_data {
>
> struct sun4i_pwm_chip {
> struct pwm_chip chip;
> + struct clk *bus_clk;
> struct clk *clk;
> struct reset_control *rst;
> void __iomem *base;
> @@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
> }
> }
>
> + pwm->bus_clk = devm_clk_get_optional(>dev, "bus");
> + if (IS_ERR(pwm->bus_clk)) {
> + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> + dev_err(>dev, "get bus clock failed %pe\n",
> + pwm->bus_clk);
> + return PTR_ERR(pwm->bus_clk);
> + }
> +
> pwm->rst = devm_reset_control_get_optional_shared(>dev, NULL);
> if (IS_ERR(pwm->rst)) {
> if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> @@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
> return ret;
> }
>
> + /*
> + * We're keeping the bus clock on for the sake of simplicity.
> + * Actually it only needs to be on for hardware register accesses.
> + */
> + ret = clk_prepare_enable(pwm->bus_clk);
> + if (ret) {
> + dev_err(>dev, "Cannot prepare and enable bus_clk %d\n",
> + ret);
nitpick: other error messages in this driver start with a lower case
letter.
Until there is an equivalent for %pe that consumes an int, I suggest to
use
dev_err(>dev, "Cannot prepare and enable bus_clk: %pe\n",
ERR_PTR(ret));
to benefit from a symbolic error name instead of an error constant.
Best regards
Uwe
--
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Industrial Linux Solutions | https://www.pengutronix.de/ |
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[linux-sunxi] [PATCH v8 6/6] pwm: sun4i: Add support for H6 PWM
From: Jernej Skrabec
Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.
Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.
Signed-off-by: Jernej Skrabec
Acked-by: Uwe Kleine-König
Signed-off-by: Clément Péron
---
drivers/pwm/pwm-sun4i.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 0fe9c680d6d0..84f3ccab47f9 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass
= {
.npwm = 1,
};
+static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
+ .has_prescaler_bypass = true,
+ .has_direct_mod_clk_output = true,
+ .npwm = 2,
+};
+
static const struct of_device_id sun4i_pwm_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-pwm",
@@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
}, {
.compatible = "allwinner,sun8i-h3-pwm",
.data = _pwm_single_bypass,
+ }, {
+ .compatible = "allwinner,sun50i-h6-pwm",
+ .data = _h6_pwm_data,
}, {
/* sentinel */
},
--
2.20.1
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[linux-sunxi] [PATCH v8 5/6] pwm: sun4i: Add support to output source clock directly
From: Jernej Skrabec
PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.
Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.
This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.
Signed-off-by: Jernej Skrabec
Signed-off-by: Clément Péron
---
drivers/pwm/pwm-sun4i.c | 48 +++--
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 1fa2057419fb..0fe9c680d6d0 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -3,6 +3,10 @@
* Driver for Allwinner sun4i Pulse Width Modulation Controller
*
* Copyright (C) 2014 Alexandre Belloni
+ *
+ * Limitations:
+ * - When outputing the source clock directly, the PWM logic will be bypassed
+ * and the currently running period is not guaranteed to be completed
*/
#include
@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
struct sun4i_pwm_data {
bool has_prescaler_bypass;
+ bool has_direct_mod_clk_output;
unsigned int npwm;
};
@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ /*
+* PWM chapter in H6 manual has a diagram which explains that if bypass
+* bit is set, no other setting has any meaning. Even more, experiment
+* proved that also enable bit is ignored in this case.
+*/
+ if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
+ sun4i_pwm->data->has_direct_mod_clk_output) {
+ state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
+ state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = true;
+ return;
+ }
+
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
sun4i_pwm->data->has_prescaler_bypass)
prescaler = 1;
@@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
const struct pwm_state *state,
- u32 *dty, u32 *prd, unsigned int *prsclr)
+ u32 *dty, u32 *prd, unsigned int *prsclr,
+ bool *bypass)
{
u64 clk_rate, div = 0;
unsigned int pval, prescaler = 0;
clk_rate = clk_get_rate(sun4i_pwm->clk);
+ *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
+ state->enabled &&
+ (state->period * clk_rate >= NSEC_PER_SEC) &&
+ (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
+
+ /* Skip calculation of other parameters if we bypass them */
+ if (*bypass)
+ return 0;
+
if (sun4i_pwm->data->has_prescaler_bypass) {
/* First, test without any prescaler when available */
prescaler = PWM_PRESCAL_MASK;
@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
pwm_device *pwm,
int ret;
unsigned int delay_us, prescaler;
unsigned long now;
+ bool bypass;
pwm_get_state(pwm, );
@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
pwm_device *pwm,
spin_lock(_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
- ret = sun4i_pwm_calculate(sun4i_pwm, state, , , );
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, , , ,
+ );
if (ret) {
dev_err(chip->dev, "period exceeds the maximum value\n");
spin_unlock(_pwm->ctrl_lock);
@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
pwm_device *pwm,
return ret;
}
+ if (sun4i_pwm->data->has_direct_mod_clk_output) {
+ if (bypass) {
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ /* We can skip other parameter */
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ spin_unlock(_pwm->ctrl_lock);
+ return 0;
+ } else {
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ }
+ }
+
if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
/* Prescaler changed, the clock has to be gated */
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
--
2.20.1
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[linux-sunxi] [PATCH v8 2/6] pwm: sun4i: Prefer "mod" clock to unnamed
New device tree bindings called the source clock of the module
"mod" when several clocks are defined.
Try to get a clock called "mod" if nothing is found try to get
an unnamed clock.
Reviewed-by: Uwe Kleine-König
Signed-off-by: Clément Péron
---
drivers/pwm/pwm-sun4i.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index e353a03ec614..369990ae7d09 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);
- pwm->clk = devm_clk_get(>dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+* All hardware variants need a source clock that is divided and
+* then feeds the counter that defines the output wave form. In the
+* device tree this clock is either unnamed or called "mod".
+* Some variants (e.g. H6) need another clock to access the
+* hardware registers; this is called "bus".
+* So we request "mod" first (and ignore the corner case that a
+* parent provides a "mod" clock while the right one would be the
+* unnamed one of the PWM device) and if this is not found we fall
+* back to the first clock of the PWM.
+*/
+ pwm->clk = devm_clk_get_optional(>dev, "mod");
+ if (IS_ERR(pwm->clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(>dev, "get mod clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {
+ pwm->clk = devm_clk_get(>dev, NULL);
+ if (IS_ERR(pwm->clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(>dev, "get unnamed clock failed
%pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }
+ }
pwm->rst = devm_reset_control_get_optional_shared(>dev, NULL);
if (IS_ERR(pwm->rst)) {
--
2.20.1
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[linux-sunxi] [PATCH v8 4/6] pwm: sun4i: Always calculate params when applying new parameters
Bypass mode will require to be re-calculated when the pwm state
is changed.
Remove the condition so pwm_sun4i_calculate is always called.
Signed-off-by: Clément Péron
---
drivers/pwm/pwm-sun4i.c | 52 ++---
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 66befd8d6f9c..1fa2057419fb 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
pwm_device *pwm,
{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
- u32 ctrl;
+ u32 ctrl, duty, period, val;
int ret;
- unsigned int delay_us;
+ unsigned int delay_us, prescaler;
unsigned long now;
pwm_get_state(pwm, );
@@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
pwm_device *pwm,
spin_lock(_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
- if ((cstate.period != state->period) ||
- (cstate.duty_cycle != state->duty_cycle)) {
- u32 period, duty, val;
- unsigned int prescaler;
-
- ret = sun4i_pwm_calculate(sun4i_pwm, state,
- , , );
- if (ret) {
- dev_err(chip->dev, "period exceeds the maximum
value\n");
- spin_unlock(_pwm->ctrl_lock);
- if (!cstate.enabled)
- clk_disable_unprepare(sun4i_pwm->clk);
- return ret;
- }
-
- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
- /* Prescaler changed, the clock has to be gated */
- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, , , );
+ if (ret) {
+ dev_err(chip->dev, "period exceeds the maximum value\n");
+ spin_unlock(_pwm->ctrl_lock);
+ if (!cstate.enabled)
+ clk_disable_unprepare(sun4i_pwm->clk);
+ return ret;
+ }
- ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
- ctrl |= BIT_CH(prescaler, pwm->hwpwm);
- }
+ if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
+ /* Prescaler changed, the clock has to be gated */
+ ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
- val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
- sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
- sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
- usecs_to_jiffies(cstate.period / 1000 + 1);
- sun4i_pwm->needs_delay[pwm->hwpwm] = true;
+ ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
+ ctrl |= BIT_CH(prescaler, pwm->hwpwm);
}
+ val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
+ sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
+ usecs_to_jiffies(cstate.period / 1000 + 1);
+ sun4i_pwm->needs_delay[pwm->hwpwm] = true;
+
if (state->polarity != PWM_POLARITY_NORMAL)
ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
else
ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+
if (state->enabled) {
ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
--
2.20.1
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[linux-sunxi] [PATCH v8 3/6] pwm: sun4i: Add an optional probe for bus clock
From: Jernej Skrabec
H6 PWM core needs bus clock to be enabled in order to work.
Add an optional probe for it.
Signed-off-by: Jernej Skrabec
Signed-off-by: Clément Péron
---
drivers/pwm/pwm-sun4i.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 369990ae7d09..66befd8d6f9c 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_chip {
struct pwm_chip chip;
+ struct clk *bus_clk;
struct clk *clk;
struct reset_control *rst;
void __iomem *base;
@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}
+ pwm->bus_clk = devm_clk_get_optional(>dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(>dev, "get bus clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);
+ }
+
pwm->rst = devm_reset_control_get_optional_shared(>dev, NULL);
if (IS_ERR(pwm->rst)) {
if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
@@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;
}
+ /*
+* We're keeping the bus clock on for the sake of simplicity.
+* Actually it only needs to be on for hardware register accesses.
+*/
+ ret = clk_prepare_enable(pwm->bus_clk);
+ if (ret) {
+ dev_err(>dev, "Cannot prepare and enable bus_clk %d\n",
+ ret);
+ goto err_bus;
+ }
+
pwm->chip.dev = >dev;
pwm->chip.ops = _pwm_ops;
pwm->chip.base = -1;
@@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return 0;
err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
reset_control_assert(pwm->rst);
return ret;
@@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
if (ret)
return ret;
+ clk_disable_unprepare(pwm->bus_clk);
reset_control_assert(pwm->rst);
return 0;
--
2.20.1
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[linux-sunxi] [PATCH v8 1/6] pwm: sun4i: Add an optional probe for reset line
From: Jernej Skrabec
H6 PWM core needs deasserted reset line in order to work.
Add an optional probe for it.
Signed-off-by: Jernej Skrabec
Reviewed-by: Uwe Kleine-König
Signed-off-by: Clément Péron
---
drivers/pwm/pwm-sun4i.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..e353a03ec614 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -78,6 +79,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;
spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
+ pwm->rst = devm_reset_control_get_optional_shared(>dev, NULL);
+ if (IS_ERR(pwm->rst)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(>dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);
+ if (ret) {
+ dev_err(>dev, "Cannot deassert reset control: %d\n",
+ ret);
+ return ret;
+ }
+
pwm->chip.dev = >dev;
pwm->chip.ops = _pwm_ops;
pwm->chip.base = -1;
@@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(>chip);
if (ret < 0) {
dev_err(>dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}
platform_set_drvdata(pdev, pwm);
return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}
static int sun4i_pwm_remove(struct platform_device *pdev)
{
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pwmchip_remove(>chip);
+ if (ret)
+ return ret;
+
+ reset_control_assert(pwm->rst);
- return pwmchip_remove(>chip);
+ return 0;
}
static struct platform_driver sun4i_pwm_driver = {
--
2.20.1
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[linux-sunxi] [PATCH v8 0/6] Add support for H6 PWM
Hi, This is a rework of Jernej's previous work[1] taking account all the previous remarks. Bindings is still strict but probe in the driver are now optionnals. If someone could confirm that the PWM is not broken, as my board doesn't output it. Thanks, Clément Jernej's cover: Allwinner H6 SoC has PWM core which is basically the same as that found in A20, it's just depends on additional bus clock and reset line. This series adds support for it and extends PWM driver functionality in a way that it's now possible to bypass whole core and output PWM source clock directly as a PWM signal. This functionality is needed by AC200 chip, which is bundled in same physical package as H6 SoC, to serve as a clock source of 24 MHz. AC200 clock input pin is bonded internally to the second PWM channel. I would be grateful if anyone can test this patch series for any kind of regression on other SoCs. [1]: https://patchwork.kernel.org/cover/11061737/ Changes in v8: - Display error return code - split commit - bypass is false if unsupported - return instead of goto Changes in v7: - Fix indent in Yaml bindings Changes in v6: - Update git commit log - Distinguish error message Changes in v5: - Move bypass calculation to pwm_calculate - Split mod_clock fallback from bus_clk probe - Update comment - Move my SoB after acked-by/reviewed-by Changes in v4: - item description in correct order and add a blank line - use %pe for printing PTR_ERR - don't print error when it's an EPROBE_DEFER - change output clock bypass formula to match PWM policy Changes in v3: - Documentation update to allow one clock without name - Change reset optional to shared - If reset probe failed return an error - Remove old clock probe - Update bypass enabled formula Changes in v2: - Remove allOf in Documentation - Add H6 example in Documentation - Change clock name from "pwm" to "mod" - Change reset quirk to optional probe - Change bus_clock quirk to optional probe - Add limitation comment about mod_clk_output - Add quirk for mod_clk_output - Change bypass formula Clément Péron (2): pwm: sun4i: Prefer "mod" clock to unnamed pwm: sun4i: Always calculate params when applying new parameters Jernej Skrabec (4): pwm: sun4i: Add an optional probe for reset line pwm: sun4i: Add an optional probe for bus clock pwm: sun4i: Add support to output source clock directly pwm: sun4i: Add support for H6 PWM drivers/pwm/pwm-sun4i.c | 187 +--- 1 file changed, 156 insertions(+), 31 deletions(-) -- 2.20.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191121195902.6906-1-peron.clem%40gmail.com.
[linux-sunxi] Re: [PATCH v11 4/7] drm/sun4i: dsi: Handle bus clock explicitly
Hi Maxime,
On Sun, Nov 3, 2019 at 11:02 PM Maxime Ripard wrote:
>
> On Fri, Nov 01, 2019 at 07:42:55PM +0530, Jagan Teki wrote:
> > Hi Maxime,
> >
> > On Tue, Oct 29, 2019 at 2:24 PM Maxime Ripard wrote:
> > >
> > > On Tue, Oct 29, 2019 at 04:03:56AM +0530, Jagan Teki wrote:
> > > > > > explicit handling of common clock would require since the A64
> > > > > > doesn't need to mention the clock-names explicitly in dts since it
> > > > > > support only one bus clock.
> > > > > >
> > > > > > Also pass clk_id NULL instead "bus" to regmap clock init function
> > > > > > since the single clock variants no need to mention clock-names
> > > > > > explicitly.
> > > > >
> > > > > You don't need explicit clock handling. Passing NULL as the argument
> > > > > in regmap_init_mmio_clk will make it use the first clock, which is the
> > > > > bus clock.
> > > >
> > > > Indeed I tried that, since NULL clk_id wouldn't enable the bus clock
> > > > during regmap_mmio_gen_context code, passing NULL triggering vblank
> > > > timeout.
> > >
> > > There's a bunch of users of NULL in tree, so finding out why NULL
> > > doesn't work is the way forward.
> >
> > I'd have looked the some of the users before checking the code as
> > well. As I said passing NULL clk_id to devm_regmap_init_mmio_clk =>
> > __devm_regmap_init_mmio_clk would return before processing the clock.
> >
> > Here is the code snippet on the tree just to make sure I'm on the same
> > page or not.
> >
> > static struct regmap_mmio_context *regmap_mmio_gen_context(struct device
> > *dev,
> > const char *clk_id,
> > void __iomem *regs,
> > const struct regmap_config *config)
> > {
> > ---
> > --
> > if (clk_id == NULL)
> > return ctx;
> >
> > ctx->clk = clk_get(dev, clk_id);
> > if (IS_ERR(ctx->clk)) {
> > ret = PTR_ERR(ctx->clk);
> > goto err_free;
> > }
> >
> > ret = clk_prepare(ctx->clk);
> > if (ret < 0) {
> > clk_put(ctx->clk);
> > goto err_free;
> > }
> > -
> > ---
> > }
> >
> > Yes, I did check on the driver in the tree before committing explicit
> > clock handle, which make similar requirements like us in [1]. this
> > imx2 wdt driver is handling the explicit clock as well. I'm sure this
> > driver is updated as I have seen few changes related to this driver in
> > ML.
>
> I guess we have two ways to go at this then.
>
> Either we remove the return, but it might have a few side-effects, or
> we call clk_get with NULL or bus depending on the case, and then call
> regmap_mmio_attach_clk.
Thanks for the inputs.
Please have a look at this snippet, I have used your second
suggestions. let me know if you have any comments?
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 8fa90cfc2ac8..91c95e56d870 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -1109,24 +1109,36 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
return PTR_ERR(dsi->regulator);
}
-dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
- _dsi_regmap_config);
-if (IS_ERR(dsi->regs)) {
-dev_err(dev, "Couldn't create the DSI encoder regmap\n");
-return PTR_ERR(dsi->regs);
-}
-
dsi->reset = devm_reset_control_get_shared(dev, NULL);
if (IS_ERR(dsi->reset)) {
dev_err(dev, "Couldn't get our reset line\n");
return PTR_ERR(dsi->reset);
}
+dsi->regs = regmap_init_mmio(dev, base, _dsi_regmap_config);
+if (IS_ERR(dsi->regs)) {
+dev_err(dev, "Couldn't init regmap\n");
+return PTR_ERR(dsi->regs);
+}
+
+dsi->bus_clk = devm_clk_get(dev, NULL);
+if (IS_ERR(dsi->bus_clk)) {
+dev_err(dev, "Couldn't get the DSI bus clock\n");
+ret = PTR_ERR(dsi->bus_clk);
+goto err_regmap;
+} else {
+printk("Jagan.. Got the BUS clock\n");
+ret = regmap_mmio_attach_clk(dsi->regs, dsi->bus_clk);
+if (ret)
+goto err_bus_clk;
+}
+
if (dsi->variant->has_mod_clk) {
dsi->mod_clk = devm_clk_get(dev, "mod");
if (IS_ERR(dsi->mod_clk)) {
dev_err(dev, "Couldn't get the DSI mod clock\n");
-return PTR_ERR(dsi->mod_clk);
+ret = PTR_ERR(dsi->mod_clk);
+goto err_attach_clk;
}
}
@@ -1167,6 +1179,14 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
err_unprotect_clk:
if (dsi->variant->has_mod_clk)
clk_rate_exclusive_put(dsi->mod_clk);
+err_attach_clk:
+if (!IS_ERR(dsi->bus_clk))
+regmap_mmio_detach_clk(dsi->regs);
+err_bus_clk:
+if (!IS_ERR(dsi->bus_clk))
+
[linux-sunxi] Re: [PATCH v7 5/8] pwm: sun4i: Add support to output source clock directly
Hi Uwe,
On Thu, 21 Nov 2019 at 08:36, Uwe Kleine-König
wrote:
>
> Hello Clément,
>
> On Tue, Nov 19, 2019 at 06:53:16PM +0100, Clément Péron wrote:
> > From: Jernej Skrabec
> >
> > PWM core has an option to bypass whole logic and output unchanged source
> > clock as PWM output. This is achieved by enabling bypass bit.
> >
> > Note that when bypass is enabled, no other setting has any meaning, not
> > even enable bit.
> >
> > This mode of operation is needed to achieve high enough frequency to
> > serve as clock source for AC200 chip which is integrated into same
> > package as H6 SoC.
> >
> > Signed-off-by: Jernej Skrabec
> > Signed-off-by: Clément Péron
> > ---
> > drivers/pwm/pwm-sun4i.c | 92 -
> > 1 file changed, 64 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index ce83d479ba0e..a1d8851b18f0 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> > @@ -3,6 +3,10 @@
> > * Driver for Allwinner sun4i Pulse Width Modulation Controller
> > *
> > * Copyright (C) 2014 Alexandre Belloni
> >
> > + *
> > + * Limitations:
> > + * - When outputing the source clock directly, the PWM logic will be
> > bypassed
> > + * and the currently running period is not guaranteed to be completed
> > */
> >
> > #include
> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
> >
> > struct sun4i_pwm_data {
> > bool has_prescaler_bypass;
> > + bool has_direct_mod_clk_output;
> > unsigned int npwm;
> > };
> >
> > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > + /*
> > + * PWM chapter in H6 manual has a diagram which explains that if
> > bypass
> > + * bit is set, no other setting has any meaning. Even more, experiment
> > + * proved that also enable bit is ignored in this case.
> > + */
> > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> > + sun4i_pwm->data->has_direct_mod_clk_output) {
> > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
> > + state->polarity = PWM_POLARITY_NORMAL;
> > + state->enabled = true;
> > + return;
> > + }
> > +
> > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
> > sun4i_pwm->data->has_prescaler_bypass)
> > prescaler = 1;
> > @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> > static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
> > const struct pwm_state *state,
> > -u32 *dty, u32 *prd, unsigned int *prsclr)
> > +u32 *dty, u32 *prd, unsigned int *prsclr,
> > +bool *bypass)
> > {
> > u64 clk_rate, div = 0;
> > unsigned int pval, prescaler = 0;
> >
> > clk_rate = clk_get_rate(sun4i_pwm->clk);
> >
> > + *bypass = state->enabled &&
> > + (state->period * clk_rate >= NSEC_PER_SEC) &&
> > + (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
> > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
> > +
> > + /* Skip calculation of other parameters if we bypass them */
> > + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output)
> > + return 0;
> > +
>
> Hmm, so if my PWM doesn't support the bypass bit *bypass might still be
> true on return of sun4i_pwm_calculate. It doesn't hurt because the value
> is only used after another check of has_direct_mod_clk_output, but still
> this is a bit confusing.
Ok will change this
>
> > if (sun4i_pwm->data->has_prescaler_bypass) {
> > /* First, test without any prescaler when available */
> > prescaler = PWM_PRESCAL_MASK;
> > @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip,
> > struct pwm_device *pwm,
> > {
> > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
> > struct pwm_state cstate;
> > - u32 ctrl;
> > + u32 ctrl, period, duty, val;
> > int ret;
> > - unsigned int delay_us;
> > + unsigned int delay_us, prescaler;
> > unsigned long now;
> > + bool bypass;
> >
> > pwm_get_state(pwm, );
> >
> > @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip,
> > struct pwm_device *pwm,
> > spin_lock(_pwm->ctrl_lock);
> > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > - if ((cstate.period != state->period) ||
> > - (cstate.duty_cycle != state->duty_cycle)) {
> > - u32 period, duty, val;
> > - unsigned int prescaler;n write the register and return
But
> > + ret = sun4i_pwm_calculate(sun4i_pwm, state, , ,
> > ,
> > + );
> > + if
[linux-sunxi] Re: [PATCH v7 4/8] pwm: sun4i: Add an optional probe for bus clock
Hi Uwe,
On Thu, 21 Nov 2019 at 08:28, Uwe Kleine-König
wrote:
>
> Hello Clément,
>
> On Tue, Nov 19, 2019 at 06:53:15PM +0100, Clément Péron wrote:
> > + /*
> > + * We're keeping the bus clock on for the sake of simplicity.
> > + * Actually it only needs to be on for hardware register accesses.
> > + */
> > + ret = clk_prepare_enable(pwm->bus_clk);
> > + if (ret) {
> > + dev_err(>dev, "Cannot prepare and enable bus_clk\n");
>
> Maybe add the error code to the message?
Ok I will change it for the reset control deassert if you agree.
Clement
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K. | Uwe Kleine-König|
> Industrial Linux Solutions | https://www.pengutronix.de/ |
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[linux-sunxi] Re: [PATCH 1/3] arm64: dts: allwinner: H6: Add PMU mode
On Thu, 21 Nov 2019 08:22:30 +0100
Maxime Ripard wrote:
Hi,
> On Thu, Nov 21, 2019 at 01:18:33AM +, Andre Przywara wrote:
> > Add the Performance Monitoring Unit (PMU) device tree node to the H6
> > .dtsi, which tells DT users which interrupts are triggered by PMU
> > overflow events on each core. The numbers come from the manual and have
> > been checked in U-Boot and with perf in Linux.
> >
> > Tested with perf record and taskset on a Pine H64.
> >
> > Signed-off-by: Andre Przywara
>
> Queued all three patches for 5.6, thanks for taking the time to do
> this.
>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 29824081b43b..86a77b1734e0 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -70,6 +70,16 @@
> > clock-output-names = "ext_osc32k";
> > };
> >
> > +pmu {
>
> This was indented with spaces however, unlike the rest of the DT. I've
> fixed it while applying.
Shoot, thinks for fixing this up, also for queuing it!
Cheers,
Andre.
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