Hi Siarhei,
I'm aware this driver is used by A13 and A10. Indeed, I did test this patch
in A13 and the bit is set to 1, despite the fact that apparently is not be
used. But I did not test SPI communication on A13 with max11043.
Em sábado, 11 de fevereiro de 2017 00:33:14 UTC-3, Siarhei
In order to work appropriately, the max11043 ADC chip and probably
others, needs SPI master samples the data at the correct edge. From
max11043 datasheet: "The data at DIN is latched on the rising edge
of SCLK". Same to DOUT.
This patch add Master Sample Data Mode bit in normal sample mode.
It
On Sat, 11 Feb 2017 00:05:42 -0300
Vinicius Maciel wrote:
> Em 10 de fev de 2017 23:53, "Siarhei Siamashka"
> escreveu:
>
> > On Fri, 10 Feb 2017 19:02:47 -0300
> > Vinicius Maciel wrote:
> >
> > > In order to work
Hi Siarhei,
I was really aiming only A20 in this patch.
Em 10 de fev de 2017 23:53, "Siarhei Siamashka"
escreveu:
> On Fri, 10 Feb 2017 19:02:47 -0300
> Vinicius Maciel wrote:
>
> > In order to work appropriately, the max11043 ADC chip and
On Fri, 10 Feb 2017 19:02:47 -0300
Vinicius Maciel wrote:
> In order to work appropriately, the max11043 ADC chip and probably
> others, needs SPI master samples the data at the correct edge. From
> max11043 datasheet: "The data at DIN is latched on the rising edge
> of
In order to work appropriately, the max11043 ADC chip and probably
others, needs SPI master samples the data at the correct edge. From
max11043 datasheet: "The data at DIN is latched on the rising edge
of SCLK". Same to DOUT.
This patch add Master Sample Data Mode bit in normal sample mode.
On Fri, Feb 10, 2017 at 08:33:37PM +1100, Jonathan Liu wrote:
> The A20-OLinuXino-Micro has 3.5 mm sockets for headphone output and
> microphone input.
>
> Signed-off-by: Jonathan Liu
Queued for 4.12. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel
On Fri, Feb 10, 2017 at 11:42:34AM +0800, Chen-Yu Tsai wrote:
> The GR8, like other sun5i SoCs, has only 1 pin option for PWM0 output.
> Other SoCs had named the pingroup "pwm0_pins" in their dtsi files, while
> GR8 named it "pwm0_pins_a". When we switched to the new common sun5i
> dtsi file, we
Some body have experience with LVDS Allwinner A20 SoC and the kernel
4.10-rc5 ?
My LVDS connexion works fine because I display correctly the console under
uboot (I work with CONFIG_VIDEO_LCD_MODE)
I use the wiki : http://linux-sunxi.org/LCD to convert fex to
CONFIG_VIDEO_LCD_MODE for the
Hi,
Just to say LEDE has released an -rc2 candidate for sunxi boards:
https://downloads.lede-project.org/releases/17.01.0-rc2/targets/sunxi/generic/
If you have some devices in the list, please test and report issues.
Best,
--
Benjamin Henrion
FFII Brussels - +32-484-566109 - +32-2-3500762
On Fri, Feb 10, 2017 at 4:32 PM, Icenowy Zheng wrote:
>
> 2017年2月10日 16:07于 Maxime Ripard 写道:
>>
>> On Wed, Feb 08, 2017 at 07:08:46PM +0800, Icenowy Zheng wrote:
>> > 08.02.2017, 18:15, "Maxime Ripard" :
>> > >
The A20-OLinuXino-Micro has 3.5 mm sockets for headphone output and
microphone input.
Signed-off-by: Jonathan Liu
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
On Wed, Feb 08, 2017 at 08:44:44PM +0100, Jelle van der Waa wrote:
> add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
> board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram.
>
> Signed-off-by: Jelle van der Waa
Queued for 4.12.
Thanks!
Hi,
On Wed, Feb 08, 2017 at 07:41:55PM +0300, Волков Сергей wrote:
> Hello all,
>
> >> This patch not introduce new features, just prepare code for
> >> adding sun6i PWM driver in next commits.
> >>
> >> A31 SoC have a different map of PWM registers than others ASoCs,
> >> but register bits
On Wed, Feb 08, 2017 at 07:08:46PM +0800, Icenowy Zheng wrote:
> 08.02.2017, 18:15, "Maxime Ripard" :
> > On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote:
> >> Allwinner A64 SoC has a R_PIO node like the one in H3.
> >>
> >> Add the node as well as
On Tue, Feb 07, 2017 at 09:36:35PM +0800, Icenowy Zheng wrote:
> >> >> @@ -51,7 +64,8 @@ static u8 sunxi_sid_read_byte(const struct
> >> sunxi_sid *sid,
> >> >> {
> >> >> u32 sid_key;
> >> >>
> >> >> - sid_key = ioread32be(sid->base + round_down(offset, 4));
> >> >> + sid_key
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