On 1/6/21 7:11 PM, André Przywara wrote:
> On 05/01/2021 22:36, Jaehoon Chung wrote:
>
> Hi,
>
> thanks for having a look!
>
>> Hi Jernej
>>
>> On 1/3/21 6:26 PM, Jernej Skrabec wrote:
>>> This PMIC can be found on H616 boards and it's very similar to AXP805
>>> and AXP806.
>>
>> Is there any
Dne sreda, 06. januar 2021 ob 10:24:35 CET je Andre Przywara napisal(a):
> Hi,
>
> a small update fixing the strncpy bug and addressing too long DT names
> properly. Thanks to Samuel for pointing this out.
> ==
>
> So far creating a bootable SPL image for Allwinner based boards
Dne sreda, 06. januar 2021 ob 21:46:30 CET je Jernej Skrabec napisal(a):
> From: Roman Stratiienko
>
> To set blending channel order register software needs to know state and
> position of each channel, which impossible at plane commit stage.
>
> Move this procedure to atomic_flush stage, where
From: Roman Stratiienko
To set blending channel order register software needs to know state and
position of each channel, which impossible at plane commit stage.
Move this procedure to atomic_flush stage, where all necessary information
is available.
Fixes: f88c5ee77496 ("drm/sun4i: Implement
On Sun, Jan 3, 2021 at 11:00 AM Samuel Holland wrote:
> As there is an RSB controller in the H6 SoC, there should be some pin
> configuration for it. While no such configuration is documented, the
> "s_i2c" pins are suspiciously on the "alternate" function 3, with no
> primary function 2 given.
Deinterlace core is completely compatible to H3.
Add a node for it.
Signed-off-by: Jernej Skrabec
---
Note: I didn't add H5 fallback, since the only reason why this node
is not in common H3/H5 dtsi is that it's located on different addresses.
If anyone feel fallback compatible is needed, I'll
R40 contains deinterlace core compatible to that in H3. One peculiarity
is that RAM gate is shared with CSI1. User manual states it's separate
but that's not true. Shared gate was verified with BSP Linux code check
and with runtime tests (CPU crashed if CSI1 gate was not ungated).
Signed-off-by:
These two patches add support for deinterlace core found on R40. It's
compatible to H3 one, so only DT node is needed.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (2):
dt-bindings: media: Add Allwinner R40 deinterlace compatible
ARM: dts: sun8i: r40: Add deinterlace node
Allwinner R40 SoC also contains deinterlace core, compatible to H3.
Add compatible string for it.
Signed-off-by: Jernej Skrabec
---
.../bindings/media/allwinner,sun8i-h3-deinterlace.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
This commit adds support for Tanix TX6 TV box, based on H6. It's low end
H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
peripherals.
DT file is taken from Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/Makefile| 3 +-
Updated H6 DT files are based on Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 70 +++-
arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 117 ++
arch/arm/dts/sun50i-h6-orangepi-lite2.dts| 71 +++-
This series introduces Tanix TX6 TV box support based on Allwinner H6
SoC. First patch syncs H6 DT files from Linux 5.11-rc1 release and
second one adds support for Tanix TX6 board.
Please take a look.
Best regards,
Jernej
Changes from v2:
- added OrangePi One Plus DT update in patch 1
-
On Wed, Jan 06, 2021 at 02:32:46PM +, Andre Przywara wrote:
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use
On Thu, Dec 24, 2020 at 10:41:38AM +0800, Icenowy Zheng wrote:
> As the original PineTab DT (which uses sun50i-a64-pinetab name) is only
> for development samples, document this.
>
> Signed-off-by: Icenowy Zheng
Applied all three patches, thanks for your persistence on this
Maxime
--
You
Dne sreda, 06. januar 2021 ob 16:51:09 CET je André Przywara napisal(a):
> On 03/01/2021 10:00, Jernej Skrabec wrote:
> > This commit adds support for Tanix TX6 TV box, based on H6. It's low end
> > H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
> > peripherals.
> >
> > DT
Dne sreda, 06. januar 2021 ob 16:41:02 CET je André Przywara napisal(a):
> On 03/01/2021 10:00, Jernej Skrabec wrote:
> > Updated H6 DT files are based on Linux 5.11-rc1 release.
> >
> > Signed-off-by: Jernej Skrabec
>
> That looks alright, but it seems like the OrangePi One Plus .dts is not
>
On 06/01/2021 15:53, Chen-Yu Tsai wrote:
Hi,
> On Wed, Jan 6, 2021 at 11:05 PM Andre Przywara wrote:
>>
>> The Pine64-LTS board features a blue status LED on pin PL7.
>
> I'd like some clarification about this.
>
> My Pine64-LTS was a used unit personally given to me by TL Lim, which came
>
On Wed, Jan 6, 2021 at 10:33 PM Andre Przywara wrote:
>
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the
On Wed, Jan 6, 2021 at 11:06 PM Andre Przywara wrote:
>
> The H6 manual explicitly lists a frequency limit of 150 MHz for the bus
> frequency of the MMC controllers. So far we had no explicit limits in the
> DT, which limited eMMC to a rather conservative 52 MHz.
I'd say this is implementation
On Wed, Jan 06, 2021 at 03:05:20PM +, Andre Przywara wrote:
> The Pine64-LTS board features a blue status LED on pin PL7.
>
> Describe it in the DT.
>
> Signed-off-by: Andre Przywara
> ---
> .../boot/dts/allwinner/sun50i-a64-pine64-lts.dts | 11 +++
> 1 file changed, 11
On Wed, Jan 6, 2021 at 11:06 PM Andre Przywara wrote:
>
> The eMMC modules offered for the Pine64 boards are capable of the HS200
> eMMC speed mode, when observing the frequency limit of 150 MHz.
>
> Enable that in the DT.
>
> This increases the interface speed from ~80 MB/s to ~120 MB/s.
>
>
On Wed, Jan 6, 2021 at 11:06 PM Andre Przywara wrote:
>
> The eMMC modules offered for the Pine64 boards are capable of the HS200
> eMMC speed mode, when observing the frequency limit of 150 MHz.
>
> Enable that in the DT.
>
> This increases the interface speed from ~80 MB/s to ~120 MB/s.
>
>
On Wed, Jan 6, 2021 at 11:06 PM Andre Przywara wrote:
>
> In contrast to the H6 (and later) manuals, the A64 datasheet does not
> specify any limitations in the maximum possible frequency for eMMC
> controllers.
> However experimentation has found that a 150 MHz limit similar to other
> SoCs and
On Wed, Jan 6, 2021 at 11:05 PM Andre Przywara wrote:
>
> The SD card on the SoPine SoM module is somewhat concealed, so was
> originally defined as "non-removable".
> However there is a working card-detect pin, and in certain SoM base
> boards it might be actually accessible at runtime.
> Also
Hi,
On Wed, Jan 6, 2021 at 11:05 PM Andre Przywara wrote:
>
> In recent Allwinner SoCs the first USB host controller (HCI0) shares
> the first PHY with the MUSB controller. Probably to make this sharing
> work, we were avoiding to declare this in the DT. This has two
> shortcomings:
> - U-Boot
Hi,
On Wed, Jan 6, 2021 at 11:05 PM Andre Przywara wrote:
>
> The Pine64-LTS board features a blue status LED on pin PL7.
I'd like some clarification about this.
My Pine64-LTS was a used unit personally given to me by TL Lim, which came
with LEDs that I assume were soldered on by hand as their
On 03/01/2021 10:00, Jernej Skrabec wrote:
> This commit adds support for Tanix TX6 TV box, based on H6. It's low end
> H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
> peripherals.
>
> DT file is taken from Linux 5.11-rc1 release.
>
> Signed-off-by: Jernej Skrabec
> ---
>
On 03/01/2021 10:00, Jernej Skrabec wrote:
> Updated H6 DT files are based on Linux 5.11-rc1 release.
>
> Signed-off-by: Jernej Skrabec
That looks alright, but it seems like the OrangePi One Plus .dts is not
updated?
Cheers,
Andre
> ---
> arch/arm/dts/sun50i-h6-beelink-gs1.dts| 70 +++-
The eMMC modules offered for the Pine64 boards are capable of the HS200
eMMC speed mode, when observing the frequency limit of 150 MHz.
Enable that in the DT.
This increases the interface speed from ~80 MB/s to ~120 MB/s.
Signed-off-by: Andre Przywara
---
The eMMC modules offered for the Pine64 boards are capable of the HS200
eMMC speed mode, when observing the frequency limit of 150 MHz.
Enable that in the DT.
This increases the interface speed from ~80 MB/s to ~120 MB/s.
Signed-off-by: Andre Przywara
---
In contrast to the H6 (and later) manuals, the A64 datasheet does not
specify any limitations in the maximum possible frequency for eMMC
controllers.
However experimentation has found that a 150 MHz limit similar to other
SoCs and also the MMC0 and MMC1 controllers on the A64 seems to exist
for
The H6 manual explicitly lists a frequency limit of 150 MHz for the bus
frequency of the MMC controllers. So far we had no explicit limits in the
DT, which limited eMMC to a rather conservative 52 MHz.
Put those maximum frequencies in the SoC .dtsi, to allow higher speed
modes (which still would
The SD card on the SoPine SoM module is somewhat concealed, so was
originally defined as "non-removable".
However there is a working card-detect pin, and in certain SoM base
boards it might be actually accessible at runtime.
Also the Pine64-LTS shares the SoPine base .dtsi, so inherited the
The Pine64-LTS board features a blue status LED on pin PL7.
Describe it in the DT.
Signed-off-by: Andre Przywara
---
.../boot/dts/allwinner/sun50i-a64-pine64-lts.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
In recent Allwinner SoCs the first USB host controller (HCI0) shares
the first PHY with the MUSB controller. Probably to make this sharing
work, we were avoiding to declare this in the DT. This has two
shortcomings:
- U-Boot (which uses the same .dts) cannot use this port in host mode
without a
The CEC clock on the H6 SoC is a bit special, since it uses a fixed
pre-dividier for one source clock (the PLL), but conveys the other clock
(32K OSC) directly.
We are using a fixed predivider array for that, but fail to use the right
flag to actually activate that.
Fixes: 524353ea480b ("clk:
On Wed, Jan 6, 2021 at 6:50 PM Maxime Ripard wrote:
>
> Hi!
>
> On Sun, Jan 03, 2021 at 05:06:31AM -0600, Samuel Holland wrote:
> > This series adds system (complete power down) and runtime (clock gate)
> > PM hooks to the RSB controller driver. Tested on A64 and H6.
> >
> > Samuel Holland (4):
>
On Wed, Jan 6, 2021 at 7:06 PM Maxime Ripard wrote:
>
> On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> > On 03/01/2021 10:00, Samuel Holland wrote:
> > > On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> > > PMIC, configure the connection to use the RSB
On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> On 03/01/2021 10:00, Samuel Holland wrote:
> > On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> > PMIC, configure the connection to use the RSB bus rather than the I2C
> > bus. Compared to the I2C controller
On Sun, Jan 03, 2021 at 04:00:03AM -0600, Samuel Holland wrote:
> The Allwinner H6 SoC contains an RSB controller. It is almost completely
> undocumented, so it was missed when doing the initial SoC bringup.
>
> This series adds the clock/reset, pin configuration, and device tree
> node needed to
Hi!
On Sun, Jan 03, 2021 at 05:06:31AM -0600, Samuel Holland wrote:
> This series adds system (complete power down) and runtime (clock gate)
> PM hooks to the RSB controller driver. Tested on A64 and H6.
>
> Samuel Holland (4):
> bus: sunxi-rsb: Move OF match table
> bus: sunxi-rsb: Split
On 05/01/2021 22:36, Jaehoon Chung wrote:
Hi,
thanks for having a look!
> Hi Jernej
>
> On 1/3/21 6:26 PM, Jernej Skrabec wrote:
>> This PMIC can be found on H616 boards and it's very similar to AXP805
>> and AXP806.
>
> Is there any plan to cleanup codes?
There is no support for either of
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> The Ethernet MAC and PHY are usually major consumers of power on boards
> which may not be able to fully power off (that have no PMIC). Powering
> down the MAC and internal PHY saves power while these boards are "off".
>
> Signed-off-by:
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> Adjust the spacing and use an explicit "return 0" in the success path
> to make the function easier to parse.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
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On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> Use the appropriate function instead of reimplementing it,
> and update the error message to match the code.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
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You received this message because you are subscribed to the
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> sun8i_dwmac_unpower_internal_phy already checks if the PHY is powered,
> so there is no need to do it again here.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
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You received this message because you are subscribed to
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> This is a deinitialization function that always returned zero, and that
> return value was always ignored. Have it return void instead.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
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You received this message because
Switch the SPL boot image generation from using mksunxiboot to the new
sunxi_egon format of mkimage.
Verified to create identical results for all 152 Allwinner boards.
Signed-off-by: Andre Przywara
---
scripts/Makefile.spl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
So far we used the separate mksunxiboot tool for generating a bootable
image for Allwinner SPLs, probably just for historical reasons.
Use the mkimage framework to generate a so called eGON image the
Allwinner BROM expects.
The new image type is called "sunxi_egon", to differentiate it
from the
To be able to easily share the Allwinner eGON BROM header structure
between the tools and the SPL code, move the struct definition into a
separate header file.
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/arch-sunxi/spl.h | 65 +
include/sunxi_image.h
Hi,
a small update fixing the strncpy bug and addressing too long DT names
properly. Thanks to Samuel for pointing this out.
==
So far creating a bootable SPL image for Allwinner based boards uses
the mksunxiboot tool. Most other platforms seemed to have integrated this
kind of
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