Use the sunxi gpio driver to configure pins, instead of directly
writing magic numbers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/mmc/sunxi_mmc.c | 56 +++--
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc
Add definitions for pull-up/downs, and several pin functions used
by various drivers, such as gmac, i2c, and mmc.
Also remove any pin functions not currently used by drivers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/gpio.h | 48
group. Macros for UARTs were left
as-is, as one of them is not consecutive. Also pull-ups are only enabled
on the RX pin, leaving RX/TX in the name helps reading the code.
* Fixed sun5i UART1 name.
* Fixed a compile error introduced in v1.
Cheers
ChenYu
Chen-Yu Tsai (6):
ARM: sunxi: Add
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/sunxi_gmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
index b8b9016..7a36581 100644
--- a/drivers/net/sunxi_gmac.c
+++ b/drivers/net/sunxi_gmac.c
@@ -31,7 +31,7
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/sunxi_emac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 0cadf89..5a06d68 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -497,7
The pin definition for uart1 was mis-named as uart0.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4 ++--
arch/arm/include/asm/arch-sunxi/gpio.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
sys_config/a23/ippo-q8h-v5.fex | 844 +
1 file changed, 844 insertions(+)
create mode 100644 sys_config/a23/ippo-q8h-v5.fex
diff --git a/sys_config/a23/ippo-q8h-v5.fex b/sys_config/a23/ippo-q8h-v5.fex
new file
Hi,
On Mon, Mar 24, 2014 at 4:21 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 03/23/2014 04:13 PM, Ian Campbell wrote:
On Sat, 2014-03-22 at 20:22 +0100, Hans de Goede wrote:
One thing that stands out when doing a diff against sunxi-merge-v2014.04-rc2
is this:
---
On Mon, Mar 24, 2014 at 4:39 PM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-03-24 at 12:55 +0800, Chen-Yu Tsai wrote:
Hi,
On Mon, Mar 24, 2014 at 4:21 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 03/23/2014 04:13 PM, Ian Campbell wrote:
On Sat, 2014-03-22 at 20:22
On Fri, Mar 28, 2014 at 5:29 AM, Carlo Caione ca...@caione.org wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 13 +
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 13
Hi,
On Fri, Mar 28, 2014 at 6:16 PM, Hans de Goede hdego...@redhat.com wrote:
Hi All,
Here is a u-boot-sunxi patch series adding initial sun6i support, it is
based on Maxime's bring up work for sun6i, to which I've added mmc support.
Note that this makes some changes to how we handle the
Hi Hans,
On Sun, Mar 30, 2014 at 8:04 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
After wens pointed me to:
http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;h=9275ca21ac99592c7d520a41c0914b359c27b913;hb=refs/heads/lichee/jb-4.2.2-a31
I've tried
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The Bluetooth
part is a BCM20710 device connected to UART2 in the A20 SoC.
The IC requires a 32.768 KHz low power clock input for proper
auto-detection of the main clock, and an enable signal via GPIO.
Signed-off-by: Chen-Yu Tsai w
rfkill-gpio has clk_enabled = blocked, which is true when rfkill
blocks the device. This results in calling clock enable/disable at
the wrong time. Reversing the value fixes this.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
net/rfkill/rfkill-gpio.c | 2 +-
1 file changed, 1 insertion(+), 1
Some devices, such as Broadcom Bluetooth devices, require a specific
clock rate for the clock tied to the rfkill device. Add a clock-frequency
property so we can specify this from the device tree.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/rfkill/rfkill
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/rfkill/rfkill-gpio.txt | 24 ++
net/rfkill/rfkill-gpio.c | 23 +
2 files changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings
This patch provides of_get_gpiod_flags_by_name(), which looks up GPIO
phandles by name only, through gpios/gpio-names, and not by index.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/gpio/gpiolib-of.c | 48 +++
include/linux/of_gpio.h | 3
to everyone who gave reviews and suggestions.
Changes since RFC:
- Dropped gpio name buffer fix patch (not needed after cleanup patches)
- New gpios/gpio-names support for device trees
- Simplify device tree bindings due to name cleanup and gpio-names
support
Cheers
ChenYu
Chen-Yu
On Mon, Apr 14, 2014 at 11:15 PM, Hans de Goede hdego...@redhat.com wrote:
Hi Arend,
On 04/11/2014 12:31 PM, Arend van Spriel wrote:
Hi Hans,
I have put some effort in adding device tree support in brcmfmac.
Unfortunately, I had no luck getting MMC up and running on pandaboard
extension
Hi Hans,
On Mon, Apr 14, 2014 at 11:23 PM, Hans de Goede hdego...@redhat.com wrote:
Hi All,
I've just updated:
https://github.com/linux-sunxi/linux-sunxi/commits/sunxi-devel
to 3.15-rc1
This means that a whole lot of patches have been dropped as they have all
been merged, hurray! The big
On Tue, Apr 15, 2014 at 10:42 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Apr 15, 2014 at 02:41:41PM +0800, Chen-Yu Tsai wrote:
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The Bluetooth
part is a BCM20710 device connected to UART2 in the A20 SoC.
The IC
+0800, Chen-Yu Tsai wrote:
This patch provides of_get_gpiod_flags_by_name(), which looks up GPIO
phandles by name only, through gpios/gpio-names, and not by index.
IIRC, gpios only uses the *-gpios properties, and not gpios/gpio-names
pattern seen on various other things.
Is it some new
Hi,
On Wed, Apr 16, 2014 at 5:44 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
Please try to keep me in CC, even though the ML doesn't make it easy..
Sorry about that.
On Wed, Apr 16, 2014 at 12:06:59AM +0800, Chen-Yu Tsai wrote:
@@ -139,4 +152,16 @@
reg_usb2_vbus
Hi,
On Tue, Apr 15, 2014 at 3:46 AM, Ian Campbell i...@hellion.org.uk wrote:
For clock_get_pll5 just remove it since it is unused.
For clock_get_pll6 introduce the necessary #defines.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock.c | 18
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
fel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/fel.c b/fel.c
index ba4212c..97f265e 100644
--- a/fel.c
+++ b/fel.c
@@ -166,6 +166,7 @@ void aw_fel_get_version(libusb_device_handle *usb)
case 0x1625: soc_name=A13;break;
case
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/p2wi.c| 2 +-
arch/arm/cpu/armv7/sunxi/prcm.c| 14
The original default may have been miscalculated as it was for 624MHz.
The A23 user manual states that PLL6 should be fixed to 600MHz, and
not any other rate.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
1 file changed, 1 insertion(+), 1
anything, as there is nothing to boot at the moment.
Cheers
ChenYu
Chen-Yu Tsai (7):
ARM: sunxi: Fix sun6i PLL6 default to 600MHz
ARM: sunxi: Fix macro names for mmc and uart reset offsets
ARM: sunxi: Correct comment for MBUS1 register in sun6i clock
definitions
ARM: sunxi: Allow
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 88b1d1f..1397b35 100644
--- a/arch
The Ippo-q8h is the first A23 based device spotted in the wild.
This was used to bring basic support to u-boot. Add build options
for it
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
boards.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/boards.cfg b/boards.cfg
index b3a1494..d3a1e50
The R_UART is the only uart other than UART0 on port F which has
usable pads for attaching a console. Support it so we can still
have a console when using MMC on port F.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/cpu/armv7/sunxi
On Sun, Apr 27, 2014 at 11:25 PM, Ian Campbell i...@hellion.org.uk wrote:
On Sat, 2014-04-26 at 20:28 +0200, Marek Vasut wrote:
On Friday, April 18, 2014 at 08:05:50 PM, Ian Campbell wrote:
From: Jens Kuske jensku...@gmail.com
The GMAC module in Allwinner sunxi SoCs seems to have problems
On Mon, Apr 28, 2014 at 2:08 AM, Marek Vasut ma...@denx.de wrote:
On Sunday, April 27, 2014 at 05:29:29 PM, Chen-Yu Tsai wrote:
On Sun, Apr 27, 2014 at 11:25 PM, Ian Campbell i...@hellion.org.uk wrote:
On Sat, 2014-04-26 at 20:28 +0200, Marek Vasut wrote:
On Friday, April 18, 2014 at 08:05
Hi,
On Mon, Apr 28, 2014 at 10:58 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0 clk and
Hi,
On Mon, Apr 28, 2014 at 10:58 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
On Sun, Apr 27, 2014 at 1:54 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 04/24/2014 06:39 PM, Chen-Yu Tsai wrote:
The original default may have been miscalculated as it was for 624MHz.
The A23 user manual states that PLL6 should be fixed to 600MHz, and
not any other rate.
Good
On Tue, Apr 29, 2014 at 1:27 AM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
On 28/04/2014 18:02, Chen-Yu Tsai wrote:
Hi,
On Mon, Apr 28, 2014 at 10:58 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management
On Mon, May 5, 2014 at 12:02 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 02, 2014 at 05:57:29PM +0200, Hans de Goede wrote:
From: Chen-Yu Tsai w...@csie.org
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The WiFi
part is a BCM43362 IC connected to MMC3
Hi,
On Tue, May 6, 2014 at 6:55 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, May 04, 2014 at 04:02:38PM +0200, Carlo Caione wrote:
The so called system controller in Allwinner A20 and A31 SoCs is
multi-purpose controller that tries to add misc functionality to one
memory
On Thu, May 8, 2014 at 11:17 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, May 07, 2014 at 07:25:54PM +0200, Boris BREZILLON wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON
On Sun, May 11, 2014 at 9:48 PM, Zoltan HERPAI wigy...@uid0.hu wrote:
File taken from vendor site, original comments cleaned up.
Signed-off-by: Zoltan HERPAI wigy...@uid0.hu
---
sys_config/a20/linksprite_pcduino3.fex | 1066
1 file changed, 1066
Hi,
On Sun, May 11, 2014 at 4:06 PM, Hans de Goede hdego...@redhat.com wrote:
The sun4i resisitive touchscreen controller also comes with a built-in
temperature sensor. This commit adds support for it.
This commit also introduces a new ts-attached device-tree property,
when this is not set,
Hi,
On Wed, Apr 30, 2014 at 6:54 PM, Александр Берсенев b...@hackerdom.ru wrote:
[PATCH v4 01/03] ARM: sunxi: Add documentation for sunxi consumer infrared
devices
This patch adds documentation for Device-Tree bindings for sunxi IR
controller.
Signed-off-by: Alexander Bersenev
Hi,
On Sat, May 10, 2014 at 8:56 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were
having
a single clock for all the phys.
Hi,
On Tue, May 13, 2014 at 9:09 PM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
Hi,
There is the following page on the cubieboard.org website:
http://cubieboard.org/2014/01/13/upgrade-new-android-for-cubietruckv1-01/
It provides an SD card image, with the following description
Hi,
On Sun, May 18, 2014 at 10:14 PM, Ian Campbell i...@hellion.org.uk wrote:
My cubieboard2 (which uses the designware GMAC driver) doesn't seem to
work with my 100MB netgear hub. From both Linux (3.14.4) and u-boot
IIRC the associated DT and clock drivers were merged in 3.15.
3.14 only had
the driver accesses the correct registers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi,
This patch fixes the pinctrl driver failing to set pinmuxes for the R_PIO
block found on the A31 and A23. The problem was found while working on
bringing up the A23 SoC. The R_UART pins weren't properly muxed when
Hi Benn,
In March you mentioned you may be building A23 development boards.
I am currently working on mainline kernel support for A23 (patches have
been posted), and I'm wondering if you have any more documents that can
help me. I am looking for A23 standard designs (STD PADs) and AXP223
user
On Tue, May 27, 2014 at 4:02 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Mon, May 26, 2014 at 09:47:56AM +0200, Hans de Goede wrote:
From: Chen-Yu Tsai w...@csie.org
The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled
On Tue, May 27, 2014 at 5:09 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/27/2014 10:07 AM, Maxime Ripard wrote:
On Mon, May 26, 2014 at 09:47:57AM +0200, Hans de Goede wrote:
From: Chen-Yu Tsai w...@csie.org
The sunxi pinctrl irq chip driver does not support wakeup at the
moment
On Tue, May 27, 2014 at 10:11 PM, Linus Walleij
linus.wall...@linaro.org wrote:
On Mon, May 26, 2014 at 9:47 AM, Hans de Goede hdego...@redhat.com wrote:
From: Chen-Yu Tsai w...@csie.org
The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled
On Thu, May 22, 2014 at 8:34 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The Allwinner A31 DMA controller is rather simple to describe in the DT. Add
the bindings documentation.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Hi,
On Mon, Jun 9, 2014 at 6:59 PM, LABBE Corentin
clabbe.montj...@gmail.com wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE
On Wed, Jun 11, 2014 at 10:05 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
Is there a DMAEngine implementation for the A20?
Audio drivers will want that.
Emilio (CC-ed) has been working on one, and he pushed out a branch I think.
Depending on how much time it would take to implement the
On Wed, Jun 11, 2014 at 10:23 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
On Wed, Jun 11, 2014 at 10:17 AM, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Jun 11, 2014 at 10:05 PM, jonsm...@gmail.com jonsm...@gmail.com
wrote:
Is there a DMAEngine implementation for the A20?
Audio drivers
On Wed, Jun 11, 2014 at 11:11 PM, Emilio López emi...@elopez.com.ar wrote:
El 11/06/14 11:43, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 10:25 AM, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Jun 11, 2014 at 10:23 PM, jonsm...@gmail.com jonsm...@gmail.com
wrote:
On Wed, Jun 11, 2014
On Thu, Jun 12, 2014 at 10:18 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
Any ideas why the second CPU isn't booting?
root@linaro-developer:/etc# dmesg | grep -i CPU
[0.00] Booting Linux on physical CPU 0x0
[0.00] Initializing cgroup subsys cpuset
[0.00]
On Thu, Jun 12, 2014 at 10:26 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
On Thu, Jun 12, 2014 at 10:20 AM, Chen-Yu Tsai w...@csie.org wrote:
On Thu, Jun 12, 2014 at 10:18 PM, jonsm...@gmail.com jonsm...@gmail.com
wrote:
Any ideas why the second CPU isn't booting?
root@linaro-developer
Hi,
On Sun, Jun 15, 2014 at 10:56 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
I built a spreadsheet and worked out all of the possible divider
combinations for the audio PLL2.
These two from the Allwinner code are the only two useful combinations.
/* FactorN=79, PreDiv=21,
On Tue, Jun 17, 2014 at 9:05 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
On Tue, Jun 17, 2014 at 8:45 AM, Enrico ebut...@gmail.com wrote:
Il giorno martedì 17 giugno 2014 13:34:45 UTC+2, baani@gmail.com ha
scritto:
hi enrico,
are you able to fix the tvin drivers ?? can you pls send
for
the A23, allwinner,sun8i-a23-apb0-gates-clk.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1
PLL1 on sun6i is a factor clock with the N multiplier factor starting
from 1. Set the .n_from_one field in the clock data to match.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b
.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 57 +
2 files changed, 59 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
diff --git a/arch
The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/Kconfig | 8
arch/arm/mach-sunxi/sunxi.c | 10 ++
2 files changed, 18 insertions(+)
diff
The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1
factor in the clock driver, calculates the
rate for PLL6x2, and fixes the comment describing it.
A further patch (to the DT) should add a fixed-factor /2 clock as
the normally used PLL6 output.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 8 +++-
1
the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.
This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sun6i
factor starts from 1 instead of 0.
This patch adds support for PLL1 and all the basic clock gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 +
drivers/clk/sunxi/clk-sunxi.c | 115 ++
2 files changed
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.
This patch adds support for optional divider tables,
so the clock framework will know about the odd values.
Signed-off-by: Chen-Yu Tsai w
The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.
This patch adds optional reset support to the driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt | 1 +
drivers/tty/serial/8250
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the clock driver's config data structures
to define the difference.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free
On Wed, Jun 18, 2014 at 1:45 PM, Code Kipper codekip...@gmail.com wrote:
Hi Jon,
from what I've seen from the code it looks like Allwinner cripples the
functionality of the controllers by hardcoding whether the block is used as
to connect to a I2S device or a PCM device. I've not seen anything
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
sys_config/a31/hummingbird_a31.fex | 963 +
1 file changed, 963 insertions(+)
create mode 100644 sys_config/a31/hummingbird_a31.fex
diff --git a/sys_config/a31/hummingbird_a31.fex
b/sys_config/a31/hummingbird_a31
On Wed, Jun 18, 2014 at 6:16 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Jun 17, 2014 at 10:52:48PM +0800, Chen-Yu Tsai wrote:
The clock control unit on the A23 is similar to the one found on the A31.
The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
On Wed, Jun 18, 2014 at 6:26 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Jun 17, 2014 at 10:52:49PM +0800, Chen-Yu Tsai wrote:
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.
This patch extends
On Wed, Jun 18, 2014 at 8:26 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Jun 17, 2014 at 10:52:54PM +0800, Chen-Yu Tsai wrote:
The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.
Signed-off-by: Chen-Yu
On Thu, Jun 19, 2014 at 5:28 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Thu, Jun 19, 2014 at 12:33:41PM +0800, Chen-Yu Tsai wrote:
On Wed, Jun 18, 2014 at 6:26 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Jun 17, 2014 at 10:52:49PM +0800, Chen-Yu Tsai
has different divisors, and some clock gates are
gone.
This patch adds a compatible with a modified subdevice list for
the A23.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/mfd/sun6i-prcm.txt | 2 +-
drivers/mfd/sun6i-prcm.c
The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/Kconfig | 5 +
arch/arm/mach-sunxi/sunxi.c | 9 +
2 files changed, 14 insertions(+)
diff --git
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 160 +++
1 file changed, 160 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a23
sun6i/sun8i have a UART in the RTC block group, which can be used
as an early console. This is most useful on sun8i as UART0 is muxed
with MMC0, which is not available if we boot from MMC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch
, 1 or 2 camera sensors, USB OTG,
microphone and speaker.
v5 of these board designs has a ESP8089 WiFi chip (not supported)
connected to mmc1. This patch adds very basic support.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts
depends on for DEBUG_SUNXI_R_UART
- Added memory node to sun8i DTSI
Thanks, and sorry for the noise from the previous patches.
Cheers
ChenYu
Chen-Yu Tsai (4):
ARM: sunxi: Introduce Allwinner A23 support
ARM: sunxi: Add earlyprintk support using R_UART (sun6i/sun8i)
ARM: sunxi: Add
On Sun, Jun 22, 2014 at 11:48 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
Why is the channel for TX one less than RX? In the manual both of the
DRQs are 27.
If you looked at the bindings in the patch, you would see that
dma 1 xx
specifies dedicated DMA, which indeed has separate
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1
-based divider clocks
- Added table-based divider axi clock
- Fixed incorrectly squashed fixups
Cheers
ChenYu
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265211.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/259097.html
Chen-Yu Tsai (6
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free
factor starts from 1 instead of 0.
This patch adds support for PLL1 and all the basic clock muxes and gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 ++
drivers/clk/sunxi/clk-sunxi.c | 103 ++
2 files
Now that we have support for sun8i specific clocks in the driver,
add the corresponding clock nodes to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 115 +++
1 file changed, 115 insertions(+)
diff --git a/arch/arm
On Tue, Jun 24, 2014 at 5:59 PM, Chen-Yu Tsai w...@csie.org wrote:
Now that we have support for sun8i specific clocks in the driver,
add the corresponding clock nodes to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 115
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard
://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265211.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/259097.html
Chen-Yu Tsai (6):
clk: sunxi: register clock gates with clkdev
clk: sunxi: move ahb_sdram to protected clock list
clk: sunxi: Support factor clocks
factor starts from 1 instead of 0.
This patch adds support for PLL1 and all the basic clock muxes and gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 ++
drivers/clk/sunxi/clk-sunxi.c
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.
This patch adds support for optional divider tables,
so the clock framework will know about the odd values.
Signed-off-by: Chen-Yu Tsai w
Now that we have support for sun8i specific clocks in the driver,
add the corresponding clock nodes to the DTSI. Also update the
existing peripherals with the correct clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 125
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