Sopine has Winbond SPI flash, so enable the same to use
flash on Sopine board.
Cc: TL Lim
Signed-off-by: Jagan Teki
---
.../dts/sun50i-a64-sopine-baseboard-u-boot.dtsi | 16
configs/sopine_baseboard_defconfig | 7 +++
2 files changed, 23 insertions
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.
Cc: Marek Vasut
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 77 ---
1 file changed, 57 insertions(+), 20 dele
Add reset_valid to check whether given reset is valid
or not.
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
include/reset.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/reset.h b/include/reset.h
index bc495a90c2..65aa7a4ce5 100644
--- a/include/reset.h
+++ b/include
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.
Cc: Marek Vasut
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/usb/musb-new/sunxi.c | 81 ++--
1 file changed, 40 insertions(+), 41 dele
CLK and DM_RESET drivers are now available for most
of the Allwinner platforms, so enable in mach-sunxi/Kconfig
Enabling CLK will select DM_RESET by default.
Signed-off-by: Jagan Teki
---
arch/arm/mach-sunxi/Kconfig | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm
should add as part of ccu_clock_gate.
Signed-off-by: Jagan Teki
---
arch/arm/include/asm/arch-sunxi/ccu.h | 192 +-
drivers/clk/sunxi/clk_a64.c | 40 ++
drivers/clk/sunxi/clk_sunxi.c | 182
3 files changed, 413 insertions
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 9 +
drivers/clk/sunxi/clk_a10s.c | 5 +
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 7 +++
drivers/clk
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_h6.c | 53 ++
3 files changed, 61 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_h6.c
diff
patch from
commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691
Author: Andre Przywara
Date: Mon Oct 29 00:56:47 2018 +
sunxi: A64: Update .dts/.dtsi files
Signed-off-by: Jagan Teki
---
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include
deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig| 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a83t.c | 63
3 files changed, 71 insertions(+)
create
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 7 +++
drivers/clk/sunxi/clk_a64.c | 6 ++
drivers/clk/sunxi/clk_a83t.c | 6 ++
drivers/clk
common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a23.c | 63 +
3 files changed, 71 insertions
deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_v3s.c | 51 +
3 files changed, 59 insertions(+)
create
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_r40.c | 70 +
3 files changed, 78 insertions(+)
create mode
deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a31.c | 68 +
3 files changed, 76 insertions(+)
create
deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig| 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a10s.c | 56
3 files changed, 64 insertions
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/ccu.h | 65
to add code for other parts especially for
MMC since we have migration deadline for BLK, MMC, SCSI.
So, please do let me know if anyone have any inputs.
All these changes available at u-boot-sunxi/clk-next
thanks,
Jagan.
[1] https://patchwork.ozlabs.org/cover/962226/
Jagan Teki (26):
clk
deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a10.c | 59 +
3 files changed, 67 insertions(+)
create
table defined from
CLK driver.
Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/ccu.h | 29 ++
drivers/clk/sunxi/Kc
reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_h3.c | 79 ++
3 files changed, 87 insertions(+)
create
On Wed, Dec 26, 2018 at 4:49 PM Nikolai Zhubr wrote:
>
> And while at it, why not finally add the DT register definitions for
> Allwinner A20 NFC. I'm certainly not the author of these, and they have
> been around for many years already. Its quite unlikely they will
> suddenly change, or vary betw
On Wed, Dec 19, 2018 at 6:32 PM Andre Przywara wrote:
>
> From: "From: Karl Palsson"
>
> Commit a8011eb84dfa("sunxi: board: Print error after power initialization
> fails") moved the DRAM init after the increase of the CPU clock
> frequency. This lead to various DRAM initialisation failures on so
On Wed, Dec 26, 2018 at 4:20 PM Nikolai Zhubr wrote:
>
> Add Hynix H27UBG8T2BTR nand chip identification.
> These chips are sometimes present in e.g. older A20-olinuxino-micro boards.
So the older boards were broken these releases?
--
You received this message because you are subscribed to the
On Sun, Dec 23, 2018 at 11:11 PM Nikolai Zhubr wrote:
>
> Hi all,
>
> Could some kind soul please add this id attached below?
> Maybe even for 2019.01 if possible?
Create it in a patch and send via 'git send-email'
--
You received this message because you are subscribed to the Google Groups
"l
On Fri, Dec 21, 2018 at 6:30 PM Maxime Ripard wrote:
>
> On Thu, Dec 20, 2018 at 06:24:34PM +0530, Jagan Teki wrote:
> > Unfortunately default CSI_SCLK rate cannot work properly to
> > drive the connected sensor interface, particularly on few
> > Allwinner SoC's like
On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
wrote:
>
> On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > Video start delay can be computed by subtracting total vertical
> > timing with front porch timing and with adding 1 delay line for TCON.
> >
> >
: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 89a0deb3fe6a..dd5740bc3fc9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64
for reset pin
- PE17 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 65 +++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64
Add dts node details for Allwinner A64 CSI controller.
A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20
CSI block in Allwinner A64 has similar features as like in H3,
but default mod clock rate in BSP along with latest mainline testing
require to operate it at 300MHz.
So, add A64 CSI compatibe along with mod_rate quirk.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi
clock rate.
Signed-off-by: Jagan Teki
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 34 +++
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index ee
[1] https://patchwork.kernel.org/cover/10705905/
Jagan Teki (6):
dt-bindings: media: sun6i: Add A64 CSI compatible
media: sun6i: Add mod_rate quirk
media: sun6i: Add A64 CSI block support
arm64: dts: allwinner: a64: Add A64 CSI controller
arm64: dts: allwinner: a64: Add pinmux setting for CSI M
Allwinner A64 CSI is a single channel time-multiplexed BT.656
protocol interface.
Add separate compatible string for A64 since it require explicit
change in sun6i_csi driver to update default CSI_SCLK rate.
Reviewed-by: Rob Herring
Signed-off-by: Jagan Teki
---
Documentation/devicetree
On Wed, Dec 19, 2018 at 3:37 PM Maxime Ripard wrote:
>
> On Tue, Dec 18, 2018 at 09:08:17PM +0530, Jagan Teki wrote:
> > On Tue, Dec 18, 2018 at 8:53 PM Maxime Ripard
> > wrote:
> > >
> > > On Tue, Dec 18, 2018 at 05:03:17PM +0530, Jagan Teki wrote:
>
On Wed, Dec 19, 2018 at 3:55 PM Maxime Ripard wrote:
>
> On Tue, Dec 18, 2018 at 08:58:22PM +0530, Jagan Teki wrote:
> > On Tue, Dec 18, 2018 at 8:51 PM Maxime Ripard
> > wrote:
> > >
> > > On Tue, Dec 18, 2018 at 05:03:14PM +0530, Jagan Teki wrote:
> >
On Wed, Dec 19, 2018 at 1:23 PM Priit Laes wrote:
>
> Heya!
>
> I ran into following error when trying to fel-boot
> A20 OLinuxino Lime2 eMMC board with latest u-boot:
>
> [snip]
> U-Boot 2019.01-rc2-5-gbf60dae9dd (Dec 19 2018 - 09:47:08 +0200) Allwinner
> Technology
>
> CPU: Allwinner A20
On Tue, Dec 18, 2018 at 8:53 PM Maxime Ripard wrote:
>
> On Tue, Dec 18, 2018 at 05:03:17PM +0530, Jagan Teki wrote:
> > Unfortunately A64 CSI cannot work with default CSI_SCLK rate.
> >
> > A64 BSP is using 300MHz clock rate as default csi clock,
> > so sun6i_
On Tue, Dec 18, 2018 at 8:51 PM Maxime Ripard wrote:
>
> On Tue, Dec 18, 2018 at 05:03:14PM +0530, Jagan Teki wrote:
> > This series support CSI on Allwinner A64.
> >
> > Tested 640x480, 320x240, 720p, 1080p resolutions UYVY8_2X8 format.
> >
> > Changes for v4
On Tue, Dec 18, 2018 at 6:02 PM Karl Palsson wrote:
>
>
> Jagan Teki wrote:
> > On Tue, Dec 18, 2018 at 4:09 PM wrote:
> > >
> > > From: Karl Palsson
> > >
> > > This reverts commit a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1
>
On Tue, Dec 18, 2018 at 4:09 PM wrote:
>
> From: Karl Palsson
>
> This reverts commit a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1
>
> This causes DRAM init failures on (at least)
> * allwinner h3 nanopi-duo2
> * allwinner h2+ orangepi zero v1.1
>
> Signed-off-by: Karl Palsson
> ---
>
> Ideally, thi
Add compatible string for Allwinner A64 CSI.
A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.
A64 BSP is also operating same rate as default csi clock.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi
: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 89a0deb3fe6a..dd5740bc3fc9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64
for reset pin
- PE17 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 65 +++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64
Unfortunately A64 CSI cannot work with default CSI_SCLK rate.
A64 BSP is using 300MHz clock rate as default csi clock,
so sun6i_csi require explicit change to update CSI_SCLK
rate to 300MHZ for A64 SoC's.
So, set the clk_mod to 300MHz only for A64.
Signed-off-by: Jagan Teki
---
drivers/
Allwinner A64 CSI is a single channel time-multiplexed BT.656
protocol interface.
Add separate compatible string for A64 since it require explicit
change in sun6i_csi driver to update default CSI_SCLK rate.
Reviewed-by: Rob Herring
Signed-off-by: Jagan Teki
---
Documentation/devicetree
mod clock via csi driver
- remove assign clocks from dtsi
- remove i2c-gpio opendrian
- fix avdd and dovdd supplies
- remove vcc-csi pin group supply
Note: This series created on top of H3 changes [1]
[1] https://patchwork.kernel.org/cover/10705905/
Any inputs,
Jagan.
Jagan Teki (6):
dt
Add dts node details for Allwinner A64 CSI controller.
A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20
On Fri, Dec 14, 2018 at 1:25 AM Sean Paul wrote:
>
> On Fri, Dec 14, 2018 at 12:56:03AM +0530, Jagan Teki wrote:
> > On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote:
> > >
> > > On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote:
> > > > Feiyang
On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote:
>
> On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote:
> > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
> >
> > Add panel driver for it.
> >
> > Signed-off-by:
Hi Maxime,
On Tue, Dec 11, 2018 at 10:30 PM Jagan Teki wrote:
>
> On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> wrote:
> >
> > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > > Video start delay can be computed by subtracting total vertical
On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
wrote:
>
> On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > Video start delay can be computed by subtracting total vertical
> > timing with front porch timing and with adding 1 delay line for TCON.
> >
> >
On 11/12/18 10:20 PM, Maxime Ripard wrote:
On Tue, Dec 11, 2018 at 10:05:43PM +0530, Jagan Teki wrote:
On 11/12/18 10:02 PM, Maxime Ripard wrote:
On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by
On 11/12/18 10:04 PM, Maxime Ripard wrote:
On Mon, Dec 10, 2018 at 09:47:29PM +0530, Jagan Teki wrote:
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper
On 11/12/18 10:02 PM, Maxime Ripard wrote:
On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver
On Tue, Dec 11, 2018 at 9:14 PM Maxime Ripard wrote:
>
> On Mon, Dec 10, 2018 at 05:22:43PM +0530, Jagan Teki wrote:
> > The default CSI_SCLK seems unable to drive the sensor to capture
> > the image, so update it to working clock rate 300MHz for A64.
> >
>
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI LCD panel
with inbuilt ST7701 chip.
The default regulator names in ST7701 chip is renamed in Techstar TS8550B
so, add specific binding names for them.
Signed-off-by: Jagan Teki
---
Changes for v5:
- found the chip from vendor, so added
registering mipi_dsi device, but indeed it can extendable
for RGB if any requirement trigger in future.
Signed-off-by: Jagan Teki
---
Changes for v5:
- found the chip from vendor, so added new panel driver
- here is v4: https://patchwork.kernel.org/patch/10680335/
MAINTAINERS
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45
Most of the Allwinner MIPI DSI controllers are supply with
VCC-DSI pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property so-that the required board
can eable it via device tree.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
drivers
;htotal - (mode->hsync_end - mode->hsync_start))
So, update the DSI hblk timing accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
drivers/gpu/drm
ngs->hor_sync_time)
=> timmings->hor_back_porch
=> mode->htotal - mode->hsync_end
So, update the MIPI-DSI hbp value accordingly.
Tested on 2-lane, 4-lane DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 2 +-
1 file changed, 1 insertion(+),
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
1 file
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 5 +
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files chang
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
1 file chang
]/8-(4+4+2);
So, add 10 bytes packet overhead for DSI hblk.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b
*dsi_pixel_bits[format]/8)*vt-(4+dsi_hblk+2);
dsi_vblk = (lane-tmp%lane);
So, update the vblk timing calculation accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 29 +++---
1 file changed, 22
t_porch - x)
* fmt - 16
=> (timmings->hor_total_time - x - timmings->hor_total_time +
timmings->hor_front_porch + x) * fmt - 16
=> timmings->hor_front_porch * fmt - 16
So, update the DSI hfp timing accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Ja
lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-o
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39
essages
- fixed checkpatch warnings/errors
[3] https://patchwork.kernel.org/cover/10680247/
[2] https://patchwork.kernel.org/patch/10657541/
[1] https://patchwork.kernel.org/patch/10657619/
Note: the respetive dts consumer for dsi will send once the panel
driver finalized or in burst mode patch
t;lcd_y
- panel->lcd_y - panel->lcd_vbp
=> timmings->ver_front_porch
So, update the start delay computation accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
dif
Hi Thierry and David,
On Fri, Nov 16, 2018 at 10:10 PM Jagan Teki wrote:
>
> Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
>
> Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> ---
> MAINTAINERS | 6 +
On Fri, Dec 7, 2018 at 6:51 PM Maxime Ripard wrote:
>
> On Tue, Nov 27, 2018 at 04:34:35PM +0530, Jagan Teki wrote:
> > On Tue, Nov 27, 2018 at 3:55 PM Maxime Ripard
> > wrote:
> > >
> > > On Tue, Nov 20, 2018 at 09:55:42PM +0530, Jagan Teki wrote:
> >
: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 89a0deb3fe6a..dd5740bc3fc9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64
- remove i2c-gpio opendrian
- fix avdd and dovdd supplies
- remove vcc-csi pin group supply
Note: This series created on top of H3 changes [1]
[1] https://patchwork.kernel.org/cover/10705905/
Any inputs,
Jagan.
Jagan Teki (6):
dt-bindings: media: sun6i: Add A64 CSI compatible
media: sun6i: Add
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
Add a compatible string for it.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 +
1 file changed, 1 insertion
for reset pin
- PE15 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64-amarula-relic.dts| 53 +++
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
So use separate compatibe to support it.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
1 file changed, 1
The default CSI_SCLK seems unable to drive the sensor to capture
the image, so update it to working clock rate 300MHz for A64.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/media/platform/sunxi
Allwinner A64 CSI controller has similar features as like in
H3, but work by lowering clock than default mod clock.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
On Wed, Nov 21, 2018 at 11:35 PM Priit Laes wrote:
>
> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3" series,
> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
> initial discussion [1], but most Olimex Lime2 boards are still running
> into this bug.
On Sat, Dec 1, 2018 at 11:25 PM Ralph Spitzner wrote:
>
> small patch to enable loading of u-boot from spi-flash on allwinner r40
> boards
> ( Bananapi_M2_Ultra/Berry)
>
> testet on my Berry, now loading linux from scsi :-)
>
>
Please check [1] before sending, patch doesn't have proper inf
On Mon, Dec 3, 2018 at 4:11 PM Chen-Yu Tsai wrote:
>
> On Mon, Dec 3, 2018 at 6:16 PM Jagan Teki wrote:
> >
> > vcc-supply property is need for some Goodix CTP controller like GT5663
> > where 3.3V external pull-up regulator connected via controller VCC pin.
>
&g
GPIO0, GPIO1 can be used as LDO like ldo_io0, ldo_io1 in
AXP803.
So, attach the LDO GPIO pins along with pinctrl properties.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
GT5663 is capacitive touch controller with customized smart wakeup gestures,
the existing goodix driver will work by phandle vcc-supply regulator.
So, document compatible and example node for the same.
Signed-off-by: Jagan Teki
---
.../bindings/input/touchscreen/goodix.txt | 13
vcc-supply property is need for some Goodix CTP controller like GT5663
where 3.3V external pull-up regulator connected via controller VCC pin.
So, enable the regulator for those it attached the vcc-supply.
Signed-off-by: Jagan Teki
---
drivers/input/touchscreen/goodix.c | 39
GT5663 is capacitive touch controller with customized smart wakeup gestures,
the existing goodix driver will work by phandle vcc-supply regulator.
So, add compatible for the same.
Signed-off-by: Jagan Teki
---
drivers/input/touchscreen/goodix.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Add GPIO/pinctrl support for AXP803.
This will reuse the similar compatible to that of AXP813,
since both PMIC GPIO's are same.
Signed-off-by: Jagan Teki
---
drivers/mfd/axp20x.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/axp20x.c b/driver
Add Goodix GT5663 capacitive touch controller node on
Amarula A64-Relic board.
The CTP connected to board with,
- SDA, SCK from i2c1
- GPIO-LD0 as vcc supply
- PH4 gpio as interrupt pin
- PH8 gpio as reset pin
- X and Y axis are inverted
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64
Add GPIO/pinctrl node for AXP803 PMIC.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi
b/arch/arm64/boot/dts/allwinner/axp803.dtsi
index e5eae8bafc42..c6b95980d476
AXP803 PMIC has two GPIO's which is similar to the one in
AXP813 PMIC.
Add a compatible string for it with AXP813 fallback compatible string, in
this case the AXP813 driver can be used.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/gpio/gpio-axp209.txt | 1 +
1 file ch
vcc-supply property is need for some Goodix CTP controller like GT5663
where 3.3V external pull-up regulator connected via controller VCC pin.
So, document the same as optional property.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/input/touchscreen/goodix.txt | 1 +
1 file
On Tue, Nov 27, 2018 at 3:55 PM Maxime Ripard wrote:
>
> On Tue, Nov 20, 2018 at 09:55:42PM +0530, Jagan Teki wrote:
> > On Tue, Nov 20, 2018 at 9:27 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Nov 15, 2018 at 11:19:53PM +0530, Jagan Teki wrote:
>
On 20/11/18 9:55 PM, Jagan Teki wrote:
On Tue, Nov 20, 2018 at 9:27 PM Maxime Ripard wrote:
On Thu, Nov 15, 2018 at 11:19:53PM +0530, Jagan Teki wrote:
On Thu, Nov 15, 2018 at 3:26 PM Maxime Ripard wrote:
Hi,
On Tue, Nov 13, 2018 at 04:46:15PM +0530, Jagan Teki wrote:
The horizontal and
000..683c5c31a9
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
> @@ -0,0 +1,179 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Device Tree Source for Beelink X2
> +//
> +// Copyright (C) 2018 Marcus Cooper
need space, but this doesn't look like
601 - 700 of 1289 matches
Mail list logo
