Hello,
thank you for the review.
On 24.6.2016 04:41, Chen-Yu Tsai wrote:
> On Fri, Jun 24, 2016 at 3:20 AM, wrote:
>> From: Josef Gajdusek
>>
>> Add a node describing the Security ID memory to the Allwinner H3 .dtsi file.
>>
>> Signed-off-by: Josef Gajdusek
On 26.6.2016 13:26, Mark Brown wrote:
> On Sat, Jun 25, 2016 at 05:45:01AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> SY8106A is I2C attached single output voltage regulator
>> made by Silergy.
>
> I'm missing almost all of this series, I've just got this and
On 26.6.2016 13:27, Mark Brown wrote:
> On Sat, Jun 25, 2016 at 05:45:02AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> This patch adds the binding documentation for the
>> sy8106a regulator driver.
>
> Please submit patches using subject lines reflecting the
Hello,
comments below.
On 24.6.2016 05:48, Chen-Yu Tsai wrote:
> On Fri, Jun 24, 2016 at 3:20 AM, wrote:
>> From: Ondrej Jirman
>>
>> Add label to the first cpu so that it can be referenced
>> from derived dts files.
>>
>> Signed-off-by: Ondrej Jirman
On 24.6.2016 05:09, Chen-Yu Tsai wrote:
>> +static int sun8i_ths_h3_init(struct platform_device *pdev,
>> +struct sun8i_ths_data *data)
>> +{
>> + int ret;
>> + size_t callen;
>> + s32 *caldata;
>> +
>> + data->busclk = devm_clk_get(>dev, "ahb");
OR_WM8994) += wm8994-regulator.o
>> -
>> +obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
>
> Follow the existing ordering in the Makefile.
>
>>
>> ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
>> diff --git a/drivers/regulator/sy8106a-regulator.
On 25.6.2016 02:54, Chen-Yu Tsai wrote:
> On Sat, Jun 25, 2016 at 8:35 AM, Ondřej Jirman <meg...@megous.com> wrote:
>> On 24.6.2016 05:09, Chen-Yu Tsai wrote:
>>>> +static int sun8i_ths_h3_init(struct platform_device *pdev,
>>>> +
Hi Julian,
thank you for the review. You're right. I added the pinctrl client
nodes. Also the patches were split incorrectly, so I fixed that too.
regards,
Ondrej
On 24.6.2016 04:51, Julian Calaby wrote:
> Hi Ondrej,
>
> On Fri, Jun 24, 2016 at 5:21 AM, wrote:
>> From:
On 25.6.2016 09:02, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <meg...@megous.com> wrote:
>>> Hello,
>>>
>>> comments below.
>>>
>>> On 24.6.2016
On 25.6.2016 09:10, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 05:44:59AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman <meg...@megous.com>
>>
>> This patch adds support for the sun8i thermal sensor on
>> Allwinner H3 SoC.
>>
>> Si
Hi Maxime,
I try to base everything on the torvalds's kernel.
I did notice the patches. Is there some main git tree/branch where this
work is tracked in? I'd gladly use it.
Also there's a PLL1 rate application patch, that would need to be ported
to the new CCU code, in the case I would use it
Hi Maxime,
I don't have your sunxi-ng clock patches in my mailbox, so I'm replying
to this.
On 26.7.2016 08:32, Maxime Ripard wrote:
> On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
>>>>> If so, then yes, trying to switch to the 24MHz oscillator before
>>
Hello Michal,
On 30.6.2016 13:13, Michal Suchanek wrote:
> Hello,
>
> On 25 June 2016 at 05:45, wrote:
>> From: Ondrej Jirman
>>
>> Use Xulong Orange Pi One GPIO based regulator for
>> passive cooling and thermal management.
>>
>> Signed-off-by: Ondrej
On 28.7.2016 23:00, Maxime Ripard wrote:
> Hi Ondrej,
>
> On Thu, Jul 28, 2016 at 01:27:05PM +0200, Ondřej Jirman wrote:
>> Hi Maxime,
>>
>> I don't have your sunxi-ng clock patches in my mailbox, so I'm replying
>> to this.
>
> You can find it
On 26.7.2016 08:32, Maxime Ripard wrote:
> On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
>>>>> If so, then yes, trying to switch to the 24MHz oscillator before
>>>>> applying the factors, and then switching back when the PLL is stable
>>>
Hi,
On 31.7.2016 12:31, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jul 29, 2016 at 12:01:09AM +0200, Ondřej Jirman wrote:
>> On 28.7.2016 23:00, Maxime Ripard wrote:
>>> Hi Ondrej,
>>>
>>> On Thu, Jul 28, 2016 at 01:27:05PM +0200, Ondřej Jirman wrote:
&
On 21.7.2016 11:48, Maxime Ripard wrote:
> On Fri, Jul 15, 2016 at 12:38:54PM +0200, Ondřej Jirman wrote:
>> On 15.7.2016 10:53, Maxime Ripard wrote:
>>> On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
>>>>>> /**
>>>>>>
On 25.6.2016 09:02, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <meg...@megous.com> wrote:
>>> Hello,
>>>
>>> comments below.
>>>
>>> On 24.6.20
On 15.7.2016 10:53, Maxime Ripard wrote:
> On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
>>>> /**
>>>> + * sun8i_h3_apply_pll1_factors() - applies n, k, m, p factors to the
>>>> + * register using an algorithm that tries to reserve the PLL
On 15.7.2016 15:27, Jean-Francois Moine wrote:
> On Fri, 15 Jul 2016 12:38:54 +0200
> Ondřej Jirman <meg...@megous.com> wrote:
>
>>> If so, then yes, trying to switch to the 24MHz oscillator before
>>> applying the factors, and then switching back when the
On 15.7.2016 16:22, Michal Suchanek wrote:
> Hello,
>
> On 15 July 2016 at 15:48, Ondřej Jirman <meg...@megous.com> wrote:
>>
>>
>> On 15.7.2016 15:27, Jean-Francois Moine wrote:
>>> On Fri, 15 Jul 2016 12:38:54 +0200
>>> Ondřej Jirman <meg..
Hi,
if anyone wants to play with the OTG port support on Orange Pi PC, you
can try these patches:
https://files.megous.com/orange-pi-dvfs/linux-4.7-OrangePI/usb-otg/
I don't have much time to test it extensively, but it seems to work.
I'm not yet submitting them "formally". This is just a
On 27.6.2016 16:54, Mark Brown wrote:
> On Sun, Jun 26, 2016 at 05:07:16PM +0200, Ondřej Jirman wrote:
>> On 26.6.2016 13:26, Mark Brown wrote:
>
>>> I'm missing almost all of this series, I've just got this and another
>>> patch which look like a standalone
On 28.6.2016 17:37, Jean-Francois Moine wrote:
> Most of the clocks in the Allwinner's SoCs are configured in the CCU
> (Clock Configuration Unit).
>
> The PLL clocks are driven from the main clock. Their rates are controlled
> by a set of multiply and divide factors, named from the Allwinner's
>
Hi,
hopefuly, it was the NPE that I fixed. It was specifically in the H3 usb
phy code path for phy0. So I believe it was untested,
because I didn't find any dts file that would use phy0.
Good luck with the audio driver.
regards,
o.
On 30.6.2016 07:17, boob...@gmail.com wrote:
> Nice work.
Hello,
On 30.6.2016 13:13, Michal Suchanek wrote:
> Hello,
>
> On 25 June 2016 at 05:45, wrote:
>> From: Ondrej Jirman
>>
>> Use Xulong Orange Pi One GPIO based regulator for
>> passive cooling and thermal management.
>>
>> Signed-off-by: Ondrej Jirman
On 30.6.2016 17:50, Michal Suchanek wrote:
> On 30 June 2016 at 17:16, Michal Suchanek <hramr...@gmail.com> wrote:
>> On 30 June 2016 at 16:19, Ondřej Jirman <meg...@megous.com> wrote:
>>> Hello,
>>>
>>> On 30.6.2016 13:13, Michal Suchanek wrote
On 30.6.2016 17:16, Michal Suchanek wrote:
> On 30 June 2016 at 16:19, Ondřej Jirman <meg...@megous.com> wrote:
>> Hello,
>>
>> On 30.6.2016 13:13, Michal Suchanek wrote:
>>> Hello,
>>>
>>> On 25 June 2016 at 05:45, <meg...@megou
On 30.6.2016 20:21, Michal Suchanek wrote:
> On 30 June 2016 at 20:06, Michal Suchanek <hramr...@gmail.com> wrote:
>> Hello,
>>
>> On 30 June 2016 at 16:44, Ondřej Jirman <m...@xff.cz> wrote:
>>> Hi,
>>>
>>> hopefuly, it was the NPE that
On 30.6.2016 22:40, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 25, 2016 at 05:45:03AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> PLL1 on H3 requires special factors application algorithm,
>> when the rate is changed. This algorithm was extracted
>> from the
On 30.6.2016 16:23, Siarhei Siamashka wrote:
> On Thu, 30 Jun 2016 13:13:48 +0200
> Michal Suchanek wrote:
>
>> Hello,
>>
>> On 25 June 2016 at 05:45, wrote:
>>> From: Ondrej Jirman
>>>
>>> Use Xulong Orange Pi One GPIO based
Hi,
On 30.6.2016 22:40, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 25, 2016 at 05:45:03AM +0200, meg...@megous.com wrote:
>> From: Ondrej Jirman
>>
>> PLL1 on H3 requires special factors application algorithm,
>> when the rate is changed. This algorithm was extracted
>> from
On 1.7.2016 07:37, Jean-Francois Moine wrote:
> On Fri, 1 Jul 2016 02:50:57 +0200
> Ondřej Jirman <meg...@megous.com> wrote:
>
>>> Since this is really specific, I guess you could simply make the
>>> clk_ops for the nkmp clocks public, and just re-implement set_r
On 29.6.2016 22:45, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 25, 2016 at 04:50:24PM +0200, Ondřej Jirman wrote:
>> On 25.6.2016 09:02, Maxime Ripard wrote:
>>> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>>>> On Sat, Jun 25, 2016 at 6:51
On 1.7.2016 13:19, Michal Suchanek wrote:
> On 1 July 2016 at 13:02, Michal Suchanek <hramr...@gmail.com> wrote:
>> On 30 June 2016 at 22:30, Ondřej Jirman <m...@xff.cz> wrote:
>>> On 30.6.2016 20:21, Michal Suchanek wrote:
>>>> On 30 June 2016 at
Dne 16.1.2017 v 20:14 Icenowy Zheng napsal(a):
> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> controller.
>
> The original driver wired it to OHCI/EHCI controller; however, as the
> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> unusable.
>
> Rename
Dne 18.1.2017 v 17:56 Maxime Ripard napsal(a):
>>> What's your current plan to fix that? I guess the easiest (and most
>>> likely to be reusable) would be to allow for clock tables, instead of
>>> using the generic approach. We might have some other clocks (like
>>> audio or video) that would need
Hi Maxime,
Dne 16.1.2017 v 17:43 Maxime Ripard napsal(a):
>> It does lock up quickly with mainline ccu_nkmp_find_best algorithm
>> for finding factors.
>>
>> Even with linux kernel, it breaks. It's just more difficult to hit the
>> right conditions. I got oops only right after boot when running
Hi,
I think you may be hitting this issue:
https://lkml.org/lkml/2016/8/26/150
regards,
Ondrej
Dne 27.8.2016 v 00:07 Paulo Costa napsal(a):
> Hello, folks.
>
> It's my first time working with this, please let me know if this isn't
> the right mailing list or not the right way to ask for
Dne 22.10.2016 v 15:28 Jean-Francois Moine napsal(a):
> This patchset series adds HDMI audio and video support to the Allwinner
> sun8i SoCs which include the display engine 2 (DE2).
Hi,
I've tested your patches on top of my 4.9-rc1 changes on Orange Pi PC,
and HDMI display output works well --
Dne 24.10.2016 v 05:59 Icenowy Zheng napsal(a):
> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
> The code that poke some unknown bit of PMU for H3/A64 didn't check
> the PHY, and will cause kernel oops when PHY 0 is used.
>
> Fixes: b3e0d141ca9f (phy: sun4i: add support
Dne 21.11.2016 v 19:14 Jean-Francois Moine napsal(a):
> On Mon, 21 Nov 2016 01:54:53 +0100
> Ondřej Jirman <meg...@megous.com> wrote:
>
>> Dne 20.11.2016 v 12:32 Jean-Francois Moine napsal(a):
>>> This patchset series adds HDMI video support to the Allwinne
Dne 25.11.2016 v 06:27 Icenowy Zheng napsal(a):
>
>
> 20.11.2016, 20:07, "Jean-Francois Moine" :
>> Signed-off-by: Jean-Francois Moine
>> ---
>> arch/arm/boot/dts/sun8i-h3.dtsi | 51
>> +
>> 1 file changed, 51
Dne 20.11.2016 v 12:32 Jean-Francois Moine napsal(a):
> This patchset series adds HDMI video support to the Allwinner
> sun8i SoCs which include the display engine 2 (DE2).
> The driver contains the code for the A83T and H3, but it could be
> used/extended for other SoCs as the A64, H2 and H5.
Dne 1.11.2016 v 00:55 Rune Petersen napsal(a):
> On 25/10/16 16:36, Olliver Schinagl wrote:
>> Hey all,
>>
>> as some of you are probably aware, some users occasionally experience
>> some
>> instability using the mainline components. I specifically only want to
>> focus on
>> mainline, as with the
Maxime,
Dne 25.11.2016 v 01:28 meg...@megous.com napsal(a):
> From: Ondrej Jirman
>
> When adjusting PLL_CPUX on H3, the PLL is temporarily driven
> too high, and the system becomes unstable (oopses or hangs).
>
> Add a notifier to avoid this situation by temporarily
Dne 9.1.2017 v 10:59 Maxime Ripard napsal(a):
> On Sat, Jan 07, 2017 at 04:49:18PM +0100, Ondřej Jirman wrote:
>> Maxime,
>>
>> Dne 25.11.2016 v 01:28 meg...@megous.com napsal(a):
>>> From: Ondrej Jirman <meg...@megous.com>
>>>
>>> When a
Hi Icenowy,
when I was trying to add OTG support I found an issue with powercycling.
When I have USB cable connecting PC and the OTG port on the SBC, when
the board enables the vbus, it would become impossible to power cycle
the board after poweroff. The reason being that when vbus is enabled,
On Mon, Jun 24, 2019 at 10:29:27AM -0700, David Miller wrote:
> From: meg...@megous.com
> Date: Thu, 20 Jun 2019 15:47:42 +0200
>
> > From: Ondrej Jirman
> >
> > This series implements support for Xunlong Orange Pi 3 board.
> >
> > - ethernet support (patches 1-3)
> > - HDMI support (patches
On Mon, Jun 24, 2019 at 01:24:56PM -0700, David Miller wrote:
> From: Ondřej Jirman
> Date: Mon, 24 Jun 2019 19:46:37 +0200
>
> > This series was even longer before, with patches all around for various
> > maintainers. I'd expect that relevant maintainers pick the range
Hi Samuel,
On Mon, Aug 19, 2019 at 10:23:05PM -0500, Samuel Holland wrote:
> Allwinner sun8i, sun9i, and sun50i SoCs contain a hardware message box
> used for communication between the ARM CPUs and the ARISC management
> coprocessor. The hardware contains 8 unidirectional 4-message FIFOs.
>
>
Hi,
On Tue, Aug 20, 2019 at 08:07:53AM -0500, Samuel Holland wrote:
> On 8/20/19 6:18 AM, Ondřej Jirman wrote:
> > Hi Samuel,
> >
> > On Mon, Aug 19, 2019 at 10:23:05PM -0500, Samuel Holland wrote:
> >> Allwinner sun8i, sun9i, and sun50i SoCs contain a
Hello Jernej,
On Sat, Aug 24, 2019 at 11:09:49PM +0200, Jernej Škrabec wrote:
> > Visually?
> >
> > That would explain why it doesn't work for you. The mainline RTC driver
> > disables auto-switch feature, and if your board doesn't have a crystal for
> > LOSC, RTC will not generate a clock for
On Sat, Aug 24, 2019 at 11:36:26PM +0200, Jernej Škrabec wrote:
> Dne sobota, 24. avgust 2019 ob 23:27:46 CEST je Ondřej Jirman napisal(a):
> > Hello Jernej,
> >
> > On Sat, Aug 24, 2019 at 11:09:49PM +0200, Jernej Škrabec wrote:
> > > > Visually?
> &
Hi,
On Sat, Aug 24, 2019 at 10:06:14AM +0200, Jernej Škrabec wrote:
> Dne sobota, 24. avgust 2019 ob 10:04:24 CEST je Jernej Škrabec napisal(a):
> > Hi!
> >
> > Dne torek, 20. avgust 2019 ob 17:19:31 CEST je meg...@megous.com napisal(a):
> > > From: Ondrej Jirman
> > >
> > > I went through the
On Sat, Aug 24, 2019 at 03:16:41PM +0200, Jernej Škrabec wrote:
> Dne sobota, 24. avgust 2019 ob 15:05:44 CEST je Ondřej Jirman napisal(a):
> > On Sat, Aug 24, 2019 at 02:51:54PM +0200, Jernej Škrabec wrote:
> > > Dne sobota, 24. avgust 2019 ob 14:46:54 CEST je Ondřej Jirman napi
On Sat, Aug 24, 2019 at 02:51:54PM +0200, Jernej Škrabec wrote:
> Dne sobota, 24. avgust 2019 ob 14:46:54 CEST je Ondřej Jirman napisal(a):
> > Hi,
> >
> > On Sat, Aug 24, 2019 at 02:32:32PM +0200, Jernej Škrabec wrote:
> > > Hi!
> > >
> > > Dn
Hi,
On Sat, Aug 24, 2019 at 02:32:32PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne torek, 20. avgust 2019 ob 17:19:33 CEST je meg...@megous.com napisal(a):
> > From: Ondrej Jirman
> >
> > RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> > mostly in features that are not
Hi,
On Tue, Aug 27, 2019 at 03:34:43PM +0200, Maxime Ripard wrote:
> On Sun, Aug 25, 2019 at 03:03:36PM +0200, Jernej Skrabec wrote:
> > Depending on kernel and bootloader configuration, it's possible that
> > Realtek ethernet PHY isn't powered on properly. It needs some time
> > before it can be
Hi,
On Wed, Jan 30, 2019 at 04:41:53PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series enables DVFS for the CPU cores (aka cpufreq) on the
> Allwinner H5 SoC. The OPP table was taken from Armbian, with minor
> tweaks to the maximum voltage to account for slightly increased voltage
> on
On Wed, Sep 04, 2019 at 07:29:39AM +0200, Jernej Škrabec wrote:
> Dne sreda, 04. september 2019 ob 05:08:14 CEST je 张宁 napisal(a):
> > just check drm_mode_cursor_universal, cursor plane needs to support
> > DRM_FORMAT_ARGB
> >
> > but VI layer doesn't support alpha, directly change VI layer
Hello Samuel,
On Mon, Aug 19, 2019 at 10:23:01PM -0500, Samuel Holland wrote:
> This series adds support for the "hardware message box" in sun8i, sun9i,
> and sun50i SoCs, used for communication with the ARISC management
> processor (the platform's equivalent of the ARM SCP). The end goal is to
>
Hi,
On Sun, Sep 08, 2019 at 10:54:17PM -0500, Samuel Holland wrote:
> On 9/8/19 10:22 PM, Ondřej Jirman wrote:
> > Hello Samuel,
> >
> > On Mon, Aug 19, 2019 at 10:23:01PM -0500, Samuel Holland wrote:
> >> This series adds support for the "hardware message bo
September 5, 2019 at 5:38:05 AM UTC+8, Jernej Škrabec wrote:
> >
> > Dne sreda, 04. september 2019 ob 23:10:15 CEST je Ondřej Jirman
> > napisal(a):
> > > On Wed, Sep 04, 2019 at 11:02:33PM +0200, Jernej Škrabec wrote:
> > > > Dne sreda, 04. september 2019 ob 22:
rs don't fit in current DRM design.
>
>
> On Thursday, September 5, 2019 at 5:38:05 AM UTC+8, Jernej Škrabec wrote:
> >
> > Dne sreda, 04. september 2019 ob 23:10:15 CEST je Ondřej Jirman
> > napisal(a):
> > > On Wed, Sep 04, 2019 at 11:02:33PM +0200, Jernej Šk
On Wed, Sep 04, 2019 at 11:02:33PM +0200, Jernej Škrabec wrote:
> Dne sreda, 04. september 2019 ob 22:45:47 CEST je Ondřej Jirman napisal(a):
> > On Wed, Sep 04, 2019 at 07:29:39AM +0200, Jernej Škrabec wrote:
> > > Dne sreda, 04. september 2019 ob 05:08:14 CEST je 张宁 napisa
7b48cc
https://megous.com/git/linux/commit/?h=private-5.3=5af208e90de5ced30350fc0fba8419e9662e9bb7
> On Monday, September 9, 2019 at 1:27:08 AM UTC, 张宁 wrote:
> >
> > thanks for your patches.
> >
> > BR.
> > Ning.
> >
> > On Sunday, September 8, 2019 at
gt;
> >
> > On Thursday, September 5, 2019 at 5:38:05 AM UTC+8, Jernej Škrabec wrote:
> > >
> > > Dne sreda, 04. september 2019 ob 23:10:15 CEST je Ondřej Jirman
> > > napisal(a):
> > > > On Wed, Sep 04, 2019 at 11:02:33PM +0200, Jernej Škrabec
Hi,
On Sun, Sep 08, 2019 at 07:01:42PM +0200, Jernej Škrabec wrote:
> Dne nedelja, 08. september 2019 ob 12:20:50 CEST je Ondřej Jirman napisal(a):
> > Hi,
> >
> > On Sun, Sep 08, 2019 at 12:21:45AM +0200, megous hlavni wrote:
> > > On Thu, Sep 05, 2019
On Wed, Sep 04, 2019 at 11:38:01PM +0200, Jernej Škrabec wrote:
> Dne sreda, 04. september 2019 ob 23:10:15 CEST je Ondřej Jirman napisal(a):
> > On Wed, Sep 04, 2019 at 11:02:33PM +0200, Jernej Škrabec wrote:
> > > Dne sreda, 04. september 2019 ob 22:45:47 CEST je Ondřej
On Mon, Aug 05, 2019 at 06:54:17PM +0800, Chen-Yu Tsai wrote:
> On Mon, Aug 5, 2019 at 6:45 PM Ondřej Jirman wrote:
> >
> > On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> > > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> > > wrote:
&g
On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> wrote:
> >
> > From: Ondrej Jirman
> >
> > RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> > mostly in features that are not yet supported by this
On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> wrote:
> >
> > From: Ondrej Jirman
> >
> > RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> > mostly in features that are not yet supported by this
On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote:
> On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> wrote:
> >
> > From: Ondrej Jirman
> >
> > I went through the datasheets for H6 and H5, and compared the differences.
> > RTCs are largely similar, but not entirely
On Tue, Aug 06, 2019 at 08:30:45PM +0200, megous hlavni wrote:
> On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote:
> > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> > wrote:
> > >
> > > From: Ondrej Jirman
> > >
> > > I went through the datasheets for H6 and H5, and
On Fri, Aug 09, 2019 at 10:25:32AM +0200, Code Kipper wrote:
> On Tue, 6 Aug 2019 at 17:57, wrote:
> >
> > From: Ondrej Jirman
> >
> > Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC
> > I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high.
> >
On Fri, Aug 09, 2019 at 01:39:30AM +0200, Alexandre Belloni wrote:
> On 08/08/2019 14:12:37+0200, Ondřej Jirman wrote:
> > On Wed, Aug 07, 2019 at 12:55:02PM +0200, Alexandre Belloni wrote:
> > > Hi,
> > >
> > > On 06/08/2019 20:30:45+0200, Ondřej Jirman wro
On Wed, Aug 07, 2019 at 12:55:02PM +0200, Alexandre Belloni wrote:
> Hi,
>
> On 06/08/2019 20:30:45+0200, Ondřej Jirman wrote:
> > Maybe whether XO or DCXO is used also matters if you want to do some fine
> > tunning of DCXO (control register has pletny of options), but
Hello Rikard,
On Thu, Nov 07, 2019 at 09:46:45PM +0100, Rikard Falkeborn wrote:
> Arguments are supposed to be ordered high then low.
>
> Signed-off-by: Rikard Falkeborn
> ---
> Spotted while trying to add compile time checks of GENMASK arguments.
> Patch has only been compile tested.
thank
Hi,
On Thu, Oct 31, 2019 at 07:55:43PM +0100, Clément Péron wrote:
> Hi Ondrej,
>
> On Thu, 31 Oct 2019 at 19:14, Ondrej Jirman wrote:
> >
> > I have failures to boot on Orange Pi 3, because this driver determined
> > that my SoC is from the normal bin, but my SoC only works reliably with
> >
On Fri, Nov 08, 2019 at 07:29:21PM +0800, Icenowy Zheng wrote:
>
>
> 于 2019年11月8日 GMT+08:00 上午5:45:14, "Ondřej Jirman" 写到:
> >Hello Rikard,
> >
> >On Thu, Nov 07, 2019 at 09:46:45PM +0100, Rikard Falkeborn wrote:
> >> Arguments are supposed to b
Hi,
On Wed, Apr 24, 2019 at 01:44:12PM +0800, Icenowy Zheng wrote:
> The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
> it mismatches the real voltage supplied to the VCC to the PIO supply,
> the PIO will work improperly.
>
> The PIO controller also has a register that
Hello Dmitry,
On Mon, Oct 28, 2019 at 04:38:28PM -0700, Dmitry Torokhov wrote:
> Hi Ondrej,
>
> On Mon, Oct 28, 2019 at 11:15:02PM +0100, Ondrej Jirman wrote:
> > Allow the driver to wakeup the system on key press.
> >
> > Signed-off-by: Ondrej Jirman
> > ---
> >
On Mon, Oct 28, 2019 at 05:12:50PM -0700, Dmitry Torokhov wrote:
> On Tue, Oct 29, 2019 at 12:56:26AM +0100, Ondřej Jirman wrote:
> > On Mon, Oct 28, 2019 at 04:38:28PM -0700, Dmitry Torokhov wrote:
> > > > +
> > > > + error = dev_pm_set_wake_irq(dev
On Tue, Oct 29, 2019 at 09:09:40AM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 29, 2019 at 5:49 AM Ondrej Jirman wrote:
> >
> > PRCM_PWROFF_GATING_REG has CPU0 at bit 4 on A83T. So without this
> > patch, instead of gating the CPU0, the whole cluster was power gated,
> > when shutting down first CPU
On Mon, Oct 28, 2019 at 09:18:04PM -0700, Dmitry Torokhov wrote:
> On Tue, Oct 29, 2019 at 02:45:59AM +0100, Ondřej Jirman wrote:
> > On Mon, Oct 28, 2019 at 05:12:50PM -0700, Dmitry Torokhov wrote:
> > > On Tue, Oct 29, 2019 at 12:56:26AM +0100, Ondřej Jirman wrote:
> >
Hi Marco,
On Tue, Oct 29, 2019 at 09:55:45AM +0100, Marco Felsch wrote:
> Hi Dmitry,
>
> On 19-10-28 21:12, Dmitry Torokhov wrote:
> > On Tue, Oct 29, 2019 at 01:58:04AM +0100, Ondrej Jirman wrote:
> > > From: Mylčne Josserand
> > >
> > > Add the support for enabling optional regulator that
Hello Marco,
On Tue, Oct 29, 2019 at 10:08:01AM +0100, Marco Felsch wrote:
> Hi,
>
> On 19-10-29 01:58, Ondrej Jirman wrote:
> > From: Mylčne Josserand
> >
> > Enable a FocalTech EDT-FT5x06 Polytouch touchscreen.
> >
> > Signed-off-by: Ondrej Jirman
> > Signed-off-by: Mylčne Josserand
> >
Hi,
On Thu, Nov 28, 2019 at 10:26:08AM +0800, Yong wrote:
> Hi Ondrej,
>
> This has been discussed.
> And Maxime sent a patch for this:
> https://www.mail-archive.com/linux-media@vger.kernel.org/msg127149.html
Thanks for pointing to the previous patch. But that patch doesn't make any
sense,
On Thu, Nov 28, 2019 at 11:26:24AM +0800, Chen-Yu Tsai wrote:
> On Thu, Nov 28, 2019 at 11:06 AM Ondřej Jirman wrote:
> >
> > Hi,
> >
> > On Thu, Nov 28, 2019 at 10:26:08AM +0800, Yong wrote:
> > > Hi Ondrej,
> > >
> > > This has been discusse
On Fri, Nov 01, 2019 at 04:07:01PM +0100, Maxime Ripard wrote:
> On Thu, Oct 31, 2019 at 07:13:58PM +0100, Ondrej Jirman wrote:
> > I have failures to boot on Orange Pi 3, because this driver determined
> > that my SoC is from the normal bin, but my SoC only works reliably with
> > the OPP values
Hi,
On Thu, Oct 31, 2019 at 08:12:57PM +0100, megous hlavni wrote:
> Hi,
>
> On Thu, Oct 31, 2019 at 07:55:43PM +0100, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Thu, 31 Oct 2019 at 19:14, Ondrej Jirman wrote:
> > >
> > > I have failures to boot on Orange Pi 3, because this driver
On Fri, Nov 01, 2019 at 04:07:01PM +0100, Maxime Ripard wrote:
> On Thu, Oct 31, 2019 at 07:13:58PM +0100, Ondrej Jirman wrote:
> > I have failures to boot on Orange Pi 3, because this driver determined
> > that my SoC is from the normal bin, but my SoC only works reliably with
> > the OPP values
Hello Maxime,
On Mon, Oct 21, 2019 at 01:09:46PM +0200, Maxime Ripard wrote:
> On Sun, Oct 20, 2019 at 03:42:29PM +0200, meg...@megous.com wrote:
> > From: Ondrej Jirman
> >
> > Enable Allwinner's USB 3.0 phy and the host controller. Orange Pi 3
> > board has GL3510 USB 3.0 4-port hub connected
HI Icenowy,
On Sun, Oct 06, 2019 at 11:12:43PM +0800, Icenowy Zheng wrote:
> 在 2019-10-06日的 22:44 +0800,Icenowy Zheng写道:
> > 在 2019-10-03四的 09:53 +0530,Jagan Teki写道:
> > > Hi Wens,
> > >
> > > On Tue, Oct 1, 2019 at 1:34 PM Icenowy Zheng
> > > wrote:
> > > > This reverts commit
Hi,
On Mon, Feb 10, 2020 at 06:40:07PM +0100, Jernej Skrabec wrote:
> OrangePi 3 can optionally have 8 GiB eMMC (soldered on board). Because
> those pins are dedicated to eMMC exclusively, node can be added for both
> variants (with and without eMMC). Kernel will then scan bus for presence
> of
On Sun, Feb 23, 2020 at 02:27:30PM +0100, megous hlavni wrote:
> On Sun, Feb 23, 2020 at 02:14:31PM +0100, megous hlavni wrote:
> > The tablet has a charger LED exposed on the top. This LED is controlled
> > by AXP813 PMIC. Add support for enabling the LED and using it either
> > for charging
On Sun, Feb 23, 2020 at 02:14:31PM +0100, megous hlavni wrote:
> The tablet has a charger LED exposed on the top. This LED is controlled
> by AXP813 PMIC. Add support for enabling the LED and using it either
> for charging indication (handled by PMIC automatically) or for other uses
> via user
Hi,
On Mon, Feb 24, 2020 at 06:06:20PM +0100, Daniel Lezcano wrote:
> On 24/02/2020 17:54, Ondrej Jirman wrote:
> > This enables passive cooling by down-regulating CPU voltage
> > clocks = < CLK_C1CPUX>;
> > @@ -1188,12 +1188,60 @@ cpu0_thermal: cpu0-thermal {
> >
On Mon, Feb 24, 2020 at 06:23:28PM +0100, megous hlavni wrote:
> Hi,
>
> On Mon, Feb 24, 2020 at 06:06:20PM +0100, Daniel Lezcano wrote:
> > On 24/02/2020 17:54, Ondrej Jirman wrote:
> > > This enables passive cooling by down-regulating CPU voltage
> > > clocks = < CLK_C1CPUX>;
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