Hi,
On 08/12/2015 03:29 PM, Michal Suchanek wrote:
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
350ms.
This does not make mmc clock gating look like good option to have
2015-08-12 8:55 GMT+03:00 Nithin Chakravarthy nithin.mukthin...@gmail.com:
here kernel log
6usb 5-1: new full-speed USB device number 2 using sw-ohci
3bluetooth: exports duplicate symbol baswap (owned by kernel)
[ 94.643972] bluetooth: exports duplicate symbol baswap (owned by kernel)
Hi,
On 11-08-15 16:18, Lee Jones wrote:
On Sat, 08 Aug 2015, Hans de Goede wrote:
Add a cell for the usb power_supply part of the axp20x PMICs.
Note that this cell is only for the usb power_supply part and not the
ac-power / battery-charger / rtc-backup-bat-charger bits.
Depending on the
Hi,
On 12-08-15 07:31, Code Kipper wrote:
On 11 August 2015 at 18:48, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Aug 12, 2015 at 12:19 AM, codekip...@gmail.com wrote:
From: Marcus Cooper codekip...@gmail.com
Signed-off-by: Marcus Cooper codekip...@gmail.com
---
On Tue, 2015-08-11 at 03:39 -0700, ghl.b...@gmail.com wrote:
On Tuesday, August 11, 2015 at 1:10:45 PM UTC+5:30, Ian Campbell
wrote:
On Mon, 2015-08-10 at 12:27 +0200, Michal Suchanek wrote:
I assume that all allwinner core enable in hyp mode and
following
code
checks for hyp
On Wed, Aug 12, 2015 at 5:13 PM, Code Kipper codekip...@gmail.com wrote:
On 12 August 2015 at 10:34, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 12-08-15 07:31, Code Kipper wrote:
On 11 August 2015 at 18:48, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Aug 12, 2015 at 12:19 AM,
On 12 August 2015 at 10:34, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 12-08-15 07:31, Code Kipper wrote:
On 11 August 2015 at 18:48, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Aug 12, 2015 at 12:19 AM, codekip...@gmail.com wrote:
From: Marcus Cooper codekip...@gmail.com
Hi,
On 12-08-15 11:18, Chen-Yu Tsai wrote:
On Wed, Aug 12, 2015 at 5:13 PM, Code Kipper codekip...@gmail.com wrote:
On 12 August 2015 at 10:34, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 12-08-15 07:31, Code Kipper wrote:
On 11 August 2015 at 18:48, Chen-Yu Tsai w...@csie.org wrote:
On Wed, 12 Aug 2015, Hans de Goede wrote:
Hi,
On 12-08-15 11:29, Lee Jones wrote:
On Wed, 12 Aug 2015, Hans de Goede wrote:
Hi,
On 11-08-15 16:18, Lee Jones wrote:
On Sat, 08 Aug 2015, Hans de Goede wrote:
Add a cell for the usb power_supply part of the axp20x PMICs.
Note that
On Wed, 12 Aug 2015, Hans de Goede wrote:
Hi,
On 11-08-15 16:18, Lee Jones wrote:
On Sat, 08 Aug 2015, Hans de Goede wrote:
Add a cell for the usb power_supply part of the axp20x PMICs.
Note that this cell is only for the usb power_supply part and not the
ac-power / battery-charger /
Actually, I've reverted hans's
mmc: sunxi: Don't start commands while the card is busy
and that makes it disapear as well. So it looks like that patch triggers
the aggressiveness more?
I'll apply your patch and undo the revert to see if that fixes the root
issue.
Olliver
On 12-08-15
Hi Sebastian,
On 24-07-15 17:10, Sebastian Reichel wrote:
Hi,
On Fri, Jun 26, 2015 at 12:59:17PM +0200, Hans de Goede wrote:
This adds a driver for the usb power_supply bits of the axp20x PMICs.
I initially started writing my own driver, before coming aware of
Bruno Prémont's excellent
The driver has open-coded test for SDIO cards. Use the mmc core provided
MMC_QUIRK_BROKEN_CLK_GATING flag instead.
As a bonus this may enable clock gating on SDIO cards that are known to
work with it.
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
drivers/mmc/host/dw_mmc.c | 33
When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
automatic hardware controlled clock gating on the mmc interface.
Signed-off-by: Michal Suchanek hramr...@gmail.com
---
drivers/mmc/host/sunxi-mmc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
350ms.
This does not make mmc clock gating look like good option to have on
sunxi but the system should not crash with mmc
On 12 August 2015 at 13:55, Olliver Schinagl oliver+l...@schinagl.nl wrote:
Actually, I've reverted hans's
mmc: sunxi: Don't start commands while the card is busy
and that makes it disapear as well. So it looks like that patch triggers the
aggressiveness more?
It probably inserts delays
Hello,
The first sunxi patch from this series was rejected on the basis that this clock
gating functionality is obsolete and should be eventually removed.
However, the function still exists in the current code and until removed it
should be corrected to work properly. Turning off the clock may
Hi,
On 12-08-15 14:23, michal.sucha...@ruk.cuni.cz wrote:
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
350ms.
This does not make mmc clock gating look like good option
Hello,
On 12 August 2015 at 13:40, Olliver Schinagl oliver+l...@schinagl.nl wrote:
Hey all,
I'm noticing the exact same thing using hans's sunxi-wip from a few days
ago.
I did see a patch from you about this very issue I belive
mmc: sunxi: fix timeout in sunxi_mmc_oclk_onoff
but can't
Hi,
On 12-08-15 14:23, Michal Suchanek wrote:
When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
automatic hardware controlled clock gating on the mmc interface.
Signed-off-by: Michal Suchanek hramr...@gmail.com
In general this looks good, but I wonder how intensively this
While I can't speak for Michal obviously,
I left the debugging bit (in my v2 that i sent 2 minutes ago) as both
you and Hans where content with it back then and both acked it.
Michal, feel free to send the v3 without the debug info, unless you want
me to do it ;)
Olliver
On 12-08-15
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
350ms.
This does not make mmc clock gating look like good option to have on
sunxi but the system should not crash with mmc
On 12 August 2015 at 15:19, Olliver Schinagl oliver+l...@schinagl.nl wrote:
Hey,
On 12-08-15 14:35, Hans de Goede wrote:
Hi,
On 12-08-15 14:23, Michal Suchanek wrote:
When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
automatic hardware controlled clock gating on the mmc
Hey,
On 12-08-15 14:35, Hans de Goede wrote:
Hi,
On 12-08-15 14:23, Michal Suchanek wrote:
When core does not set the MMC_QUIRK_BROKEN_CLK_GATING flag enable
automatic hardware controlled clock gating on the mmc interface.
Signed-off-by: Michal Suchanek hramr...@gmail.com
In general this
Hey Yassin,
I'm affraid. The strange thing that seems very related here is that when
writing a file onto the flash, it fails and succeeds alternating. It
never fails or succeeds twice in a row! And this on any board and any
partition.
root@system-020502824168:/boot# nandwrite -p /dev/mtd0
From: Marcus Cooper codekip...@gmail.com
Signed-off-by: Marcus Cooper codekip...@gmail.com
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
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