On Thu, Apr 24, 2014 at 04:22:44PM +0200, Maxime Ripard wrote:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
On Wed, Apr 30, 2014 at 02:53:22PM -0700, Maxime Ripard wrote:
Hi Vinod,
On Wed, Apr 30, 2014 at 12:34:08PM +0530, Vinod Koul wrote:
On Thu, Apr 24, 2014 at 04:22:44PM +0200, Maxime Ripard wrote:
+static inline void sun6i_dma_free(struct sun6i_dma_dev *sdc)
+{
+ int i
On Wed, May 07, 2014 at 10:19:49PM -0500, Maxime Ripard wrote:
On Fri, May 02, 2014 at 10:04:29PM +0530, Vinod Koul wrote:
On Wed, Apr 30, 2014 at 02:53:22PM -0700, Maxime Ripard wrote:
Hi Vinod,
On Wed, Apr 30, 2014 at 12:34:08PM +0530, Vinod Koul wrote:
On Thu, Apr 24, 2014
On Tue, May 13, 2014 at 03:42:58PM +0200, Maxime Ripard wrote:
Hi Vinod,
On Wed, Apr 30, 2014 at 12:34:08PM +0530, Vinod Koul wrote:
+
+static int sun6i_dma_terminate_all(struct sun6i_vchan *vchan)
+{
+ struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan-vc.chan.device
On Thu, Jul 24, 2014 at 04:44:20PM -0700, Andrew Morton wrote:
On Thu, 24 Jul 2014 14:13:15 +0200 Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Thu, Jul 17, 2014 at 09:46:14PM +0200, Maxime Ripard wrote:
Hi,
This patchset adds support for the DMA controller found in the
On Fri, Jul 25, 2014 at 11:41:30AM +0530, Vinod Koul wrote:
On Thu, Jul 24, 2014 at 04:44:20PM -0700, Andrew Morton wrote:
On Thu, 24 Jul 2014 14:13:15 +0200 Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Thu, Jul 17, 2014 at 09:46:14PM +0200, Maxime Ripard wrote:
Hi
On Thu, Jul 17, 2014 at 09:46:14PM +0200, Maxime Ripard wrote:
Hi,
This patchset adds support for the DMA controller found in the
Allwinner A31 and A23 SoCs.
This has been tested using the newly introduced SPI driver on an A31
EVK. Support for DMA-driven SPI transfers will be the subject
On Fri, Jul 25, 2014 at 06:37:46PM +0200, Maxime Ripard wrote:
Can you please send follow patches for these:
- don't recall if I pointed earlier, but can we use direct conversion for
calculating convert_burst() and convert_buswidth(), latter one at least
seem doable
Ok. Do you still
On Mon, Jul 28, 2014 at 12:14:02PM +0200, Maxime Ripard wrote:
On Fri, Jul 25, 2014 at 10:12:18PM +0530, Vinod Koul wrote:
On Fri, Jul 25, 2014 at 06:37:46PM +0200, Maxime Ripard wrote:
Can you please send follow patches for these:
- don't recall if I pointed earlier, but can we use
On Sat, Sep 06, 2014 at 06:47:28PM +0800, Chen-Yu Tsai wrote:
The sun6i DMA controller requires the AHB1 bus clock to be
clocked from PLL6. This was originally done by the dmaengine
driver during probe time. The AHB1 clock driver has since been
unified, so the original code does not work.
On Fri, Sep 26, 2014 at 11:06:01AM +0800, Chen-Yu Tsai wrote:
On Thu, Sep 18, 2014 at 11:24 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi everyone,
This is v2 of my sun8i DMA controller support series. This series
adds support for the DMA controller found in the Allwinner A23 SoC.
It is the
On Thu, Nov 06, 2014 at 03:54:35PM +0800, Chen-Yu Tsai wrote:
The patches look fine to me so I tried applying them but they fail to apply,
can you please rebase these two and resend
Hi Vinod,
Could you publish an updated slave-dma/next branch? Currently I see it at
v3.18-rc1. And the
On Sat, Jan 31, 2015 at 07:58:44PM -0300, Emilio López wrote:
+/** Dedicated DMA register layout **/
+
+/* Dedicated DMA configuration register layout */
+#define DDMA_CFG_LOADING BIT(31)
+#define DDMA_CFG_BUSYBIT(30)
+#define
On Wed, May 06, 2015 at 12:13:42PM +0200, Maxime Ripard wrote:
On Wed, May 06, 2015 at 11:31:31AM +0200, Jens Kuske wrote:
The H3 SoC has the same dma engine as the A31 (sun6i), with a
reduced amount of endpoints and physical channels. Add the proper
config data and compatible string to
On Wed, May 06, 2015 at 11:31:31AM +0200, Jens Kuske wrote:
The H3 SoC has the same dma engine as the A31 (sun6i), with a
reduced amount of endpoints and physical channels. Add the proper
config data and compatible string to support it.
Applied, thanks
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On Mon, May 11, 2015 at 03:27:32PM +0200, Maxime Ripard wrote:
+
+/** Normal DMA register values **/
+
+/* Normal DMA source/destination data request type values */
+#define NDMA_DRQ_TYPE_SDRAM 0x16
+#define NDMA_DRQ_TYPE_LIMIT (0x1F + 1)
+
+/** Normal DMA
On Mon, Jun 08, 2015 at 11:12:25PM +0200, Maxime Ripard wrote:
+
+static int sanitize_config(struct dma_slave_config *sconfig)
+{
+ switch (sconfig-direction) {
all was fine but this part is not :( the dma_slave_config direction is
deprecated, so here you should honour the direction
On Thu, May 21, 2015 at 09:47:35AM +0200, Maxime Ripard wrote:
On Mon, May 18, 2015 at 02:16:14PM +0530, Vinod Koul wrote:
+static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
+dma_cookie_t cookie
On Thu, May 21, 2015 at 01:45:27PM -0300, Emilio López wrote:
Hi Maxime, Vinod,
El 20/05/15 a las 18:17, Maxime Ripard escibió:
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t
len,
+size_t period_len,
On Fri, Mar 11, 2016 at 10:40:55AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 11:54:52 +0530
> Vinod Koul <vinod.k...@intel.com> wrote:
>
> > On Wed, Mar 09, 2016 at 11:14:34AM +0100, Boris Brezillon wrote:
> > > > > > > > + * stru
On Fri, Mar 11, 2016 at 10:45:52AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 11:56:07 +0530
> Vinod Koul <vinod.k...@intel.com> wrote:
>
> > On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> > > On Tue, 8 Mar 2016 08:25:47 +0530
> >
On Fri, Mar 11, 2016 at 11:55:49AM +0100, Maxime Ripard wrote:
> On Fri, Mar 11, 2016 at 03:39:02PM +0530, Vinod Koul wrote:
> > On Fri, Mar 11, 2016 at 10:45:52AM +0100, Boris Brezillon wrote:
> > > On Fri, 11 Mar 2016 11:56:07 +0530
> > > Vinod Koul &
On Fri, Mar 11, 2016 at 11:26:31AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 15:36:07 +0530
> Vinod Koul <vinod.k...@intel.com> wrote:
>
> > On Fri, Mar 11, 2016 at 10:40:55AM +0100, Boris Brezillon wrote:
> > > On Fri, 11 Mar 2016 11:54:52 +0530
> >
On Mon, Mar 14, 2016 at 12:46:41PM +0100, Maxime Ripard wrote:
> On Fri, Mar 11, 2016 at 04:48:26PM +0530, Vinod Koul wrote:
> > > > But this nees to be property for clients and not driver. Client can then
> > > > program these
> > >
> > > Yes, total
On Wed, Mar 09, 2016 at 11:14:34AM +0100, Boris Brezillon wrote:
> > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > + *
> > > > > > + * @para: contains information about block size and time before
> > > > > > checking
> > > > > > + * DRQ line. This is device specific
On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:25:47 +0530
> Vinod Koul <vinod.k...@intel.com> wrote:
> >
> > Why does dmaengine need to wait? Can you explain that
>
> I don't have an answer for that one, but when I set W
On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
> > Hi Vinod,
> >
> > On Mon, 7 Mar 2016 20:24:29 +0530
> > Vinod Koul <vinod.k...@intel.com> wrote:
> >
> > >
On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
> On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> > On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
Also just noticed the subsystem name on this is not correct, pls fix that in
subsequen
On Tue, Mar 08, 2016 at 09:46:25AM +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:51:31 +0100
> Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
>
> > On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
> > > On Mon, Mar 07, 2016 at 09:30:2
On Tue, Mar 08, 2016 at 09:42:31AM +0100, Hans de Goede wrote:
>
>
> I see 2 possible reasons why waiting till checking for drq can help:
>
> 1) A lot of devices have an internal fifo hooked up to a single mmio data
> register which gets read using the general purpose dma-engine, it allows
>
On Tue, Mar 08, 2016 at 08:51:31AM +0100, Maxime Ripard wrote:
> > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > + *
> > > > > > + * @para: contains information about block size and time before
> > > > > > checking
> > > > > > + * DRQ line. This is device specific
On Tue, Mar 08, 2016 at 12:15:13PM +0100, Boris Brezillon wrote:
>
> +#ifdef CONFIG_HAS_DMA
Shouldn't this be CONFIG_DMA_ENGINE as you are preparing these descriptors
for DMA transfer?
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On Mon, Mar 07, 2016 at 10:59:31AM +0100, Boris Brezillon wrote:
> +/* Dedicated DMA parameter register layout */
> +#define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n) (((n) - 1) << 24)
> +#define SUN4I_DDMA_PARA_DST_WAIT_CYCLES(n) (((n) - 1) << 16)
> +#define SUN4I_DDMA_PARA_SRC_DATA_BLK_SIZE(n)
On Fri, Apr 22, 2016 at 08:48:40AM +0200, Jean-Francois Moine wrote:
> Some DMA clients, as audio, don't set the maxburst size and bus width
> on the memory side when starting DMA transfers.
> This patch prevents such transfers to be aborted by providing system
> default values to the lacking
On Fri, Apr 22, 2016 at 08:22:56AM +0200, Jean-Francois Moine wrote:
> This patch series replaces part of the previous series
> 'dmaengine: sun6i: Fixes and upgrade for audio transfers'.
> It contains only fixes for a normal use of the DMA driver.
Applied, thanks
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On Fri, Apr 22, 2016 at 08:49:55AM +0200, Jean-Francois Moine wrote:
> DMA cyclic transfers are required by audio streaming.
>
> Acked-by: Maxime Ripard
> Signed-off-by: Jean-Francois Moine
> ---
> drivers/dma/sun6i-dma.c | 129
>
On Fri, Apr 22, 2016 at 08:47:29AM +0200, Jean-Francois Moine wrote:
> Checking the DMA config before setting the lli list avoids to do tests
> inside the setting loop.
Applied, thanks
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> submitted when a consensus with Maxime Ripard will be found.
> This series is based on the previous patches applied by Vinod Koul.
Applied, thanks
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On Sat, Apr 02, 2016 at 11:49:13AM +0200, Jean-Francois Moine wrote:
> This patch series contains most of the required changes to
> the sun6i DMA driver for audio streaming (tested in
> a Allwinner H3 - Orange PI 2).
> It is based on the previous series 'dmaengine: sun6i: Fixes'
> (2016-03-18).
On Sun, Jan 29, 2017 at 10:33:29AM +0800, Icenowy Zheng wrote:
> As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA
> driver should be allowed to be built for ARM64, in order to make it work on
> H5.
Applied, thanks
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On Tue, Jan 31, 2017 at 02:23:55AM +0800, Icenowy Zheng wrote:
>
>
> 31.01.2017, 00:41, "Vinod Koul" <vinod.k...@intel.com>:
> > On Sun, Jan 29, 2017 at 10:33:29AM +0800, Icenowy Zheng wrote:
> >> As 64-bit Allwinner H5 SoC has the same DMA engine with H3
On Sun, Sep 18, 2016 at 09:59:50AM +0200, Jean-Francois Moine wrote:
> The A83T SoC has the same dma engine as the A31 (sun6i), with a reduced
> amount of endpoints and physical channels.
Applied, thanks
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On Tue, Oct 04, 2016 at 03:46:51PM +0200, Jean-Francois Moine wrote:
> On Tue, 4 Oct 2016 14:12:21 +0200
> Thomas Petazzoni wrote:
>
> > > > Add the case of a burst of 4 which is handled by the SoC.
> > > >
> > > > Signed-off-by: Mylčne Josserand
On Tue, Nov 01, 2016 at 10:55:13PM +0800, Chen-Yu Tsai wrote:
> >> * @src_maxburst: the maximum number of words (note: words, as in
> >> * units of the src_addr_width member, not bytes) that can be sent
> >> * in one burst to the device. Typically something like half the
> >> * FIFO depth on
On Sun, Mar 05, 2017 at 09:36:57PM +0800, Icenowy Zheng wrote:
> Allwinner V3s features a audio codec with dedicated digital and analog parts,
> like the ones on A23/H3, but much simpler (lack of MIC2, LINE IN and MBIAS).
>
> Add support for it.
>
> In order to make the codec usable, DMA support
Fixed Arnd email now..
On Wed, May 24, 2017 at 04:10:08PM +0530, Vinod Koul wrote:
> On Wed, May 24, 2017 at 06:05:58PM +0800, Icenowy Zheng wrote:
> > Allwinner V3s features a audio codec with dedicated digital and analog
> > parts,
> > like the ones on A23/H3, but much
On Wed, May 24, 2017 at 06:05:58PM +0800, Icenowy Zheng wrote:
> Allwinner V3s features a audio codec with dedicated digital and analog parts,
> like the ones on A23/H3, but much simpler (lack of MIC2, LINE IN and MBIAS).
>
> Add support for it.
>
> In order to make the codec usable, DMA support
On Mon, Jun 05, 2017 at 08:33:47PM +0800, Icenowy Zheng wrote:
> From: Icenowy Zheng
>
> Originally we enable a special gate bit when the compatible indicates
> A23/33.
>
> But according to BSP sources and user manuals, more SoCs will need this
> gate bit.
>
> So make it a
On Wed, Jun 14, 2017 at 04:32:57PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年6月14日 GMT+08:00 下午4:32:52, Vinod Koul <vinod.k...@intel.com> 写到:
> >On Mon, Jun 05, 2017 at 08:33:47PM +0800, Icenowy Zheng wrote:
> >> From: Icenowy Zheng <icen...@aosc.xyz>
>
On Thu, Sep 28, 2017 at 03:49:17AM +0200, Stefan Brüns wrote:
> Commit 3a03ea763a67 ("dmaengine: sun6i: Add support for Allwinner A83T
> (sun8i) variant") and commit f008db8c00c1 ("dmaengine: sun6i: Add support for
> Allwinner H3 (sun8i) variant") added support for the A83T resp. H3, but missed
>
On Thu, Sep 28, 2017 at 03:49:24AM +0200, Stefan Brüns wrote:
> To avoid introduction of a new compatible for each small SoC/DMA controller
> variation, move the definition of the channel count to the devicetree.
>
> The number of vchans is no longer explicit, but limited by the highest
>
On Mon, Oct 16, 2017 at 02:21:02PM +, Brüns, Stefan wrote:
> On Montag, 16. Oktober 2017 09:02:17 CEST Vinod Koul wrote:
> > On Thu, Sep 28, 2017 at 03:49:24AM +0200, Stefan Brüns wrote:
> > > To avoid introduction of a new compatible for each small SoC/DMA
> > >
On Tue, Aug 29, 2017 at 12:51:25PM +0800, Icenowy Zheng wrote:
> This is a dedicated patchset of Allwinner V3s DMA support, which used
> to be part of the audio codec support patchset.
>
> It's a derivation of the DMA part of v3 of the codec patchset.
Applied, thanks
--
~Vinod
--
You
On Tue, Oct 17, 2017 at 01:06:34AM +0200, Stefan Brüns wrote:
> To avoid introduction of a new compatible for each small SoC/DMA controller
> variation, move the definition of the channel count to the devicetree.
>
> The number of vchans is no longer explicit, but limited by the highest
>
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