Am Donnerstag, den 15.03.2018, 09:33 +0200 schrieb Mathias Nyman:
> On 14.03.2018 12:29, Oliver Neukum wrote:
> >
> > We should also export all raw data we have. User space can be trusted
> > to get a multiplication right and it is not the kernels job
> > to interpret such data.
>
> Do I
On 14.03.2018 12:29, Oliver Neukum wrote:
Am Dienstag, den 13.03.2018, 19:22 +0200 schrieb Mathias Nyman:
My understanding is that Gen XxY notion is only used for symmetric devices
where tx lanes = rx lanes. Only SSIC devices can be asymmetric.
USB 3.2 spec mentions the (Gen 1x1, 1x2, 2x1 and
Am Dienstag, den 13.03.2018, 19:22 +0200 schrieb Mathias Nyman:
> My understanding is that Gen XxY notion is only used for symmetric devices
> where tx lanes = rx lanes. Only SSIC devices can be asymmetric.
>
> USB 3.2 spec mentions the (Gen 1x1, 1x2, 2x1 and 2x2) alternatives, nothing
> more.
On 13.03.2018 21:58, Adrian Bocaniciu wrote:
On Tue, 13 Mar 2018 17:27:21 +0200
Mathias Nyman wrote:
Example for clarification:
Gen 1x1 = 5Gbps, SuperSpeed, one lane, same as USB3.0, and USB 3.1 Gen1
Gen 2x1 = 10Gbps, SuperSpeedPlus, one lane, same as USB 3.1
On Tue, 13 Mar 2018 17:27:21 +0200
Mathias Nyman wrote:
> Example for clarification:
> Gen 1x1 = 5Gbps, SuperSpeed, one lane, same as USB3.0, and USB 3.1 Gen1
> Gen 2x1 = 10Gbps, SuperSpeedPlus, one lane, same as USB 3.1 Gen2
> Gen 1x2 = 10Gbps, SuperSpeed,
On 13.03.2018 17:27, Felipe Balbi wrote:
Hi,
Mathias Nyman writes:
The USB 3.2 specification adds support for Dual-lane, doubling the
maximum rate to 20Gbps by taking into use another set of rx and tx
wires and pins in the Type-C cable and connector.
The
Hi,
Mathias Nyman writes:
> The USB 3.2 specification adds support for Dual-lane, doubling the
> maximum rate to 20Gbps by taking into use another set of rx and tx
> wires and pins in the Type-C cable and connector.
>
> The changes to support this in USB core and