nsertion(+)
>
Acked-by: Rob Herring
+--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring
On Fri, Aug 23, 2019 at 03:57:13PM +0800, Chunfeng Yun wrote:
> It's used to support dual role switch via GPIO when use Type-B
> receptacle, typically the USB ID pin is connected to an input
> GPIO, and also used to enable/disable device when the USB Vbus
> pin is connected to an input GPIO.
>
> S
eviewed-by: JC Kuo
> ---
> .../devicetree/bindings/usb/nvidia,tegra-xudc.txt | 110
> +
> 1 file changed, 110 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt
>
Reviewed-by: Rob Herring
xt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Wed, Jul 31, 2019 at 03:49:52PM +0530, Srinath Mannam wrote:
> Increase #phy-cells from 1 to 2 to have bitmask of PHY enabled ports.
And from 0 to 1...
Are you going to update all the dts files so when we convert this to
schema we don't get a bunch of warnings? (Feel free to convert this
to
On Wed, Jul 24, 2019 at 8:29 PM Ran Wang wrote:
>
> Hi Rob,
>
> On Thursday, July 25, 2019 04:42 Rob Herring wrote:
> >
> > On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> > > Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter
> &g
On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter USB
> detect failues when adding dma-coherent to DWC3 node. This is because the
> HW default cache type configuration of those SoC are not right, need to
> be updated in D
On Fri, Jul 05, 2019 at 05:11:47PM +0530, Nagarjuna Kristam wrote:
> Add device-tree binding documentation for the XUSB device mode controller
> present on Tegra210 SoC. This controller supports the USB 3.0
> specification.
>
> Signed-off-by: Nagarjuna Kristam
> Reviewed-by: JC Kuo
> ---
> .../
On Thu, May 16, 2019 at 12:09:28PM +0530, Nagarjuna Kristam wrote:
> Add device-tree binding documentation for the XUSB device mode controller
> present on Tegra210 SoC. This controller supports the USB 3.0
> specification.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> .../devicetree/bindings/usb
On Tue, 14 May 2019 09:56:02 -0500, Chris Brandt wrote:
> Add support for r7s9210 (RZ/A2M) SoC
>
> Signed-off-by: Chris Brandt
> ---
> Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rob Herring
On Tue, 14 May 2019 09:55:57 -0500, Chris Brandt wrote:
> Document RZ/A2 (R7S9210) SoC bindings.
>
> Signed-off-by: Chris Brandt
> ---
> Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring
On Tue, 14 May 2019 09:55:56 -0500, Chris Brandt wrote:
> Document the optional dr_mode property
>
> Signed-off-by: Chris Brandt
> ---
> Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Rob Herring
gt; * document that 'usb_x1' clock node will be detected to determine if
>48MHz clock exists
> ---
> Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring
property
> ---
> .../devicetree/bindings/usb/mediatek,mtu3.txt | 10 ++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Rob Herring
On Tue, May 14, 2019 at 04:47:19PM +0800, Chunfeng Yun wrote:
> It's used to support dual role switch via GPIO when use Type-B
> receptacle, typically the USB ID pin is connected to an input
> GPIO pin
>
> Signed-off-by: Chunfeng Yun
> ---
> v5 changes:
> 1. treat type-B connector as child devic
-
> Changes in v3:
> -None
>
> Changes in v2
> 1. As suggested by Thinh Nguyen changed the "snps,dis_u1_entry_quirk"
> to "snps,dis-u1-entry-quirk"
> ---
> Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rob Herring
devicetree/bindings/usb/generic.txt | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring
On Sat, May 4, 2019 at 10:13 PM Peter Chen wrote:
>
>
> > > ---
> > > arch/arm/boot/dts/imx7ulp.dtsi | 30 ++
> > > 1 file changed, 30 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > > b/arch/arm/boot/dts/imx7ulp.dtsi index fca6e50f37c8..e2944
On Sun, 28 Apr 2019 02:51:20 +, Peter Chen wrote:
> Add compatible string for imx7ulp.
>
> Signed-off-by: Peter Chen
> ---
> Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Sun, 28 Apr 2019 02:51:13 +, Peter Chen wrote:
> Add compatible for 7ulp USB PHY.
>
> Signed-off-by: Peter Chen
> ---
> Documentation/devicetree/bindings/phy/mxs-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Sun, Apr 28, 2019 at 08:27:46PM +0800, Chunfeng Yun wrote:
> Add a property usb-role-switch to tell Dual-Role controller driver
> that use USB Role Switch framework to handle the role switch between
> host mode and device mode, it's useful when the driver has already
> supported other ways, such
On Sun, 28 Apr 2019 02:51:23 +, Peter Chen wrote:
> Add compatible string for imx7ulp
>
> Signed-off-by: Peter Chen
> ---
> Documentation/devicetree/bindings/usb/usbmisc-imx.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Sat, Apr 27, 2019 at 9:51 PM Peter Chen wrote:
>
> Add imx7ulp USBOTG1 support.
>
> Signed-off-by: Peter Chen
> ---
> arch/arm/boot/dts/imx7ulp.dtsi | 30 ++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7
On Mon, Mar 11, 2019 at 10:40:09AM +, Jun Li wrote:
> Some typec super speed active channel switch can be controlled via
> a GPIO, this binding can be used to specify the switch node by
> a GPIO and the remote endpoint of its consumer.
>
> Signed-off-by: Li Jun
> ---
> .../devicetree/binding
On Sun, Feb 24, 2019 at 7:36 PM Min Guo wrote:
>
> Hi Rob,
> On Fri, 2019-02-22 at 10:49 -0600, Rob Herring wrote:
> > On Tue, Feb 19, 2019 at 03:36:30PM +0800, min@mediatek.com wrote:
> > > From: Min Guo
> > >
> > > This adds support for MediaTek
On Tue, Feb 12, 2019 at 04:14:09PM +0100, Neil Armstrong wrote:
> Adds the bindings for the Amlogic G12A USB Glue HW.
>
> The Amlogic G12A SoC Family embeds 2 USB Controllers :
> - a DWC3 IP configured as Host for USB2 and USB3
> - a DWC2 IP configured as Peripheral USB2 Only
>
> A glue connects
rtion(+)
>
Reviewed-by: Rob Herring
; create mode 100644
> Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
>
Reviewed-by: Rob Herring
On Mon, Feb 25, 2019 at 10:57 PM Srinath Mannam
wrote:
>
> Hi Rob,
> Thanks for the review, Please see my comments below in line.
>
> Regards,
> Srinath.
> On Tue, Feb 26, 2019 at 3:08 AM Rob Herring wrote:
> >
> > On Tue, Feb 05, 2019 at 11:48:53AM +0530, Srinat
On Tue, 26 Feb 2019 06:59:21 +, Ran Wang wrote:
> When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
> (or its control signal) will turn on immediately on related Root Hub
> ports. Then the VBUS will be de-asserted for a little while during xhci
> reset (conducted by xhci dri
On Sun, Feb 03, 2019 at 12:59:07AM +0100, Linus Walleij wrote:
> This adds device tree bindings for the PXA25x USB Device
> Controller as found in the PXA25x and the IXP4xx.
>
> Cc: Robert Jarzmik
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Linus Walleij
> ---
> .../devicetree/bindings/us
On Tue, Feb 05, 2019 at 11:48:53AM +0530, Srinath Mannam wrote:
> Add usb-phy-port-reset optional property to set quirk in xhci platform
> driver which forces USB port PHY reset on port disconnect event.
>
> Signed-off-by: Srinath Mannam
> Reviewed-by: Ray Jui
> ---
> Documentation/devicetree/b
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring
On Tue, Jan 22, 2019 at 10:37:17AM +, Jun Li wrote:
> The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock
> source to a small part of the USB3 core that operates when the
> SS PHY is in its lowest power(P3) state, and therefore does
> not provide a clock. The power down scale specifies
b/dwc3.txt |3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
Reviewed-by: Rob Herring
On Tue, Feb 19, 2019 at 03:36:30PM +0800, min@mediatek.com wrote:
> From: Min Guo
>
> This adds support for MediaTek musb controller in
> host, peripheral and otg mode.
>
> Signed-off-by: Min Guo
> ---
> changes in v5:
> suggested by Rob:
> 1. Modify compatible as
> - compatible : should b
On Mon, Feb 18, 2019 at 9:03 PM Chunfeng Yun wrote:
>
> Hi,
> On Tue, 2019-02-19 at 09:50 +0800, Chen Yu wrote:
> > Hi,
> >
> > On 2019/2/19 4:18, Rob Herring wrote:
> > > On Mon, Feb 18, 2019 at 07:23:01PM +0800, Yu Chen wrote:
> > >> This pat
On Mon, Feb 18, 2019 at 07:23:01PM +0800, Yu Chen wrote:
> This patch adds binding documentation for supporting the hi3660 usb
> phy on boards like the HiKey960.
>
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: John Stultz
> Cc: Binghui Wang
> Signed-off-by: Yu Chen
; 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/cdns-usb3.txt
>
Reviewed-by: Rob Herring
On Thu, Feb 14, 2019 at 12:08 AM Pawel Laszczak wrote:
>
> Hi Rob,
> >On Thu, Jan 31, 2019 at 11:52:28AM +, Pawel Laszczak wrote:
> >> This patch aim at documenting USB related dt-bindings for the
> >> Cadence USBSS-DRD controller.
> >>
> >> Signed-off-by: Pawel Laszczak
> >> ---
> >> .../de
On Thu, Jan 31, 2019 at 11:52:28AM +, Pawel Laszczak wrote:
> This patch aim at documenting USB related dt-bindings for the
> Cadence USBSS-DRD controller.
>
> Signed-off-by: Pawel Laszczak
> ---
> .../devicetree/bindings/usb/cdns-usb3.txt | 33 +++
> 1 file changed, 33 i
e Ramirez-Ortiz
> ---
> Documentation/devicetree/bindings/connector/usb-connector.txt | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring
; delete mode 100644
> Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
>
Reviewed-by: Rob Herring
On Thu, Feb 07, 2019 at 12:17:33PM +0100, Jorge Ramirez-Ortiz wrote:
> Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed phy
> controller embedded in QCS404.
>
> Based on Sriharsha Allenki's original
> definitions.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
> .../bindings/phy/qcom
On Wed, Feb 6, 2019 at 8:11 AM Jorge Ramirez
wrote:
>
> On 2/5/19 12:02, Jorge Ramirez wrote:
> > On 1/30/19 21:02, Rob Herring wrote:
> >> On Tue, Jan 29, 2019 at 12:35:14PM +0100, Jorge Ramirez-Ortiz wrote:
> >>> Binding description for Qualcomm's Synopsys
On Tue, Jan 29, 2019 at 12:35:14PM +0100, Jorge Ramirez-Ortiz wrote:
> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> controller embedded in QCS404.
>
> Based on Sriharsha Allenki's original
> definitions.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
> .../devicetree/bindi
On Tue, Jan 29, 2019 at 12:35:13PM +0100, Jorge Ramirez-Ortiz wrote:
> This set adds USB SS PHY support to Qualcomm's QCS404 SoC
> The PHY is implemented using Synopsys SS PHY 1.0.0 IP
>
> The code is losely based on Sriharsha Allenki's
> original implementation.
>
> v2:
> enable OTG mode dete
On Mon, Jan 21, 2019 at 02:32:46PM -0700, Jeffrey Hugo wrote:
> msm8998 USB has a dwc3 controller just like the existing sdm845 support.
>
> Signed-off-by: Jeffrey Hugo
> Reviewed-by: Bjorn Andersson
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 1 +
> 1 file changed, 1 insertio
On Mon, Jan 21, 2019 at 9:49 AM Gregory CLEMENT
wrote:
>
> Hi Rob,
>
> On lun., janv. 21 2019, Rob Herring wrote:
>
> > On Mon, 21 Jan 2019 12:23:32 +0100, Miquel Raynal wrote:
> >> Add bindings for Marvell Armada 3700 USB2 UTMI+ PHY.
> >
On Mon, Jan 21, 2019 at 8:38 PM Ran Wang wrote:
>
> Hi Rob,
>
> On January 22, 2019 09:03, Rob Herring wrote:
> >
> > On Wed, Jan 16, 2019 at 06:48:06AM +, Ran Wang wrote:
> > > When DWC3 is set to host mode by programming register DWC3_GCTL,
> > VUBS
&g
On Tue, Jan 22, 2019 at 3:09 AM wrote:
>
> Hi Rob,
>
> On 22/01/2019 at 02:10, Rob Herring wrote:
> > On Wed, Jan 16, 2019 at 10:57:40AM +0100, Nicolas Ferre wrote:
> >> This removes a line left while adding the correct compatibility string for
> >> sama5d3
On Tue, Jan 22, 2019 at 3:00 AM wrote:
>
> Hi Rob,
>
> On 22/01/2019 at 02:07, Rob Herring wrote:
> > On Wed, Jan 16, 2019 at 10:57:38AM +0100, Nicolas Ferre wrote:
> >> Update the Reset Controller's binding to add new SoC compatibility string.
> &
On Wed, Jan 16, 2019 at 10:57:40AM +0100, Nicolas Ferre wrote:
> This removes a line left while adding the correct compatibility string for
> sama5d3 10/100 interface. Now use the "atmel,sama5d3-macb" string.
>
> Signed-off-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/net/macb.txt
On Wed, Jan 16, 2019 at 10:57:38AM +0100, Nicolas Ferre wrote:
> Update the Reset Controller's binding to add new SoC compatibility string.
>
> Signed-off-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/D
ed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rob Herring
On Wed, Jan 16, 2019 at 06:48:06AM +, Ran Wang wrote:
> When DWC3 is set to host mode by programming register DWC3_GCTL, VUBS
s/VUBS/VBUS/
> (or its control signal) will on immediately on related Root Hub ports.
/will on/will turn on/
> Then the VUBS will be de-asserted for a little while d
3 +++
> arch/x86/platform/olpc/olpc_dt.c | 3 +++
> arch/x86/xen/p2m.c| 11 +--
> arch/xtensa/mm/kasan_init.c | 4
> arch/xtensa/mm/mmu.c | 3 +++
> drivers/clk/ti/clk.c | 3 +++
> driv
100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
>
Reviewed-by: Rob Herring
On Mon, Jan 21, 2019 at 08:22:26PM +0800, min@mediatek.com wrote:
> From: Min Guo
>
> This adds support for MediaTek musb controller in
> host, peripheral and otg mode.
>
> Signed-off-by: Min Guo
> ---
> changes in v4:
> suggested by Sergei:
> 1. String alignment
>
> changes in v3:
> 1. no
On Mon, 14 Jan 2019 09:36:27 -0700, Jeffrey Hugo wrote:
> msm8998 USB has a dwc3 controller just like the existing sdm845 support
>
> Signed-off-by: Jeffrey Hugo
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Wed, Jan 16, 2019 at 02:20:21PM +0100, Miquel Raynal wrote:
> Hi Rob,
>
> Rob Herring wrote on Tue, 15 Jan 2019 15:44:29 -0600:
>
> > On Fri, Jan 11, 2019 at 02:31:29PM +0100, Miquel Raynal wrote:
> > > Add bindings for Marvell Armada 3700 USB2 UTMI+ PHY.
> &g
y: Richard Leitner
> ---
> Changes:
> v3:
> - no changes
> v2:
> - rename property s/sw-dx-lanes-ports/swap-dx-lanes
>
> Documentation/devicetree/bindings/usb/usb251xb.txt | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring
off-by: Philipp Puschmann
> ---
> Changes in v3: add description
> ---
> Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Fri, Jan 11, 2019 at 02:31:29PM +0100, Miquel Raynal wrote:
> Add bindings for Marvell Armada 3700 USB2 UTMI+ PHY.
>
> Signed-off-by: Miquel Raynal
> ---
> .../bindings/phy/phy-mvebu-utmi.txt | 37 +++
> 1 file changed, 37 insertions(+)
> create mode 100644 Document
tions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring
On Fri, Jan 04, 2019 at 09:50:47AM -0700, Jeffrey Hugo wrote:
> MSM8998 contains a single QMP v3 USB3 phy similar to the existing sdm845
> support, however MSM8998 does not have display port (DP) support.
>
> Signed-off-by: Jeffrey Hugo
> ---
> .../devicetree/bindings/phy/qcom-qmp-phy.txt
On Fri, Jan 4, 2019 at 5:21 AM Andreas Färber wrote:
>
> Ignore our device in cdc-acm probing and add a new driver for it,
> dispatching to cdc-acm for the actual implementation.
>
> WARNING: It is likely that this VID/PID is in use for unrelated devices.
> Only the Product string hints what this
On Thu, Jan 3, 2019 at 9:00 PM Min Guo wrote:
>
> On Thu, 2019-01-03 at 16:14 -0600, Rob Herring wrote:
> > On Thu, Dec 27, 2018 at 03:34:23PM +0800, min@mediatek.com wrote:
> > > From: Min Guo
> > >
> > > This adds support for MediaTek musb controller
On Thu, Dec 27, 2018 at 03:34:23PM +0800, min@mediatek.com wrote:
> From: Min Guo
>
> This adds support for MediaTek musb controller in
> host, peripheral and otg mode
>
> Signed-off-by: Min Guo
> ---
> .../devicetree/bindings/usb/mediatek,musb.txt | 49
> ++
> 1
On Wed, Dec 19, 2018 at 03:59:40PM +0100, Marco Felsch wrote:
> Add optional binding to allow USB differential-pair (D+/D-) data lane
> swapping. The swapping can be specified for each port separately,
> default is no swapping.
>
> Signed-off-by: Marco Felsch
> ---
> Documentation/devicetree/bin
On Sat, Dec 22, 2018 at 4:24 PM Pawel Laszczak wrote:
>
> Hi Rob,
>
> >On Mon, Dec 10, 2018 at 12:39:14PM +, Pawel Laszczak wrote:
> >> This patch aim at documenting USB related dt-bindings for the
> >> Cadence USBSS-DRD controller.
> >>
> >> Signed-off-by: Pawel Laszczak
[...]
> >> + - phy
On Thu, Dec 20, 2018 at 6:22 PM Thinh Nguyen wrote:
>
> Hi,
>
> On 12/19/2018 10:48 PM, Felipe Balbi wrote:
> > Hi,
> >
> > Thinh Nguyen writes:
> >>>> On 12/18/2018 8:39 AM, Rob Herring wrote:
> >>>>> On Fri, Dec 07, 2018 at 06:27
On Thu, 13 Dec 2018 20:22:18 +, Fabrizio Castro wrote:
> Document RZ/G2E (R8A774C0) SoC bindings.
>
> Signed-off-by: Fabrizio Castro
> ---
> Documentation/devicetree/bindings/usb/renesas_usb3.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Thu, 13 Dec 2018 20:21:03 +, Fabrizio Castro wrote:
> Document RZ/G2E (R8A774C0) SoC bindings.
>
> Signed-off-by: Fabrizio Castro
> ---
> Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
On Thu, 13 Dec 2018 20:21:11 +, Fabrizio Castro wrote:
> Document RZ/G2E (R8A774C0) SoC bindings.
>
> Signed-off-by: Fabrizio Castro
> ---
> Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring
--
> .../bindings/usb/ingenic,jz4740-musb.txt | 24
> ++
> 1 file changed, 24 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/usb/ingenic,jz4740-musb.txt
>
Reviewed-by: Rob Herring
On Mon, Dec 10, 2018 at 12:39:14PM +, Pawel Laszczak wrote:
> This patch aim at documenting USB related dt-bindings for the
> Cadence USBSS-DRD controller.
>
> Signed-off-by: Pawel Laszczak
> ---
> .../devicetree/bindings/usb/cdns3-usb.txt | 31 +++
> 1 file changed, 31 i
On Thu, Dec 20, 2018 at 10:52:45AM +0100, Jorge Ramirez-Ortiz wrote:
> On 07/12/18 10:55:57, Jorge Ramirez-Ortiz wrote:
> > Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> > controller embedded in QCS404.
> >
> > Based on Sriharsha Allenki's original
> > definitions.
> >
> >
On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> controller embedded in QCS404.
>
> Based on Sriharsha Allenki's original
> definitions.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> Reviewed-by: Vinod Koul
>
On Thu, Dec 20, 2018 at 12:52 AM Felipe Balbi wrote:
>
>
> Hi,
>
> Rob Herring writes:
> > On Fri, Dec 07, 2018 at 06:27:43PM -0800, Thinh Nguyen wrote:
> >> This patch adds a property to enable the controller to track the
> >> frame number based on the re
On Thu, Dec 20, 2018 at 12:46 AM Felipe Balbi
wrote:
>
>
> Hi,
>
> Rob Herring writes:
> >> >>>> +Example:
> >> >>>> +usb3: hisi_dwc3 {
> >> >>>> +compatible = "hisilicon,hi3660-
On Mon, Dec 03, 2018 at 11:45:06AM +0800, Yu Chen wrote:
> This patch adds binding documentation to support usb hub and usb
> data role switch of Hisilicon HiKey&HiKey960 Board.
>
> Cc: Sergei Shtylyov
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: John Stultz
> Cc: B
On Mon, Dec 03, 2018 at 11:45:05AM +0800, Yu Chen wrote:
> This patch adds binding documentation for supporting the hi3660 usb
> phy on boards like the HiKey960.
>
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: John Stultz
> Cc: Binghui Wang
> Signed-off-by: Yu Chen
&g
> on HiSilicon SoCs and boards like the HiKey960.
> >>>>
> >>>> Cc: Greg Kroah-Hartman
> >>>> Cc: Rob Herring
> >>>> Cc: Mark Rutland
> >>>> Cc: John Stultz
> >>>> Signed-off-by: Yu Chen
> >>>> ---
On Tue, Dec 18, 2018 at 6:22 PM Thinh Nguyen wrote:
>
> Hi Rob,
>
> On 12/18/2018 8:39 AM, Rob Herring wrote:
> > On Fri, Dec 07, 2018 at 06:27:30PM -0800, Thinh Nguyen wrote:
> >> This patch introduces property "snps,refclk-period-ns" to inform the
> >
On Fri, Dec 07, 2018 at 06:27:43PM -0800, Thinh Nguyen wrote:
> This patch adds a property to enable the controller to track the
> frame number based on the reference clock.
>
> When operating in USB 2.0 mode, the peripheral controller uses the USB2
> PHY clocks to track the frame number. This pre
On Fri, Dec 07, 2018 at 06:27:30PM -0800, Thinh Nguyen wrote:
> This patch introduces property "snps,refclk-period-ns" to inform the
> controller of the reference clock period. If the reference clock period
> is different from the default Core Consultant setting, then this
> property can be set to
" state.
>
> Signed-off-by: Peter Chen
> ---
> .../devicetree/bindings/usb/ci-hdrc-usb2.txt | 31
> +-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring
On Tue, Nov 27, 2018 at 04:57:05PM +, David R. Piegdon wrote:
> Hi,
>
> on our embedded systems we rely on systemd's persistent netdev names.
> Those currently do not work for USB netdevs that are connected to a
> platform USB bus.
>
> In https://github.com/systemd/systemd/pull/7273 a systemd
On Wed, Dec 05, 2018 at 07:57:37AM +, PETER CHEN wrote:
>
> > On 04.12.18 21:01, Fabio Estevam wrote:
> > > Hi Frieder,
> > >
> > > On Tue, Dec 4, 2018 at 12:31 PM Schrempf Frieder
> > > wrote:
> > >
> > >> There are many other optional properties for this driver and a lot of
> > >> them are
On Sun, Nov 18, 2018 at 10:08:59AM +, Pawel Laszczak wrote:
> Thsi patch aim at documenting USB related dt-bindings for the
typo
> Cadence USBSS-DRD controller.
>
> Signed-off-by: Pawel Laszczak
> ---
> .../devicetree/bindings/usb/cdns3-usb.txt | 17 +
> 1 file change
On Fri, Nov 16, 2018 at 8:29 PM Chen Yu wrote:
>
> Hi,
>
> On 2018/11/13 0:02, Rob Herring wrote:
> > On Sat, Oct 27, 2018 at 05:58:11PM +0800, Yu Chen wrote:
> >> This patch adds binding descriptions to support the dwc3 controller
> >> on HiSilicon SoCs and bo
s changed, 28 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/usb/brcm,bcm7445-ehci.txt
>
Reviewed-by: Rob Herring
On Thu, Nov 15, 2018 at 11:32:53AM -0800, Prakruthi Deepak Heragu wrote:
> Documentation for Embedded USB Debugger (EUD) device tree bindings.
I asked questions on v2 which were never answered.
>
> Signed-off-by: Satya Durga Srinivasu Prabhala
> Signed-off-by: Prakruthi Deepak Heragu
> ---
>
sable the SW workaround when it is not needed.
>
> Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
> endpoints.
>
> Signed-off-by: Thinh Nguyen
> ---
> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
> 1 file changed, 3 insertions(+)
Acked-by: Rob Herring
t; Signed-off-by: Badhri Jagan Sridharan
>
> Rob, I can see you acked one of the patches modifying tcpm.c in this
> series, but did you mean to put the tag to this patch instead?
Hum, indeed. Looks like a scripting fail in my reply. The R-by was for this one.
Reviewed-by: Rob Herring
Rob
44
> Documentation/devicetree/bindings/usb/brcm,bcm7445-ohci.txt
> create mode 100644
> Documentation/devicetree/bindings/usb/brcm,bcm7445-xhci.txt
>
Reviewed-by: Rob Herring
On Wed, Sep 26, 2018 at 06:20:10PM -0400, Al Cooper wrote:
> Add DT bindings document for Broadcom STB USB OHCI, EHCI and
> XHCI drivers.
>
> Signed-off-by: Al Cooper
> ---
> .../devicetree/bindings/usb/brcm,ehci-brcm.txt | 22 +
> .../devicetree/bindings/usb/brcm,ohci-br
s/usb/typec/tcpm/tcpm.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring
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