[PATCH v5 2/2] powerpc/hv-24x7: Add sysfs files inside hv-24x7 device to show cpumask

Patch here adds a cpumask attr to hv_24x7 pmu along with ABI documentation. Primary use to expose the cpumask is for the perf tool which has the capability to parse the driver sysfs folder and understand the cpumask file. Having cpumask file will reduce the number of perf command line parameters

[PATCH v5 0/2] Add cpu hotplug support for powerpc/perf/hv-24x7

This patchset add cpu hotplug support for hv_24x7 driver by adding online/offline cpu hotplug function. It also add sysfs file "cpumask" to expose current online cpu that can be used for hv_24x7 event count. Changelog: v4 -> v5 - Since we are making PMU fail incase hotplug init failed, hence

[PATCH v5 1/2] powerpc/perf/hv-24x7: Add cpu hotplug support

Patch here adds cpu hotplug functions to hv_24x7 pmu. A new cpuhp_state "CPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE" enum is added. The online callback function updates the cpumask only if its empty. As the primary intention of adding hotplug support is to designate a CPU to make HCALL to collect the

Re: [RFC PATCH v0 2/2] KVM: PPC: Book3S HV: Use H_RPT_INVALIDATE in nested KVM

On Fri, Jul 03, 2020 at 04:14:20PM +0530, Bharata B Rao wrote: > In the nested KVM case, replace H_TLB_INVALIDATE by the new hcall > H_RPT_INVALIDATE if available. The availability of this hcall > is determined from "hcall-rpt-invalidate" string in ibm,hypertas-functions > DT property. What are

Re: [PATCH v5 1/4] riscv: Move kernel mapping to vmalloc zone

On Sun, 07 Jun 2020 00:59:46 PDT (-0700), a...@ghiti.fr wrote: This is a preparatory patch for relocatable kernel. The kernel used to be linked at PAGE_OFFSET address and used to be loaded physically at the beginning of the main memory. Therefore, we could use the linear mapping for the kernel

Re: [PATCH v2 2/3] powerpc/64s: remove PROT_SAO support

On Fri, Jul 03, 2020 at 11:19:57AM +1000, Nicholas Piggin wrote: > ISA v3.1 does not support the SAO storage control attribute required to > implement PROT_SAO. PROT_SAO was used by specialised system software > (Lx86) that has been discontinued for about 7 years, and is not thought > to be used

[PATCH v2 2/5] powerpc/lib: Initialize a temporary mm for code patching

When code patching a STRICT_KERNEL_RWX kernel the page containing the address to be patched is temporarily mapped with permissive memory protections. Currently, a per-cpu vmalloc patch area is used for this purpose. While the patch area is per-cpu, the temporary page mapping is inserted into the

[PATCH v2 3/5] powerpc/lib: Use a temporary mm for code patching

Currently, code patching a STRICT_KERNEL_RWX exposes the temporary mappings to other CPUs. These mappings should be kept local to the CPU doing the patching. Use the pre-initialized temporary mm and patching address for this purpose. Also add a check after patching to ensure the patch succeeded.

[PATCH v2 5/5] powerpc: Add LKDTM test to hijack a patch mapping

When live patching with STRICT_KERNEL_RWX, the CPU doing the patching must use a temporary mapping which allows for writing to kernel text. During the entire window of time when this temporary mapping is in use, another CPU could write to the same mapping and maliciously alter kernel text.

Re: [PATCH 1/1] KVM/PPC: Fix typo on H_DISABLE_AND_GET hcall

On Mon, Jul 06, 2020 at 09:48:12PM -0300, Leonardo Bras wrote: > On PAPR+ the hcall() on 0x1B0 is called H_DISABLE_AND_GET, but got > defined as H_DISABLE_AND_GETC instead. > > This define was introduced with a typo in commit > ("[PATCH] powerpc: Extends HCALL interface for InfiniBand usage"),

[PATCH 0/5] Use per-CPU temporary mappings for patching

When compiled with CONFIG_STRICT_KERNEL_RWX, the kernel must create temporary mappings when patching itself. These mappings temporarily override the strict RWX text protections to permit a write. Currently, powerpc allocates a per-CPU VM area for patching. Patching occurs as follows: 1.

[PATCH v2 1/5] powerpc/mm: Introduce temporary mm

x86 supports the notion of a temporary mm which restricts access to temporary PTEs to a single CPU. A temporary mm is useful for situations where a CPU needs to perform sensitive operations (such as patching a STRICT_KERNEL_RWX kernel) requiring temporary mappings without exposing said mappings to

[PATCH v2 4/5] powerpc/lib: Add LKDTM accessor for patching addr

When live patching a STRICT_RWX kernel, a mapping is installed at a "patching address" with temporary write permissions. Provide a LKDTM-only accessor function for this address in preparation for a LKDTM test which attempts to "hijack" this mapping by writing to it from another CPU.

Re: [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc

> On 08-Jul-2020, at 5:34 PM, Michael Ellerman wrote: > > Athira Rajeev > writes: >> From: Anju T Sudhakar >> >> Add extended regs to sample_reg_mask in the tool side to use >> with `-I?` option. Perf tools side uses extended mask to display >> the

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

> On 08-Jul-2020, at 5:12 PM, Michael Ellerman wrote: > > Athira Rajeev > writes: > >> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). > ^ > a >> First is the addition of BHRB disable bit and

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

> On 08-Jul-2020, at 1:13 PM, Gautham R Shenoy wrote: > > On Tue, Jul 07, 2020 at 05:17:55PM +1000, Michael Neuling wrote: >> On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote: >>> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). >>> First is the addition of BHRB

Re: [PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs

> On 08-Jul-2020, at 4:34 PM, Michael Ellerman wrote: > > Athira Rajeev > writes: >> From: Madhavan Srinivasan >> >> PowerISA v3.1 added three new perfromance >> monitoring unit (PMU) speical purpose register (SPR). >> They are Monitor Mode Control

Re: [PATCH V4 0/3] arm64: Enable vmemmap mapping from device memory

On 07/06/2020 08:26 AM, Anshuman Khandual wrote: > This series enables vmemmap backing memory allocation from device memory > ranges on arm64. But before that, it enables vmemmap_populate_basepages() > and vmemmap_alloc_block_buf() to accommodate struct vmem_altmap based > alocation requests. >

[PATCH v6 23/23] powerpc/book3s64/pkeys: Remove is_pkey_enabled()

There is only one caller to this function and the function is wrongly named. Avoid further confusion w.r.t name and open code this at the only call site. Also remove read_uamor(). There are no users for the same after this. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/book3s64/pkeys.c |

[PATCH v6 22/23] powerpc/selftest/ptrace-pkey: Don't update expected UAMOR value

with commit: 4a4a5e5d2aad ("powerpc/pkeys: key allocation/deallocation must not change pkey registers") we are not updating UAMOR on key allocation. So don't update the expected uamor value in the test. Fixes: 4a4a5e5d2aad ("powerpc/pkeys: key allocation/deallocation must not change pkey

[PATCH v6 21/23] powerpc/selftest/ptrace-pkey: Update the test to mark an invalid pkey correctly

Signed-off-by: Aneesh Kumar K.V --- .../selftests/powerpc/ptrace/ptrace-pkey.c| 30 --- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c b/tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c index

[PATCH v6 19/23] powerpc/book3s64/kuap: Move UAMOR setup to key init function

UAMOR values are not application-specific. The kernel initializes its value based on different reserved keys. Remove the thread-specific UAMOR value and don't switch the UAMOR on context switch. Move UAMOR initialization to key initialization code and remove thread_struct.uamor because it is not

[PATCH v6 18/23] powerpc/book3s64/keys/kuap: Reset AMR/IAMR values on kexec

As we kexec across kernels that use AMR/IAMR for different purposes we need to ensure that new kernels get kexec'd with a reset value of AMR/IAMR. For ex: the new kernel can use key 0 for kernel mapping and the old AMR value prevents access to key 0. This patch also removes reset if IAMR and AMOR

[PATCH v6 20/23] powerpc/selftest/ptrave-pkey: Rename variables to make it easier to follow code

Rename variable to indicate that they are invalid values which we will use to test ptrace update of pkeys. Signed-off-by: Aneesh Kumar K.V --- .../selftests/powerpc/ptrace/ptrace-pkey.c| 26 +-- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git

[PATCH v6 17/23] powerpc/book3s64/keys: Print information during boot.

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/book3s64/pkeys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/mm/book3s64/pkeys.c b/arch/powerpc/mm/book3s64/pkeys.c index f388c8d5359a..c682eefd3fc1 100644 --- a/arch/powerpc/mm/book3s64/pkeys.c +++

[PATCH v6 16/23] powerpc/book3s64/pkeys: Use MMU_FTR_PKEY instead of pkey_disabled static key

Instead of pkey_disabled static key use mmu feature MMU_FTR_PKEY. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/pkeys.h | 2 +- arch/powerpc/include/asm/pkeys.h | 14 ++ arch/powerpc/mm/book3s64/pkeys.c | 17 +++-- 3 files

[PATCH v6 15/23] powerpc/book3s64/pkeys: Use pkey_execute_disable_supported

Use pkey_execute_disable_supported to check for execute key support instead of pkey_disabled. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/pkeys.h | 10 +- arch/powerpc/mm/book3s64/pkeys.c | 6 +++--- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git

[PATCH v6 14/23] powerpc/book3s64/kuep: Add MMU_FTR_KUEP

This will be used to enable/disable Kernel Userspace Execution Prevention (KUEP). Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/mmu.h | 8 arch/powerpc/mm/book3s64/radix_pgtable.c | 4 +++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git

[PATCH v6 13/23] powerpc/book3s64/pkeys: Add MMU_FTR_PKEY

Parse storage keys related device tree entry in early_init_devtree and enable MMU feature MMU_FTR_PKEY if pkeys are supported. MMU feature is used instead of CPU feature because this enables us to group MMU_FTR_KUAP and MMU_FTR_PKEY in asm feature fixup code. Signed-off-by: Aneesh Kumar K.V ---

[PATCH v6 12/23] powerpc/book3s64/pkeys: Mark all the pkeys above max pkey as reserved

The hypervisor can return less than max allowed pkey (for ex: 31) instead of 32. We should mark all the pkeys above max allowed as reserved so that we avoid the allocation of the wrong pkey(for ex: key 31 in the above case) by userspace. Signed-off-by: Aneesh Kumar K.V ---

[PATCH v6 11/23] powerpc/book3s64/pkeys: Make initial_allocation_mask static

initial_allocation_mask is not used outside this file. Also mark reserved_allocation_mask and initial_allocation_mask __ro_after_init; Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/pkeys.h | 1 - arch/powerpc/mm/book3s64/pkeys.c | 7 +-- 2 files changed, 5 insertions(+), 3

[PATCH v6 10/23] powerpc/book3s64/pkeys: Convert pkey_total to num_pkey

num_pkey now represents max number of keys supported such that we return to userspace 0 - num_pkey - 1. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/pkeys.h | 7 +-- arch/powerpc/mm/book3s64/pkeys.c | 14 +++--- 2 files changed, 12 insertions(+), 9 deletions(-)

[PATCH v6 09/23] powerpc/book3s64/pkeys: Simplify pkey disable branch

Make the default value FALSE (pkey enabled) and set to TRUE when we find the total number of keys supported to be zero. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/pkeys.h | 2 +- arch/powerpc/mm/book3s64/pkeys.c | 7 +++ 2 files changed, 4 insertions(+), 5 deletions(-)

[PATCH v6 08/23] powerpc/book3s64/pkeys: kill cpu feature key CPU_FTR_PKEY

We don't use CPU_FTR_PKEY anymore. Remove the feature bit and mark it free. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/cputable.h | 13 ++--- arch/powerpc/kernel/dt_cpu_ftrs.c | 6 -- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git

[PATCH v6 07/23] powerpc/book3s64/pkeys: Prevent key 1 modification from userspace.

Key 1 is marked reserved by ISA. Setup uamor to prevent userspace modification of the same. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/book3s64/pkeys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/mm/book3s64/pkeys.c b/arch/powerpc/mm/book3s64/pkeys.c index

[PATCH v6 06/23] powerpc/book3s64/pkeys: Simplify the key initialization

Add documentation explaining the execute_only_key. The reservation and initialization mask details are also explained in this patch. No functional change in this patch. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/book3s64/pkeys.c | 199 ++- 1 file changed,

[PATCH v6 05/23] powerpc/book3s64/pkeys: Explain key 1 reservation details

This explains the details w.r.t key 1. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/book3s64/pkeys.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/book3s64/pkeys.c b/arch/powerpc/mm/book3s64/pkeys.c index d69b4cfc5792..6ff9fe4112ef 100644 ---

[PATCH v6 04/23] powerpc/book3s64/pkeys: Move pkey related bits in the linux page table

To keep things simple, all the pkey related bits are kept together in linux page table for 64K config with hash translation. With hash-4k kernel requires 4 bits to store slots details. This is done by overloading some of the RPN bits for storing the slot details. Due to this PKEY_BIT0 on the 4K

[PATCH v6 03/23] powerpc/book3s64/pkeys: pkeys are supported only on hash on book3s.

Move them to hash specific file and add BUG() for radix path. --- .../powerpc/include/asm/book3s/64/hash-pkey.h | 32 arch/powerpc/include/asm/book3s/64/pkeys.h| 25 + arch/powerpc/include/asm/pkeys.h | 37 --- 3 files changed, 64

[PATCH v6 02/23] powerpc/book3s64/pkeys: Fixup bit numbering

This number the pkey bit such that it is easy to follow. PKEY_BIT0 is the lower order bit. This makes further changes easy to follow. No functional change in this patch other than linux page table for hash translation now maps pkeys differently. Signed-off-by: Aneesh Kumar K.V ---

[PATCH v6 01/23] powerpc/book3s64/pkeys: Use PVR check instead of cpu feature

We are wrongly using CPU_FTRS_POWER8 to check for P8 support. Instead, we should use PVR value. Now considering we are using CPU_FTRS_POWER8, that implies we returned true for P9 with older firmware. Keep the same behavior by checking for P9 PVR value. Fixes: cf43d3b26452 ("powerpc: Enable pkey

[PATCH v6 00/23] powerpc/book3s/64/pkeys: Simplify the code

This patch series update the pkey subsystem with more documentation and rename variables so that it is easy to follow the code. We drop the changes to support KUAP/KUEP with hash translation in this update. The changes are adding 200 cycles to null syscalls benchmark and I want to look at that

[powerpc:merge] BUILD SUCCESS 71d6070a8e0e0a1ed82365544f97b86475cb161e

allmodconfig powerpc defconfig powerpc allyesconfig powerpc rhel-kconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a002-20200708 i386

[powerpc:next-test] BUILD SUCCESS 18fcf96cb354eb003297e14b1e19c1f7c067c49b

allmodconfig powerpc allnoconfig i386 randconfig-a002-20200708 i386 randconfig-a001-20200708 i386 randconfig-a006-20200708 i386 randconfig-a005-20200708 i386 randconfig-a004-20200708 i386

[powerpc:fixes-test] BUILD SUCCESS 4557ac6b344b8cdf948ff8b007e8e1de34832f2e

allmodconfig powerpc defconfig powerpc allyesconfig powerpc rhel-kconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a002-20200708 i386

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

> On 08-Jul-2020, at 4:32 PM, Michael Ellerman wrote: > > Athira Rajeev writes: > ... >> diff --git a/arch/powerpc/perf/core-book3s.c >> b/arch/powerpc/perf/core-book3s.c >> index cd6a742..5c64bd3 100644 >> --- a/arch/powerpc/perf/core-book3s.c >> +++ b/arch/powerpc/perf/core-book3s.c >> @@

Re: powerpc: Incorrect stw operand modifier in __set_pte_at

On Wed, Jul 08, 2020 at 06:16:54PM +0200, Christophe Leroy wrote: > Le 08/07/2020 à 16:45, Mathieu Desnoyers a écrit : > >Reviewing use of the patterns "Un%Xn" with lwz and stw instructions > >(where n should be the operand number) within the Linux kernel led > >me to spot those 2 weird cases: > >

Re: Failure to build librseq on ppc

On Wed, Jul 08, 2020 at 08:01:23PM -0400, Mathieu Desnoyers wrote: > > > #define RSEQ_ASM_OP_CMPEQ(var, expect, label) > > > \ > > > LOAD_WORD "%%r17, %[" __rseq_str(var) "]\n\t" > > > \ > > > > The way this hardcodes r17

Re: Failure to build librseq on ppc

On Wed, Jul 08, 2020 at 10:32:20AM -0400, Mathieu Desnoyers wrote: > > As far as I can see, %U is mentioned in > > https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html in the > > powerpc subpart, at the "m" constraint. > > Yep, I did notice it, but mistakenly thought it was only needed for

Re: [PATCH] powerpc/64s/exception: Fix 0x1500 interrupt handler crash

On Wed, 8 Jul 2020 17:49:42 +1000, Nicholas Piggin wrote: > A typo caused the interrupt handler to branch immediately to the common > "unknown interrupt" handler and skip the special case test for denormal > cause. > > This does not affect KVM softpatch handling (e.g., for POWER9 TM assist) >

Re: Failure to build librseq on ppc

Hi! On Wed, Jul 08, 2020 at 10:00:01AM -0400, Mathieu Desnoyers wrote: > >> So perhaps you have code like > >> > >> int *p; > >> int x; > >> ... > >> asm ("lwz %0,%1" : "=r"(x) : "m"(*p)); > > > > We indeed have explicit "lwz" and "stw" instructions in there. > > > >> > >> where that last

Re: Failure to build librseq on ppc

- Segher Boessenkool wrote: > Hi! > > On Wed, Jul 08, 2020 at 10:27:27PM +1000, Michael Ellerman wrote: > > Segher Boessenkool writes: > > > You'll have to show the actual failing machine code, and with enough > > > context that we can relate this to the source code. > > > > > >

Re: [PATCH v3 0/6] powerpc: queued spinlocks and rwlocks

On 7/8/20 7:50 PM, Waiman Long wrote: On 7/8/20 1:10 AM, Nicholas Piggin wrote: Excerpts from Waiman Long's message of July 8, 2020 1:33 pm: On 7/7/20 1:57 AM, Nicholas Piggin wrote: Yes, powerpc could certainly get more performance out of the slow paths, and then there are a few parameters

Re: [PATCH v3 0/6] powerpc: queued spinlocks and rwlocks

On 7/8/20 4:41 AM, Peter Zijlstra wrote: On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote: Yes, powerpc could certainly get more performance out of the slow paths, and then there are a few parameters to tune. Can you clarify? The slow path is already in use on ARM64 which is

Re: Failure to build librseq on ppc

Hi! On Wed, Jul 08, 2020 at 10:27:27PM +1000, Michael Ellerman wrote: > Segher Boessenkool writes: > > You'll have to show the actual failing machine code, and with enough > > context that we can relate this to the source code. > > > > -save-temps helps, or use -S instead of -c, etc. > >

Re: [PATCH v3 0/6] powerpc: queued spinlocks and rwlocks

On 7/8/20 4:32 AM, Peter Zijlstra wrote: On Tue, Jul 07, 2020 at 11:33:45PM -0400, Waiman Long wrote: From 5d7941a498935fb225b2c7a3108cbf590114c3db Mon Sep 17 00:00:00 2001 From: Waiman Long Date: Tue, 7 Jul 2020 22:29:16 -0400 Subject: [PATCH 2/9] locking/pvqspinlock: Introduce

Re: [PATCH v3 0/6] powerpc: queued spinlocks and rwlocks

On 7/8/20 1:10 AM, Nicholas Piggin wrote: Excerpts from Waiman Long's message of July 8, 2020 1:33 pm: On 7/7/20 1:57 AM, Nicholas Piggin wrote: Yes, powerpc could certainly get more performance out of the slow paths, and then there are a few parameters to tune. We don't have a good alternate

[PATCH 2/2] selftests/powerpc: Use proper error code to check fault address

ERR_NX_TRANSLATION (CSB.CC=5) is for internal to VAS for fault handling and should not used by OS. ERR_NX_AT_FAULT(CSB.CC=250) is the proper error code reported by OS when NX encounters address translation failure. This patch uses ERR_NX_AT_FAULT (CSB.CC=250) to determine the fault address when

[PATCH 1/2] powerpc/vas: Report proper error for address translation failure

DMA controller uses CC=5 internally for translation fault handling. So OS should be using CC=250 and should report this error to the user space when NX encounters address translation failure on the request buffer. Not an issue in earlier releases as NX does not get faults on kernel addresses.

Re: [PATCH v2 2/4] powerpc/mm/radix: Free PUD table when freeing pagetable

On Thu, Jun 25, 2020 at 12:15:45PM +0530, Aneesh Kumar K.V wrote: remove_pagetable() isn't freeing PUD table. This causes memory leak during memory unplug. Fix this. This has come up before: https://lore.kernel.org/linuxppc-dev/20190731061920.ga18...@in.ibm.com/ tl;dr, x86 intentionally does

Re: kernel since 5.6 do not boot anymore on Apple PowerBook

Le 08/07/2020 à 19:36, Giuseppe Sacco a écrit : Hi Cristophe, Il giorno mer, 08/07/2020 alle 19.09 +0200, Christophe Leroy ha scritto: Hi Le 08/07/2020 à 19:00, Giuseppe Sacco a écrit : Hello, while trying to debug a problem using git bisect, I am now at a point where I cannot build the

Re: [PATCH 3/3] misc: cxl: flash: Remove unused variable 'drc_index'

Hi Lee, I love your patch! Yet something to improve: [auto build test ERROR on char-misc/char-misc-testing] [also build test ERROR on soc/for-next linux/master linus/master v5.8-rc4 next-20200708] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch

[PATCH 1/1] powerpc: Fix incorrect stw{, ux, u, x} instructions in __set_pte_at

The placeholder for instruction selection should use the second argument's operand, which is %1, not %0. This could generate incorrect assembly code if the instruction selection for argument %0 ever differs from argument %1. Fixes: 9bf2b5cdc5fe ("powerpc: Fixes for CONFIG_PTE_64BIT for SMP

Re: kernel since 5.6 do not boot anymore on Apple PowerBook

Hi Cristophe, Il giorno mer, 08/07/2020 alle 19.09 +0200, Christophe Leroy ha scritto: > Hi > > Le 08/07/2020 à 19:00, Giuseppe Sacco a écrit : > > Hello, > > while trying to debug a problem using git bisect, I am now at a point > > where I cannot build the kernel at all. This is the error

Re: kernel since 5.6 do not boot anymore on Apple PowerBook

Hi Le 08/07/2020 à 19:00, Giuseppe Sacco a écrit : Hello, while trying to debug a problem using git bisect, I am now at a point where I cannot build the kernel at all. This is the error message I get: $ LANG=C make ARCH=powerpc \ CROSS_COMPILE=powerpc-linux- \

Re: kernel since 5.6 do not boot anymore on Apple PowerBook

Hello, while trying to debug a problem using git bisect, I am now at a point where I cannot build the kernel at all. This is the error message I get: $ LANG=C make ARCH=powerpc \ CROSS_COMPILE=powerpc-linux- \ CONFIG_MODULE_COMPRESS_GZIP=true \ INSTALL_MOD_STRIP=1 CONFIG_MODULE_COMPRESS=1 \

Re: powerpc: Incorrect stw operand modifier in __set_pte_at

Le 08/07/2020 à 16:45, Mathieu Desnoyers a écrit : Hi, Reviewing use of the patterns "Un%Xn" with lwz and stw instructions (where n should be the operand number) within the Linux kernel led me to spot those 2 weird cases: arch/powerpc/include/asm/nohash/pgtable.h:__set_pte_at()

Re: Failure to build librseq on ppc

Le 08/07/2020 à 16:32, Mathieu Desnoyers a écrit : - On Jul 8, 2020, at 10:21 AM, Christophe Leroy christophe.le...@csgroup.eu wrote: Le 08/07/2020 à 16:00, Mathieu Desnoyers a écrit : - On Jul 8, 2020, at 8:33 AM, Mathieu Desnoyers mathieu.desnoy...@efficios.com wrote: - On

[PATCH 5/5] powerpc: use the generic dma_ops_bypass mode

Use the DMA API bypass mechanism for direct window mappings. This uses common code and speed up the direct mapping case by avoiding indirect calls just when not using dma ops at all. It also fixes a problem where the sync_* methods were using the bypass check for DMA allocations, but those are

[PATCH 4/5] dma-mapping: add a dma_ops_bypass flag to struct device

Several IOMMU drivers have a bypass mode where they can use a direct mapping if the devices DMA mask is large enough. Add generic support to the core dma-mapping code to do that to switch those drivers to a common solution. Signed-off-by: Christoph Hellwig --- include/linux/device.h | 8 +

[PATCH 3/5] dma-mapping: make support for dma ops optional

Avoid the overhead of the dma ops support for tiny builds that only use the direct mapping. Signed-off-by: Christoph Hellwig --- arch/alpha/Kconfig | 1 + arch/arm/Kconfig| 1 + arch/ia64/Kconfig | 1 + arch/mips/Kconfig | 1 + arch/parisc/Kconfig

[PATCH 2/5] dma-mapping: inline the fast path dma-direct calls

Inline the single page map/unmap/sync dma-direct calls into the now out of line generic wrappers. This restores the behavior of a single function call that we had before moving the generic calls out of line. Besides the dma-mapping callers there are just a few callers in IOMMU drivers that have a

[PATCH 1/5] dma-mapping: move the remaining DMA API calls out of line

For a long time the DMA API has been implemented inline in dma-mapping.h, but the function bodies can be quite large. Move them all out of line. This also removes all the dma_direct_* exports as those are just implementation details and should never be used by drivers directly. Signed-off-by:

generic DMA bypass flag v4

Hi all, I've recently beeing chatting with Lu about using dma-iommu and per-device DMA ops in the intel IOMMU driver, and one missing feature in dma-iommu is a bypass mode where the direct mapping is used even when an iommu is attached to improve performance. The powerpc code already has a

powerpc: Incorrect stw operand modifier in __set_pte_at

Hi, Reviewing use of the patterns "Un%Xn" with lwz and stw instructions (where n should be the operand number) within the Linux kernel led me to spot those 2 weird cases: arch/powerpc/include/asm/nohash/pgtable.h:__set_pte_at() __asm__ __volatile__("\

Re: Failure to build librseq on ppc

- On Jul 8, 2020, at 10:21 AM, Christophe Leroy christophe.le...@csgroup.eu wrote: > Le 08/07/2020 à 16:00, Mathieu Desnoyers a écrit : >> - On Jul 8, 2020, at 8:33 AM, Mathieu Desnoyers >> mathieu.desnoy...@efficios.com wrote: >> >>> - On Jul 7, 2020, at 8:59 PM, Segher Boessenkool

Re: Failure to build librseq on ppc

Le 08/07/2020 à 16:00, Mathieu Desnoyers a écrit : - On Jul 8, 2020, at 8:33 AM, Mathieu Desnoyers mathieu.desnoy...@efficios.com wrote: - On Jul 7, 2020, at 8:59 PM, Segher Boessenkool seg...@kernel.crashing.org wrote: [...] So perhaps you have code like int *p; int x;

Re: [PATCH] powerpc: select ARCH_HAS_MEMBARRIER_SYNC_CORE

- On Jul 8, 2020, at 1:17 AM, Nicholas Piggin npig...@gmail.com wrote: > Excerpts from Mathieu Desnoyers's message of July 7, 2020 9:25 pm: >> - On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote: >> [...] >>> I should actually change the comment for 64-bit because soft

Re: Failure to build librseq on ppc

- On Jul 8, 2020, at 8:33 AM, Mathieu Desnoyers mathieu.desnoy...@efficios.com wrote: > - On Jul 7, 2020, at 8:59 PM, Segher Boessenkool > seg...@kernel.crashing.org > wrote: [...] >> >> So perhaps you have code like >> >> int *p; >> int x; >> ... >> asm ("lwz %0,%1" : "=r"(x) :

Re: [PATCH 18/20] Documentation: security/keys: eliminate duplicated word

On Tue, Jul 07, 2020 at 11:04:12AM -0700, Randy Dunlap wrote: > Drop the doubled word "in". > > Signed-off-by: Randy Dunlap > Cc: Jonathan Corbet > Cc: linux-...@vger.kernel.org > Cc: James Bottomley > Cc: Jarkko Sakkinen > Cc: Mimi Zohar > Cc: linux-integr...@vger.kernel.org > Cc:

Re: [PATCH V4 2/3] mm/sparsemem: Enable vmem_altmap support in vmemmap_alloc_block_buf()

On Mon, Jul 06, 2020 at 08:26:17AM +0530, Anshuman Khandual wrote: > There are many instances where vmemap allocation is often switched between > regular memory and device memory just based on whether altmap is available > or not. vmemmap_alloc_block_buf() is used in various platforms to allocate

Re: [PATCH 3/3] misc: cxl: flash: Remove unused variable 'drc_index'

On 8/7/20 10:57 pm, Lee Jones wrote: Keeping the pointer increment though. Fixes the following W=1 kernel build warning: drivers/misc/cxl/flash.c: In function ‘update_devicetree’: drivers/misc/cxl/flash.c:178:16: warning: variable ‘drc_index’ set but not used [-Wunused-but-set-variable]

Re: [PATCH 04/20] Documentation: kgdb: eliminate duplicated word

On Tue, Jul 07, 2020 at 11:03:58AM -0700, Randy Dunlap wrote: > Drop the doubled word "driver". > > Signed-off-by: Randy Dunlap > Cc: Jonathan Corbet > Cc: linux-...@vger.kernel.org > Cc: Jason Wessel > Cc: Daniel Thompson > Cc: Douglas Anderson > Cc: kgdb-bugrep...@lists.sourceforge.net

[PATCH 3/3] misc: cxl: flash: Remove unused variable 'drc_index'

Keeping the pointer increment though. Fixes the following W=1 kernel build warning: drivers/misc/cxl/flash.c: In function ‘update_devicetree’: drivers/misc/cxl/flash.c:178:16: warning: variable ‘drc_index’ set but not used [-Wunused-but-set-variable] 178 | __be32 *data, drc_index, phandle;

Re: [PATCH] selftests/powerpc: Purge extra count_pmc() calls of ebb selftests

On 7/8/20 7:38 AM, Sachin Sant wrote: On 26-Jun-2020, at 10:17 PM, Desnes A. Nunes do Rosario wrote: An extra count on ebb_state.stats.pmc_count[PMC_INDEX(pmc)] is being per- formed when count_pmc() is used to reset PMCs on a few selftests. This extra pmc_count can occasionally invalidate

Re: Failure to build librseq on ppc

- On Jul 7, 2020, at 8:59 PM, Segher Boessenkool seg...@kernel.crashing.org wrote: > Hi! > > On Tue, Jul 07, 2020 at 03:17:10PM -0400, Mathieu Desnoyers wrote: >> I'm trying to build librseq at: >> >> https://git.kernel.org/pub/scm/libs/librseq/librseq.git >> >> on powerpc, and I get

Re: Failure to build librseq on ppc

Segher Boessenkool writes: > Hi! > > On Tue, Jul 07, 2020 at 03:17:10PM -0400, Mathieu Desnoyers wrote: >> I'm trying to build librseq at: >> >> https://git.kernel.org/pub/scm/libs/librseq/librseq.git >> >> on powerpc, and I get these errors when building the rseq basic >> test mirrored from

Re: [PATCH 2/2] KVM: PPC: Book3S HV: rework secure mem slot dropping

Le 08/07/2020 à 13:25, Bharata B Rao a écrit : On Fri, Jul 03, 2020 at 05:59:14PM +0200, Laurent Dufour wrote: When a secure memslot is dropped, all the pages backed in the secure device (aka really backed by secure memory by the Ultravisor) should be paged out to a normal page. Previously,

Re: [PATCH v2 4/4] powerpc/mm/radix: Create separate mappings for hot-plugged memory

"Aneesh Kumar K.V" writes: > On 7/8/20 10:14 AM, Michael Ellerman wrote: >> "Aneesh Kumar K.V" writes: >>> To enable memory unplug without splitting kernel page table >>> mapping, we force the max mapping size to the LMB size. LMB >>> size is the unit in which hypervisor will do memory

Re: [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc

Athira Rajeev writes: > From: Anju T Sudhakar > > Add extended regs to sample_reg_mask in the tool side to use > with `-I?` option. Perf tools side uses extended mask to display > the platform supported register names (with -I? option) to the user > and also send this mask to the kernel to

Re: [PATCH v2 10/10] powerpc/perf: Add extended regs support for power10 platform

Athira Rajeev writes: > Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 > and expose MMCR3, SIER2, SIER3 registers as part of extended regs. > Also introduce `PERF_REG_PMU_MASK_31` to define extended mask > value at runtime for power10 > > Signed-off-by: Athira Rajeev > --- >

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

Athira Rajeev writes: > PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). ^ a > First is the addition of BHRB disable bit and second new filtering ^

Re: [PATCH 2/2] KVM: PPC: Book3S HV: rework secure mem slot dropping

On Fri, Jul 03, 2020 at 05:59:14PM +0200, Laurent Dufour wrote: > When a secure memslot is dropped, all the pages backed in the secure device > (aka really backed by secure memory by the Ultravisor) should be paged out > to a normal page. Previously, this was achieved by triggering the page >

Re: [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes

> On 07-Jul-2020, at 12:47 PM, Michael Neuling wrote: > > On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote: >> PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). >> First is the addition of BHRB disable bit and second new filtering >> modes for BHRB. >> >> BHRB

[PATCH] arch: powerpc: Remove unnecessary cast in kfree()

Remove unnecassary casts in the argument to kfree. Signed-off-by: Xu Wang --- arch/powerpc/platforms/pseries/dlpar.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c index

Re: [PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs

Athira Rajeev writes: > From: Madhavan Srinivasan > > Add power10 feature function to dt_cpu_ftrs.c along > with a power10 specific init() to initialize pmu sprs. > > Signed-off-by: Madhavan Srinivasan > --- > arch/powerpc/include/asm/reg.h| 3 +++ >

Re: [PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs

Athira Rajeev writes: > From: Madhavan Srinivasan > > PowerISA v3.1 added three new perfromance > monitoring unit (PMU) speical purpose register (SPR). > They are Monitor Mode Control Register 3 (MMCR3), > Sampled Instruction Event Register 2 (SIER2), > Sampled Instruction Event Register 3

Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs

Athira Rajeev writes: ... > diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c > index cd6a742..5c64bd3 100644 > --- a/arch/powerpc/perf/core-book3s.c > +++ b/arch/powerpc/perf/core-book3s.c > @@ -39,10 +39,10 @@ struct cpu_hw_events { > unsigned int

Re: [PATCH v2 06/10] powerpc/perf: power10 Performance Monitoring support

> On 07-Jul-2020, at 12:20 PM, Michael Neuling wrote: > > >> @@ -480,6 +520,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev, >> mmcr[1] = mmcr1; >> mmcr[2] = mmcra; >> mmcr[3] = mmcr2; >> +mmcr[4] = mmcr3; > > This is fragile like the kvm vcpu case I commented on

Re: [PATCH] selftests/powerpc: Purge extra count_pmc() calls of ebb selftests

> On 26-Jun-2020, at 10:17 PM, Desnes A. Nunes do Rosario > wrote: > > An extra count on ebb_state.stats.pmc_count[PMC_INDEX(pmc)] is being per- > formed when count_pmc() is used to reset PMCs on a few selftests. This > extra pmc_count can occasionally invalidate results, such as the ones

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