On 26-Feb-2021, at 2:28 PM, Srikar Dronamraju wrote:* Athira Rajeev [2021-02-25 11:50:02]:In systems having higher node numbers available like node255, perf numa bench will fail with SIGABORT.<<>>perf: bench/numa.c:1416: init: Assertion `!(g->p.nr_nodes > 64 || g->p.nr_nodes
> On 26-Feb-2021, at 3:05 PM, Peter Zijlstra wrote:
>
> On Thu, Feb 25, 2021 at 05:10:39AM -0500, Athira Rajeev wrote:
>> diff --git a/arch/powerpc/perf/core-book3s.c
>> b/arch/powerpc/perf/core-book3s.c
>> index 4b4319d8..c8be44c 100644
>> --- a/arch/powerpc
s a fix to dynamically allocate size for the
two arrays and bitmask value based on the node numbers available in the
system. With the fix, perf numa benchmark will work with node configuration
on any system and thus removes the static MAX_NR_NODES value.
Signed-off-by: Athira Rajee
l address leak to
userspace via BHRB buffer")
We only allow creation of events that has already passed the privilege
checks in perf_event_open. So these paranoid checks are not needed at
event time. As a fix, patch uses 'event->attr.exclude_kernel' check
to prevent exposing kernel address for us
> On 23-Feb-2021, at 6:24 PM, Michael Ellerman wrote:
>
> Peter Zijlstra writes:
>> On Tue, Feb 23, 2021 at 01:31:49AM -0500, Athira Rajeev wrote:
>>> Running "perf mem record" in powerpc platforms with selinux enabled
>>> resulted in soft lock
025 ("powerpc/perf: Prevent kernel address leak to
userspace via BHRB buffer")
As a fix, patch caches 'perf_allow_kernel' value in event_init in
'pmu_private' field of perf_event. The cached value is used in the
PMI code path.
Suggested-by: Michael Ellerman
Signed-off-by: Athira Rajeev
> On 09-Feb-2021, at 6:17 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Wed, Feb 03, 2021 at 12:31:48PM -0300, Arnaldo Carvalho de Melo escreveu:
>> Em Tue, Feb 02, 2021 at 04:02:36PM +0530, Athira Rajeev escreveu:
>>>
>>>
>>>On
-by: Athira Rajeev
---
Changes in v2:
-- Changed the approach to include PERF_SAMPLE_IP
condition while checking siar_valid as Suggested by
Michael Ellerman.
arch/powerpc/perf/core-book3s.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf
> On 04-Feb-2021, at 8:25 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> While sampling for marked events, currently we record the sample only
>> if the SIAR valid bit of Sampled Instruction Event Register (SIER) is
>> set. SIAR_VALID bit is used f
> On 03-Feb-2021, at 9:55 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Wed, Feb 03, 2021 at 01:55:37AM -0500, Athira Rajeev escreveu:
>> To enable presenting of Performance Monitor Counter Registers
>> (PMC1 to PMC6) as part of extended regsiters, patch adds these
> On 03-Feb-2021, at 9:01 PM, Arnaldo Carvalho de Melo wrote:
>
> Thanks, collected the Tested-by from Kajol and the Acked-by from Jiri
> and applied to my local tree for testing, then up to my perf/core
> branch.
>
> - Arnaldo
Thanks Arnaldo for taking this fix.
sample_period.
Perf event attribute will not have PERF_SAMPLE_IP set in the
sample_type if exact IP of the overflow event is not requested. So
while profiling if SAMPLE_IP is not set, just record the counter overflow
irrespective of SIAR_VALID check.
Signed-off-by: Athira Rajeev
---
arch/powerpc
extended mask value for
CPU_FTR_ARCH_300.
Signed-off-by: Athira Rajeev
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++--
tools/perf/arch/powerpc/include/perf_regs.h | 6 ++
tools/perf/arch/powerpc/util/perf_regs.c| 6 ++
3 files changed, 34
.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event.h | 2 ++
arch/powerpc/include/uapi/asm/perf_regs.h | 28 ++--
arch/powerpc/perf/core-book3s.c | 11 +++
arch/powerpc/perf/perf_regs.c | 13 -
4 files changed, 39
' will be capturing the modified value.
To solve this, add a per-cpu array as part of structure cpu_hw_events
and use this array to capture PMC values in the perf interrupt handler.
Patch also re-factor's the interrupt handler code to use this per-cpu
array instead of current local array.
Signed-off-by: Athira
to PMC6 to sample_reg_mask to use with -I? option.
Athira Rajeev (3):
powerpc/perf: Include PMCs as part of per-cpu cpuhw_events struct
powerpc/perf: Expose Performance Monitor Counter SPR's as part of
extended regs
tools/perf: Add perf tools support to expose Performance Monitor
Counter
On 18-Jan-2021, at 3:51 PM, kajoljain wrote:On 1/12/21 3:08 PM, Jiri Olsa wrote:On Mon, Dec 28, 2020 at 09:14:14PM -0500, Athira Rajeev wrote:SNIPc2799370 b backtrace_flagc2799378 B radix_tree_node_cachepc2799380 B __bss_stopc27a B _endc0080389 t
and if there is no permission
to monitor qemu threads, we return permission denied ( EACCES ).
Fix this by returning EACCES only if there is no CAP_SYS_ADMIN and the
event doesn’t have inheritance.
Fixes: 012ae244845f ("powerpc/perf: Trace imc PMU functions")
Signed-off-by: Ath
ace logs:<<>>replay_soft_interrupts <-arch_local_irq_restoreirq_enter <-performance_monitor_exception_asyncirq_enter_rcu <-performance_monitor_exception_asyncdummy_perf <-performance_monitor_exception_asyncirq_exit <-performance_monitor_exception_async<<>>Reviewe
On 20-Jan-2021, at 8:39 AM, Nicholas Piggin wrote:Excerpts from Athira Rajeev's message of January 19, 2021 8:24 pm:On 15-Jan-2021, at 10:19 PM, Nicholas Piggin wrote:This is required in order to allow more significant differences betweenNMI type interrupt handlers and regular asynchronous
sy_wait(delay); trace_printk("IN IRQ TEST DONE\n"); local_irq_restore(flags); mtspr(SPRN_MMCR0, 0x8000); mtspr(SPRN_PMC6, 0);}<<>>With the patch, there is no soft lockup’s.Tested-by: Athira Rajeev ---arch/powerpc/kernel/irq.c | 14 ++1 file changed, 14 insertio
> On 15-Jan-2021, at 10:19 PM, Nicholas Piggin wrote:
>
> This is required in order to allow more significant differences between
> NMI type interrupt handlers and regular asynchronous handlers.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kernel/traps.c | 31
> On 12-Jan-2021, at 3:08 PM, Jiri Olsa wrote:
>
> On Mon, Dec 28, 2020 at 09:14:14PM -0500, Athira Rajeev wrote:
>
> SNIP
>
>> c2799370 b backtrace_flag
>> c2799378 B radix_tree_node_cachep
>> c2799380 B __bss_stop
>> c00
g calloc fails.
Fix this by detecting the kernel's last symbol and limiting
the range of last kernel symbol to pagesize.
Signed-off-by: Athira Rajeev
---
tools/perf/arch/powerpc/util/Build | 1 +
tools/perf/arch/powerpc/util/machine.c | 24
2 files changed, 25
On 28-Nov-2020, at 8:10 PM, Nicholas Piggin wrote:This is required in order to allow more significant differences betweenNMI type interrupt handlers and regular asynchronous handlers.Signed-off-by: Nicholas Piggin Reviewed this patch and the changes looks good to me.Reviewed-by: Athira Rajeev
Srinivasan
Signed-off-by: Athira Rajeev
---
Changelog v2 -> v3:
- Since in POWER10 it's actually 8 bits which will hopefully be
fixed in ISA3.1 update, bring back the cpu feature check which
is the appropriate one.
Changelog v1 -> v2:
- Fixed the commit message
- Fixed the condition check to u
and checking the backtrace when timer_interrupt
was hit.
Reported-by: Sebastian Andrzej Siewior
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core
updates to event codes
can be made in the original list, ie, power10_events_attr. Update the
power10 pmu init code to pick the dd1 list while registering
the power PMU, based on the pvr (Processor Version Register) value.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-pmu.c | 152
boot and during the PMU event enable/disable callback
functions.
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/cpu_setup_power.c | 1 +
arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
arch/powerpc/perf/core-book3s.c | 4
arch/powerpc
Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
(PM_L3_PF_MISS_L3) via sysfs, and also add these to list of
cache_events.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-events-list.h | 6 ++
arch/powerpc/perf/power10-pmu.c | 12 +---
2 files
Fix the event code for events: branch-instructions (to PM_BR_FIN),
branch-misses (to PM_MPRED_BR_FIN) and cache-misses (to
PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update the
list of generic events with this modified event code.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10
/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 7 ++-
arch/powerpc/perf/isa207-common.h | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/isa207-common.c
b/arch/powerpc/perf/isa20
lit Patch 3 also to address event code updates
separately for generic and cache events.
Fixed commit messages and also PMCCEXT bit setting
during event enable.
Athira Rajeev (7):
powerpc/perf: Fix to update radix_scope_qual in power10
powerpc/perf: Update the PMU group constraints for l
patch handles
group constrints checks for l2/l3 bits in MMCR2.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/p
the radix_scope_qual bit.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 12
arch/powerpc/perf/isa207-common.h | 13 ++---
arch/powerpc/perf/power10-pmu.c | 11 +++
3 files c
) locks on to kernel address even when
freeze on supervisor is set. Patch here adds a check to
drop those samples.
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Initial patch was sent along with series:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=209195
Moving this patch
b7a ("powerpc/perf: Update perf_regs structure to include SIER")
Reported-by: Sachin Sant
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Corrected the commit message as suggested by
Michael Ellerman.
arch/powerpc/perf/core-book3s.c | 3 +++
1 file changed, 3 insertions(+)
diff --
> On 11-Nov-2020, at 3:13 PM, Nicholas Piggin wrote:
>
> This is required in order to allow more significant differences between
> NMI type interrupt handlers and regular asynchronous handlers.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kernel/traps.c | 31
> On 23-Nov-2020, at 4:49 PM, Michael Ellerman wrote:
>
> Hi Athira,
>
> Athira Rajeev writes:
>> On systems without any platform specific PMU driver support registered or
>> Generic Compat PMU support registered,
>
> The compat PMU is registered just like
turning false in
'is_sier_available()' if 'ppmu' is not set.
Fixes: 333804dc3b7a ("powerpc/perf: Update perf_regs structure to include SIER")
Reported-by: Sachin Sant
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/power
> On 18-Nov-2020, at 10:06 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> Fix the event code for events: branch-instructions (to PM_BR_FIN),
>> branch-misses (to PM_BR_MPRED_FIN) and cache-misses (to
>> PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update th
> On 18-Nov-2020, at 10:02 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> In Power9, L2/L3 bus events are always available as a
>> "bank" of 4 events. To obtain the counts for any of the
>> l2/l3 bus events in a given bank, the user will have
patch handles
group constrints checks for l2/l3 bits in MMCR2.
Patch also updates constraints for threshold events in power10.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 15 +++
, based on the pvr
(Processor Version Register) value.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/power10-events-list.h | 9 ++
arch/powerpc/perf/power10-pmu.c | 166 +++-
2 files changed, 173 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf
the radix_scope_qual bit.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 12
arch/powerpc/perf/isa207-common.h | 13 ++---
arch/powerpc/perf/power10-pmu.c | 11 +++
3 files c
=0b00
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/cpu_setup_power.S | 2 ++
arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
arch/powerpc/perf/core-book3s.c | 16
4 files changed, 20 insertions(+)
diff --git a/arch
and
some of the generic events.
Patch4 adds fixes for PMCCEXT bit in power10.
Athira Rajeev (4):
powerpc/perf: Fix to update radix_scope_qual in power10
powerpc/perf: Update the PMU group constraints for l2l3 and threshold
events in power10
powerpc/perf: Fix to update l2l3 events
). Patch adds a check to drop
these samples at such conditions.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index c018004..10a2d1f 100644
--- a/arch
is set.
So add a condition check for power10 DD1 to use SIER[CMPL] bit
instead.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index
. Hence add a check to use the address in Sampled Instruction Address
Register (SIAR) to identify the privilege level.
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc
Add a new power PMU flag "PPMU_P10_DD1" which can be
used to conditionally add any code path for power10 DD1 processor
version. Also modify power10 PMU driver code to set this
flag only for DD1, based on the Processor Version Register (PVR)
value.
Signed-off-by: Athira Rajeev
---
ar
userspace profiling.
Athira Rajeev (4):
powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1
powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID]
powerpc/perf: Use the address from SIAR register to set cpumode flags
powerpc/perf: Exclude kernel samples whil
bol 'p9_dd21_bl_ev'
> was not declared. Should it be static?
> arch/powerpc/perf/power9-pmu.c:115:5: warning: symbol 'p9_dd22_bl_ev'
> was not declared. Should it be static?
>
> Those symbols are used only in the files that define them so we declare
> them as static to fix the warnings.
Hi,
Loo
> On 22-Sep-2020, at 4:16 PM, Paul A. Clarke wrote:
>
> Just one nit in a comment below...
> (and this is not worthy of tags like "reviewed-by" ;-)
>
> On Mon, Sep 21, 2020 at 03:10:04AM -0400, Athira Rajeev wrote:
>> PMU counter support functions en
> On 21-Sep-2020, at 4:55 PM, Wang Wensheng wrote:
>
> Build kernel with `C=2`:
> arch/powerpc/perf/isa207-common.c:24:18: warning: symbol
> 'isa207_pmu_format_attr' was not declared. Should it be static?
> arch/powerpc/perf/power9-pmu.c:101:5: warning: symbol 'p9_dd21_bl_ev'
> was not
: 7ffd948 ("powerpc/perf: factor out power8 pmu functions")
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Added a block comment in the fix path explaining
why the change is needed.
arch/powerpc/perf/isa207-common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/ar
> On 17-Sep-2020, at 5:43 PM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> PMU counter support functions enforces event constraints for group of
>> events to check if all events in a group can be monitored. Incase of
>> event codes using PMC5 and PMC6 ( 5
ent_init(struct perf_event
> *event)
> mutex_unlock(_global_refc.lock);
>
> event->hw.idx = -1;
> - target = event->hw.target;
Reviewed-by: Athira Rajeev
Thanks
Athira
>
> event->pmu->task_ctx_nr = perf_hw_context;
> event->destroy = reset_global_refc;
> --
> 2.25.4
>
: 7ffd948 ('powerpc/perf: factor out power8 pmu functions')
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/perf/isa207-common.c
b/arch/powerpc/perf/isa207-common.c
index 964437a..186fad8 100644
--- a/arch
;)
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/imc-pmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
index a45d694..62d0b54 100644
--- a/arch/powerpc/perf/imc-pmu.c
+++ b/arch/powerpc/perf/imc-pmu.c
@@ -1
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
Reviewed
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
Reviewed-by: Kajol Jain
Reviewed-and-tested-by: Ravi Bangoria
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools
from Ravi Bangoria to initialize
`perf_reg_extended_max`
and define it in lowercase since it is local variable.
Anju T Sudhakar (1):
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (1):
tools/perf: Add perf tools support for extended regs i
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
[Fix build issue using
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
d support for outputting extended regs in perf
intr_regs
Athira Rajeev (1):
powerpc/perf: Add extended regs support for power10 platform
arch/powerpc/include/asm/perf_event.h| 3 ++
arch/powerpc/include/asm/perf_event_server.h | 5
arch/powerpc/include/uapi/asm/perf_regs.
> On 06-Aug-2020, at 5:50 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Fri, Jul 31, 2020 at 11:04:14PM +0530, Athira Rajeev escreveu:
>>
>>
>>> On 31-Jul-2020, at 1:20 AM, Jiri Olsa wrote:
>>>
>>> On Thu, Jul 30, 2020 at 01:24:40PM +0530,
is more than max_samples_per_tick. This leads to soft lockup.
Fix this by adding perf_event_account_interrupt in the invalid siar
code path for a sampling event. ie if siar is invalid, just do interrupt
check and don't record the sample information.
Signed-off-by: Athira Rajeev
Reported-by: Alexey
> On 31-Jul-2020, at 1:20 AM, Jiri Olsa wrote:
>
> On Thu, Jul 30, 2020 at 01:24:40PM +0530, Athira Rajeev wrote:
>>
>>
>>> On 27-Jul-2020, at 10:46 PM, Athira Rajeev
>>> wrote:
>>>
>>> Patch set to add support for perf extende
> On 27-Jul-2020, at 10:46 PM, Athira Rajeev
> wrote:
>
> Patch set to add support for perf extended register capability in
> powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to
> indicate the PMU which support extended registers. The generic code
> On 28-Jul-2020, at 6:14 AM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>>> On 27-Jul-2020, at 6:05 PM, Michael Ellerman wrote:
>>>
>>> Athira Rajeev writes:
>>>>> On 27-Jul-2020, at 11:39 AM, Nicholas Piggin wrote:
>>&g
DT CPU features")
Signed-off-by: Athira Rajeev
Suggested-by: Michael Ellerman
---
arch/powerpc/include/asm/reg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index ae71027..41419f1 100644
--- a/arch/power
> On 27-Jul-2020, at 6:05 PM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>>> On 27-Jul-2020, at 11:39 AM, Nicholas Piggin wrote:
>>>
>>> Commit 2f92447f9f96 ("powerpc/book3s64/hash: Use the pte_t address from the
>>> caller
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
Reviewed
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
Reviewed-by: Kajol Jain
Reviewed-and-tested-by: Ravi Bangoria
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
[Fix build issue using
r_regs
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (2):
powerpc/perf: Add extended regs support for power10 platform
tools/perf: Add perf tools support for extended regs in power10
arch/powerpc/include/asm/perf_event.h | 3 ++
037f024 wp_page_copy+0x364/0xce0
> [c0002ac1cc69bc20] c038272c do_wp_page+0xdc/0xa60
> [c0002ac1cc69bc70] c03857bc handle_mm_fault+0xb9c/0x1b60
> [c0002ac1cc69bd50] c006c434 __do_page_fault+0x314/0xc90
> [c0002ac1cc69be20] c000c5c8 handle_page_faul
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
Reviewed
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
Reviewed-by: Kajol Jain
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools/perf/arch/powerpc/util/header.c
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
[Fix build issue using
ine it in lowercase since it is local variable.
Anju T Sudhakar (2):
powerpc/perf: Add support for outputting extended regs in perf
intr_regs
tools/perf: Add perf tools support for extended register capability in
powerpc
Athira Rajeev (2):
powerpc/perf: Add extended regs support for power10 platf
ain random value which
> will
> allow user to pass this if condition unintentionally.
>
> Neat: PERF_REG_EXTENDED_MAX is a local variable so it should be in lowercase.
> Any specific reason to define it in capital?
Hi Ravi
There is no specific reason. I will include both these changes in next version
Thanks
Athira Rajeev
>
> Ravi
> On 24-Jul-2020, at 4:32 PM, Ravi Bangoria wrote:
>
> Hi Athira,
>
> On 7/17/20 8:08 PM, Athira Rajeev wrote:
>> From: Anju T Sudhakar
>> Add extended regs to sample_reg_mask in the tool side to use
>> with `-I?` option. Perf tools side uses extende
> On 23-Jul-2020, at 8:26 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Thu, Jul 23, 2020 at 11:14:16AM +0530, kajoljain escreveu:
>>
>>
>> On 7/21/20 11:32 AM, kajoljain wrote:
>>>
>>>
>>> On 7/17/20 8:08 PM, Athira Rajeev wrote:
>&
wood/next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-
t;> the above relies on preempt_count() already having been incremented with
>>> NMI_MASK.
>>
>> Hmm. My patch seems simpler.
>
> And your patches fix my error while Peter's do not:
>
>
> IRQs not enabled as expected
> WARNING: CPU: 0 PID: 1377 at /home/aik/p/
re at boot for power10.
Signed-off-by: Athira Rajeev
---
Dependency:
- On power10 PMU base enablement series V3:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=190462
Changes from v3 -> v4
- Addressed review comments from Jordan and Michael Ellerman.
This patch was initially part o
> On 22-Jul-2020, at 4:19 PM, Jordan Niethe wrote:
>
> On Wed, Jul 22, 2020 at 5:55 PM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>>
>>
>> On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote:
>>
>> On Sat, Jul 18, 20
> On 22-Jul-2020, at 9:48 AM, Jordan Niethe wrote:
>
> On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>> From: Madhavan Srinivasan
>>
>> PowerISA v3.1 includes new performance monitoring un
> On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote:
>
> On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>> From: Madhavan Srinivasan
>>
>> Add power10 feature function to dt_cpu_ftrs.c along
>>
> On 22-Jul-2020, at 10:07 AM, Michael Ellerman wrote:
>
> Athira Rajeev <mailto:atraj...@linux.vnet.ibm.com>> writes:
>>> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote:
>>> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
>>>&
> On 21-Jul-2020, at 9:12 AM, Jordan Niethe wrote:
>
> On Sat, Jul 18, 2020 at 12:48 AM Athira Rajeev
> mailto:atraj...@linux.vnet.ibm.com>> wrote:
>>
>> core-book3s currently uses array to store the MMCR registers as part
>> of per-cpu `cpu_hw_events
> On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote:
>
> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
>> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers
>> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs
>> Split this
the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-Add-support-for-power10-PM
extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++-
tools/perf/arch/powerpc/include/perf_regs.h | 5 ++-
tools/perf/arch/powerpc/util/header.c | 9 +
tools
Added support for supported regs which are new in power10
( MMCR3, SIER2, SIER3 ) to sample_reg_mask in the tool side
to use with `-I?` option. Also added PVR check to send extended
mask for power10 at kernel while capturing extended regs in
each sample.
Signed-off-by: Athira Rajeev
---
tools
Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10
and expose MMCR3, SIER2, SIER3 registers as part of extended regs.
Also introduce `PERF_REG_PMU_MASK_31` to define extended mask
value at runtime for power10
Signed-off-by: Athira Rajeev
[Fix build failure on PPC32 platform
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