Re: [question] Can the execution of the atomtic operation instruction pair lwarx/stwcx be interrrupted by local HW interruptions?
On Tue, 2014-01-07 at 15:22 +0800, wyang wrote:
On 01/07/2014 02:35 PM, Scott Wood wrote:
On Tue, 2014-01-07 at 09:00 +0800, wyang wrote:
Yeah, Can you provide more detail info about why they can handle that
case? The following is my understand:
Let us assume that there is a atomic global variable(var_a) and its
initial value is 0.
The kernel attempts to execute atomic_add(1, var_a), after lwarx a async
interrupt happens, and the ISR also accesses var_a variable and
executes atomic_add.
static __inline__ void atomic_add(int a, atomic_t *v)
{
int t;
__asm__ __volatile__(
1:lwarx%0,0,%3# atomic_add\n\
-- --- interrupt
happens---ISR also operates this global variable var_a
such as also executing atomic_add(1, var_a). so the
var_a would is 1.
add%0,%2,%0\n
PPC405_ERR77(0,%3)
stwcx.%0,0,%3 \n\ - After interrupt code returns, the
reservation is cleared. so CR0 is not equal to 0, and then jump the 1
label. the var_a will be 2.
bne-1b
: =r (t), +m (v-counter)
: r (a), r (v-counter)
: cc);
}
So the value of var_a is 2 rather than 1. Thats why i said that
atomic_add does not handle such case. If I miss something, please
correct me.:-)
2 is the correct result, since atomic_add(1, var_a) was called twice
(once in the ISR, once in the interrupted context).
Scott, thanks for your confirmation. I guess that Gavin thought that 1
is a correct result. So thats why I said that if he wanna get 1,
he should have responsibility to disable local interrupts.
If you disable interrupts, that will just delay the interrupt until
afterward, at which point the interrupt will increment var_a to 2.
I mean that
atomic_add is not able to guarantee that 1 is a correct result.:-)
Well, no. It's atomic_add(), not set_var_to_one(). :-)
-Scott
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[PATCH 1/2] pci: Fix root port bus-self is NULL
From: Wang Dongsheng dongsheng.w...@freescale.com
the root port bus-self always NULL, so put root port pci device
into root port bus-self.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 38e403d..7f2d1ab 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
if (!dev-is_added)
nr++;
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+ bus-self = dev;
+
for (fn = next_fn(bus, dev, 0); fn 0; fn = next_fn(bus, dev, fn)) {
dev = pci_scan_single_device(bus, devfn + fn);
if (dev) {
--
1.8.5
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[PATCH 2/2] fsl/pci: The new pci suspend/resume implementation
From: Wang Dongsheng dongsheng.w...@freescale.com
The new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume.
Add a PME handler, to response PME message interrupt.
Change platform_driver-suspend/resume to syscore-suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c
b/arch/powerpc/platforms/85xx/c293pcie.c
index 213d5b8..84476b6 100644
--- a/arch/powerpc/platforms/85xx/c293pcie.c
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -68,6 +68,7 @@ define_machine(c293_pcie) {
.init_IRQ = c293_pcie_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..aa8b9a3 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -163,6 +163,7 @@ define_machine(corenet_generic) {
.init_IRQ = corenet_gen_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_coreint_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c
b/arch/powerpc/platforms/85xx/ge_imp3a.c
index e6285ae..11790e0 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) {
.show_cpuinfo = ge_imp3a_show_cpuinfo,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c
b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 15ce4b5..a378ba3 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) {
.init_IRQ = mpc8536_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 7a31a0e..b0753e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) {
#ifdef CONFIG_PCI
.restart= mpc85xx_cds_restart,
.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#else
.restart= fsl_rstcr_restart,
#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 9ebb91e..ffdf021 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) {
.init_IRQ = mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) {
.init_IRQ = mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -237,6 +239,7 @@ define_machine(p2020_ds) {
.init_IRQ = mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..6cd3b8a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -416,6 +416,7 @@ define_machine(mpc8568_mds) {
.progress = udbg_progress,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
Re: [PATCH 1/2] pci: Fix root port bus-self is NULL
On 2014/1/7 16:04, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
the root port bus-self always NULL, so put root port pci device
into root port bus-self.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 38e403d..7f2d1ab 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
if (!dev-is_added)
nr++;
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+ bus-self = dev;
In this case, bus is the pci root bus I think, so why set bus-self = root port
?
bus-self should pointer to the pci device that bridge out this bus.
+
for (fn = next_fn(bus, dev, 0); fn 0; fn = next_fn(bus, dev, fn)) {
dev = pci_scan_single_device(bus, devfn + fn);
if (dev) {
--
Thanks!
Yijing
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Re: [02/12,v3] pci: fsl: add structure fsl_pci
On Mon, 2014-01-06 at 14:10 +0800, Lian Minghuan-b31939 wrote:
On 01/04/2014 06:19 AM, Scott Wood wrote:
I don't like the extent to which this duplicates (not moves) PPC's struct
pci_controller. Also this leaves some fields like indirect_type
unexplained (PPC_INDIRECT_TYPE_xxx is only in the PPC header).
Does the arch-independent part of the driver really need all this? Given
how closely this tracks the PPC code, how would this work on ARM?
[Minghuan] I added the duplicate fields because PPC's struct
pci_controller need them.
I think a better approach would be to create a cleanly architected
arch-independent driver. Share what you reasonably can with the current
fsl_pci.c, but not to the extent of propagating PPCisms that don't match
up with what we ultimately want to see in generic code, or copying
things that ought to be controller-independent infrastructure into
controller-specific code.
See these threads:
http://www.spinics.net/lists/linux-pci/msg25769.html
https://lkml.org/lkml/2013/5/4/103
The following is for ARM, I will submit them after verification:
[snip]
+static int fsl_pcie_register(struct fsl_pcie *pcie)
+{
+pcie-controller = fsl_hw_pcie.nr_controllers;
+fsl_hw_pcie.nr_controllers = 1;
+fsl_hw_pcie.private_data = (void **)pcie;
I believe this should be:
fsl_hw_pcie.private_data = pcie;
+pci_common_init(fsl_hw_pcie);
+pci_assign_unassigned_resources();
+#ifdef CONFIG_PCI_DOMAINS
+fsl_hw_pcie.domain++;
+#endif
What serializes that non-atomic increment?
-Scott
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Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
Hi Joonsoo,
On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote:
On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
[...]
Hello,
I think that we need more efforts to solve unbalanced node problem.
With this patch, even if node of current cpu slab is not favorable to
unbalanced node, allocation would proceed and we would get the unintended
memory.
We have a machine:
[0.00] Node 0 Memory:
[0.00] Node 4 Memory: 0x0-0x1000 0x2000-0x6000
0x8000-0xc000
[0.00] Node 6 Memory: 0x1000-0x2000 0x6000-0x8000
[0.00] Node 10 Memory: 0xc000-0x18000
[0.041486] Node 0 CPUs: 0-19
[0.041490] Node 4 CPUs:
[0.041492] Node 6 CPUs:
[0.041495] Node 10 CPUs:
The pages of current cpu slab should be allocated from fallback zones/nodes
of the memoryless node in buddy system, how can not favorable happen?
And there is one more problem. Even if we have some partial slabs on
compatible node, we would allocate new slab, because get_partial() cannot
handle
this unbalance node case.
To fix this correctly, how about following patch?
So I think we should fold both of your two patches to one.
Regards,
Wanpeng Li
Thanks.
-8
diff --git a/mm/slub.c b/mm/slub.c
index c3eb3d3..a1f6dfa 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1672,7 +1672,19 @@ static void *get_partial(struct kmem_cache *s, gfp_t
flags, int node,
{
void *object;
int searchnode = (node == NUMA_NO_NODE) ? numa_node_id() : node;
+ struct zonelist *zonelist;
+ struct zoneref *z;
+ struct zone *zone;
+ enum zone_type high_zoneidx = gfp_zone(flags);
+ if (!node_present_pages(searchnode)) {
+ zonelist = node_zonelist(searchnode, flags);
+ for_each_zone_zonelist(zone, z, zonelist, high_zoneidx) {
+ searchnode = zone_to_nid(zone);
+ if (node_present_pages(searchnode))
+ break;
+ }
+ }
object = get_partial_node(s, get_node(s, searchnode), c, flags);
if (object || node != NUMA_NO_NODE)
return object;
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Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 06:10:16PM +0900, Joonsoo Kim wrote:
On Tue, Jan 07, 2014 at 04:48:40PM +0800, Wanpeng Li wrote:
Hi Joonsoo,
On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote:
On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
[...]
Hello,
I think that we need more efforts to solve unbalanced node problem.
With this patch, even if node of current cpu slab is not favorable to
unbalanced node, allocation would proceed and we would get the unintended
memory.
We have a machine:
[0.00] Node 0 Memory:
[0.00] Node 4 Memory: 0x0-0x1000 0x2000-0x6000
0x8000-0xc000
[0.00] Node 6 Memory: 0x1000-0x2000 0x6000-0x8000
[0.00] Node 10 Memory: 0xc000-0x18000
[0.041486] Node 0 CPUs: 0-19
[0.041490] Node 4 CPUs:
[0.041492] Node 6 CPUs:
[0.041495] Node 10 CPUs:
The pages of current cpu slab should be allocated from fallback zones/nodes
of the memoryless node in buddy system, how can not favorable happen?
Hi, Wanpeng.
IIRC, if we call kmem_cache_alloc_node() with certain node #, we try to
allocate the page in fallback zones/node of that node #. So fallback list isn't
related to fallback one of memoryless node #. Am I wrong?
Anton add node_spanned_pages(node) check, so current cpu slab mentioned
above is against memoryless node. If I miss something?
Regards,
Wanpeng Li
Thanks.
And there is one more problem. Even if we have some partial slabs on
compatible node, we would allocate new slab, because get_partial() cannot
handle
this unbalance node case.
To fix this correctly, how about following patch?
So I think we should fold both of your two patches to one.
Regards,
Wanpeng Li
Thanks.
-8
diff --git a/mm/slub.c b/mm/slub.c
index c3eb3d3..a1f6dfa 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1672,7 +1672,19 @@ static void *get_partial(struct kmem_cache *s, gfp_t
flags, int node,
{
void *object;
int searchnode = (node == NUMA_NO_NODE) ? numa_node_id() : node;
+ struct zonelist *zonelist;
+ struct zoneref *z;
+ struct zone *zone;
+ enum zone_type high_zoneidx = gfp_zone(flags);
+ if (!node_present_pages(searchnode)) {
+ zonelist = node_zonelist(searchnode, flags);
+ for_each_zone_zonelist(zone, z, zonelist, high_zoneidx) {
+ searchnode = zone_to_nid(zone);
+ if (node_present_pages(searchnode))
+ break;
+ }
+ }
object = get_partial_node(s, get_node(s, searchnode), c, flags);
if (object || node != NUMA_NO_NODE)
return object;
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RE: [RFC] linux/pci: move pci_platform_pm_ops to linux/pci.h
-Original Message- From: Rafael J. Wysocki [mailto:r...@rjwysocki.net] Sent: Monday, January 06, 2014 8:13 PM To: Bjorn Helgaas Cc: Wang Dongsheng-B40534; Zang Roy-R61911; Wood Scott-B07421; Kumar Gala; Linux PM list; linux-...@vger.kernel.org; linuxppc-dev Subject: Re: [RFC] linux/pci: move pci_platform_pm_ops to linux/pci.h On Friday, December 20, 2013 09:42:59 AM Bjorn Helgaas wrote: On Fri, Dec 20, 2013 at 3:03 AM, Dongsheng Wang dongsheng.w...@freescale.com wrote: From: Wang Dongsheng dongsheng.w...@freescale.com make Freescale platform use pci_platform_pm_ops struct. This changelog doesn't say anything about what the patch does. I infer that you want to use pci_platform_pm_ops from some Freescale code. This patch should be posted along with the patches that add that Freescale code, so we can see how you intend to use it. The existing use is in drivers/pci/pci-acpi.c, so it's possible that your new use should be added in the same way, in drivers/pci, so we don't have to make pci_platform_pm_ops part of the public PCI interface in include/linux/pci.h. That said, if Raphael thinks this makes sense, it's OK with me. Well, I'd like to know why exactly the change is needed in the first place. Thanks for review, I think the idea is not suitable for freescale platform implementation of the right now. I will drop this RFC patch. -Dongsheng Thanks! -- I speak only for myself. Rafael J. Wysocki, Intel Open Source Technology Center. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
We noticed a huge amount of slab memory consumed on a large ppc64 box:
Slab:2094336 kB
Almost 2GB. This box is not balanced and some nodes do not have local
memory, causing slub to be very inefficient in its slab usage.
Each time we call kmem_cache_alloc_node slub checks the per cpu slab,
sees it isn't node local, deactivates it and tries to allocate a new
slab. On empty nodes we will allocate a new remote slab and use the
first slot, but as explained above when we get called a second time
we will just deactivate that slab and retry.
As such we end up only using 1 entry in each slab:
slabmem objects
used active
kmalloc-16384 1404 MB4.90%
task_struct 668 MB2.90%
kmalloc-128 193 MB3.61%
kmalloc-192 152 MB5.23%
kmalloc-8192 72 MB 23.40%
kmalloc-1664 MB7.43%
kmalloc-512 33 MB 22.41%
The patch below checks that a node is not empty before deactivating a
slab and trying to allocate it again. With this patch applied we now
use about 352MB:
Slab: 360192 kB
And our efficiency is much better:
slabmem objects
used active
kmalloc-16384 92 MB 74.27%
task_struct 23 MB 83.46%
idr_layer_cache 18 MB 100.00%
pgtable-2^12 17 MB 100.00%
kmalloc-65536 15 MB 100.00%
inode_cache 14 MB 100.00%
kmalloc-256 14 MB 97.81%
kmalloc-8192 14 MB 85.71%
Signed-off-by: Anton Blanchard an...@samba.org
---
Thoughts? It seems like we could hit a similar situation if a machine
is balanced but we run out of memory on a single node.
Index: b/mm/slub.c
===
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -2278,10 +2278,17 @@ redo:
if (unlikely(!node_match(page, node))) {
stat(s, ALLOC_NODE_MISMATCH);
- deactivate_slab(s, page, c-freelist);
- c-page = NULL;
- c-freelist = NULL;
- goto new_slab;
+
+ /*
+ * If the node contains no memory there is no point in trying
+ * to allocate a new node local slab
+ */
+ if (node_spanned_pages(node)) {
+ deactivate_slab(s, page, c-freelist);
+ c-page = NULL;
+ c-freelist = NULL;
+ goto new_slab;
+ }
}
/*
Hello,
I think that we need more efforts to solve unbalanced node problem.
With this patch, even if node of current cpu slab is not favorable to
unbalanced node, allocation would proceed and we would get the unintended
memory.
And there is one more problem. Even if we have some partial slabs on
compatible node, we would allocate new slab, because get_partial() cannot handle
this unbalance node case.
To fix this correctly, how about following patch?
Thanks.
-8
diff --git a/mm/slub.c b/mm/slub.c
index c3eb3d3..a1f6dfa 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1672,7 +1672,19 @@ static void *get_partial(struct kmem_cache *s, gfp_t
flags, int node,
{
void *object;
int searchnode = (node == NUMA_NO_NODE) ? numa_node_id() : node;
+ struct zonelist *zonelist;
+ struct zoneref *z;
+ struct zone *zone;
+ enum zone_type high_zoneidx = gfp_zone(flags);
+ if (!node_present_pages(searchnode)) {
+ zonelist = node_zonelist(searchnode, flags);
+ for_each_zone_zonelist(zone, z, zonelist, high_zoneidx) {
+ searchnode = zone_to_nid(zone);
+ if (node_present_pages(searchnode))
+ break;
+ }
+ }
object = get_partial_node(s, get_node(s, searchnode), c, flags);
if (object || node != NUMA_NO_NODE)
return object;
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Re: [PATCH 1/2] pci: Fix root port bus-self is NULL
On 2014/1/7 16:27, Yijing Wang wrote:
On 2014/1/7 16:04, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
the root port bus-self always NULL, so put root port pci device
into root port bus-self.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 38e403d..7f2d1ab 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
if (!dev-is_added)
nr++;
+if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+bus-self = dev;
In this case, bus is the pci root bus I think, so why set bus-self = root
port ?
bus-self should pointer to the pci device that bridge out this bus.
Yes, this patch seems wrong. If dev is root port, bus should be root
bus, so we shouldn't set root_bus-self = pci_dev_of_root_port.
Actually PCI core has correctly setup pci_bus-self for secondary bus
of PCIe root port.
Thanks!
Gerry
+
for (fn = next_fn(bus, dev, 0); fn 0; fn = next_fn(bus, dev, fn)) {
dev = pci_scan_single_device(bus, devfn + fn);
if (dev) {
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Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 04:48:40PM +0800, Wanpeng Li wrote:
Hi Joonsoo,
On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote:
On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
[...]
Hello,
I think that we need more efforts to solve unbalanced node problem.
With this patch, even if node of current cpu slab is not favorable to
unbalanced node, allocation would proceed and we would get the unintended
memory.
We have a machine:
[0.00] Node 0 Memory:
[0.00] Node 4 Memory: 0x0-0x1000 0x2000-0x6000
0x8000-0xc000
[0.00] Node 6 Memory: 0x1000-0x2000 0x6000-0x8000
[0.00] Node 10 Memory: 0xc000-0x18000
[0.041486] Node 0 CPUs: 0-19
[0.041490] Node 4 CPUs:
[0.041492] Node 6 CPUs:
[0.041495] Node 10 CPUs:
The pages of current cpu slab should be allocated from fallback zones/nodes
of the memoryless node in buddy system, how can not favorable happen?
Hi, Wanpeng.
IIRC, if we call kmem_cache_alloc_node() with certain node #, we try to
allocate the page in fallback zones/node of that node #. So fallback list isn't
related to fallback one of memoryless node #. Am I wrong?
Thanks.
And there is one more problem. Even if we have some partial slabs on
compatible node, we would allocate new slab, because get_partial() cannot
handle
this unbalance node case.
To fix this correctly, how about following patch?
So I think we should fold both of your two patches to one.
Regards,
Wanpeng Li
Thanks.
-8
diff --git a/mm/slub.c b/mm/slub.c
index c3eb3d3..a1f6dfa 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1672,7 +1672,19 @@ static void *get_partial(struct kmem_cache *s, gfp_t
flags, int node,
{
void *object;
int searchnode = (node == NUMA_NO_NODE) ? numa_node_id() : node;
+ struct zonelist *zonelist;
+ struct zoneref *z;
+ struct zone *zone;
+ enum zone_type high_zoneidx = gfp_zone(flags);
+ if (!node_present_pages(searchnode)) {
+ zonelist = node_zonelist(searchnode, flags);
+ for_each_zone_zonelist(zone, z, zonelist, high_zoneidx) {
+ searchnode = zone_to_nid(zone);
+ if (node_present_pages(searchnode))
+ break;
+ }
+ }
object = get_partial_node(s, get_node(s, searchnode), c, flags);
if (object || node != NUMA_NO_NODE)
return object;
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Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 05:21:45PM +0800, Wanpeng Li wrote: On Tue, Jan 07, 2014 at 06:10:16PM +0900, Joonsoo Kim wrote: On Tue, Jan 07, 2014 at 04:48:40PM +0800, Wanpeng Li wrote: Hi Joonsoo, On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote: On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote: [...] Hello, I think that we need more efforts to solve unbalanced node problem. With this patch, even if node of current cpu slab is not favorable to unbalanced node, allocation would proceed and we would get the unintended memory. We have a machine: [0.00] Node 0 Memory: [0.00] Node 4 Memory: 0x0-0x1000 0x2000-0x6000 0x8000-0xc000 [0.00] Node 6 Memory: 0x1000-0x2000 0x6000-0x8000 [0.00] Node 10 Memory: 0xc000-0x18000 [0.041486] Node 0 CPUs: 0-19 [0.041490] Node 4 CPUs: [0.041492] Node 6 CPUs: [0.041495] Node 10 CPUs: The pages of current cpu slab should be allocated from fallback zones/nodes of the memoryless node in buddy system, how can not favorable happen? Hi, Wanpeng. IIRC, if we call kmem_cache_alloc_node() with certain node #, we try to allocate the page in fallback zones/node of that node #. So fallback list isn't related to fallback one of memoryless node #. Am I wrong? Anton add node_spanned_pages(node) check, so current cpu slab mentioned above is against memoryless node. If I miss something? I thought following scenario. memoryless node # : 1 1's fallback node # : 0 On node 1's cpu, 1. kmem_cache_alloc_node (node 2) 2. allocate the page on node 2 for the slab, now cpu slab is that one. 3. kmem_cache_alloc_node (local node, that is, node 1) 4. It check node_spanned_pages() and find it is memoryless node. So return node 2's memory. Is it impossible scenario? Thanks. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 06:31:56PM +0900, Joonsoo Kim wrote: On Tue, Jan 07, 2014 at 05:21:45PM +0800, Wanpeng Li wrote: On Tue, Jan 07, 2014 at 06:10:16PM +0900, Joonsoo Kim wrote: On Tue, Jan 07, 2014 at 04:48:40PM +0800, Wanpeng Li wrote: Hi Joonsoo, On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote: On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote: [...] Hello, I think that we need more efforts to solve unbalanced node problem. With this patch, even if node of current cpu slab is not favorable to unbalanced node, allocation would proceed and we would get the unintended memory. We have a machine: [0.00] Node 0 Memory: [0.00] Node 4 Memory: 0x0-0x1000 0x2000-0x6000 0x8000-0xc000 [0.00] Node 6 Memory: 0x1000-0x2000 0x6000-0x8000 [0.00] Node 10 Memory: 0xc000-0x18000 [0.041486] Node 0 CPUs: 0-19 [0.041490] Node 4 CPUs: [0.041492] Node 6 CPUs: [0.041495] Node 10 CPUs: The pages of current cpu slab should be allocated from fallback zones/nodes of the memoryless node in buddy system, how can not favorable happen? Hi, Wanpeng. IIRC, if we call kmem_cache_alloc_node() with certain node #, we try to allocate the page in fallback zones/node of that node #. So fallback list isn't related to fallback one of memoryless node #. Am I wrong? Anton add node_spanned_pages(node) check, so current cpu slab mentioned above is against memoryless node. If I miss something? I thought following scenario. memoryless node # : 1 1's fallback node # : 0 On node 1's cpu, 1. kmem_cache_alloc_node (node 2) 2. allocate the page on node 2 for the slab, now cpu slab is that one. 3. kmem_cache_alloc_node (local node, that is, node 1) 4. It check node_spanned_pages() and find it is memoryless node. So return node 2's memory. Is it impossible scenario? Indeed, it can happen. Regards, Wanpeng Li Thanks. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
From: Anton Blanchard
We noticed a huge amount of slab memory consumed on a large ppc64 box:
Slab:2094336 kB
Almost 2GB. This box is not balanced and some nodes do not have local
memory, causing slub to be very inefficient in its slab usage.
Each time we call kmem_cache_alloc_node slub checks the per cpu slab,
sees it isn't node local, deactivates it and tries to allocate a new
slab. ...
...
if (unlikely(!node_match(page, node))) {
stat(s, ALLOC_NODE_MISMATCH);
deactivate_slab(s, page, c-freelist);
c-page = NULL;
c-freelist = NULL;
goto new_slab;
}
Why not just delete the entire test?
Presumably some time a little earlier no local memory was available.
Even if there is some available now, it is very likely that some won't
be available again in the near future.
David.
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RE: [PATCH 1/2] pci: Fix root port bus-self is NULL
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 38e403d..7f2d1ab 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) if (!dev-is_added) nr++; + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + bus-self = dev; In this case, bus is the pci root bus I think, so why set bus-self = root port ? bus-self should pointer to the pci device that bridge out this bus. Yes, this patch seems wrong. If dev is root port, bus should be root bus, so we shouldn't set root_bus-self = pci_dev_of_root_port. Why the root bus-self pointer to the bridge? If child bus create from root bus, the child-self will get the bridge(root port) pci device. Actually PCI core has correctly setup pci_bus-self for secondary bus of PCIe root port. Yes, right. But the root-bus-self is NULL. I think the root bus should get root port pci device for itself. If there is no bridge at board how to get the root port device? -Dongsheng Thanks! Gerry ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote:
On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
We noticed a huge amount of slab memory consumed on a large ppc64 box:
Slab:2094336 kB
Almost 2GB. This box is not balanced and some nodes do not have local
memory, causing slub to be very inefficient in its slab usage.
Each time we call kmem_cache_alloc_node slub checks the per cpu slab,
sees it isn't node local, deactivates it and tries to allocate a new
slab. On empty nodes we will allocate a new remote slab and use the
first slot, but as explained above when we get called a second time
we will just deactivate that slab and retry.
As such we end up only using 1 entry in each slab:
slabmem objects
used active
kmalloc-16384 1404 MB4.90%
task_struct 668 MB2.90%
kmalloc-128 193 MB3.61%
kmalloc-192 152 MB5.23%
kmalloc-8192 72 MB 23.40%
kmalloc-1664 MB7.43%
kmalloc-512 33 MB 22.41%
The patch below checks that a node is not empty before deactivating a
slab and trying to allocate it again. With this patch applied we now
use about 352MB:
Slab: 360192 kB
And our efficiency is much better:
slabmem objects
used active
kmalloc-16384 92 MB 74.27%
task_struct 23 MB 83.46%
idr_layer_cache 18 MB 100.00%
pgtable-2^12 17 MB 100.00%
kmalloc-65536 15 MB 100.00%
inode_cache 14 MB 100.00%
kmalloc-256 14 MB 97.81%
kmalloc-8192 14 MB 85.71%
Signed-off-by: Anton Blanchard an...@samba.org
---
Thoughts? It seems like we could hit a similar situation if a machine
is balanced but we run out of memory on a single node.
Index: b/mm/slub.c
===
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -2278,10 +2278,17 @@ redo:
if (unlikely(!node_match(page, node))) {
stat(s, ALLOC_NODE_MISMATCH);
-deactivate_slab(s, page, c-freelist);
-c-page = NULL;
-c-freelist = NULL;
-goto new_slab;
+
+/*
+ * If the node contains no memory there is no point in trying
+ * to allocate a new node local slab
+ */
+if (node_spanned_pages(node)) {
+deactivate_slab(s, page, c-freelist);
+c-page = NULL;
+c-freelist = NULL;
+goto new_slab;
+}
}
/*
Hello,
I think that we need more efforts to solve unbalanced node problem.
With this patch, even if node of current cpu slab is not favorable to
unbalanced node, allocation would proceed and we would get the unintended
memory.
And there is one more problem. Even if we have some partial slabs on
compatible node, we would allocate new slab, because get_partial() cannot
handle
this unbalance node case.
To fix this correctly, how about following patch?
Thanks.
-8
diff --git a/mm/slub.c b/mm/slub.c
index c3eb3d3..a1f6dfa 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1672,7 +1672,19 @@ static void *get_partial(struct kmem_cache *s, gfp_t
flags, int node,
{
void *object;
int searchnode = (node == NUMA_NO_NODE) ? numa_node_id() : node;
+ struct zonelist *zonelist;
+ struct zoneref *z;
+ struct zone *zone;
+ enum zone_type high_zoneidx = gfp_zone(flags);
+ if (!node_present_pages(searchnode)) {
+ zonelist = node_zonelist(searchnode, flags);
+ for_each_zone_zonelist(zone, z, zonelist, high_zoneidx) {
+ searchnode = zone_to_nid(zone);
+ if (node_present_pages(searchnode))
+ break;
+ }
+ }
Why change searchnode instead of depending on fallback zones/nodes in
get_any_partial() to allocate partial slabs?
Regards,
Wanpeng Li
object = get_partial_node(s, get_node(s, searchnode), c, flags);
if (object || node != NUMA_NO_NODE)
return object;
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RE: [PATCH] powerpc/mpic: supply a .disable callback
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, January 07, 2014 2:39 PM To: Wang Dongsheng-B40534 Cc: b...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] powerpc/mpic: supply a .disable callback On Tue, 2014-01-07 at 13:38 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com Why did you change the author field? :(. I forgot that, I added this code, not use git. Sorry about that, I'll change back after our discussion -Dongsheng -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, January 07, 2014 2:58 PM To: Wang Dongsheng-B40534 Cc: linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989; Kumar Gala Subject: Re: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts On Tue, 2014-01-07 at 14:27 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com AFAICT this patch was originally written by Shaohui Xie. On P3041, P1020, P1021, P1022, P1023 eLBC event interrupts are routed to Int9(P3041) Int3(P102x) while ELBC error interrupts are routed to Int0, we need to call request_irq for each. For p3041 I thought that was only on early silicon revs that we don't support anymore. As for p102x, have you tested that this is actually what happens? How would we distinguish eLBC errors from other error sources, given that there's no EISR0? Do we just hope that no other error interrupts happen? Yes, I tested. The interrupt is shard eLBC interrupt handler could check the error. This patch is fix nobody cared the error interrupt. After sleep resume the lbc will get a chip select error. -Dongsheng -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel] [PATCH] ASoC: fsl_ssi: Fixed wrong printf format identifier
On Tue, Jan 7, 2014 at 4:04 AM, Alexander Shiyan shc_w...@mail.ru wrote: sound/soc/fsl/fsl_ssi.c: In function 'fsl_ssi_probe': sound/soc/fsl/fsl_ssi.c:1180:6: warning: format '%d' expects argument of type 'int', but argument 3 has type 'long int' [-Wformat=] Reported-by: kbuild test robot fengguang...@intel.com Signed-off-by: Alexander Shiyan shc_w...@mail.ru I have sent the same fix as well as I haven't seen your patch before I submitted mine. It is usually a good idea to specify in the commit log what was the commit that caused the warning. Regards, Fabio Estevam ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/mpic: supply a .disable callback
-Original Message- From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org] Sent: Tuesday, January 07, 2014 1:50 PM To: Wang Dongsheng-B40534 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] powerpc/mpic: supply a .disable callback On Tue, 2014-01-07 at 13:38 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com Currently MPIC provides .mask, but not .disable. This means that effectively disable_irq() soft-disables the interrupt, and you get a .mask call if an interrupt actually occurs. I'm not sure if this was intended as a performance benefit (it seems common to omit .disable on powerpc interrupt controllers, but nowhere else), but it interacts badly with threaded/workqueue interrupts (including KVM reflection). In such cases, where the real interrupt handler does a disable_irq_nosync(), schedules defered handling, and returns, we get two interrupts for every real interrupt. The second interrupt does nothing but see that IRQ_DISABLED is set, and decide that it would be a good idea to actually call .mask. We probably don't want to do that for edge, only level interrupts. Sorry Ben, I am not understand your comments. This issue is the kernel api irq_disable() only use chip-irq_disable(), but mpic not have this interface so we don't real disable the interrupt. -Dongsheng Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] slub: Don't throw away partial remote slabs if there is no local memory
On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
We noticed a huge amount of slab memory consumed on a large ppc64 box:
Slab:2094336 kB
Almost 2GB. This box is not balanced and some nodes do not have local
memory, causing slub to be very inefficient in its slab usage.
Each time we call kmem_cache_alloc_node slub checks the per cpu slab,
sees it isn't node local, deactivates it and tries to allocate a new
slab. On empty nodes we will allocate a new remote slab and use the
first slot, but as explained above when we get called a second time
we will just deactivate that slab and retry.
Deactive cpu slab cache doesn't always mean free the slab cache to buddy
system,
maybe the slab cache will be putback to the remote node's partial list if there
are objects still in used in this unbalance situation. In this case, the slub
slow
path can freeze the partial slab in remote node again. So why the slab cache is
fragmented as below?
Regards,
Wanpeng Li
As such we end up only using 1 entry in each slab:
slabmem objects
used active
kmalloc-16384 1404 MB4.90%
task_struct 668 MB2.90%
kmalloc-128 193 MB3.61%
kmalloc-192 152 MB5.23%
kmalloc-8192 72 MB 23.40%
kmalloc-1664 MB7.43%
kmalloc-512 33 MB 22.41%
The patch below checks that a node is not empty before deactivating a
slab and trying to allocate it again. With this patch applied we now
use about 352MB:
Slab: 360192 kB
And our efficiency is much better:
slabmem objects
used active
kmalloc-16384 92 MB 74.27%
task_struct 23 MB 83.46%
idr_layer_cache 18 MB 100.00%
pgtable-2^12 17 MB 100.00%
kmalloc-65536 15 MB 100.00%
inode_cache 14 MB 100.00%
kmalloc-256 14 MB 97.81%
kmalloc-8192 14 MB 85.71%
Signed-off-by: Anton Blanchard an...@samba.org
---
Thoughts? It seems like we could hit a similar situation if a machine
is balanced but we run out of memory on a single node.
Index: b/mm/slub.c
===
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -2278,10 +2278,17 @@ redo:
if (unlikely(!node_match(page, node))) {
stat(s, ALLOC_NODE_MISMATCH);
- deactivate_slab(s, page, c-freelist);
- c-page = NULL;
- c-freelist = NULL;
- goto new_slab;
+
+ /*
+ * If the node contains no memory there is no point in trying
+ * to allocate a new node local slab
+ */
+ if (node_spanned_pages(node)) {
+ deactivate_slab(s, page, c-freelist);
+ c-page = NULL;
+ c-freelist = NULL;
+ goto new_slab;
+ }
}
/*
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Re: [PATCH 1/2] powerpc/dts: fix lbc lack of error interrupt
On Tue, Jan 07, 2014 at 06:26:42AM +, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com P1020, P1021, P1022, P1023 when the lbc get error, the error interrupt will be triggered. The corresponding interrupt is internal IRQ0. So system have to process the lbc IRQ0 interrupt. The corresponding lbc general interrupt is internal IRQ3. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi index 68cc5e7..13f209f 100644 --- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi @@ -36,7 +36,8 @@ #address-cells = 2; #size-cells = 1; compatible = fsl,p1020-elbc, fsl,elbc, simple-bus; - interrupts = 19 2 0 0; + interrupts = 19 2 0 0 + 16 2 0 0; Minor nit: please bracket individual list elements like so: interrupts = 19 2 0 0, 16 2 0 0; Otherwise this looks fine to me. Thanks, Mark. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel] [PATCH] ASoC: fsl_ssi: Fixed wrong printf format identifier
On Tue, Jan 07, 2014 at 08:08:14AM -0200, Fabio Estevam wrote: I have sent the same fix as well as I haven't seen your patch before I submitted mine. I saw Fabio's patch first too. signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] fsl/pci: The new pci suspend/resume implementation
On Tuesday, January 07, 2014 04:04:08 PM Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
The new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume.
Add a PME handler, to response PME message interrupt.
Change platform_driver-suspend/resume to syscore-suspend/resume.
Can you please first describe the problem you're trying to address?
Thanks!
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c
b/arch/powerpc/platforms/85xx/c293pcie.c
index 213d5b8..84476b6 100644
--- a/arch/powerpc/platforms/85xx/c293pcie.c
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -68,6 +68,7 @@ define_machine(c293_pcie) {
.init_IRQ = c293_pcie_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..aa8b9a3 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -163,6 +163,7 @@ define_machine(corenet_generic) {
.init_IRQ = corenet_gen_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_coreint_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c
b/arch/powerpc/platforms/85xx/ge_imp3a.c
index e6285ae..11790e0 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) {
.show_cpuinfo = ge_imp3a_show_cpuinfo,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c
b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 15ce4b5..a378ba3 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) {
.init_IRQ = mpc8536_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 7a31a0e..b0753e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) {
#ifdef CONFIG_PCI
.restart= mpc85xx_cds_restart,
.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#else
.restart= fsl_rstcr_restart,
#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 9ebb91e..ffdf021 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) {
.init_IRQ = mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) {
.init_IRQ = mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -237,6 +239,7 @@ define_machine(p2020_ds) {
.init_IRQ = mpc85xx_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..6cd3b8a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -416,6 +416,7 @@
Re: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts
On Tue, 2014-01-07 at 04:01 -0600, Wang Dongsheng-B40534 wrote: -Original Message- From: Wood Scott-B07421 Sent: Tuesday, January 07, 2014 2:58 PM To: Wang Dongsheng-B40534 Cc: linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989; Kumar Gala Subject: Re: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts On Tue, 2014-01-07 at 14:27 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com AFAICT this patch was originally written by Shaohui Xie. On P3041, P1020, P1021, P1022, P1023 eLBC event interrupts are routed to Int9(P3041) Int3(P102x) while ELBC error interrupts are routed to Int0, we need to call request_irq for each. For p3041 I thought that was only on early silicon revs that we don't support anymore. As for p102x, have you tested that this is actually what happens? How would we distinguish eLBC errors from other error sources, given that there's no EISR0? Do we just hope that no other error interrupts happen? Yes, I tested. The interrupt is shard eLBC interrupt handler could check the error. This patch is fix nobody cared the error interrupt. After sleep resume the lbc will get a chip select error. s/no other error interrupts happen/no other error interrupts for which we don't have a handler registered or which don't even have an associated status register happen/ -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mpic: supply a .disable callback
On Tue, 2014-01-07 at 04:18 -0600, Wang Dongsheng-B40534 wrote: -Original Message- From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org] Sent: Tuesday, January 07, 2014 1:50 PM To: Wang Dongsheng-B40534 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] powerpc/mpic: supply a .disable callback On Tue, 2014-01-07 at 13:38 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com Currently MPIC provides .mask, but not .disable. This means that effectively disable_irq() soft-disables the interrupt, and you get a .mask call if an interrupt actually occurs. I'm not sure if this was intended as a performance benefit (it seems common to omit .disable on powerpc interrupt controllers, but nowhere else), but it interacts badly with threaded/workqueue interrupts (including KVM reflection). In such cases, where the real interrupt handler does a disable_irq_nosync(), schedules defered handling, and returns, we get two interrupts for every real interrupt. The second interrupt does nothing but see that IRQ_DISABLED is set, and decide that it would be a good idea to actually call .mask. We probably don't want to do that for edge, only level interrupts. Sorry Ben, I am not understand your comments. This issue is the kernel api irq_disable() only use chip-irq_disable(), but mpic not have this interface so we don't real disable the interrupt. I think he means that the two interrupts for every real interrupt effect will only happen with level triggered interrupts, and he'd like to keep the potential performance benefit of lazy disabling for edge interrupts. To implement this for ordinary edge interrupts (not IPI, timer, etc) we'd need to add a new .irq_disable() function that checks whether it's level/edge and only calls .irq_mask() if level -- or, introduce a separate struct irq_chip for edge versus level. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mpic: supply a .disable callback
On Tue, 2014-01-07 at 10:18 +, dongsheng.w...@freescale.com wrote: -Original Message- From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org] Sent: Tuesday, January 07, 2014 1:50 PM To: Wang Dongsheng-B40534 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] powerpc/mpic: supply a .disable callback On Tue, 2014-01-07 at 13:38 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com Currently MPIC provides .mask, but not .disable. This means that effectively disable_irq() soft-disables the interrupt, and you get a .mask call if an interrupt actually occurs. I'm not sure if this was intended as a performance benefit (it seems common to omit .disable on powerpc interrupt controllers, but nowhere else), but it interacts badly with threaded/workqueue interrupts (including KVM reflection). In such cases, where the real interrupt handler does a disable_irq_nosync(), schedules defered handling, and returns, we get two interrupts for every real interrupt. The second interrupt does nothing but see that IRQ_DISABLED is set, and decide that it would be a good idea to actually call .mask. We probably don't want to do that for edge, only level interrupts. Sorry Ben, I am not understand your comments. This issue is the kernel api irq_disable() only use chip-irq_disable(), but mpic not have this interface so we don't real disable the interrupt. Yes, because we want to keep the existing behaviour of lazy disable for edge interrupts. It's faster. Cheers, Ben. -Dongsheng Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v3, 3/7] powerpc: enable the relocatable support for the fsl booke 32bit kernel
On Sat, 2014-01-04 at 14:34 +0800, Kevin Hao wrote: On Fri, Jan 03, 2014 at 06:49:09PM -0600, Scott Wood wrote: On Fri, 2013-12-20 at 15:43 +0800, Kevin Hao wrote: On Wed, Dec 18, 2013 at 05:48:25PM -0600, Scott Wood wrote: On Wed, Aug 07, 2013 at 09:18:31AM +0800, Kevin Hao wrote: This is based on the codes in the head_44x.S. The difference is that the init tlb size we used is 64M. With this patch we can only load the kernel at address between memstart_addr ~ memstart_addr + 64M. We will fix this restriction in the following patches. Which following patch fixes the restriction? With all seven patches applied, I was still only successful booting within 64M of memstart_addr. There is bug in this patch series when booting above the 64M. It seems that I missed to test this previously. Sorry for that. With the following change I can boot the kernel at 0x500. I tried v4 and it still doesn't work for me over 64M (without increasing the start of memory). I pulled the following out of the log buffer when booting at 0x500 (after cleaning up the binary goo -- is that something new?): Unable to handle kernel paging request for data at address 0xbffe4008 Actually there still have one limitation that we have to make sure that the kernel and dtb are in the 64M memory mapped by the init tlb entry. I booted the kernel successfully by using the following u-boot commands: setenv fdt_high 0x dhcp 600 128.224.162.196:/vlm-boards/p5020/uImage tftp 6f0 128.224.162.196:/vlm-boards/p5020/p5020ds.dtb bootm 600 - 6f0 OK, that was it -- I hadn't set fdt_high and thus U-Boot was relocating the fdt under 64M. We should probably be using ioremap_prot() (or some other mechanism) to create a special mapping, rather than assuming the fdt is covered by the initial TLB entry. That doesn't need to happen as part of this patchset, of course, as it's not a new limitation. I'm having a hard time following the logic here. What is PAGE_OFFSET - offset supposed to be? Why would we map anything belowe PAGE_OFFSET? No, we don't map the address below PAGE_OFFSET. memstart_addr is the physical start address of RAM. start is the kernel running physical address aligned with 64M. offset = memstart_addr - start So if memstart_addr start, the offset is negative. The PAGE_OFFSET - offset is the virtual start address we should use for the init 64M map. It's above the PAGE_OFFSET instead of below. Oh. I think it'd be more readable to do offset = start - memstart_addr and add offset instead of subtracting it. Also, offset should be phys_addr_t -- even if you don't expect to support offsets greater than 4G on 32-bit, it's semantically the right type to use. Plus, int would break if this code were ever used with 64-bit. If you're OK with these changes, I can fix it while applying. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v5 1/1] powerpc/embedded6xx: Add support for Motorola/Emerson MVME5100
On Mon, 2014-01-06 at 12:23 +1100, Stephen Chivers wrote: Add support for the Motorola/Emerson MVME5100 Single Board Computer. The MVME5100 is a 6U form factor VME64 computer with: - A single MPC7410 or MPC750 CPU - A HAWK Processor Host Bridge (CPU to PCI) and MultiProcessor Interrupt Controller (MPIC) - Up to 500Mb of onboard memory - A M48T37 Real Time Clock (RTC) and Non-Volatile Memory chip - Two 16550 compatible UARTS - Two Intel E100 Fast Ethernets - Two PCI Mezzanine Card (PMC) Slots - PPCBug Firmware The HAWK PHB/MPIC is compatible with the MPC10x devices. There is no onboard disk support. This is usually provided by installing a PMC in first PMC slot. This patch revives the board support, it was present in early 2.6 series kernels. The board support in those days was by Matt Porter of MontaVista Software. CSC Australia has around 31 of these boards in service. The kernel in use for the boards is based on 2.6.31. The boards are operated without disks from a file server. This patch is based on linux-3.13-rc2 and has been boot tested. Only boards with 512 Mb of memory are known to work. V1-V2: Address comments by Kumar Gala and Scott Wood. Minor adjustment to platforms/embedded6xx/Kconfig to ensure correct indentation where possible. V2-V3: Address comments by Scott Wood and Ben Herrenschmidt. Address errors reported by checkpatch. V3-V4: Address comment by Geert Uytterhoeven Add tested by Alessio Bogani. V4-V5: Correct horrible typo in patch history. Kular Gama is Kumar Gala. The patch history should go below the --- line, as it's for reviewers who have seen previous versions rather than for the git history. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7] clk: corenet: Adds the clock binding
On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote: +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present Why are we specifying #address-cells/#size-cells here? +2. Clock Provider/Consumer Binding + +Most of the bindings are from the common clock binding[1]. + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : Should include one of the following: + * fsl,qoriq-core-pll-1.0 for core PLL clocks (v1.0) +* fsl,qoriq-core-pll-2.0 for core PLL clocks (v2.0) +* fsl,qoriq-core-mux-1.0 for core mux clocks (v1.0) +* fsl,qoriq-core-mux-2.0 for core mux clocks (v2.0) + * fsl,qoriq-sysclk-1.0: for input system clock (v1.0) + * fsl,qoriq-sysclk-2.0: for input system clock (v2.0) Some of those lines use tabs and others spaces -- I can fix when applying. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [V6,2/2] powerpc/85xx: Add TWR-P1025 board support
On Wed, Nov 06, 2013 at 05:08:03PM +0800, Xie Xiaobo wrote: TWR-P1025 Overview - 512Mbyte DDR3 (on board DDR) 64MB Nor Flash eTSEC1: Connected to RGMII PHY AR8035 eTSEC3: Connected to RGMII PHY AR8035 Two USB2.0 Type A One microSD Card slot One mini-PCIe slot One mini-USB TypeB dual UART Signed-off-by: Michael Johnston michael.johns...@freescale.com Signed-off-by: Xie Xiaobo x@freescale.com --- Patch V6: Add a binding doc for ssd1289 device. Patch V5: Miscellaneous modification. e.g. move the qe ucc node into dtsi. Patch V4: Fix the mdio phy interrupt issue in dts Patch V3: fix pcie range issue in dts Patch V2: QE related init codes were factored out to a common file .../devicetree/bindings/video/ssd1289fb.txt| 13 + arch/powerpc/boot/dts/p1025twr.dts | 95 +++ arch/powerpc/boot/dts/p1025twr.dtsi| 280 + arch/powerpc/platforms/85xx/Kconfig| 6 + arch/powerpc/platforms/85xx/Makefile | 1 + arch/powerpc/platforms/85xx/twr_p102x.c| 147 +++ No mpc85xx_smp_defconfig update? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v4] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig
On Fri, Nov 15, 2013 at 05:28:20PM -0600, Lijun Pan wrote: mpc85xx_smp_defconfig and mpc85xx_defconfig already have CONFIG_P1023RDS=y. Merge CONFIG_P1023RDB=y and other relevant configurations into mpc85xx_smp_defconfig and mpc85_defconfig. Signed-off-by: Lijun Pan lijun@freescale.com I'll fix it when applying, but please keep commit messages wrapped to around 70 characters, and keep subject lines even shorter. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: drivers/tty: ehv_bytechan fails to build as a module
On Sat, 2014-01-04 at 11:15 -0800, Guenter Roeck wrote: On Mon, Dec 09, 2013 at 04:03:10PM +1100, Anton Blanchard wrote: ehv_bytechan is marked tristate but fails to build as a module: drivers/tty/ehv_bytechan.c:363:1: error: type defaults to ‘int’ in declaration of ‘console_initcall’ [-Werror=implicit-int] It doesn't make much sense for a console driver to be built as a module, so change it to a bool. Signed-off-by: Anton Blanchard an...@samba.org Any comments on this patch ? The problem still causes powerpc:allmodconfig to fail. It's fine with me... Greg, are you going to take this via tty.git or do you want it to go via PPC? -Scott Guenter --- Index: b/drivers/tty/Kconfig === --- a/drivers/tty/Kconfig +++ b/drivers/tty/Kconfig @@ -366,7 +366,7 @@ config TRACE_SINK Trace data router for MIPI P1149.7 cJTAG standard. config PPC_EPAPR_HV_BYTECHAN - tristate ePAPR hypervisor byte channel driver + bool ePAPR hypervisor byte channel driver depends on PPC select EPAPR_PARAVIRT help ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: drivers/tty: ehv_bytechan fails to build as a module
On Tue, Jan 07, 2014 at 07:21:03PM -0600, Scott Wood wrote: On Sat, 2014-01-04 at 11:15 -0800, Guenter Roeck wrote: On Mon, Dec 09, 2013 at 04:03:10PM +1100, Anton Blanchard wrote: ehv_bytechan is marked tristate but fails to build as a module: drivers/tty/ehv_bytechan.c:363:1: error: type defaults to ‘int’ in declaration of ‘console_initcall’ [-Werror=implicit-int] It doesn't make much sense for a console driver to be built as a module, so change it to a bool. Signed-off-by: Anton Blanchard an...@samba.org Any comments on this patch ? The problem still causes powerpc:allmodconfig to fail. It's fine with me... Greg, are you going to take this via tty.git or do you want it to go via PPC? Feel free to take it through PPC. Acked-by: Greg Kroah-Hartman gre...@linuxfoundation.org ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] pci: Fix root port bus-self is NULL
On 2014/1/7 17:51, dongsheng.w...@freescale.com wrote: diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 38e403d..7f2d1ab 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) if (!dev-is_added) nr++; + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + bus-self = dev; In this case, bus is the pci root bus I think, so why set bus-self = root port ? bus-self should pointer to the pci device that bridge out this bus. Yes, this patch seems wrong. If dev is root port, bus should be root bus, so we shouldn't set root_bus-self = pci_dev_of_root_port. Why the root bus-self pointer to the bridge? If child bus create from root bus, the child-self will get the bridge(root port) pci device. Actually PCI core has correctly setup pci_bus-self for secondary bus of PCIe root port. Yes, right. But the root-bus-self is NULL. I think the root bus should get root port pci device for itself. If there is no bridge at board how to get the root port device? Hi Dongsheng, PCI root bus represents PCI host bridge, which has no corresponding PCI device. -Dongsheng Thanks! Gerry ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v3, 3/7] powerpc: enable the relocatable support for the fsl booke 32bit kernel
On Tue, Jan 07, 2014 at 05:46:04PM -0600, Scott Wood wrote: On Sat, 2014-01-04 at 14:34 +0800, Kevin Hao wrote: Actually there still have one limitation that we have to make sure that the kernel and dtb are in the 64M memory mapped by the init tlb entry. I booted the kernel successfully by using the following u-boot commands: setenv fdt_high 0x dhcp 600 128.224.162.196:/vlm-boards/p5020/uImage tftp 6f0 128.224.162.196:/vlm-boards/p5020/p5020ds.dtb bootm 600 - 6f0 OK, that was it -- I hadn't set fdt_high and thus U-Boot was relocating the fdt under 64M. We should probably be using ioremap_prot() (or some other mechanism) to It is too early to use ioremap_prot() for this case. create a special mapping, rather than assuming the fdt is covered by the initial TLB entry. That doesn't need to happen as part of this patchset, of course, as it's not a new limitation. In order to fix this limitation we would have to create a separate map for the dtb if it is not covered by the init 64M tlb. I would like to give it a try if I can get some time. I'm having a hard time following the logic here. What is PAGE_OFFSET - offset supposed to be? Why would we map anything belowe PAGE_OFFSET? No, we don't map the address below PAGE_OFFSET. memstart_addr is the physical start address of RAM. start is the kernel running physical address aligned with 64M. offset = memstart_addr - start So if memstart_addr start, the offset is negative. The PAGE_OFFSET - offset is the virtual start address we should use for the init 64M map. It's above the PAGE_OFFSET instead of below. Oh. I think it'd be more readable to do offset = start - memstart_addr and add offset instead of subtracting it. Yes, I agree. The reason that I use offset = memstart_addr - start is that it seems memstart_addr is always greater than start when we are booting a kdump kernel with a kernel option like crashkernel=64M@80M. :-) Also, offset should be phys_addr_t -- even if you don't expect to support offsets greater than 4G on 32-bit, it's semantically the right type to use. Plus, int would break if this code were ever used with 64-bit. I thought about using phy_addr_t for the offset originally but gave it up for the following reasons: * It will not be greater than 4G. * We have to use the ugly #ifdef CONFIG_PHYS_64BIT in restore_to_as0(). * Need more registers for arguments for restore_to_as0(). Of course you can change it to phys_addr_t if you prefer. Thanks, Kevin If you're OK with these changes, I can fix it while applying. -Scott pgpv7dsFDc2nR.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/2] pci: Fix root port bus-self is NULL
-Original Message- From: Jiang Liu [mailto:jiang@linux.intel.com] Sent: Wednesday, January 08, 2014 10:33 AM To: Wang Dongsheng-B40534; Yijing Wang; bhelg...@google.com; r...@rjwysocki.net Cc: Wood Scott-B07421; ga...@codeaurora.org; Zang Roy-R61911; linux- p...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 1/2] pci: Fix root port bus-self is NULL On 2014/1/7 17:51, dongsheng.w...@freescale.com wrote: diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 38e403d..7f2d1ab 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) if (!dev-is_added) nr++; +if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) +bus-self = dev; In this case, bus is the pci root bus I think, so why set bus-self = root port ? bus-self should pointer to the pci device that bridge out this bus. Yes, this patch seems wrong. If dev is root port, bus should be root bus, so we shouldn't set root_bus-self = pci_dev_of_root_port. Why the root bus-self pointer to the bridge? If child bus create from root bus, the child-self will get the bridge(root port) pci device. Actually PCI core has correctly setup pci_bus-self for secondary bus of PCIe root port. Yes, right. But the root-bus-self is NULL. I think the root bus should get root port pci device for itself. If there is no bridge at board how to get the root port device? Hi Dongsheng, PCI root bus represents PCI host bridge, which has no corresponding PCI device. Yes, agree. If more than one bridge on the root bus, this patch is wrong. Thanks for your review. :) -Dongsheng -Dongsheng Thanks! Gerry ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Fix alignment of secondary cpu spin vars
On Fri, 2014-01-03 at 00:12 -0800, Olof Johansson wrote: On Thu, Jan 02, 2014 at 11:56:04PM -0800, Olof Johansson wrote: This makes things interesting though. The BE/LE trampoline code assumes at least 3 consecutive instructions. What was the reasoning behind entering the kernel LE instead of keeping the old boot protocol and just switching to LE once kernel is loaded? Is it actually used on some platforms or is this just a theoretical thing? Actually, adding a little hack that zeroes out the memory once we're done executing it will work just fine too. I know this is sort of icky, but maybe it'll be good enough for now? Of course, main worry is that this is just hiding some latent NULL deref in the kernel now... :-/ Wow, that would have to come close to winning the grossest-hack-in-arch-powerpc award :) Have you tried changing the value at 8 to point to a reserved page? Some other possibilities: * Change the #define so FIXUP_ENDIAN is empty for PASEMI, that would mean you'd only be able to boot pasemi_defconfig. * Move the hack into FIXUP_ENDIAN cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: add vr save/restore functions
On Mon, 2013-12-30 at 15:31 +0100, Andreas Schwab wrote: GCC 4.8 now generates out-of-line vr save/restore functions when optimizing for size. They are needed for the raid6 altivec support. It looks like they're identical for 32 64-bit ? If so can't we arrange to have a single version? cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Fix alignment of secondary cpu spin vars
On Wed, 2014-01-08 at 15:09 +1100, Michael Ellerman wrote:
Of course, main worry is that this is just hiding some latent NULL
deref in
the kernel now... :-/
Wow, that would have to come close to winning the
grossest-hack-in-arch-powerpc
award :)
Have you tried changing the value at 8 to point to a reserved page?
Some other possibilities:
* Change the #define so FIXUP_ENDIAN is empty for PASEMI, that would
mean
you'd only be able to boot pasemi_defconfig.
* Move the hack into FIXUP_ENDIAN
We actually found the root cause on irc the other day, I was waiting for
Olof to send a fix :-)
Olof: Can you try this totally untested patch ?
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -1986,8 +1986,6 @@ static void __init prom_init_stdout(void)
/* Get the full OF pathname of the stdout device */
memset(path, 0, 256);
call_prom(instance-to-path, 3, 1, prom.stdout, path, 255);
- stdout_node = call_prom(instance-to-package, 1, 1, prom.stdout);
- val = cpu_to_be32(stdout_node);
prom_setprop(prom.chosen, /chosen, linux,stdout-package,
val, sizeof(val));
prom_printf(OF stdout device is: %s\n, of_stdout_device);
@@ -1995,10 +1993,14 @@ static void __init prom_init_stdout(void)
path, strlen(path) + 1);
/* If it's a display, note it */
- memset(type, 0, sizeof(type));
- prom_getprop(stdout_node, device_type, type, sizeof(type));
- if (strcmp(type, display) == 0)
- prom_setprop(stdout_node, path, linux,boot-display, NULL, 0);
+ stdout_node = call_prom(instance-to-package, 1, 1, prom.stdout);
+ if (stdout_node != PROM_ERROR) {
+ val = cpu_to_be32(stdout_node);
+ memset(type, 0, sizeof(type));
+ prom_getprop(stdout_node, device_type, type, sizeof(type));
+ if (strcmp(type, display) == 0)
+ prom_setprop(stdout_node, path, linux,boot-display, NU
+ }
}
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[PATCH 02/12][v4] pci: fsl: add structure fsl_pci
PowerPC uses structure pci_controller to describe PCI controller,
but ARM uses structure pci_sys_data. In order to support PowerPC
and ARM simultaneously, the patch adds a structure fsl_pci that
contains most of the members of the pci_controller and pci_sys_data.
Meanwhile, it defines a interface fsl_arch_sys_to_pci() which should
be implemented in architecture-specific PCI controller driver to
convert pci_controller or pci_sys_data to fsl_pci.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
Added indirect type macro
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
include/linux/fsl/pci-common.h | 48 ++
1 file changed, 48 insertions(+)
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 5e4f683..7ea20a1 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -102,5 +102,53 @@ struct ccsr_pci {
};
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct fsl_pci {
+ struct list_head node;
+ bool is_pcie;
+ struct device_node *dn;
+ struct device *dev;
+
+ int first_busno;
+ int last_busno;
+ int self_busno;
+ struct resource busn;
+
+ struct pci_ops *ops;
+ struct ccsr_pci __iomem *regs;
+
+#define INDIRECT_TYPE_SET_CFG_TYPE 0x0001
+#define INDIRECT_TYPE_EXT_REG 0x0002
+#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x0004
+#define INDIRECT_TYPE_NO_PCIE_LINK 0x0008
+#define INDIRECT_TYPE_BIG_ENDIAN 0x0010
+#define INDIRECT_TYPE_BROKEN_MRM 0x0020
+#define INDIRECT_TYPE_FSL_CFG_REG_LINK 0x0040
+ u32 indirect_type;
+
+ struct resource io_resource;
+ resource_size_t io_base_phys;
+ resource_size_t pci_io_size;
+
+ struct resource mem_resources[3];
+ resource_size_t mem_offset[3];
+
+ int global_number; /* PCI domain number */
+
+ resource_size_t dma_window_base_cur;
+ resource_size_t dma_window_size;
+
+ void *sys;
+};
+
+/*
+ * Convert architecture specific pci controller structure to fsl_pci
+ * PowerPC uses structure pci_controller and ARM uses structure pci_sys_data
+ * to describe pci controller.
+ */
+extern struct fsl_pci *fsl_arch_sys_to_pci(void *sys);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
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[PATCH 03/12][v4] pci: fsl: add PCI indirect access support
The patch adds PCI indirect read/write functions. The main code
is ported from arch/powerpc/sysdev/indirect_pci.c. We use general
IO API iowrite32be/ioread32be instead of out_be32/in_be32, and
use structure fsl_Pci instead of PowerPC's pci_controller.
The patch also provides fsl_pcie_check_link() to check PCI link.
The weak function fsl_arch_pci_exclude_device() is provided to
call ppc_md.pci_exclude_device() for PowerPC architecture.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
moved indirect type macro to header file
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 163 --
include/linux/fsl/pci-common.h| 6 ++
2 files changed, 145 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index 69d338b..d1846ee 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -35,52 +35,167 @@
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
-static int fsl_pcie_check_link(struct pci_controller *hose)
+
+int __weak fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int fsl_pci_read_config(struct fsl_pci *pci, int bus, int devfn,
+ int offset, int len, u32 *val)
+{
+ u32 bus_no, reg, data;
+
+ if (pci-indirect_type INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus != pci-first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ if (fsl_arch_pci_exclude_device(pci, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ bus_no = (bus == pci-first_busno) ? pci-self_busno : bus;
+
+ if (pci-indirect_type INDIRECT_TYPE_EXT_REG)
+ reg = ((offset 0xf00) 16) | (offset 0xfc);
+ else
+ reg = offset 0xfc;
+
+ if (pci-indirect_type INDIRECT_TYPE_BIG_ENDIAN)
+ iowrite32be(0x8000 | (bus_no 16) | (devfn 8) | reg,
+ pci-regs-config_addr);
+ else
+ iowrite32(0x8000 | (bus_no 16) | (devfn 8) | reg,
+ pci-regs-config_addr);
+
+ /*
+* Note: the caller has already checked that offset is
+* suitably aligned and that len is 1, 2 or 4.
+*/
+ data = ioread32(pci-regs-config_data);
+ switch (len) {
+ case 1:
+ *val = (data (8 * (offset 3))) 0xff;
+ break;
+ case 2:
+ *val = (data (8 * (offset 3))) 0x;
+ break;
+ default:
+ *val = data;
+ break;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int fsl_pci_write_config(struct fsl_pci *pci, int bus, int devfn,
+int offset, int len, u32 val)
+{
+ void __iomem *cfg_data;
+ u32 bus_no, reg;
+
+ if (pci-indirect_type INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus != pci-first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ if (fsl_arch_pci_exclude_device(pci, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ bus_no = (bus == pci-first_busno) ?
+ pci-self_busno : bus;
+
+ if (pci-indirect_type INDIRECT_TYPE_EXT_REG)
+ reg = ((offset 0xf00) 16) | (offset 0xfc);
+ else
+ reg = offset 0xfc;
+
+ if (pci-indirect_type INDIRECT_TYPE_BIG_ENDIAN)
+ iowrite32be(0x8000 | (bus_no 16) | (devfn 8) | reg,
+ pci-regs-config_addr);
+ else
+ iowrite32(0x8000 | (bus_no 16) | (devfn 8) | reg,
+ pci-regs-config_addr);
+
+ /* suppress setting of PCI_PRIMARY_BUS */
+ if (pci-indirect_type INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
+ if ((offset == PCI_PRIMARY_BUS)
+ (bus == pci-first_busno))
+ val = 0xff00;
+
+ /*
+* Note: the caller has already checked that offset is
+* suitably aligned and that len is 1, 2 or 4.
+*/
+ cfg_data = ((void *) (pci-regs-config_data)) + (offset 3);
+ switch (len) {
+ case 1:
+ iowrite8(val, cfg_data);
+ break;
+ case 2:
+ iowrite16(val, cfg_data);
+ break;
+ default:
+ iowrite32(val, cfg_data);
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+bool fsl_pci_check_link(struct fsl_pci *pci)
{
u32 val = 0;
-
[PATCH 04/12][v4] pci: fsl: add early PCI indirect access support
The driver needs to read/write PCI configuration very early, at
that time architecture-specific PCI controller structure and
PCI bus have not been created. The patch provides an interface
fsl_arch_fake_pci_bus which should be implemented in
architecture-specific PCI driver to fake a PCI controller structure
and PCI bus. Using the fake PCI controller and PCI bus, the patch
provides the early indirect read/write functions.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 26 ++
include/linux/fsl/pci-common.h| 7 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index d1846ee..a706100 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -198,6 +198,32 @@ static struct pci_ops fsl_indirect_pci_ops = {
.write = fsl_indirect_write_config,
};
+#define EARLY_FSL_PCI_OP(rw, size, type) \
+int early_fsl_##rw##_config_##size(struct fsl_pci *pci, int bus, \
+ int devfn, int offset, type value) \
+{ \
+ return pci_bus_##rw##_config_##size(fsl_arch_fake_pci_bus(pci, bus),\
+ devfn, offset, value); \
+}
+
+EARLY_FSL_PCI_OP(read, byte, u8 *)
+EARLY_FSL_PCI_OP(read, word, u16 *)
+EARLY_FSL_PCI_OP(read, dword, u32 *)
+EARLY_FSL_PCI_OP(write, byte, u8)
+EARLY_FSL_PCI_OP(write, word, u16)
+EARLY_FSL_PCI_OP(write, dword, u32)
+
+static int early_fsl_find_capability(struct fsl_pci *pci,
+int busnr, int devfn, int cap)
+{
+ struct pci_bus *bus = fsl_arch_fake_pci_bus(pci, busnr);
+
+ if (!bus)
+ return 0;
+
+ return pci_bus_find_capability(bus, devfn, cap);
+}
+
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
unsigned int index, const struct resource *res,
resource_size_t offset)
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 726f27b..fd6c497 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -156,5 +156,12 @@ bool fsl_pci_check_link(struct fsl_pci *pci);
/* To avoid touching specified devices */
int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn);
+/*
+ * To fake a PCI bus
+ * it is called by early_fsl_*(), at that time the architecture-dependent
+ * pci controller and pci bus have not been created.
+ */
+extern struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr);
+
#endif /* __PCI_COMMON_H */
#endif /* __KERNEL__ */
--
1.8.1.2
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[PATCH 01/12][v4] pci: fsl: derive the common PCI driver to drivers/pci/host
The Freescale's Layerscape series processors will use ARM cores.
The LS1's PCIe controllers is the same as T4240's. So it's better
the PCIe controller driver can support PowerPC and ARM
simultaneously. This patch is for this purpose. It derives
the common functions from arch/powerpc/sysdev/fsl_pci.c to
drivers/pci/host/pci-fsl-common.c and leaves the architecture
specific functions which should be implemented in arch related files.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v2-v4:
no change
v1-v2:
1. rename pci.h to pci-common.h
2. rename pci-fsl.c to pci-fsl-common.c
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.c | 521 +-
arch/powerpc/sysdev/fsl_pci.h | 89
.../fsl_pci.c = drivers/pci/host/pci-fsl-common.c | 592 +
.../fsl_pci.h = include/linux/fsl/pci-common.h| 45 +-
4 files changed, 7 insertions(+), 1240 deletions(-)
copy arch/powerpc/sysdev/fsl_pci.c = drivers/pci/host/pci-fsl-common.c (54%)
copy arch/powerpc/sysdev/fsl_pci.h = include/linux/fsl/pci-common.h (79%)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4dfd61d..0764385 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -27,6 +27,7 @@
#include linux/log2.h
#include linux/slab.h
#include linux/uaccess.h
+#include linux/fsl/pci-common.h
#include asm/io.h
#include asm/prom.h
@@ -58,57 +59,8 @@ static void quirk_fsl_pcie_early(struct pci_dev *dev)
return;
}
-static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
- int, int, u32 *);
-
-static int fsl_pcie_check_link(struct pci_controller *hose)
-{
- u32 val = 0;
-
- if (hose-indirect_type PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- if (hose-ops-read == fsl_indirect_read_config) {
- struct pci_bus bus;
- bus.number = hose-first_busno;
- bus.sysdata = hose;
- bus.ops = hose-ops;
- indirect_read_config(bus, 0, PCIE_LTSSM, 4, val);
- } else
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, val);
- if (val PCIE_LTSSM_L0)
- return 1;
- } else {
- struct ccsr_pci __iomem *pci = hose-private_data;
- /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- val = (in_be32(pci-pex_csr0) PEX_CSR0_LTSSM_MASK)
-PEX_CSR0_LTSSM_SHIFT;
- if (val != PEX_CSR0_LTSSM_L0)
- return 1;
- }
-
- return 0;
-}
-
-static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 *val)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
-
- if (fsl_pcie_check_link(hose))
- hose-indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
- else
- hose-indirect_type = ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
-
- return indirect_read_config(bus, devfn, offset, len, val);
-}
-
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-static struct pci_ops fsl_indirect_pcie_ops =
-{
- .read = fsl_indirect_read_config,
- .write = indirect_write_config,
-};
-
#define MAX_PHYS_ADDR_BITS 40
static u64 pci64_dma_offset = 1ull MAX_PHYS_ADDR_BITS;
@@ -132,291 +84,6 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64
dma_mask)
return 0;
}
-static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
-{
- resource_size_t pci_addr = res-start - offset;
- resource_size_t phys_addr = res-start;
- resource_size_t size = resource_size(res);
- u32 flags = 0x80044000; /* enable mem R/W */
- unsigned int i;
-
- pr_debug(PCI MEM resource start 0x%016llx, size 0x%016llx.\n,
- (u64)res-start, (u64)size);
-
- if (res-flags IORESOURCE_PREFETCH)
- flags |= 0x1000; /* enable relaxed ordering */
-
- for (i = 0; size 0; i++) {
- unsigned int bits = min(ilog2(size),
- __ffs(pci_addr | phys_addr));
-
- if (index + i = 5)
- return -1;
-
- out_be32(pci-pow[index + i].potar, pci_addr 12);
- out_be32(pci-pow[index + i].potear, (u64)pci_addr 44);
- out_be32(pci-pow[index + i].powbar, phys_addr 12);
- out_be32(pci-pow[index + i].powar, flags | (bits - 1));
-
- pci_addr += (resource_size_t)1U bits;
- phys_addr += (resource_size_t)1U bits;
- size -= (resource_size_t)1U bits;
-
[PATCH 05/12][v4] pci: fsl: port PCI ATMU related code
The patch ports PCI ATMU related code, just uses general IO API
iowrite32be/ioread32be instead of out_be32/in_be32, uses structure
fsl_pci instead of PowerPC's pci_controller and uses dev_*()
instead of pr_*() to output the information.
The patch also provides the weak function
fsl_arch_pci64_dma_offset(), the architecture-specific driver may
return different offset.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 190 --
include/linux/fsl/pci-common.h| 3 +
2 files changed, 103 insertions(+), 90 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index a706100..26ee4c3 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -35,6 +35,10 @@
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
+u64 __weak fsl_arch_pci64_dma_offset(void)
+{
+ return 0;
+}
int __weak fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
{
@@ -225,8 +229,8 @@ static int early_fsl_find_capability(struct fsl_pci *pci,
}
static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
+ unsigned int index, const struct resource *res,
+ resource_size_t offset)
{
resource_size_t pci_addr = res-start - offset;
resource_size_t phys_addr = res-start;
@@ -247,10 +251,10 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
if (index + i = 5)
return -1;
- out_be32(pci-pow[index + i].potar, pci_addr 12);
- out_be32(pci-pow[index + i].potear, (u64)pci_addr 44);
- out_be32(pci-pow[index + i].powbar, phys_addr 12);
- out_be32(pci-pow[index + i].powar, flags | (bits - 1));
+ iowrite32be(pci_addr 12, pci-pow[index + i].potar);
+ iowrite32be((u64)pci_addr 44, pci-pow[index + i].potear);
+ iowrite32be(phys_addr 12, pci-pow[index + i].powbar);
+ iowrite32be(flags | (bits - 1), pci-pow[index + i].powar);
pci_addr += (resource_size_t)1U bits;
phys_addr += (resource_size_t)1U bits;
@@ -261,21 +265,19 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
}
/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose)
+static void setup_pci_atmu(struct fsl_pci *pci)
{
- struct ccsr_pci __iomem *pci = hose-private_data;
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
u64 mem, sz, paddr_hi = 0;
u64 offset = 0, paddr_lo = ULLONG_MAX;
u32 pcicsrbar = 0, pcicsrbar_sz;
u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
- const char *name = hose-dn-full_name;
const u64 *reg;
int len;
- if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- if (in_be32(pci-block_rev1) = PCIE_IP_REV_2_2) {
+ if (pci-is_pcie) {
+ if (in_be32(pci-regs-block_rev1) = PCIE_IP_REV_2_2) {
win_idx = 2;
start_idx = 0;
end_idx = 3;
@@ -283,47 +285,54 @@ static void setup_pci_atmu(struct pci_controller *hose)
}
/* Disable all windows (except powar0 since it's ignored) */
- for(i = 1; i 5; i++)
- out_be32(pci-pow[i].powar, 0);
+ for (i = 1; i 5; i++)
+ iowrite32be(0, pci-regs-pow[i].powar);
for (i = start_idx; i end_idx; i++)
- out_be32(pci-piw[i].piwar, 0);
+ iowrite32be(0, pci-regs-piw[i].piwar);
/* Setup outbound MEM window */
- for(i = 0, j = 1; i 3; i++) {
- if (!(hose-mem_resources[i].flags IORESOURCE_MEM))
+ for (i = 0, j = 1; i 3; i++) {
+ if (!(pci-mem_resources[i].flags IORESOURCE_MEM))
continue;
- paddr_lo = min(paddr_lo, (u64)hose-mem_resources[i].start);
- paddr_hi = max(paddr_hi, (u64)hose-mem_resources[i].end);
+ paddr_lo = min_t(u64, paddr_lo, pci-mem_resources[i].start);
+ paddr_hi = max_t(u64, paddr_hi, pci-mem_resources[i].end);
/* We assume all memory resources have the same offset */
- offset = hose-mem_offset[i];
- n = setup_one_atmu(pci, j, hose-mem_resources[i], offset);
+ offset = pci-mem_offset[i];
+ n = setup_one_atmu(pci-regs, j, pci-mem_resources[i],
+ offset);
if
[PATCH 07/12][v4] pci: fsl: port PCI platform driver
1. The patch ports FSL PCI platform driver. probe function
initialize fsl_pci and register it to architecture PCI system,
remove function removes fsl_pci from architecture PCI system.
fsl_arch_pci_sys_register() and fsl_arch_pci_sys_remove() should
be implemented in architecture-specific driver to provide
register/remove functionality.
2. Remove architecture-specific header and unnecessary header.
3. Change Kconfig and Makefile to support FSL PCI common driver
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/Kconfig | 1 +
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-fsl-common.c | 43 +++
include/linux/fsl/pci-common.h| 6 ++
5 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b44b52c..c708d80 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -694,6 +694,7 @@ config FSL_SOC
config FSL_PCI
bool
+ select PCI_FSL_COMMON if FSL_SOC_BOOKE || PPC_86xx
select PPC_INDIRECT_PCI
select PCI_QUIRKS
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..290afaa 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCI_FSL_COMMON
+ bool Common driver for Freescale PCI/PCIe controller
+ depends on FSL_SOC_BOOKE || PPC_86xx
+ help
+ This driver provides common support for PCI/PCIE controller
+ on Freescale embedded processors 85xx/86xx/QorIQ/Layerscape.
+ Additional drivers must be enabled in order to provide some
+ architecture-dependent functions and register the controller
+ to PCI subsystem.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..1f8de80 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCI_FSL_COMMON) += pci-fsl-common.o
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index 7184ac7..d608550 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -16,16 +16,12 @@
*/
#include linux/kernel.h
#include linux/pci.h
-#include linux/delay.h
-#include linux/string.h
#include linux/init.h
-#include linux/bootmem.h
#include linux/memblock.h
#include linux/log2.h
-#include linux/slab.h
-#include linux/uaccess.h
#include linux/of_address.h
#include linux/of_pci.h
+#include linux/fsl/pci-common.h
#include asm/io.h
#include asm/prom.h
@@ -665,12 +661,40 @@ static const struct of_device_id pci_ids[] = {
static int fsl_pci_probe(struct platform_device *pdev)
{
int ret;
- struct device_node *node;
+ struct fsl_pci *pci;
- node = pdev-dev.of_node;
- ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+ if (!of_device_is_available(pdev-dev.of_node)) {
+ dev_dbg(pdev-dev, disabled\n);
+ return -ENODEV;
+ }
+
+ pci = devm_kzalloc(pdev-dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci) {
+ dev_err(pdev-dev, no memory for fsl_pci\n);
+ return -ENOMEM;
+ }
+
+ ret = fsl_pci_setup(pdev, pci);
+ if (ret)
+ return ret;
+
+ ret = fsl_arch_pci_sys_register(pci);
+ if (ret) {
+ dev_err(pdev-dev, failed to register pcie to Arch\n);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fsl_pci_remove(struct platform_device *pdev)
+{
+ struct fsl_pci *pci = platform_get_drvdata(pdev);
+
+ if (!pci)
+ return -ENODEV;
- mpc85xx_pci_err_probe(pdev);
+ fsl_arch_pci_sys_remove(pci);
return 0;
}
@@ -714,6 +738,7 @@ static struct platform_driver fsl_pci_driver = {
.of_match_table = pci_ids,
},
.probe = fsl_pci_probe,
+ .remove = fsl_pci_remove,
};
static int __init fsl_pci_init(void)
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 02bcf5b..8d33354 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -166,5 +166,11 @@ extern struct pci_bus *fsl_arch_fake_pci_bus(struct
fsl_pci *pci, int busnr);
/* Return PCI64 DMA offset */
u64 fsl_arch_pci64_dma_offset(void);
+/* Register PCI/PCIe controller to architecture system */
+extern
[PATCH 08/12][v4] pci: fsl: add PowerPC PCI driver
1. Implement fsl_arch_pci64_dma_offset() to return PowerPC PCI64
DMA offset
2. Implement fsl_arch_sys_to_pci() to convert pci_controller
to fsl_pci
3. Implement fsl_arch_fake_pci_bus() to fake pci_controller
and PCI bus.
4. Implement fsl_arch_pci_exclude_device() to call
ppc_md.pci_exclude_device()
5. Implement fsl_arch_pci_sys_register() to initialize pci_controller
according to fsl_pci, add register PCI controller to PowerPC PCI
subsystem.
6. Implement fsl_arch_pci_sys_remove() to remove PCI controller from
PowerPC PCI subsystem.
7. Add mpc83xx_pcie_check_link() because pci-fsl-common dose not
support mpc83xx.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.c | 142 +++---
1 file changed, 135 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 0764385..38e8dca 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -62,7 +62,11 @@ static void quirk_fsl_pcie_early(struct pci_dev *dev)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull MAX_PHYS_ADDR_BITS;
+
+u64 fsl_arch_pci64_dma_offset(void)
+{
+ return 1ull MAX_PHYS_ADDR_BITS;
+}
static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
{
@@ -77,17 +81,44 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64
dma_mask)
if ((dev-bus == pci_bus_type)
dma_mask = DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
set_dma_ops(dev, dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
+ set_dma_offset(dev, fsl_arch_pci64_dma_offset());
}
*dev-dma_mask = dma_mask;
return 0;
}
+struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
+{
+ struct pci_controller *hose = sys;
+ struct fsl_pci *pci = hose-private_data;
+
+ /* Update the first bus number */
+ if (pci-first_busno != hose-first_busno)
+ pci-first_busno = hose-first_busno;
+
+ return pci;
+}
+
+struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr)
+{
+ static struct pci_bus bus;
+ static struct pci_controller hose;
+
+ bus.number = busnr;
+ bus.sysdata = hose;
+ hose.private_data = pci;
+ bus.ops = pci-ops;
+
+ return bus;
+}
+
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
- int i, is_pcie = 0, no_link;
+ bool is_pcie, no_link;
+ int i;
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(hose);
/* The root complex bridge comes up with bogus resources,
* we copy the PHB ones in.
@@ -97,9 +128,8 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
* tricky.
*/
- if (fsl_pcie_bus_fixup)
- is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
- no_link = !!(hose-indirect_type PPC_INDIRECT_TYPE_NO_PCIE_LINK);
+ is_pcie = pci-is_pcie;
+ no_link = !fsl_pci_check_link(pci);
if (bus-parent == hose-bus (is_pcie || no_link)) {
for (i = 0; i PCI_BRIDGE_RESOURCE_NUM; ++i) {
@@ -121,6 +151,94 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
+int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ struct pci_controller *hose = pci-sys;
+
+ if (!hose)
+ return PCIBIOS_SUCCESSFUL;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(hose, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int fsl_arch_pci_sys_register(struct fsl_pci *pci)
+{
+ struct pci_controller *hose;
+
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ hose = pcibios_alloc_controller(pci-dn);
+ if (!hose)
+ return -ENOMEM;
+
+ /* set platform device as the parent */
+ hose-private_data = pci;
+ hose-parent = pci-dev;
+ hose-first_busno = pci-first_busno;
+ hose-last_busno = pci-last_busno;
+ hose-ops = pci-ops;
+
+#ifdef CONFIG_PPC32
+ /* On 32 bits, limit I/O space to 16MB */
+ if (pci-pci_io_size 0x0100)
+ pci-pci_io_size = 0x0100;
+
+ /* 32 bits needs to map IOs here */
+ hose-io_base_virt = ioremap(pci-io_base_phys + pci-io_resource.start,
+pci-pci_io_size);
+
+ /* Expect trouble if pci_addr is not 0 */
+ if (fsl_pci_primary == pci-dn)
+ isa_io_base = (unsigned long)hose-io_base_virt;
+#endif /* CONFIG_PPC32 */
+
+ hose-pci_io_size = pci-io_resource.start + pci-pci_io_size;
+
[PATCH 06/12][v4] pci: fsl: port PCI controller setup code
PCI controller setup code will initialize structure fsl_pci
according to PCI dts node and initialize PCI command register
and ATMU. The patch uses general API of_pci_parse_bus_range
to parse PCI bus range, uses general of_address's API to parse
PCI IO/MEM ranges.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 179 +-
1 file changed, 97 insertions(+), 82 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index 26ee4c3..7184ac7 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -24,6 +24,8 @@
#include linux/log2.h
#include linux/slab.h
#include linux/uaccess.h
+#include linux/of_address.h
+#include linux/of_pci.h
#include asm/io.h
#include asm/prom.h
@@ -498,131 +500,144 @@ static void setup_pci_atmu(struct fsl_pci *pci)
}
}
-static void __init setup_pci_cmd(struct pci_controller *hose)
+static void __init setup_pci_cmd(struct fsl_pci *pci)
{
u16 cmd;
int cap_x;
- early_read_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+ early_fsl_read_config_word(pci, 0, 0, PCI_COMMAND, cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+ early_fsl_write_config_word(pci, 0, 0, PCI_COMMAND, cmd);
- cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
+ cap_x = early_fsl_find_capability(pci, 0, 0, PCI_CAP_ID_PCIX);
if (cap_x) {
int pci_x_cmd = cap_x + PCI_X_CMD;
cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
- } else {
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
- }
+ early_fsl_write_config_word(pci, 0, 0, pci_x_cmd, cmd);
+ } else
+ early_fsl_write_config_byte(pci, 0, 0, PCI_LATENCY_TIMER,
+ 0x80);
}
-int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
+static int __init
+fsl_pci_setup(struct platform_device *pdev, struct fsl_pci *pci)
{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
+ struct resource *rsrc;
u8 hdr_type, progif;
- struct device_node *dev;
- struct ccsr_pci __iomem *pci;
-
- dev = pdev-dev.of_node;
+ struct device_node *dn;
+ struct of_pci_range range;
+ struct of_pci_range_parser parser;
+ int mem = 0;
- if (!of_device_is_available(dev)) {
- pr_warning(%s: disabled\n, dev-full_name);
- return -ENODEV;
- }
+ dn = pdev-dev.of_node;
+ pci-dn = dn;
+ pci-dev = pdev-dev;
- pr_debug(Adding PCI host bridge %s\n, dev-full_name);
+ dev_info(pdev-dev, Find controller %s\n, dn-full_name);
/* Fetch host bridge registers address */
- if (of_address_to_resource(dev, 0, rsrc)) {
- printk(KERN_WARNING Can't get pci register base!);
- return -ENOMEM;
+ rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!rsrc) {
+ dev_err(pdev-dev, Can't get pci register base!);
+ return -EINVAL;
}
+ dev_info(pdev-dev, REG 0x%016llx..0x%016llx\n,
+(u64)rsrc-start, (u64)rsrc-end);
- /* Get bus range if any */
- bus_range = of_get_property(dev, bus-range, len);
- if (bus_range == NULL || len 2 * sizeof(int))
- printk(KERN_WARNING Can't get bus-range for %s, assume
-bus 0\n, dev-full_name);
-
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
+ /* Parse pci range resources from device tree */
+ if (of_pci_range_parser_init(parser, dn)) {
+ dev_err(pdev-dev, missing ranges property\n);
+ return -EINVAL;
+ }
- /* set platform device as the parent */
- hose-parent = pdev-dev;
- hose-first_busno = bus_range ? bus_range[0] : 0x0;
- hose-last_busno = bus_range ? bus_range[1] : 0xff;
+ /* Get the I/O and memory ranges from device tree */
+ for_each_of_pci_range(parser, range) {
+ unsigned long restype = range.flags IORESOURCE_TYPE_BITS;
+ if (restype == IORESOURCE_IO) {
+ of_pci_range_to_resource(range, dn,
+pci-io_resource);
+
[PATCH 11/12][v4] pci: fsl: update PCI EDAC driver
1. The pci-fsl-common driver has set fsl_pci to device as drvdata,
so EDAC driver can not call dev_set_drvdata() again. fsl_pci
contains regs field to point PCI CCSR, so EDAC may directly use
the pointer and not need to call devm_ioremap().
2. Add mpc85xx_pci_err_remove() to disable PCI error interrupt
and delete PCI EDAC from EDAC subsystem.
3. AER uses the same IRQ, so change IRQ handling mode as shared
to avoid AER can not request IRQ.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
Changed IRQ handling mode as shared to avoid aer can not request IRQ.
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Added mpc85xx_pci_err_remove()
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.h | 6 +
drivers/edac/mpc85xx_edac.c | 61 +--
drivers/edac/mpc85xx_edac.h | 1 +
4 files changed, 43 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6d9bec4..2e3455e 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -236,6 +236,7 @@ void fsl_arch_pci_sys_remove(struct fsl_pci *pci)
if (!hose)
return;
+ mpc85xx_pci_err_remove(to_platform_device(pci-dev));
pcibios_free_controller(hose);
}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index ce77aad..ae4dbe2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -35,11 +35,17 @@ static inline void fsl_pci_assign_primary(void) {}
#ifdef CONFIG_EDAC_MPC85XX
int mpc85xx_pci_err_probe(struct platform_device *op);
+int mpc85xx_pci_err_remove(struct platform_device *op);
#else
static inline int mpc85xx_pci_err_probe(struct platform_device *op)
{
return -ENOTSUPP;
}
+static inline int mpc85xx_pci_err_remove(struct platform_device *op)
+{
+ return -ENOTSUPP;
+}
+
#endif
#ifdef CONFIG_FSL_PCI
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index fd46b0b..ea37db9 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -21,6 +21,7 @@
#include linux/of_platform.h
#include linux/of_device.h
+#include linux/fsl/pci-common.h
#include edac_module.h
#include edac_core.h
#include mpc85xx_edac.h
@@ -214,11 +215,13 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
int mpc85xx_pci_err_probe(struct platform_device *op)
{
+ struct fsl_pci *fslpci;
struct edac_pci_ctl_info *pci;
struct mpc85xx_pci_pdata *pdata;
- struct resource r;
int res = 0;
+ fslpci = platform_get_drvdata(op);
+
if (!devres_open_group(op-dev, mpc85xx_pci_err_probe, GFP_KERNEL))
return -ENOMEM;
@@ -239,7 +242,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
pdata = pci-pvt_info;
pdata-name = mpc85xx_pci_err;
pdata-irq = NO_IRQ;
- dev_set_drvdata(op-dev, pci);
pci-dev = op-dev;
pci-mod_name = EDAC_MOD_STR;
pci-ctl_name = pdata-name;
@@ -250,30 +252,8 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
pdata-edac_idx = edac_pci_idx++;
- res = of_address_to_resource(op-dev.of_node, 0, r);
- if (res) {
- printk(KERN_ERR %s: Unable to get resource for
- PCI err regs\n, __func__);
- goto err;
- }
-
/* we only need the error registers */
- r.start += 0xe00;
-
- if (!devm_request_mem_region(op-dev, r.start, resource_size(r),
- pdata-name)) {
- printk(KERN_ERR %s: Error while requesting mem region\n,
- __func__);
- res = -EBUSY;
- goto err;
- }
-
- pdata-pci_vbase = devm_ioremap(op-dev, r.start, resource_size(r));
- if (!pdata-pci_vbase) {
- printk(KERN_ERR %s: Unable to setup PCI err regs\n, __func__);
- res = -ENOMEM;
- goto err;
- }
+ pdata-pci_vbase = (void *)fslpci-regs + MPC85XX_PCI_ERR_OFFSET;
orig_pci_err_cap_dr =
in_be32(pdata-pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
@@ -297,7 +277,8 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata-irq = irq_of_parse_and_map(op-dev.of_node, 0);
res = devm_request_irq(op-dev, pdata-irq,
- mpc85xx_pci_isr, IRQF_DISABLED,
+ mpc85xx_pci_isr,
+ IRQF_DISABLED | IRQF_SHARED,
[EDAC] PCI err, pci);
if (res 0) {
printk(KERN_ERR
@@ -327,6 +308,34 @@ err:
}
EXPORT_SYMBOL(mpc85xx_pci_err_probe);
+int mpc85xx_pci_err_remove(struct
[PATCH 12/12][v4] pci: fsl: fix function check_pci_ctl_endpt_part
The new FSL PCI driver does not use cfg_addr of pci_controller,
we may directly access PCI CCSR using fsl_pci-regs.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
The new patch to fix function check_pci_ctl_endpt_part
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.h | 5 -
drivers/iommu/fsl_pamu_domain.c | 6 --
include/linux/fsl/pci-common.h | 1 +
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index ae4dbe2..3176eb2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,11 +16,6 @@
struct platform_device;
-
-/* FSL PCI controller BRR1 register */
-#define PCI_FSL_BRR1 0xbf8
-#define PCI_FSL_BRR1_VER 0x
-
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index c857c30..dd7bc25 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -36,6 +36,7 @@
#include asm/pci-bridge.h
#include sysdev/fsl_pci.h
+#include linux/fsl/pci-common.h
#include fsl_pamu_domain.h
#include pci.h
@@ -908,10 +909,11 @@ static struct iommu_group *get_device_iommu_group(struct
device *dev)
static bool check_pci_ctl_endpt_part(struct pci_controller *pci_ctl)
{
u32 version;
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(pci_ctl);
/* Check the PCI controller version number by readding BRR1 register */
- version = in_be32(pci_ctl-cfg_addr + (PCI_FSL_BRR1 2));
- version = PCI_FSL_BRR1_VER;
+ version = in_be32(pci-regs-block_rev1);
+ version = PCIE_IP_REV_MASK;
/* If PCI controller version is = 0x204 we can partition endpoints*/
if (version = 0x204)
return 1;
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 3247682..4e4191e 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -18,6 +18,7 @@
#define PCIE_LTSSM_L0 0x16/* L0 state */
#define PCIE_IP_REV_2_20x02080202 /* PCIE IP block version
Rev2.2 */
#define PCIE_IP_REV_3_00x02080300 /* PCIE IP block version
Rev3.0 */
+#define PCIE_IP_REV_MASK 0x
#define PIWAR_EN 0x8000 /* Enable */
#define PIWAR_PF 0x2000 /* prefetch */
#define PIWAR_TGI_LOCAL0x00f0 /* target - local
memory */
--
1.8.1.2
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[PATCH 09/12][v4] pci: fsl: update PCI PM driver
The patch updates PCI PM driver, uses fsl_pci instead of
pci_controller.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
drivers/pci/host/pci-fsl-common.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index d608550..e3696eb 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -702,19 +702,12 @@ static int fsl_pci_remove(struct platform_device *pdev)
#ifdef CONFIG_PM
static int fsl_pci_resume(struct device *dev)
{
- struct pci_controller *hose;
- struct resource pci_rsrc;
+ struct fsl_pci *pci = dev_get_drvdata(dev);
- hose = pci_find_hose_for_OF_device(dev-of_node);
- if (!hose)
+ if (!pci)
return -ENODEV;
- if (of_address_to_resource(dev-of_node, 0, pci_rsrc)) {
- dev_err(dev, Get pci register base failed.);
- return -ENODEV;
- }
-
- setup_pci_atmu(hose);
+ setup_pci_atmu(pci);
return 0;
}
--
1.8.1.2
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[PATCH 10/12][v4] pci: fsl: support function fsl_pci_assign_primary
Change pci_ids to fsl_pci_ids Freescale-specific name and change
static to extern modifier for using in fsl_pci_assign_primary().
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
change log:
v4:
no change
v1-v3:
Derived from http://patchwork.ozlabs.org/patch/278965/
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.c | 5 +++--
drivers/pci/host/pci-fsl-common.c | 4 ++--
include/linux/fsl/pci-common.h| 2 ++
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 38e8dca..6d9bec4 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -736,7 +736,8 @@ void fsl_pci_assign_primary(void)
of_node_put(np);
np = fsl_pci_primary;
- if (of_match_node(pci_ids, np) of_device_is_available(np))
+ if (of_match_node(fsl_pci_ids, np)
+ of_device_is_available(np))
return;
}
@@ -745,7 +746,7 @@ void fsl_pci_assign_primary(void)
* designate one as primary. This can go away once
* various bugs with primary-less systems are fixed.
*/
- for_each_matching_node(np, pci_ids) {
+ for_each_matching_node(np, fsl_pci_ids) {
if (of_device_is_available(np)) {
fsl_pci_primary = np;
of_node_put(np);
diff --git a/drivers/pci/host/pci-fsl-common.c
b/drivers/pci/host/pci-fsl-common.c
index e3696eb..0be7bc0 100644
--- a/drivers/pci/host/pci-fsl-common.c
+++ b/drivers/pci/host/pci-fsl-common.c
@@ -637,7 +637,7 @@ no_bridge:
return -ENODEV;
}
-static const struct of_device_id pci_ids[] = {
+const struct of_device_id fsl_pci_ids[] = {
{ .compatible = fsl,mpc8540-pci, },
{ .compatible = fsl,mpc8548-pcie, },
{ .compatible = fsl,mpc8610-pci, },
@@ -728,7 +728,7 @@ static struct platform_driver fsl_pci_driver = {
.driver = {
.name = fsl-pci,
.pm = PCI_PM_OPS,
- .of_match_table = pci_ids,
+ .of_match_table = fsl_pci_ids,
},
.probe = fsl_pci_probe,
.remove = fsl_pci_remove,
diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h
index 8d33354..3247682 100644
--- a/include/linux/fsl/pci-common.h
+++ b/include/linux/fsl/pci-common.h
@@ -143,6 +143,8 @@ struct fsl_pci {
void *sys;
};
+extern const struct of_device_id fsl_pci_ids[];
+
/*
* Convert architecture specific pci controller structure to fsl_pci
* PowerPC uses structure pci_controller and ARM uses structure pci_sys_data
--
1.8.1.2
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RE: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts
-Original Message- From: Wood Scott-B07421 Sent: Wednesday, January 08, 2014 4:45 AM To: Wang Dongsheng-B40534 Cc: linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989; Kumar Gala Subject: Re: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts On Tue, 2014-01-07 at 04:01 -0600, Wang Dongsheng-B40534 wrote: -Original Message- From: Wood Scott-B07421 Sent: Tuesday, January 07, 2014 2:58 PM To: Wang Dongsheng-B40534 Cc: linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989; Kumar Gala Subject: Re: [PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts On Tue, 2014-01-07 at 14:27 +0800, Dongsheng Wang wrote: From: Wang Dongsheng dongsheng.w...@freescale.com AFAICT this patch was originally written by Shaohui Xie. On P3041, P1020, P1021, P1022, P1023 eLBC event interrupts are routed to Int9(P3041) Int3(P102x) while ELBC error interrupts are routed to Int0, we need to call request_irq for each. For p3041 I thought that was only on early silicon revs that we don't support anymore. As for p102x, have you tested that this is actually what happens? How would we distinguish eLBC errors from other error sources, given that there's no EISR0? Do we just hope that no other error interrupts happen? Yes, I tested. The interrupt is shard eLBC interrupt handler could check the error. This patch is fix nobody cared the error interrupt. After sleep resume the lbc will get a chip select error. s/no other error interrupts happen/no other error interrupts for which we don't have a handler registered or which don't even have an associated status register happen/ If the ip-block does not handle their error interrupt is a ip-block issue that. Since the use of this shared interrupt must maintain their status, once there is no deal shared interrupt, it will affect the other ip-block. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
