[PATCH] powerpc/zImage: make the OF wrapper support ePAPR boot
This makes the OF zImage wrapper (zImage.pseries, zImage.pmac,
zImage.maple) work if booted via a flat device-tree (ePAPR boot
mode), and thus potentially usable with kexec.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/boot/Makefile| 4 ++--
arch/powerpc/boot/epapr-wrapper.c | 9 +
arch/powerpc/boot/epapr.c | 4 ++--
arch/powerpc/boot/of.c| 16 +++-
arch/powerpc/boot/wrapper | 9 +
5 files changed, 33 insertions(+), 9 deletions(-)
create mode 100644 arch/powerpc/boot/epapr-wrapper.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 6a15c96..15ca225 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -74,7 +74,7 @@ src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c
-src-plat-y := of.c
+src-plat-y := of.c epapr.c
src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
treeboot-walnut.c cuboot-acadia.c \
cuboot-kilauea.c simpleboot.c \
@@ -97,7 +97,7 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c
cuboot-mpc7448hpc2.c \
prpmc2800.c
src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
-src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c
+src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
src-wlib := $(sort $(src-wlib-y))
src-plat := $(sort $(src-plat-y))
diff --git a/arch/powerpc/boot/epapr-wrapper.c
b/arch/powerpc/boot/epapr-wrapper.c
new file mode 100644
index 000..c101910
--- /dev/null
+++ b/arch/powerpc/boot/epapr-wrapper.c
@@ -0,0 +1,9 @@
+extern void epapr_platform_init(unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6,
+ unsigned long r7);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ epapr_platform_init(r3, r4, r5, r6, r7);
+}
diff --git a/arch/powerpc/boot/epapr.c b/arch/powerpc/boot/epapr.c
index 06c1961..02e91aa 100644
--- a/arch/powerpc/boot/epapr.c
+++ b/arch/powerpc/boot/epapr.c
@@ -48,8 +48,8 @@ static void platform_fixups(void)
fdt_addr, fdt_totalsize((void *)fdt_addr), ima_size);
}
-void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
+void epapr_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+unsigned long r6, unsigned long r7)
{
epapr_magic = r6;
ima_size = r7;
diff --git a/arch/powerpc/boot/of.c b/arch/powerpc/boot/of.c
index 61d9899..62e2f43 100644
--- a/arch/powerpc/boot/of.c
+++ b/arch/powerpc/boot/of.c
@@ -26,6 +26,9 @@
static unsigned long claim_base;
+void epapr_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+unsigned long r6, unsigned long r7);
+
static void *of_try_claim(unsigned long size)
{
unsigned long addr = 0;
@@ -61,7 +64,7 @@ static void of_image_hdr(const void *hdr)
}
}
-void platform_init(unsigned long a1, unsigned long a2, void *promptr)
+static void of_platform_init(unsigned long a1, unsigned long a2, void *promptr)
{
platform_ops.image_hdr = of_image_hdr;
platform_ops.malloc = of_try_claim;
@@ -81,3 +84,14 @@ void platform_init(unsigned long a1, unsigned long a2, void
*promptr)
loader_info.initrd_size = a2;
}
}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ /* Detect OF vs. ePAPR boot */
+ if (r5)
+ of_platform_init(r3, r4, (void *)r5);
+ else
+ epapr_platform_init(r3, r4, r5, r6, r7);
+}
+
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 6761c74..cd7af84 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -148,18 +148,18 @@ make_space=y
case $platform in
pseries)
-platformo=$object/of.o
+platformo=$object/of.o $object/epapr.o
link_address='0x400'
;;
maple)
-platformo=$object/of.o
+platformo=$object/of.o $object/epapr.o
link_address='0x40'
;;
pmac|chrp)
-platformo=$object/of.o
+platformo=$object/of.o $object/epapr.o
;;
coff)
-platformo=$object/crt0.o $object/of.o
+platformo=$object/crt0.o $object/of.o $object/epapr.o
lds=$object/zImage.coff.lds
link_address='0x50'
pie=
@@ -253,6 +253,7 @@ treeboot-iss4xx-mpic)
platformo=$object/treeboot-iss4xx.o
;;
epapr)
+platformo=$object/epapr.o $object/epapr-wrapper.o
link_address='0x2000'
pie=-pie
;;
[PATCH v2] pci: fix interrupt-map for bridges
The previous scheme always put 0 as a parent slot#. However it is not always the case and QEMU's PCI bridge does not support putting device at slot#0 as it claims SHPC support for hotplug. This modifies the interrups map to let the linux guest resolve XICS global interrupt number correctly. Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru --- Changes: v2: * removed redundand r-stack push-pop --- This is the example of working system: [root@erif_root pci@1]# lspci 0001:00:01.0 PCI bridge: Red Hat, Inc. Device 0001 0001:01:02.0 PCI bridge: Red Hat, Inc. Device 0001 0001:01:03.0 PCI bridge: Red Hat, Inc. Device 0001 0001:02:01.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 0001:02:02.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 0001:03:01.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 0001:03:02.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) [root@erif_root pci@1]# pwd /proc/device-tree/pci@800200f/pci@1 [root@erif_root pci@1]# hexdump -e '9/4 %08x ' -e '\n' i*map 1000 0001 3e57f7e0 0800 0003 1000 0002 3e57f7e0 0800 1000 0003 3e57f7e0 0800 0001 1000 0004 3e57f7e0 0800 0002 1800 0001 3e57f7e0 0800 1800 0002 3e57f7e0 0800 0001 1800 0003 3e57f7e0 0800 0002 1800 0004 3e57f7e0 0800 0003 [root@erif_root pci@1]# cd pci@2/ [root@erif_root pci@2]# hexdump -e '9/4 %08x ' -e '\n' i*map 0800 0001 3e5a86f0 1000 0002 0800 0002 3e5a86f0 1000 0003 0800 0003 3e5a86f0 1000 0800 0004 3e5a86f0 1000 0001 1000 0001 3e5a86f0 1000 0003 1000 0002 3e5a86f0 1000 1000 0003 3e5a86f0 1000 0001 1000 0004 3e5a86f0 1000 0002 [root@erif_root pci@2]# cd ethernet@ ethernet@1/ ethernet@2/ [root@erif_root pci@2]# cd ethernet@1/ [root@erif_root ethernet@1]# lsprop reg reg 00020800 02020810 0002 02020814 0002 01020818 0020 02020830 0002 [root@erif_root ethernet@1]# lsprop interrupts interrupts 0002 --- board-qemu/slof/pci-interrupts.fs | 31 --- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/board-qemu/slof/pci-interrupts.fs b/board-qemu/slof/pci-interrupts.fs index a12d7bb..e11b779 100644 --- a/board-qemu/slof/pci-interrupts.fs +++ b/board-qemu/slof/pci-interrupts.fs @@ -1,17 +1,26 @@ : pci-gen-irq-map-one ( prop-addr prop-len slot pin -- prop-addr prop-len ) -2dup + 4 mod( prop-addr prop-len slot pin parentpin ) +2dup + 4 mod( prop-addr prop-len slot pin parentpin ) +r r ( prop-addr prop-len slot R: swizzledpin pin ) + +\ Child slot# +B lshift encode-int+( prop-addr prop-len R: swizzledpin pin ) +\ Child 64bit BAR (not really used) +0 encode-64+ +\ Chile pin# +r encode-int+ ( prop-addr prop-len R: swizzledpin ) + +\ Parent phandle +get-parent encode-int+ + +\ Parent slot# get-node space -pci-addr2dev + 1- 4 mod 1+ \ do swizzling ( prop-addr prop-len slot pin swizzledpin ) -r r r( prop-addr prop-len R: swizzledpin pin slot ) - -r B lshift encode-int+ -0 encode-64+\ device slot ( prop-addr prop-len R: swizzledpin pin ) -r encode-int+ \ device pin( prop-addr prop-len R: swizzledpin ) - -get-parent encode-int+ \ parent phandle -0 encode-int+ 0 encode-64+ \ parent slot -r encode-int+ \ parent swizzled pin ( prop-addr prop-len R: ) +pci-addr2dev B lshift ( prop-addr prop-len parent-slot R: swizzledpin ) +encode-int+ +\ Parent 64bit BAR (not really used) +0 encode-64+ +\
[PATCH] powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file
Currently IEEE 1588 timer reference clock source is determined through hard-coded value in gianfar_ptp driver. This patch allows to select ptp clock source by means of device tree file node. For instance: fsl,cksel = 0; for using external (TSEC_TMR_CLK input) high precision timer reference clock. Other acceptable values: 1 : eTSEC system clock 2 : eTSEC1 transmit clock 3 : RTC clock input When this attribute isn't used, eTSEC system clock will serve as IEEE 1588 timer reference clock. Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru --- Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 2 ++ drivers/net/ethernet/freescale/gianfar_ptp.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt index 2c6be03..2f889f1 100644 --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt @@ -86,6 +86,7 @@ General Properties: Clock Properties: + - fsl,ckselTimer reference clock source. - fsl,tclk-period Timer reference clock period in nanoseconds. - fsl,tmr-prsc Prescaler, divides the output clock. - fsl,tmr-add Frequency compensation value. @@ -121,6 +122,7 @@ Example: reg = 0x24E00 0xB0; interrupts = 12 0x8 13 0x8; interrupt-parent = ipic ; + fsl,cksel = 1; fsl,tclk-period = 10; fsl,tmr-prsc= 100; fsl,tmr-add = 0x99A4; diff --git a/drivers/net/ethernet/freescale/gianfar_ptp.c b/drivers/net/ethernet/freescale/gianfar_ptp.c index 098f133..e006a09 100644 --- a/drivers/net/ethernet/freescale/gianfar_ptp.c +++ b/drivers/net/ethernet/freescale/gianfar_ptp.c @@ -452,7 +452,9 @@ static int gianfar_ptp_probe(struct platform_device *dev) err = -ENODEV; etsects-caps = ptp_gianfar_caps; - etsects-cksel = DEFAULT_CKSEL; + + if (get_of_u32(node, fsl,cksel, etsects-cksel)) + etsects-cksel = DEFAULT_CKSEL; if (get_of_u32(node, fsl,tclk-period, etsects-tclk_period) || get_of_u32(node, fsl,tmr-prsc, etsects-tmr_prsc) || -- 1.8.1.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
Le 20/09/2013 23:22, Scott Wood a écrit : The hardware wants to decrement; why fight it? I see your point. However it is not clear in the documentation if the decrement is done really after the update, or at xTLB interrupt. So I propose to still set the CTR ourself as described in the reference Manual and not assume that the HW decrements it. It says every update -- do you have any reason to believe that's wrong? It could be tested... Ok. I just test it, and I observe the following: As we have set the RSV4x bit, the CPU sets Mx_CTR to a value below 0x1c after each update: * After writing entry 0x1c, Mx_CTR has value 0x1b * After writing entry 0x1d, Mx_CTR has value 0x18 * After writing entry 0x1e, Mx_CTR has value 0x19 * After writing entry 0x1f, Mx_CTR has value 0x1a Indeed the first version of my patch was complete, only the description was not fully correct. So, in order to minimise code churn, I will re-submit my initial patch with a modified description. Christophe ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three 8Mbytes pages. But the setting of MD_CTR to a pinnable entry was missing before the pinning of the third 8Mb page. As the index is decremented module 28 (MD_RSV4D is set) after every DTLB update, the third 8Mbytes page was not pinned. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S linux-3.11/arch/powerpc/kernel/head_8xx.S --- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02 22:46:10.0 +0200 +++ linux-3.11/arch/powerpc/kernel/head_8xx.S 2013-09-09 11:28:54.0 +0200 @@ -862,6 +862,9 @@ addis r11, r11, 0x0080/* Add 8M */ mtspr SPRN_MD_RPN, r11 + addir10, r10, 0x0100 + mtspr SPRN_MD_CTR, r10 + addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/dts/virtex440: declare address/size-cells for phy device
On Mon, 2013-06-03 at 12:00 +0100, Ian Campbell wrote:
This fixes a warning:
DTC arch/powerpc/boot/virtex440-ml507.dtb
Warning (reg_format): reg property in
/plb@0/xps-ll-temac@81c0/ethernet@81c0/phy@7 has invalid length (4
bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value
for /plb@0/xps-ll-temac@81c0/ethernet@81c0/phy@7
Warning (avoid_default_addr_size): Relying on default #size-cells value for
/plb@0/xps-ll-temac@81c0/ethernet@81c0/phy@7
I still see this in v3.12-rc2. Ping?
Signed-off-by: Ian Campbell ian.campb...@citrix.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: Gernot Vormayr gvorm...@gmail.com
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-ker...@vger.kernel.org
---
arch/powerpc/boot/dts/virtex440-ml507.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts
b/arch/powerpc/boot/dts/virtex440-ml507.dts
index fc7073b..391a4e2 100644
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -257,6 +257,8 @@
#size-cells = 1;
compatible = xlnx,compound;
ethernet@81c0 {
+ #address-cells = 1;
+ #size-cells = 0;
compatible = xlnx,xps-ll-temac-1.01.b;
device_type = network;
interrupt-parent = xps_intc_0;
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Re: [PATCH] powerpc/4xx: Fix warning in kilauea.dtb
On Mon, 2013-06-03 at 09:36 -0400, Josh Boyer wrote:
On Mon, Jun 03, 2013 at 12:00:24PM +0100, Ian Campbell wrote:
Currently I see:
DTC arch/powerpc/boot/kilauea.dtb
Warning (reg_format): reg property in /plb/ppc4xx-msi@C1000 has
invalid length (12 bytes) (#address-cells == 1, #size-cells == 1)
It appears that unlike the other plarforms handled by 3fb7933850fa
powerpc/4xx: Adding PCIe MSI support this platform does not use
address-cells=2.
Right, it's a 405, not a 440. I should have caught that in the initial
review.
Signed-off-by: Ian Campbell ian.campb...@citrix.com
Cc: Rupjyoti Sarmah rsar...@apm.com
Cc: Tirumala R Marri tma...@apm.com
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
That address should bounce. It hasn't been active in almost 2 years.
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-ker...@vger.kernel.org
Acked-by: Josh Boyer jwbo...@gmail.com
This still doesn't appear to be fixed v3.12-rc2. Ping?
---
arch/powerpc/boot/dts/kilauea.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/kilauea.dts
b/arch/powerpc/boot/dts/kilauea.dts
index 1613d6e..5ba7f01 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -406,7 +406,7 @@
MSI: ppc4xx-msi@C1000 {
compatible = amcc,ppc4xx-msi, ppc4xx-msi;
-reg = 0x0 0xEF62 0x100;
+reg = 0xEF62 0x100;
sdr-base = 0x4B0;
msi-data = 0x;
msi-mask = 0x;
--
1.7.10.4
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[PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
From: Wang Dongsheng dongsheng.w...@freescale.com E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Add bit definitions for PWRMGTCR0. arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/include/asm/reg_booke.h | 9 + 2 files changed, 11 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x8020 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E6500 0x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR10x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ #define SPRN_SVR 0x3FF /* System Version Register */ /* @@ -216,6 +217,14 @@ #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity checking */ #defineCCR1_TCS0x0080 /* Timer Clock Select */ +/* Bit definitions for PWRMGTCR0. */ +#define PWRMGTCR0_PW20_WAIT(1 14) /* PW20 state enable bit */ +#define PWRMGTCR0_PW20_ENT_SHIFT 8 +#define PWRMGTCR0_PW20_ENT 0x3F00 +#define PWRMGTCR0_AV_IDLE_PD_EN(1 22) /* Altivec idle enable */ +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT16 +#define PWRMGTCR0_AV_IDLE_CNT 0x3F + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x8000 /* Machine Check Summary */ #define MCSR_IB0x4000 /* Instruction PLB Error */ -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 2/4] powerpc/85xx: add hardware automatically enter altivec idle state
From: Wang Dongsheng dongsheng.w...@freescale.com Each core's AltiVec unit may be placed into a power savings mode by turning off power to the unit. Core hardware will automatically power down the AltiVec unit after no AltiVec instructions have executed in N cycles. The AltiVec power-control is triggered by hardware. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Assembly code instead of C code. *v2: Remove: delete setup_idle_hw_governor function. delete Fix erratum for rev1. Move: move setup_* into __setup/restore_cpu_e6500. arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index bfb18c7..4789056 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -53,11 +53,31 @@ _GLOBAL(__e500_dcache_setup) isync blr +/* + * FIXME - we haven't yet done testing to determine a reasonable default + * value for AV_WAIT_IDLE_BIT. + */ +#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ +_GLOBAL(setup_altivec_idle) + mfspr r3, SPRN_PWRMGTCR0 + + /* Enable Altivec Idle */ + orisr3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h + li r11, AV_WAIT_IDLE_BIT + + /* Set Automatic AltiVec Idle Count */ + rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT + + mtspr SPRN_PWRMGTCR0, r3 + + blr + _GLOBAL(__setup_cpu_e6500) mflrr6 #ifdef CONFIG_PPC64 bl .setup_altivec_ivors #endif + bl setup_altivec_idle bl __setup_cpu_e5500 mtlrr6 blr @@ -119,6 +139,7 @@ _GLOBAL(__setup_cpu_e5500) _GLOBAL(__restore_cpu_e6500) mflrr5 bl .setup_altivec_ivors + bl .setup_altivec_idle bl __restore_cpu_e5500 mtlrr5 blr -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 3/4] powerpc/85xx: add hardware automatically enter pw20 state
From: Wang Dongsheng dongsheng.w...@freescale.com Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Assembly code instead of C code. *v2: Remove: delete setup_idle_hw_governor function. delete Fix erratum for rev1. Move: move setup_* into __setup/restore_cpu_e6500. arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 4789056..49e738e 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup) /* * FIXME - we haven't yet done testing to determine a reasonable default + * value for PW20_WAIT_IDLE_BIT. + */ +#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ +_GLOBAL(setup_pw20_idle) + mfspr r3, SPRN_PWRMGTCR0 + + /* Set PW20_WAIT bit, enable pw20 state*/ + ori r3, r3, PWRMGTCR0_PW20_WAIT + li r11, PW20_WAIT_IDLE_BIT + + /* Set Automatic PW20 Core Idle Count */ + rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT + + mtspr SPRN_PWRMGTCR0, r3 + + blr + +/* + * FIXME - we haven't yet done testing to determine a reasonable default * value for AV_WAIT_IDLE_BIT. */ #define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ @@ -77,6 +96,7 @@ _GLOBAL(__setup_cpu_e6500) #ifdef CONFIG_PPC64 bl .setup_altivec_ivors #endif + bl setup_pw20_idle bl setup_altivec_idle bl __setup_cpu_e5500 mtlrr6 @@ -139,6 +159,7 @@ _GLOBAL(__setup_cpu_e5500) _GLOBAL(__restore_cpu_e6500) mflrr5 bl .setup_altivec_ivors + bl .setup_pw20_idle bl .setup_altivec_idle bl __restore_cpu_e5500 mtlrr5 -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Wang Dongsheng dongsheng.w...@freescale.com
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~47(ns): TB[63]
48~95(ns): TB[62]
96~191(ns): TB[61]
192~383(ns): TB[62]
384~767(ns): TB[60]
...
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v4:
Move code from 85xx/common.c to kernel/sysfs.c.
Remove has_pw20_altivec_idle function.
Change wait entry_bit to wait time.
arch/powerpc/kernel/sysfs.c | 291
1 file changed, 291 insertions(+)
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 27a90b9..23fece6 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -85,6 +85,279 @@ __setup(smt-snooze-delay=, setup_smt_snooze_delay);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+ u64 cycle;
+
+ cycle = div_u64(ns, 1000 / tb_ticks_per_usec);
+ if (!cycle)
+ return 0;
+
+ return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+ u32 *value = val;
+
+ *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ unsigned int cpu = dev-id;
+
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+ value = PWRMGTCR0_PW20_WAIT;
+
+ return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+ u32 *value = val;
+ u32 pw20_state;
+
+ pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+ if (*value)
+ pw20_state |= PWRMGTCR0_PW20_WAIT;
+ else
+ pw20_state = ~PWRMGTCR0_PW20_WAIT;
+
+ mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 value;
+ unsigned int cpu = dev-id;
+
+ if (kstrtou32(buf, 0, value))
+ return -EINVAL;
+
+ if (value 1)
+ return -EINVAL;
+
+ smp_call_function_single(cpu, do_store_pw20_state, value, 1);
+
+ return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ u64 tb_cycle;
+ u64 time;
+
+ unsigned int cpu = dev-id;
+
+ if (!pw20_wt) {
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+ value = (value PWRMGTCR0_PW20_ENT)
+ PWRMGTCR0_PW20_ENT_SHIFT;
+
+ tb_cycle = (1 (MAX_BIT - value)) * 2;
+ time = tb_cycle * (1000 / tb_ticks_per_usec) - 1;
+ } else {
+ time = pw20_wt;
+ }
+
+ return sprintf(buf, %llu\n, time);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+ u32 *value = val;
+ u32 pw20_idle;
+
+ pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+ /* Set Automatic PW20 Core Idle Count */
+ /* clear count */
+ pw20_idle = ~PWRMGTCR0_PW20_ENT;
+
+ /* set count */
+ pw20_idle |= ((MAX_BIT - *value) PWRMGTCR0_PW20_ENT_SHIFT);
+
+ mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 entry_bit;
+ u64 value;
+
+ unsigned int cpu = dev-id;
+
+ if (kstrtou64(buf, 0, value))
+ return -EINVAL;
+
+ if (!value)
+ return -EINVAL;
+
+ entry_bit = get_idle_ticks_bit(value);
+ if (entry_bit MAX_BIT)
+ return -EINVAL;
+
+ pw20_wt = value;
+ smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+ entry_bit, 1);
+
+ return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ unsigned int cpu = dev-id;
+
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+ value = PWRMGTCR0_AV_IDLE_PD_EN;
+
+ return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+ u32 *value = val;
+ u32 altivec_idle;
+
+ altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+ if (*value)
Re: [PATCH v2] pci: fix interrupt-map for bridges
Alexey Kardashevskiy a...@ozlabs.ru writes: The previous scheme always put 0 as a parent slot#. However it is not always the case and QEMU's PCI bridge does not support putting device at slot#0 as it claims SHPC support for hotplug. This modifies the interrups map to let the linux guest resolve XICS global interrupt number correctly. Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru Thanks, Will pull this for next build. Regards Nikunj --- Changes: v2: * removed redundand r-stack push-pop ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, September 24, 2013 7:03 AM To: Hu Mingkai-B21284 Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property On Tue, 2013-09-17 at 06:06 -0500, Hu Mingkai-B21284 wrote: Scott, Sorry for the delayed response. Please fine my comments. Thanks, Mingkai -Original Message- From: Wood Scott-B07421 Sent: Thursday, September 12, 2013 9:16 AM To: Hu Mingkai-B21284 Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property On Tue, 2013-09-10 at 21:07 -0500, Hu Mingkai-B21284 wrote: -Original Message- From: Wood Scott-B07421 Sent: Wednesday, September 11, 2013 7:33 AM To: Hu Mingkai-B21284 Cc: linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property What happens to exsting users whose flash is laid out the existing way, when they upgrade to these device trees? The SPI flash layout should be mapping the new device tree. If the existing device tree is used to deploy the SPI flash, the following issues must be run into as the commit message described: 1. Kernel images would be overlapped with U-Boot image. 2. Kernel images would be overlapped with FMAN ucode. 3. Saving environment variables will crash the kernel image. Has the SPI U-Boot image always been larger than 512K for all these platforms? Why, given that we're under 512K for other boot modes? For DPAA platform, the ld script used to link the u-boot image is ./arch/powerpc/cpu/mpc85xx/u-boot.lds which will generate the 512K u-boot Image. This image will be split into 64bytes and appended PBL command for Each 64bytes pieces, so the size of final image must be greater than 512K. What is the entry point in SRAM when you load from PBL? If it is (or can be made to be) the beginning of the image rather than the end, then turn off the resetvec and the fixed image size that results. 1. Thus a special ld script need to be provided. 2. Now the spi image size is about 540KB, that's to say the PBL needs about ~30K for PBL commands. It's hard to save such a big space even we turn off the resetvec. We really should not be putting partition layout info in the device tree to begin with... OK, I will remove the layout diagram in the commit message. That's not what I meant. I meant that the dts should be describing hardware, and this is the sort of trouble we run into when we deviate from that. A better way would be to use the mtdparts command line option. Even better would be some sort of on-flash partition table. You're right, but maybe some customer has already used the device tree partition table... My main point was to encourage us to shift away from this rather than to rip it out right this instant. Yes, that's the correct way we should go. Would you please pick up this patch first to resolve current issue we faced? And we can consider to use the mtdparts or on-flash partition table for long term. Thanks, Mingkai ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v10 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
On 09/24/2013 01:04 AM, Stephen Warren wrote:
On 09/18/2013 04:15 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+Required properties:
+
+- compatible: must include fsl,elo3-dma
+- reg : DMA General Status Registers, i.e. DGSR0 which contains
+ status for channel 1~4, and DGSR1 for channel 5~8
Is that a single entry, which is large enough to cover both registers,
or a pair of entries, one per register? Reading the text, I might assume
the former, but looking at the examples, it's the latter.
My impression is that I cannot tell it is one larger entry or two
entries by reading the description text, but the example gives the answer.
Is it so important to specify it is only one entry or entries list?
I prefer language as concise as possible, especially for the common
properties such as reg and interrupt (eg the reg is implicitly offset
and length of registers, can be continuous or not), it is difficult or
unnecessary or impossible to describe much details, the example can also
work as a complementary description, otherwise no need to put an example
in the binding document.
...
+Example:
+dma@100300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x100300 0x4,
+ 0x100600 0x4;
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[PATCH] dts/c293pcie: Add range field for IFC NAND
C290PCIe has NAND flash present on IFC Chip Select(CS) 1.
So Add ranges field for NAND flash on CS1.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
branch next
arch/powerpc/boot/dts/c293pcie.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/boot/dts/c293pcie.dts
b/arch/powerpc/boot/dts/c293pcie.dts
index 1238bda..6681cc2 100644
--- a/arch/powerpc/boot/dts/c293pcie.dts
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -45,6 +45,7 @@
ifc: ifc@fffe1e000 {
reg = 0xf 0xffe1e000 0 0x2000;
ranges = 0x0 0x0 0xf 0xec00 0x0400
+ 0x1 0x0 0xf 0xff80 0x0001
0x2 0x0 0xf 0xffdf 0x0001;
};
--
1.7.9.5
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[PATCH V4 2/3] powerpc/85xx: Use common init functions for QE
Use common init functions instead of the duplicated codes
in some platforms with QUICC Engine.
Signed-off-by: Xie Xiaobo x@freescale.com
---
V4: new patch
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 55 ++-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 36 ++--
2 files changed, 4 insertions(+), 87 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..da28d74 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
{
struct device_node *np;
- np = of_find_compatible_node(NULL, NULL, fsl,qe);
- if (!np) {
- np = of_find_node_by_name(NULL, qe);
- if (!np)
- return;
- }
-
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- qe_reset();
- of_node_put(np);
-
- np = of_find_node_by_name(NULL, par_io);
- if (np) {
- struct device_node *ucc;
-
- par_io_init(np);
- of_node_put(np);
-
- for_each_node_by_name(ucc, ucc)
- par_io_of_config(ucc);
- }
-
+ mpc85xx_qe_init();
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
@@ -293,34 +268,8 @@ static void __init mpc85xx_mds_qe_init(void)
}
}
-
-static void __init mpc85xx_mds_qeic_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, fsl,qe);
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
- if (!np) {
- np = of_find_node_by_type(NULL, qeic);
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
-}
#else
static void __init mpc85xx_mds_qe_init(void) { }
-static void __init mpc85xx_mds_qeic_init(void) { }
#endif /* CONFIG_QUICC_ENGINE */
static void __init mpc85xx_mds_setup_arch(void)
@@ -395,7 +344,7 @@ static void __init mpc85xx_mds_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
- mpc85xx_mds_qeic_init();
+ mpc85xx_qe_pic_init();
}
static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0..67d78e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -49,10 +49,6 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -69,16 +65,8 @@ void __init mpc85xx_rdb_pic_init(void)
mpic_init(mpic);
#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err(%s: Could not find qe-ic node\n, __func__);
+ mpc85xx_qe_pic_init();
#endif
-
}
/*
@@ -98,26 +86,8 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, fsl,qe);
- if (!np) {
- pr_err(%s: Could not find Quicc Engine node\n, __func__);
- goto qe_fail;
- }
+ mpc85xx_qe_init();
- qe_reset();
- of_node_put(np);
-
- np = of_find_node_by_name(NULL, par_io);
- if (np) {
- struct device_node *ucc;
-
- par_io_init(np);
- of_node_put(np);
-
- for_each_node_by_name(ucc, ucc)
- par_io_of_config(ucc);
-
- }
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
@@ -148,8 +118,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
}
#endif
-
-qe_fail:
#endif /* CONFIG_QUICC_ENGINE */
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
--
1.8.0
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[PATCH V4 1/3] powerpc/85xx: Add QE common init functions
Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.
Signed-off-by: Xie Xiaobo x@freescale.com
---
V4 - V3: Nochange
arch/powerpc/platforms/85xx/common.c | 51 +++
arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++
2 files changed, 59 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/common.c
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..08fff48 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,9 @@
*/
#include linux/of_platform.h
+#include asm/machdep.h
+#include asm/qe.h
+#include asm/qe_ic.h
#include sysdev/cpm2_pic.h
#include mpc85xx.h
@@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
}
#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_pic_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds))
+ qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+ else
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+}
+
+void __init mpc85xx_qe_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ np = of_find_node_by_name(NULL, qe);
+ if (!np) {
+ pr_err(%s: Could not find Quicc Engine node\n,
+ __func__);
+ return;
+ }
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h
b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..1d39095 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,12 @@ extern void mpc85xx_cpm2_pic_init(void);
static inline void __init mpc85xx_cpm2_pic_init(void) {}
#endif /* CONFIG_CPM2 */
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_pic_init(void);
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_pic_init(void) {}
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
#endif
--
1.8.0
___
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https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support
TWR-P1025 Overview
-
512Mbyte DDR3 (on board DDR)
64MB Nor Flash
eTSEC1: Connected to RGMII PHY AR8035
eTSEC3: Connected to RGMII PHY AR8035
Two USB2.0 Type A
One microSD Card slot
One mini-PCIe slot
One mini-USB TypeB dual UART
Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
Patch V4: Fix the mdio phy interrupt issue in dts
Patch V3: fix pcie range issue in dts
Patch V2: QE related init codes were factored out to a common file
arch/powerpc/boot/dts/p1025twr.dtsi | 244
arch/powerpc/boot/dts/p1025twr_32b.dts | 135 ++
arch/powerpc/platforms/85xx/Kconfig | 6 +
arch/powerpc/platforms/85xx/Makefile| 1 +
arch/powerpc/platforms/85xx/twr_p102x.c | 142 +++
5 files changed, 528 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c
diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi
b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000..4b1d5f7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,244 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+ aliases {
+ ethernet3 = enet3;
+ ethernet4 = enet4;
+ };
+};
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58.75MB for JFFS2 based Root file System */
+ reg = 0x0040 0x03ac;
+ label = NOR Root File System;
+ };
+
+ partition@ec {
+ /* This location must not be altered */
+ /* 256KB for QE ucode firmware*/
+ reg = 0x03ec 0x0004;
+ label = NOR QE microcode firmware;
+ read-only;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+
RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
-Original Message- From: Linuxppc-dev [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Dongsheng Wang Sent: Tuesday, September 24, 2013 2:58 PM To: Wood Scott-B07421 Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define From: Wang Dongsheng dongsheng.w...@freescale.com E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Add bit definitions for PWRMGTCR0. arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/include/asm/reg_booke.h | 9 + 2 files changed, 11 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x8020 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E65000x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff -- git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF. Also I can see SPRN_ICCR also with same SPRN, how that is possible? -Bharat #define SPRN_SVR 0x3FF /* System Version Register */ /* @@ -216,6 +217,14 @@ #define CCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_TCS0x0080 /* Timer Clock Select */ +/* Bit definitions for PWRMGTCR0. */ +#define PWRMGTCR0_PW20_WAIT (1 14) /* PW20 state enable bit */ +#define PWRMGTCR0_PW20_ENT_SHIFT 8 +#define PWRMGTCR0_PW20_ENT 0x3F00 +#define PWRMGTCR0_AV_IDLE_PD_EN (1 22) /* Altivec idle enable */ +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16 +#define PWRMGTCR0_AV_IDLE_CNT0x3F + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x8000 /* Machine Check Summary */ #define MCSR_IB 0x4000 /* Instruction PLB Error */ -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: BPF JIT compiler for 64bit LE
This enables the Berkeley Packet Filter JIT compiler
for the PowerPC running in 64bit Little Endian.
Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/ppc-opcode.h |1 +
arch/powerpc/net/bpf_jit.h| 10 ++
arch/powerpc/net/bpf_jit_64.S |9 -
arch/powerpc/net/bpf_jit_comp.c | 17 ++---
4 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 247fa1d..23c2b63 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -154,6 +154,7 @@
/* Misc instructions for BPF compiler */
#define PPC_INST_LD0xe800
#define PPC_INST_LHZ 0xa000
+#define PPC_INST_LHBRX 0x7c00062c
#define PPC_INST_LWZ 0x8000
#define PPC_INST_STD 0xf800
#define PPC_INST_STDU 0xf801
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 8a5dfaf..0baf2b8 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -92,6 +92,8 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
___PPC_RA(base) | IMM_L(i))
#define PPC_LHZ(r, base, i)EMIT(PPC_INST_LHZ | ___PPC_RT(r) |\
___PPC_RA(base) | IMM_L(i))
+#define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \
+___PPC_RA(base) | ___PPC_RB(b))
/* Convenience helpers for the above with 'far' offsets: */
#define PPC_LD_OFFS(r, base, i) do { if ((i) 32768) PPC_LD(r, base, i); \
else { PPC_ADDIS(r, base, IMM_HA(i));\
@@ -186,6 +188,14 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
PPC_ORI(d, d, (uintptr_t)(i) 0x); \
} } while (0);
+#define PPC_LHBRX_OFFS(r, base, i) \
+ do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
+#ifdef __LITTLE_ENDIAN__
+#define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i)
+#else
+#define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i)
+#endif
+
static inline bool is_nearbranch(int offset)
{
return (offset 32768) (offset = -32768);
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index 7d3a3b5..e76eba7 100644
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -43,8 +43,11 @@ sk_load_word_positive_offset:
cmpdr_scratch1, r_addr
blt bpf_slow_path_word
/* Nope, just hitting the header. cr0 here is eq or gt! */
+#ifdef __LITTLE_ENDIAN__
+ lwbrx r_A, r_D, r_addr
+#else
lwzxr_A, r_D, r_addr
- /* When big endian we don't need to byteswap. */
+#endif
blr /* Return success, cr0 != LT */
.globl sk_load_half
@@ -56,7 +59,11 @@ sk_load_half_positive_offset:
subir_scratch1, r_HL, 2
cmpdr_scratch1, r_addr
blt bpf_slow_path_half
+#ifdef __LITTLE_ENDIAN__
+ lhbrx r_A, r_D, r_addr
+#else
lhzxr_A, r_D, r_addr
+#endif
blr
.globl sk_load_byte
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index c427ae3..9e212f9 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -17,14 +17,8 @@
#include bpf_jit.h
-#ifndef __BIG_ENDIAN
-/* There are endianness assumptions herein. */
-#error Little-endian PPC not supported in BPF compiler
-#endif
-
int bpf_jit_enable __read_mostly;
-
static inline void bpf_flush_icache(void *start, void *end)
{
smp_wmb();
@@ -346,18 +340,11 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32
*image,
break;
/*** Ancillary info loads ***/
-
- /* None of the BPF_S_ANC* codes appear to be passed by
-* sk_chk_filter(). The interpreter and the x86 BPF
-* compiler implement them so we do too -- they may be
-* planted in future.
-*/
case BPF_S_ANC_PROTOCOL: /* A = ntohs(skb-protocol); */
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
protocol) != 2);
- PPC_LHZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
- protocol));
- /* ntohs is a NOP with BE loads. */
+ PPC_NTOHS_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+ protocol));
break;
case BPF_S_ANC_IFINDEX:
PPC_LD_OFFS(r_scratch1, r_skb, offsetof(struct sk_buff,
--
1.7.10.4
Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: -Original Message- From: Linuxppc-dev [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Dongsheng Wang Sent: Tuesday, September 24, 2013 2:58 PM To: Wood Scott-B07421 Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define From: Wang Dongsheng dongsheng.w...@freescale.com E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Add bit definitions for PWRMGTCR0. arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/include/asm/reg_booke.h | 9 + 2 files changed, 11 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x8020 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E6500 0x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff -- git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF. Also I can see SPRN_ICCR also with same SPRN, how that is possible? Its possibly because the register maybe in implementation specific region. I'm guessing ICCR is a 40x specific register. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file
On Tue, Sep 24, 2013 at 11:39:57AM +0400, Aida Mynzhasova wrote: Currently IEEE 1588 timer reference clock source is determined through hard-coded value in gianfar_ptp driver. This patch allows to select ptp clock source by means of device tree file node. For instance: fsl,cksel = 0; for using external (TSEC_TMR_CLK input) high precision timer reference clock. Other acceptable values: 1 : eTSEC system clock 2 : eTSEC1 transmit clock 3 : RTC clock input I think it would be useful to have this table in the binding document as well. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v10 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
On 09/24/2013 04:30 AM, Hongbo Zhang wrote: On 09/24/2013 01:04 AM, Stephen Warren wrote: On 09/18/2013 04:15 AM, hongbo.zh...@freescale.com wrote: From: Hongbo Zhang hongbo.zh...@freescale.com Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds the device tree nodes for them. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +Required properties: + +- compatible: must include fsl,elo3-dma +- reg : DMA General Status Registers, i.e. DGSR0 which contains + status for channel 1~4, and DGSR1 for channel 5~8 Is that a single entry, which is large enough to cover both registers, or a pair of entries, one per register? Reading the text, I might assume the former, but looking at the examples, it's the latter. My impression is that I cannot tell it is one larger entry or two entries by reading the description text, but the example gives the answer. Is it so important to specify it is only one entry or entries list? I prefer language as concise as possible, especially for the common properties such as reg and interrupt (eg the reg is implicitly offset and length of registers, can be continuous or not), it is difficult or unnecessary or impossible to describe much details, the example can also work as a complementary description, otherwise no need to put an example in the binding document. The description of the properties should fully describe them. The example is just an example, not a specification of the properties. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property
On Tue, 2013-09-24 at 05:27 -0500, Hu Mingkai-B21284 wrote: -Original Message- From: Wood Scott-B07421 Sent: Tuesday, September 24, 2013 7:03 AM To: Hu Mingkai-B21284 Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property On Tue, 2013-09-17 at 06:06 -0500, Hu Mingkai-B21284 wrote: Scott, Sorry for the delayed response. Please fine my comments. Thanks, Mingkai -Original Message- From: Wood Scott-B07421 Sent: Thursday, September 12, 2013 9:16 AM To: Hu Mingkai-B21284 Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property On Tue, 2013-09-10 at 21:07 -0500, Hu Mingkai-B21284 wrote: -Original Message- From: Wood Scott-B07421 Sent: Wednesday, September 11, 2013 7:33 AM To: Hu Mingkai-B21284 Cc: linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property What happens to exsting users whose flash is laid out the existing way, when they upgrade to these device trees? The SPI flash layout should be mapping the new device tree. If the existing device tree is used to deploy the SPI flash, the following issues must be run into as the commit message described: 1. Kernel images would be overlapped with U-Boot image. 2. Kernel images would be overlapped with FMAN ucode. 3. Saving environment variables will crash the kernel image. Has the SPI U-Boot image always been larger than 512K for all these platforms? Why, given that we're under 512K for other boot modes? For DPAA platform, the ld script used to link the u-boot image is ./arch/powerpc/cpu/mpc85xx/u-boot.lds which will generate the 512K u-boot Image. This image will be split into 64bytes and appended PBL command for Each 64bytes pieces, so the size of final image must be greater than 512K. What is the entry point in SRAM when you load from PBL? If it is (or can be made to be) the beginning of the image rather than the end, then turn off the resetvec and the fixed image size that results. 1. Thus a special ld script need to be provided. This is already supported. See CONFIG_SYS_MPC85XX_NO_RESETVEC. 2. Now the spi image size is about 540KB, that's to say the PBL needs about ~30K for PBL commands. It's hard to save such a big space even we turn off the resetvec. Turning off the resetvec doesn't just eliminate the resetvec code; it eliminates the padding to 512K (or if it doesn't, that's a bug to be fixed). We really should not be putting partition layout info in the device tree to begin with... OK, I will remove the layout diagram in the commit message. That's not what I meant. I meant that the dts should be describing hardware, and this is the sort of trouble we run into when we deviate from that. A better way would be to use the mtdparts command line option. Even better would be some sort of on-flash partition table. You're right, but maybe some customer has already used the device tree partition table... My main point was to encourage us to shift away from this rather than to rip it out right this instant. Yes, that's the correct way we should go. Would you please pick up this patch first to resolve current issue we faced? And we can consider to use the mtdparts or on-flash partition table for long term. Fixing U-Boot would make the problem go away without any issues with partition compatibility. Are you sure nobody's using these SPI partitions without booting from SPI? Even if nobody's using this, it seems a wasteful solution. These are pretty small flashes. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: mm: insure topdown mmap chooses addresses above security minimum
On Tue, Sep 24, 2013 at 02:23:31PM -0700, Timothy Pepper wrote: diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 0c63562..0e7355d 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -9,6 +9,7 @@ #include linux/io.h #include linux/personality.h #include linux/random.h +#include linux/security.h #include asm/cachetype.h #define COLOUR_ALIGN(addr,pgoff) \ @@ -146,7 +147,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, info.flags = VM_UNMAPPED_AREA_TOPDOWN; info.length = len; - info.low_limit = PAGE_SIZE; + info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr)); info.high_limit = mm-mmap_base; info.align_mask = do_align ? (PAGE_MASK (SHMLBA - 1)) : 0; info.align_offset = pgoff PAGE_SHIFT; This looks sane for ARM. Acked-by: Russell King rmk+ker...@arm.linux.org.uk Thanks. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 8/8][v4] powerpc/perf: Export Power7 memory hierarchy info to user space.
Anshuman Khandual [khand...@linux.vnet.ibm.com] wrote:
| On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
| +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
| + struct pt_regs *regs)
| +{
| + u64 idx;
| + u64 mmcra = regs-dsisr;
| + u64 addr;
| + int ret;
| + unsigned int instr;
| +
| + if (mmcra POWER7_MMCRA_DCACHE_MISS) {
| + idx = mmcra POWER7_MMCRA_DCACHE_SRC_MASK;
| + idx = POWER7_MMCRA_DCACHE_SRC_SHIFT;
| +
| + dsrc-val |= dcache_src_map[idx];
| + return;
| + }
| +
| + instr = 0;
| + addr = perf_instruction_pointer(regs);
| +
| + if (is_kernel_addr(addr))
| + instr = *(unsigned int *)addr;
| + else {
| + pagefault_disable();
| + ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
| + pagefault_enable();
| + if (ret)
| + instr = 0;
| + }
| + if (instr instr_is_load_store(instr))
|
|
| Wondering if there is any possibility of getting positive values for
| (mmcra POWER7_MMCRA_DCACHE_SRC_MASK) POWER7_MMCRA_DCACHE_SRC_SHIFT
| when the marked instruction did not have MMCRA[POWER7_MMCRA_DCACHE_MISS]
| bit set. In that case we should actually compute dsrc-val as in the previous
| case. I did couple of experiments on a P7 box, but was not able to find a
| instance for a marked instruction whose MMCRA[POWER7_MMCRA_DCACHE_MISS] bit
| not set and have a positive value POWER7_MMCRA_DCACHE_SRC field.
Confirmed again with the hardware team that if there was no DCACHE_MISS,
the DCACHE_SRC field will be clear.
Thanks,
Sukadev
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Re: [PATCH v3 3/3] powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
On Tue, 2013-09-24 at 11:03 +0800, Kevin Hao wrote: Currently all these boards use the same machine struct and also select the same kernel options, so it seems a bit of redundant to keep one separate kernel option for each board. Also update the defconfigs according to this change. Signed-off-by: Kevin Hao haoke...@gmail.com --- A new patch in v3. arch/powerpc/configs/corenet32_smp_defconfig | 6 +- arch/powerpc/configs/corenet64_smp_defconfig | 5 +- arch/powerpc/configs/ppc64e_defconfig| 2 +- arch/powerpc/platforms/85xx/Kconfig | 97 +++- 4 files changed, 12 insertions(+), 98 deletions(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 3dfab4c..1d9cb29 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -23,11 +23,7 @@ CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y -CONFIG_P2041_RDB=y -CONFIG_P3041_DS=y -CONFIG_P4080_DS=y -CONFIG_P5020_DS=y -CONFIG_P5040_DS=y +CONFIG_CORENET_GENERIC=y CONFIG_HIGHMEM=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index fa94fb3..63508dd 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -21,10 +21,7 @@ CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y -CONFIG_B4_QDS=y -CONFIG_P5020_DS=y -CONFIG_P5040_DS=y -CONFIG_T4240_QDS=y +CONFIG_CORENET_GENERIC=y # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig index 0085dc4..0a6be6d 100644 --- a/arch/powerpc/configs/ppc64e_defconfig +++ b/arch/powerpc/configs/ppc64e_defconfig @@ -23,7 +23,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_P5020_DS=y +CONFIG_CORENET_GENERIC=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 3bee943..04456fb 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -218,36 +218,8 @@ config GE_IMP3A This board is a 3U CompactPCI Single Board Computer with a Freescale P2020 processor. -config P2041_RDB - bool Freescale P2041 RDB - select DEFAULT_UIMAGE - select PPC_E500MC - select PHYS_64BIT - select SWIOTLB - select ARCH_REQUIRE_GPIOLIB - select GPIO_MPC8XXX - select HAS_RAPIDIO - select PPC_EPAPR_HV_PIC - select CORENET_GENERIC - help - This option enables support for the P2041 RDB board - -config P3041_DS - bool Freescale P3041 DS - select DEFAULT_UIMAGE - select PPC_E500MC - select PHYS_64BIT - select SWIOTLB - select ARCH_REQUIRE_GPIOLIB - select GPIO_MPC8XXX - select HAS_RAPIDIO - select PPC_EPAPR_HV_PIC - select CORENET_GENERIC - help - This option enables support for the P3041 DS board - -config P4080_DS - bool Freescale P4080 DS +config CORENET_GENERIC + bool Freescale CoreNet Generic select DEFAULT_UIMAGE select PPC_E500MC select PHYS_64BIT @@ -256,50 +228,20 @@ config P4080_DS select GPIO_MPC8XXX select HAS_RAPIDIO select PPC_EPAPR_HV_PIC - select CORENET_GENERIC help - This option enables support for the P4080 DS board + This option enables support for the P2041 RDB, P3041 DS, P4080 DS, P5020 DS + and P5040 DS boards config SGY_CTS1000 tristate Servergy CTS-1000 support select GPIOLIB select OF_GPIO - depends on P4080_DS + depends on CORENET_GENERIC help Enable this to support functionality in Servergy's CTS-1000 systems. endif # PPC32 -config P5020_DS - bool Freescale P5020 DS - select DEFAULT_UIMAGE - select E500 - select PPC_E500MC - select PHYS_64BIT - select SWIOTLB - select ARCH_REQUIRE_GPIOLIB - select GPIO_MPC8XXX - select HAS_RAPIDIO - select PPC_EPAPR_HV_PIC - select CORENET_GENERIC - help - This option enables support for the P5020 DS board - -config P5040_DS - bool Freescale P5040 DS - select DEFAULT_UIMAGE - select E500 - select PPC_E500MC - select PHYS_64BIT - select SWIOTLB - select ARCH_REQUIRE_GPIOLIB - select GPIO_MPC8XXX - select HAS_RAPIDIO - select PPC_EPAPR_HV_PIC - select CORENET_GENERIC - help - This option enables support for the
Re: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions
On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote:
Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.
Signed-off-by: Xie Xiaobo x@freescale.com
---
V4 - V3: Nochange
arch/powerpc/platforms/85xx/common.c | 51
+++
arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++
2 files changed, 59 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/common.c
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..08fff48 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,9 @@
*/
#include linux/of_platform.h
+#include asm/machdep.h
+#include asm/qe.h
+#include asm/qe_ic.h
#include sysdev/cpm2_pic.h
#include mpc85xx.h
@@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
}
#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_pic_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds))
+ qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+ else
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+}
Have the caller pass in a flag indicating the type of cascade. Or,
perhaps this function isn't worth factoring out. Where is the check for
p1021_mds? Where did 8568/9 MDS come from? I don't see those checks
removed in patch 2.
BTW, when you move code from one place to another, do it in one patch.
Don't add it in one patch and then remove it in another. A more useful
split would have been one patch handling qe_init and another handling
qe_pic_init.
-Scott
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Re: [PATCH 1/2][v3] powerpc/fsl-booke: Add initial T104x_QDS board support
On Thu, 2013-09-19 at 22:08 -0500, Timur Tabi wrote: Kushwaha Prabhakar-B32579 wrote: My primary object is to put base patch in Linux. once it done other things can be enabled one by one. Any features which are not enabled must be specified in the patch description. The patch says that the board supports DIU, but the code doesn't, so that's misleading. Also, I am not familiar with DIU driver:(. I can help you with the DIU driver. shall I remove the DIU node, and while adding support of DIU, all modification will be sent. I think it should be okay to leave the DIU node. I think the kernel will crash if you try to enable a DIU console (video= on the kernel command line), but I think it's okay to ignore that for the moment. Sounds like a bug in the DIU driver. It should fail gracefully in the absence of platform support. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2][RFC][v3] pci: fsl: rework PCI driver compatible with Layerscape
On Tue, 2013-09-17 at 17:23 +0800, Lian Minghuan-b31939 wrote:
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a189ff0..4cb12e8 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -62,7 +62,11 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull MAX_PHYS_ADDR_BITS;
+
+u64 fsl_arch_pci64_dma_offset(void)
+{
+ return 1ull MAX_PHYS_ADDR_BITS;
+}
static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
{
@@ -77,17 +81,43 @@ static int fsl_pci_dma_set_mask(struct device *dev,
u64 dma_mask)
if ((dev-bus == pci_bus_type)
dma_mask = DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
set_dma_ops(dev, dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
+ set_dma_offset(dev, fsl_arch_pci64_dma_offset());
}
Is the intent for fsl_arch_pci64_dma_offset() to eventually do something
that isn't calculable at compile time?
[Minghuan] fsl_arch_pci64_dma_offset() is also called by pci-fsl.c to
setup inbound ATMU.
I think different platform or architecture(LS1) may use different dma
offset(maybe I am wrong
they can use the same offset 1ull MAX_PHYS_ADDR_BITS). I selected
u64 fsl_arch_pci64_dma_offset(void) not extern u64 pci64_dma_offset to
share the global
value between /driver/pci/host/pci-fsl.c and
arch/powerpc/sysdev/fsl_pci.c or / arch/arm//fsl_pci.c
'extern' variable will cause the warning when checking patch.
It will only warn if you're doing it wrong. :-P
Put the extern in a header and the actual declaration in the
arch-specific C file.
*dev-dma_mask = dma_mask;
return 0;
}
+struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
+{
+ struct pci_controller *hose = sys;
+ struct fsl_pci *pci = hose-private_data;
If this were just to convert to fsl_pci, that seems like header
material.
[Minghuan] In arm architecture it will be implemented like this:
struct fsl_pci *fsl_arch_sys_to_pci(void *sys) {
struct pci_sys_data *sys_data = sys;
return sys_data-private_data;
}
Right, so make it an inline function in each architecture's header file.
driver/pci/host/pci-fsl.c should not include any arch specific header file.
include/linux/fsl/pci.h could include asm/fsl/pci.h. If this is the
only arch-specific thing that you need in a header, though, then I guess
leave it in the C file.
+ /* Update the first bus number */
+ if (pci-first_busno != hose-first_busno)
+ pci-first_busno = hose-first_busno;
This isn't part of the interface description in the header...
[Minghuan] Yes. host-first_busno will be reassigned if defined
PCI_REASSIGN_ALL_BUS.
and I can not find a chance to update pci-first_busno. this will cause
we can not
read/write pci configuration space when the hose-first_busno is changed
but pci-first_busno
is not updated synchronously.
the following code to check first_busno when access the configuration space.
if (pci-indirect_type INDIRECT_TYPE_NO_PCIE_LINK) {
if (bus != pci-first_busno)
return PCIBIOS_DEVICE_NOT_FOUND;
...
}
bus_no = (bus == pci-first_busno) ? pci-self_busno : bus;
So I added the sentences to this function to fix the issue.
How was this handled in the old PPC code? I don't see anything similar.
Is it only an issue on ARM?
At the very least this side-effect should be mentioned in the function
interface documentation, but I'd rather see a less hacky solution.
@@ -260,14 +259,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
/* we only need the error registers */
r.start += 0xe00;
- if (!devm_request_mem_region(op-dev, r.start, resource_size(r),
- pdata-name)) {
- printk(KERN_ERR %s: Error while requesting mem region\n,
- __func__);
- res = -EBUSY;
- goto err;
- }
Why? If the relationship between the edac driver and the main pci
driver is changing, explain that.
[Minghuan] Ok.
The main pci driver used devm_ioremap_resource() to map regester space.
And it didn't before? It'd be nice if this rework patch could be
split into digestible chunks, each explained on its own.
+config PCI_FSL
+ bool Freescale PCI/PCIe controller
+ depends on FSL_SOC_BOOKE || PPC_86xx
Needs help text.
Make it clear that this is for 85xx/86xx/QorIQ/Layerscape, not all
Freescale chips with PCI/PCIe.
[Minghuan] Ok. I will add help text.
no_bridge:
- iounmap(hose-private_data);
- /* unmap cfg_data cfg_addr separately if not on same page */
- if (((unsigned long)hose-cfg_data PAGE_MASK) !=
- ((unsigned long)hose-cfg_addr PAGE_MASK))
- iounmap(hose-cfg_data);
- iounmap(hose-cfg_addr);
-
Re: [PATCH 1/7] powerpc: Add interface to get msi region information
On Thu, Sep 19, 2013 at 12:59:17PM +0530, Bharat Bhushan wrote:
This patch adds interface to get following information
- Number of MSI regions (which is number of MSI banks for powerpc).
- Get the region address range: Physical page which have the
address/addresses used for generating MSI interrupt
and size of the page.
These are required to create IOMMU (Freescale PAMU) mapping for
devices which are directly assigned using VFIO.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/include/asm/machdep.h |8 +++
arch/powerpc/include/asm/pci.h |2 +
arch/powerpc/kernel/msi.c | 18
arch/powerpc/sysdev/fsl_msi.c | 39 +--
arch/powerpc/sysdev/fsl_msi.h | 11 -
drivers/pci/msi.c | 26
include/linux/msi.h|8 +++
include/linux/pci.h| 13
8 files changed, 120 insertions(+), 5 deletions(-)
...
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index aca7578..6d85c15 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -30,6 +30,20 @@ static int pci_msi_enable = 1;
/* Arch hooks */
+#ifndef arch_msi_get_region_count
+int arch_msi_get_region_count(void)
+{
+ return 0;
+}
+#endif
+
+#ifndef arch_msi_get_region
+int arch_msi_get_region(int region_num, struct msi_region *region)
+{
+ return 0;
+}
+#endif
This #define strategy is gone; see 4287d824 (PCI: use weak functions for
MSI arch-specific functions). Please use the weak function strategy
for your new MSI region functions.
+
#ifndef arch_msi_check_device
int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
@@ -903,6 +917,18 @@ void pci_disable_msi(struct pci_dev *dev)
}
EXPORT_SYMBOL(pci_disable_msi);
+int msi_get_region_count(void)
+{
+ return arch_msi_get_region_count();
+}
+EXPORT_SYMBOL(msi_get_region_count);
+
+int msi_get_region(int region_num, struct msi_region *region)
+{
+ return arch_msi_get_region(region_num, region);
+}
+EXPORT_SYMBOL(msi_get_region);
Please split these interface additions, i.e., the drivers/pci/msi.c,
include/linux/msi.h, and include/linux/pci.h changes, into a separate
patch.
I don't know enough about VFIO to understand why these new interfaces
are needed. Is this the first VFIO IOMMU driver? I see
vfio_iommu_spapr_tce.c and vfio_iommu_type1.c but I don't know if
they're comparable to the Freescale PAMU. Do other VFIO IOMMU
implementations support MSI? If so, do they handle the problem of
mapping the MSI regions in a different way?
/**
* pci_msix_table_size - return the number of device's MSI-X table entries
* @dev: pointer to the pci_dev data structure of MSI-X device function
diff --git a/include/linux/msi.h b/include/linux/msi.h
index ee66f3a..ae32601 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -50,6 +50,12 @@ struct msi_desc {
struct kobject kobj;
};
+struct msi_region {
+ int region_num;
+ dma_addr_t addr;
+ size_t size;
+};
This needs some sort of explanatory comment.
/*
* The arch hook for setup up msi irqs
*/
@@ -58,5 +64,7 @@ void arch_teardown_msi_irq(unsigned int irq);
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
void arch_teardown_msi_irqs(struct pci_dev *dev);
int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
+int arch_msi_get_region_count(void);
+int arch_msi_get_region(int region_num, struct msi_region *region);
#endif /* LINUX_MSI_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 186540d..2b26a59 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1126,6 +1126,7 @@ struct msix_entry {
u16 entry; /* driver uses to specify entry, OS writes */
};
+struct msi_region;
#ifndef CONFIG_PCI_MSI
static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int
nvec)
@@ -1168,6 +1169,16 @@ static inline int pci_msi_enabled(void)
{
return 0;
}
+
+static inline int msi_get_region_count(void)
+{
+ return 0;
+}
+
+static inline int msi_get_region(int region_num, struct msi_region *region)
+{
+ return 0;
+}
#else
int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
@@ -1180,6 +1191,8 @@ void pci_disable_msix(struct pci_dev *dev);
void msi_remove_pci_irq_vectors(struct pci_dev *dev);
void pci_restore_msi_state(struct pci_dev *dev);
int pci_msi_enabled(void);
+int msi_get_region_count(void);
+int msi_get_region(int region_num, struct msi_region *region);
#endif
#ifdef CONFIG_PCIEPORTBUS
--
1.7.0.4
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Re: [PATCH 1/2][v4] powerpc/fsl-booke: Add initial T104x_QDS board support
On Mon, 2013-09-23 at 09:21 +0530, Prabhakar Kushwaha wrote: +/* coreint doesn't play nice with lazy EE, use legacy mpic for now */ + .get_irq= mpic_get_coreint_irq, Remove the comment. Also note Kevin's patch to consolidate on a common corenet board file. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2][v3] powerpc/fsl-booke: Add initial T104x_QDS board support
Scott Wood wrote: I think it should be okay to leave the DIU node. I think the kernel will crash if you try to enable a DIU console (video= on the kernel command line), but I think it's okay to ignore that for the moment. Sounds like a bug in the DIU driver. It should fail gracefully in the absence of platform support. I agree. And one day, I'll get a chance to look at the code to see if it's broken. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 3/3] powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
On Tue, Sep 24, 2013 at 05:41:32PM -0500, Scott Wood wrote: On Tue, 2013-09-24 at 11:03 +0800, Kevin Hao wrote: + and B4 QDS boards [...] Is there any difference between the 32-bit and 64-bit versions of this config symbol, other than the help text? No. As you know some of these boards only support 32bit kernel and some of them only support 64bit kernel. It will definitely cause confusion when using only one kernel option for all these boards. So I divide this into two options (even the same name) for 32bit and 64bit respectively. Thanks, Kevin -Scott pgpSUpqXU8vWS.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
linux-next: build failure after merge of the akpm tree
Hi Andrew, After merging the akpm tree, linux-next builds (powerpc allmodconfig) fail like this: drivers/tty/ehv_bytechan.c:362:1: error: type defaults to 'int' in declaration of 'console_initcall' [-Werror=implicit-int] Caused by commit 0f01cf96c2d4 (./Makefile: enable -Werror=implicit-int and -Werror=strict-prototypes by default) which has bee in linux-next since Aug 16. This commit exposed that fact that drivers/tty/ehv_bytechan.c can be built as a module, but has a console_initcall (which is not available to modules). This was originally introduced in commit dcd83aaff1c8 (tty/powerpc: introduce the ePAPR embedded hypervisor byte channel driver) in v3.2. Anyone got a good solution? -- Cheers, Stephen Rothwells...@canb.auug.org.au pgpNt0jEitsIn.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: linux-next: build failure after merge of the akpm tree
On Tue, Sep 24, 2013 at 8:06 PM, Stephen Rothwell s...@canb.auug.org.au wrote:
Hi Andrew,
After merging the akpm tree, linux-next builds (powerpc allmodconfig)
fail like this:
drivers/tty/ehv_bytechan.c:362:1: error: type defaults to 'int' in
declaration of 'console_initcall' [-Werror=implicit-int]
Caused by commit 0f01cf96c2d4 (./Makefile: enable -Werror=implicit-int
and -Werror=strict-prototypes by default) which has bee in linux-next
since Aug 16. This commit exposed that fact that
drivers/tty/ehv_bytechan.c can be built as a module, but has a
console_initcall (which is not available to modules).
Is this something new? This code hasn't changed in over two years, so
I'm surprised it suddenly broke.
This was
originally introduced in commit dcd83aaff1c8 (tty/powerpc: introduce the
ePAPR embedded hypervisor byte channel driver) in v3.2.
Anyone got a good solution?
How about:
#ifndef MODULE
static int __init ehv_bc_console_init(void)
{
...
}
console_initcall(ehv_bc_console_init);
#endif
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Re: [PATCH V2 0/6] perf: New conditional branch filter
On Mon, 2013-09-23 at 14:45 +0530, Anshuman Khandual wrote: On 09/21/2013 12:25 PM, Stephane Eranian wrote: On Tue, Sep 10, 2013 at 4:06 AM, Michael Ellerman mich...@ellerman.id.au wrote: On Fri, 2013-08-30 at 09:54 +0530, Anshuman Khandual wrote: This patchset is the re-spin of the original branch stack sampling patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset also enables SW based branch filtering support for PPC64 platforms which have branch stack sampling support. With this new enablement, the branch filter support for PPC64 platforms have been extended to include all these combinations discussed below with a sample test application program. ... Mixed filters - (6) perf record -e branch-misses:u -j any_call,any_ret ./cprog Error: The perf.data file has no samples! NOTE: As expected. The HW filters all the branches which are calls and SW tries to find return branches in that given set. Both the filters are mutually exclussive, so obviously no samples found in the end profile. The semantics of multiple filters is not clear to me. It could be an OR, or an AND. You have implemented AND, does that match existing behaviour on x86 for example? The semantic on the API is OR. AND does not make sense: CALL RETURN? On x86, the HW filter is an OR (default: ALL, set bit to disable a type). I suspect it is similar on PPC. Given the situation as explained here, which semantic would be better for single HW and multiple SW filters. Accordingly validate_instruction() function will have to be re-implemented. But I believe OR-ing the SW filters will be preferable. (1) (HW_FILTER_1) (SW_FILTER_1) (SW_FILTER_2) or (2) (HW_FILTER_1) (SW_FILTER_1 || SW_FILTER_2) Please let me know your inputs and suggestions on this. Thank you. You need to implement the correct semantics, regardless of how the hardware happens to work. That means if multiple filters are specified you need to do all the filtering in software. cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
/* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff -- git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR10x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR00x3FB /* Power management control register 0 */ Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF. Yes, now only e6500 have this register. There is no problem in this definition, because no conflict in FSL platform. Also I can see SPRN_ICCR also with same SPRN, how that is possible? Its possibly because the register maybe in implementation specific region. I'm guessing ICCR is a 40x specific register. Yes, kumar is right. Its use only in 4xx series of chips. ICTC(arch/powerpc/include/asm/reg.h) also use 0x3FB, Its use only in 6xx series of chips. -dongsheng ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
mm: insure topdown mmap chooses addresses above security minimum
A security check is performed on mmap addresses in
security/security.c:security_mmap_addr(). It uses mmap_min_addr to insure
mmaps don't get addresses lower than a user configurable guard value
(/proc/sys/vm/mmap_min_addr). The arch specific mmap topdown searches
look for a map candidate address all the way down to a low_limit that is
currently hard coded as PAGE_SIZE. Depending on compile time options
and userspace setting the procfs tunable, the security check's view of
the minimum allowable address may be something greater than PAGE_SIZE.
This leaves a gap where get_unmapped_area()'s call to get_area() might
return an address above PAGE_SIZE, but below mmap_min_addr, and thus
get_unmapped_area() fails.
This was seen on x86_64 in the case of a topdown address space and a large
stack rlimit, with mmap_min_addr having been set to 32k by the distro.
This left a 28k gap where the get area search intends to place a small
mmap, but then get_unmapped_area() stumbles at the security check.
What should have happened is the address search wraps back to a higher
address, the search continues and perhaps succeeds. Indeed an mmap of
a larger size gets a topdown search that does wrap around back up into
the rlimit stack reserve and succeeds assuming suitable free space.
But a small mmap fits in the low gap and always fails. It becomes
possible to make large mmaps but not small ones.
When an explicit address hint is given, mm/mmap.c's round_hint_to_min()
will round up to mmap_min_addr.
A topdown search's low_limit should similarly consider mmap_min_addr
instead of just PAGE_SIZE.
Signed-off-by: Tim Pepper timothy.c.pep...@linux.intel.com
Cc: linux...@kvack.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
Cc: Russell King li...@arm.linux.org.uk
Cc: linux-arm-ker...@lists.infradead.org
Cc: Ralf Baechle r...@linux-mips.org
Cc: linux-m...@linux-mips.org
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Paul Mundt let...@linux-sh.org
Cc: linux...@vger.kernel.org
Cc: David S. Miller da...@davemloft.net
Cc: sparcli...@vger.kernel.org
--
arch/arm/mm/mmap.c | 3 ++-
arch/mips/mm/mmap.c | 3 ++-
arch/powerpc/mm/slice.c | 3 ++-
arch/sh/mm/mmap.c| 3 ++-
arch/sparc/kernel/sys_sparc_64.c | 3 ++-
arch/x86/kernel/sys_x86_64.c | 3 ++-
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 0c63562..0e7355d 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -9,6 +9,7 @@
#include linux/io.h
#include linux/personality.h
#include linux/random.h
+#include linux/security.h
#include asm/cachetype.h
#define COLOUR_ALIGN(addr,pgoff) \
@@ -146,7 +147,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const
unsigned long addr0,
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm-mmap_base;
info.align_mask = do_align ? (PAGE_MASK (SHMLBA - 1)) : 0;
info.align_offset = pgoff PAGE_SHIFT;
diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c
index f1baadd..8c0deb7 100644
--- a/arch/mips/mm/mmap.c
+++ b/arch/mips/mm/mmap.c
@@ -14,6 +14,7 @@
#include linux/personality.h
#include linux/random.h
#include linux/sched.h
+#include linux/security.h
unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
EXPORT_SYMBOL(shm_align_mask);
@@ -102,7 +103,7 @@ static unsigned long arch_get_unmapped_area_common(struct
file *filp,
if (dir == DOWN) {
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm-mmap_base;
addr = vm_unmapped_area(info);
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 3e99c14..34fc601 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -30,6 +30,7 @@
#include linux/err.h
#include linux/spinlock.h
#include linux/export.h
+#include linux/security.h
#include asm/mman.h
#include asm/mmu.h
#include asm/spu.h
@@ -338,7 +339,7 @@ static unsigned long slice_find_area_topdown(struct
mm_struct *mm,
addr = prev;
goto prev_slice;
}
- info.low_limit = addr;
+ info.low_limit = max(addr, PAGE_ALIGN(mmap_min_addr));
found = vm_unmapped_area(info);
if (!(found ~PAGE_MASK))
diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c
index 6777177..1e0c53d 100644
--- a/arch/sh/mm/mmap.c
+++ b/arch/sh/mm/mmap.c
@@ -11,6 +11,7 @@
#include linux/mm.h
#include linux/mman.h
#include linux/module.h
+#include
RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Tuesday, September 24, 2013 9:19 PM To: Bhushan Bharat-R65777 Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: -Original Message- From: Linuxppc-dev [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of bounces+Dongsheng Wang Sent: Tuesday, September 24, 2013 2:58 PM To: Wood Scott-B07421 Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define From: Wang Dongsheng dongsheng.w...@freescale.com E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Add bit definitions for PWRMGTCR0. arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/include/asm/reg_booke.h | 9 + 2 files changed, 11 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x8020 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E6500 0x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff -- git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR10x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR00x3FB /* Power management control register 0 */ Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF. Also I can see SPRN_ICCR also with same SPRN, how that is possible? Its possibly because the register maybe in implementation specific region. I'm guessing ICCR is a 40x specific register. Kumar, this seems to create confusion? Although I do not like so many header files but still I think we can have reg_4xx.h, reg_fsl_booke.h etc for implementation specific definitions. -Bharat - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/pseries: Do not start secondaries in Open Firmware
Starting secondary CPUs early on from Open Firmware and placing them
in a holding spin loop slows down the boot process significantly under
some hypervisors such as KVM.
This is also unnecessary when RTAS supports querying the CPU state
So let's not do it.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/kernel/prom_init.c | 21 +
arch/powerpc/platforms/pseries/smp.c | 26 --
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 12e656f..5fe2842 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -196,6 +196,8 @@ static int __initdata mem_reserve_cnt;
static cell_t __initdata regbuf[1024];
+static bool rtas_has_query_cpu_stopped;
+
/*
* Error results ... some OF calls will return -1 on error, some
@@ -1574,6 +1576,11 @@ static void __init prom_instantiate_rtas(void)
prom_setprop(rtas_node, /rtas, linux,rtas-entry,
val, sizeof(val));
+ /* Check if it supports query-cpu-stopped-state */
+ if (prom_getprop(rtas_node, query-cpu-stopped-state,
+val, sizeof(val)) != PROM_ERROR)
+ rtas_has_query_cpu_stopped = true;
+
#if defined(CONFIG_PPC_POWERNV) defined(__BIG_ENDIAN__)
/* PowerVN takeover hack */
prom_rtas_data = base;
@@ -1815,6 +1822,18 @@ static void __init prom_hold_cpus(void)
= (void *) LOW_ADDR(__secondary_hold_acknowledge);
unsigned long secondary_hold = LOW_ADDR(__secondary_hold);
+ /*
+* On pseries, if RTAS supports query-cpu-stopped-state,
+* we skip this stage, the CPUs will be started by the
+* kernel using RTAS.
+*/
+ if ((of_platform == PLATFORM_PSERIES ||
+of_platform == PLATFORM_PSERIES_LPAR)
+ rtas_has_query_cpu_stopped) {
+ prom_printf(prom_hold_cpus: skipped\n);
+ return;
+ }
+
prom_debug(prom_hold_cpus: start...\n);
prom_debug(1) spinloop = 0x%x\n, (unsigned long)spinloop);
prom_debug(1) *spinloop = 0x%x\n, *spinloop);
@@ -3011,6 +3030,8 @@ unsigned long __init prom_init(unsigned long r3, unsigned
long r4,
* On non-powermacs, put all CPUs in spin-loops.
*
* PowerMacs use a different mechanism to spin CPUs
+*
+* (This must be done after instanciating RTAS)
*/
if (of_platform != PLATFORM_POWERMAC
of_platform != PLATFORM_OPAL)
diff --git a/arch/powerpc/platforms/pseries/smp.c
b/arch/powerpc/platforms/pseries/smp.c
index 1c1771a..24f58cb 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -233,18 +233,24 @@ static void __init smp_init_pseries(void)
alloc_bootmem_cpumask_var(of_spin_mask);
- /* Mark threads which are still spinning in hold loops. */
- if (cpu_has_feature(CPU_FTR_SMT)) {
- for_each_present_cpu(i) {
- if (cpu_thread_in_core(i) == 0)
- cpumask_set_cpu(i, of_spin_mask);
- }
- } else {
- cpumask_copy(of_spin_mask, cpu_present_mask);
+ /*
+* Mark threads which are still spinning in hold loops
+*
+* We know prom_init will not have started them if RTAS supports
+* query-cpu-stopped-state.
+*/
+ if (rtas_token(query-cpu-stopped-state) == RTAS_UNKNOWN_SERVICE) {
+ if (cpu_has_feature(CPU_FTR_SMT)) {
+ for_each_present_cpu(i) {
+ if (cpu_thread_in_core(i) == 0)
+ cpumask_set_cpu(i, of_spin_mask);
+ }
+ } else
+ cpumask_copy(of_spin_mask, cpu_present_mask);
+
+ cpumask_clear_cpu(boot_cpuid, of_spin_mask);
}
- cpumask_clear_cpu(boot_cpuid, of_spin_mask);
-
/* Non-lpar has additional take/give timebase */
if (rtas_token(freeze-time-base) != RTAS_UNKNOWN_SERVICE) {
smp_ops-give_timebase = rtas_give_timebase;
___
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[git pull] Please pull powerpc.git merge branch
Hi Linus ! Here are a few things for -rc2, this time it's all written by me so it can only be perfect right ? :) So we have the fix to call irq_enter/exit on the irq stack we've been discussing, plus a cleanup on top to remove an unused (and broken) stack limit tracking feature (well, make it 32-bit only in fact where it is used and works properly). Then we have two things that I wrote over the last couple of days and made the executive decision to include just because I can (and I'm sure you won't object right ?). They fix a couple of annoying and long standing issues: - We had separate zImages for when booting via Open Firmware vs. booting via a flat device-tree, while it's trivial to make one that deals with both - We wasted a ton of cycles spinning secondary CPUs uselessly at boot instead of starting them when needed on pseries, thus contributing significantly to global warming. Cheers, Ben. The following changes since commit 4a10c2ac2f368583138b774ca41fac4207911983: Linux 3.12-rc2 (2013-09-23 15:41:09 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge for you to fetch changes up to dbe78b40118636f2d5d276144239dd4bfd5f04f9: powerpc/pseries: Do not start secondaries in Open Firmware (2013-09-25 14:19:00 +1000) Benjamin Herrenschmidt (4): powerpc/irq: Run softirqs off the top of the irq stack powerpc: Remove ksp_limit on ppc64 powerpc/zImage: make the OF wrapper support ePAPR boot powerpc/pseries: Do not start secondaries in Open Firmware arch/powerpc/boot/Makefile | 4 +- arch/powerpc/boot/epapr-wrapper.c| 9 arch/powerpc/boot/epapr.c| 4 +- arch/powerpc/boot/of.c | 16 +- arch/powerpc/boot/wrapper| 9 ++-- arch/powerpc/include/asm/irq.h | 4 +- arch/powerpc/include/asm/processor.h | 4 +- arch/powerpc/kernel/asm-offsets.c| 3 +- arch/powerpc/kernel/irq.c| 100 +++ arch/powerpc/kernel/misc_32.S| 25 +++-- arch/powerpc/kernel/misc_64.S| 10 ++-- arch/powerpc/kernel/process.c| 3 +- arch/powerpc/kernel/prom_init.c | 21 arch/powerpc/lib/sstep.c | 3 +- arch/powerpc/platforms/pseries/smp.c | 26 + 15 files changed, 147 insertions(+), 94 deletions(-) create mode 100644 arch/powerpc/boot/epapr-wrapper.c ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
-Original Message- From: Bhushan Bharat-R65777 Sent: Wednesday, September 25, 2013 11:43 AM To: Kumar Gala Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc- d...@lists.ozlabs.org Subject: RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Tuesday, September 24, 2013 9:19 PM To: Bhushan Bharat-R65777 Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: -Original Message- From: Linuxppc-dev [mailto:linuxppc-dev- bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of bounces+Dongsheng Wang Sent: Tuesday, September 24, 2013 2:58 PM To: Wood Scott-B07421 Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define From: Wang Dongsheng dongsheng.w...@freescale.com E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- *v3: Add bit definitions for PWRMGTCR0. arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/include/asm/reg_booke.h | 9 + 2 files changed, 11 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x8020 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E6500 0x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff -- git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF. Also I can see SPRN_ICCR also with same SPRN, how that is possible? Its possibly because the register maybe in implementation specific region. I'm guessing ICCR is a 40x specific register. Kumar, this seems to create confusion? I don't think this define will create a confusion, because this is only SPR number definition and we already have a document(like EREF, ISA, this register define in E6500-EREF) to describe these registers. There are no conflicts and other platform and different platforms for the same register have different purposes, it looks normal. Instead we should put together, so as to remind that the SPR will be reuse from other platforms. -dongsheng ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: Rename IO accessor generation macros
In io.h we have macros to generate our IO accessors. These are currently
named FOO_BE() and FOO_LE() to indicate big little endian. However the
distinction between the macros is not so much the endianess as the form
of the instruction that is used.
Rename the macros to reflect that, so we end up with XFORM and DFORM
variants, and use them appropriately.
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
---
arch/powerpc/include/asm/io.h | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 5a64757..8b3bd66 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -113,7 +113,7 @@ extern bool isa_io_special;
/* gcc 4.0 and older doesn't have 'Z' constraint */
#if __GNUC__ 4 || (__GNUC__ == 4 __GNUC_MINOR__ == 0)
-#define DEF_MMIO_IN_LE(name, size, insn) \
+#define DEF_MMIO_IN_XFORM(name, size, insn)\
static inline u##size name(const volatile u##size __iomem *addr) \
{ \
u##size ret;\
@@ -122,7 +122,7 @@ static inline u##size name(const volatile u##size __iomem
*addr)\
return ret; \
}
-#define DEF_MMIO_OUT_LE(name, size, insn) \
+#define DEF_MMIO_OUT_XFORM(name, size, insn) \
static inline void name(volatile u##size __iomem *addr, u##size val) \
{ \
__asm__ __volatile__(sync;#insn %1,0,%2 \
@@ -130,7 +130,7 @@ static inline void name(volatile u##size __iomem *addr,
u##size val)\
IO_SET_SYNC_FLAG(); \
}
#else /* newer gcc */
-#define DEF_MMIO_IN_LE(name, size, insn) \
+#define DEF_MMIO_IN_XFORM(name, size, insn)\
static inline u##size name(const volatile u##size __iomem *addr) \
{ \
u##size ret;\
@@ -139,7 +139,7 @@ static inline u##size name(const volatile u##size __iomem
*addr)\
return ret; \
}
-#define DEF_MMIO_OUT_LE(name, size, insn) \
+#define DEF_MMIO_OUT_XFORM(name, size, insn) \
static inline void name(volatile u##size __iomem *addr, u##size val) \
{ \
__asm__ __volatile__(sync;#insn %1,%y0 \
@@ -148,7 +148,7 @@ static inline void name(volatile u##size __iomem *addr,
u##size val)\
}
#endif
-#define DEF_MMIO_IN_BE(name, size, insn) \
+#define DEF_MMIO_IN_DFORM(name, size, insn)\
static inline u##size name(const volatile u##size __iomem *addr) \
{ \
u##size ret;\
@@ -157,7 +157,7 @@ static inline u##size name(const volatile u##size __iomem
*addr)\
return ret; \
}
-#define DEF_MMIO_OUT_BE(name, size, insn) \
+#define DEF_MMIO_OUT_DFORM(name, size, insn) \
static inline void name(volatile u##size __iomem *addr, u##size val) \
{ \
__asm__ __volatile__(sync;#insn%U0%X0 %1,%0 \
@@ -166,21 +166,21 @@ static inline void name(volatile u##size __iomem *addr,
u##size val) \
}
-DEF_MMIO_IN_BE(in_8, 8, lbz);
-DEF_MMIO_IN_BE(in_be16, 16, lhz);
-DEF_MMIO_IN_BE(in_be32, 32, lwz);
-DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
-DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
+DEF_MMIO_IN_DFORM(in_8, 8, lbz);
+DEF_MMIO_IN_DFORM(in_be16, 16, lhz);
+DEF_MMIO_IN_DFORM(in_be32, 32, lwz);
+DEF_MMIO_IN_XFORM(in_le16, 16, lhbrx);
+DEF_MMIO_IN_XFORM(in_le32, 32, lwbrx);
-DEF_MMIO_OUT_BE(out_8, 8, stb);
-DEF_MMIO_OUT_BE(out_be16, 16, sth);
-DEF_MMIO_OUT_BE(out_be32, 32, stw);
-DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
-DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
+DEF_MMIO_OUT_DFORM(out_8, 8, stb);
+DEF_MMIO_OUT_DFORM(out_be16, 16, sth);
+DEF_MMIO_OUT_DFORM(out_be32, 32, stw);
+DEF_MMIO_OUT_XFORM(out_le16, 16, sthbrx);
+DEF_MMIO_OUT_XFORM(out_le32, 32, stwbrx);
#ifdef __powerpc64__
-DEF_MMIO_OUT_BE(out_be64, 64, std);
-DEF_MMIO_IN_BE(in_be64, 64, ld);
+DEF_MMIO_OUT_DFORM(out_be64, 64, std);
+DEF_MMIO_IN_DFORM(in_be64, 64, ld);
/* There is no asm instructions for
[PATCH 2/2] powerpc: Add real mode cache inhibited IO accessors
These accessors allow us to do cache inhibited accesses when in real
mode. They should only be used in real mode.
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
---
arch/powerpc/include/asm/io.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 8b3bd66..1cac8d3 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -178,10 +178,24 @@ DEF_MMIO_OUT_DFORM(out_be32, 32, stw);
DEF_MMIO_OUT_XFORM(out_le16, 16, sthbrx);
DEF_MMIO_OUT_XFORM(out_le32, 32, stwbrx);
+/*
+ * Cache inhibitied accessors for use in real mode, you don't want to use these
+ * unless you know what you're doing.
+ */
+DEF_MMIO_OUT_XFORM(out_rm8, 8, stbcix);
+DEF_MMIO_OUT_XFORM(out_rm16, 16, sthcix);
+DEF_MMIO_OUT_XFORM(out_rm32, 32, stwcix);
+DEF_MMIO_IN_XFORM(in_rm8, 8, lbzcix);
+DEF_MMIO_IN_XFORM(in_rm16, 16, lhzcix);
+DEF_MMIO_IN_XFORM(in_rm32, 32, lwzcix);
+
#ifdef __powerpc64__
DEF_MMIO_OUT_DFORM(out_be64, 64, std);
DEF_MMIO_IN_DFORM(in_be64, 64, ld);
+DEF_MMIO_OUT_XFORM(out_rm64, 64, stdcix);
+DEF_MMIO_IN_XFORM(in_rm64, 64, ldcix);
+
/* There is no asm instructions for 64 bits reverse loads and stores */
static inline u64 in_le64(const volatile u64 __iomem *addr)
{
--
1.8.1.2
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