From: Paul Mackerras
add kvmppc_free_vcores() to free the kvmppc_vcore structures
that we allocate for a guest, which are currently being leaked.
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv.c | 10 ++
1 file changed, 10 insertions
From: "Aneesh Kumar K.V"
This moves /dev/kvm ownership to kvm.ko module. Depending on
which KVM mode we select during VM creation we take a reference
count on respective module
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_ppc.h | 1 +
arch/powerpc/kv
From: Paul Mackerras
This label is not used now.
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_interrupts.S | 3 ---
arch/powerpc/kvm/book3s_interrupts.S| 3 ---
2 files changed, 6 deletions(-)
diff --git a/arch/powerpc/kvm
Hi All,
This patch series support enabling HV and PR KVM together in the same kernel. We
extend machine property with new property "kvm_type". A value of 1 will force HV
KVM and 2 PR KVM. The default value is 0 which will select the fastest KVM mode.
ie, HV if that is supported otherwise PR.
With
From: "Aneesh Kumar K.V"
This help ups to select the relevant code in the kernel code
when we later move HV and PR bits as seperate modules.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 6 +++---
arch/powerpc/include/asm/kvm_book3s_asm.h |
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/Kconfig | 6 +++---
arch/powerpc/kvm/Makefile | 12
arch/powerpc/kvm/book3s.c | 19 ++-
arch/powerpc/kvm/book3s_64_mmu_host.c | 1 +
ar
From: "Aneesh Kumar K.V"
This help us to identify whether we are running with hypervisor mode KVM
enabled. The change is needed so that we can have both HV and PR kvm
enabled in the same kernel.
If both HV and PR KVM are included, interrupts come in to the HV version
of the kvmppc
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/arm/kvm/arm.c | 4 ++--
arch/ia64/kvm/kvm-ia64.c | 4 ++--
arch/mips/kvm/kvm_mips.c | 6 ++
arch/powerpc/include/asm/kvm_ppc.h | 2 +-
arch/powerpc/kvm/44x.c |
From: "Aneesh Kumar K.V"
This moves the kvmppc_ops callbacks to be a per VM entity. This
enables us to select HV and PR mode when creating a VM
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 3 ++
arch/powerpc/include/asm/kvm_ppc.h | 11 --
arch/p
From: "Aneesh Kumar K.V"
This patch moves PR related tracepoints to a separate header. This
enables in converting PR to a kernel module which will be done in
later patches
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_host.c | 2 +-
arch/powerpc/kvm/book3s_
From: "Aneesh Kumar K.V"
This moves HV and PR specific functions to kvmppc_ops callback.
This is needed so that we can enable HV and PR together in the
same kernel. Actual changes to enable both come in the later
patch.This also renames almost all of the symbols that exist in both PR
EXPORT_SYMBOL_GPL().
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/Makefile | 12
arch/powerpc/kvm/book3s_64_vio_hv.c | 2 ++
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
From: "Aneesh Kumar K.V"
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
arch/powerpc/platforms/pseries/lpar.c | 2 +-
2 files
From: "Aneesh Kumar K.V"
only hash 64 config we always set memory coherence, If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE.
Signed
"Aneesh Kumar K.V" writes:
> Hi All,
>
> This patch series support enabling HV and PR KVM together in the same kernel.
> We
> extend machine property with new property "kvm_type". A value of 1 will force
> HV
> KVM and 2 PR KVM. The default value is 0
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This help ups to select the relevant code in the kernel code
>> when we later move HV and PR bits as seperate modules.
>
> I don&#x
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This moves HV and PR specific functions to kvmppc_ops callback.
>> This is needed so that we can enable HV and PR together in the
>> same
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This help us to identify whether we are running with hypervisor mode KVM
>> enabled. The change is needed so that we can have both HV
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This patch moves PR related tracepoints to a separate header. This
>> enables in converting PR to a kernel module which will be done in
>&
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c
>> b/arch/powerpc/kvm/book3s_64_mmu_host.c
>> index fd5b393..775d368 100644
>> --- a/arch/powerpc/kvm/book3s_64_mmu_ho
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>
> Missing patch description.
>
>> Signed-off-by: Aneesh Kumar K.V
>
> I fail to see how this really simplifies things, but at the end of the
&
Paolo Bonzini writes:
> Il 27/09/2013 15:13, Aneesh Kumar K.V ha scritto:
>> Alexander Graf writes:
>>
>>> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>>>
>>>> From: "Aneesh Kumar K.V"
>>>
>>> Missing patch descrip
Gleb Natapov writes:
> On Sat, Sep 28, 2013 at 09:06:47PM +0530, Aneesh Kumar K.V wrote:
>> Paolo Bonzini writes:
>>
>> > Il 27/09/2013 15:13, Aneesh Kumar K.V ha scritto:
>> >> Alexander Graf writes:
>> >>
>> >>> On 27.09.2013,
Alexander Graf writes:
> On 27.09.2013, at 15:03, Aneesh Kumar K.V wrote:
>
>> Alexander Graf writes:
>>
>>
>>>> diff --git a/arch/powerpc/kvm/book3s_segment.S
>>>> b/arch/powerpc/kvm/book3s_segment.S
>>>> index 1abe478..e0229dd 10
Alexander Graf writes:
> On 27.09.2013, at 15:06, Aneesh Kumar K.V wrote:
>
>> Alexander Graf writes:
>>
>>> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>>>
>>>> From: "Aneesh Kumar K.V"
>>>>
>>>>
Alexander Graf writes:
> On 27.09.2013, at 15:08, Aneesh Kumar K.V wrote:
>
>> Alexander Graf writes:
>>
>>> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>>>
>>>> diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c
>>>> b/arch/
Alexander Graf writes:
> On 27.09.2013, at 12:52, Aneesh Kumar K.V wrote:
>
>> "Aneesh Kumar K.V" writes:
>>
>>> Hi All,
>>>
>>> This patch series support enabling HV and PR KVM together in the same
>>> kernel. We
>>>
Alexander Graf writes:
> On 09/30/2013 02:57 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>>>>> diff --git a/arch/powerpc/kvm/trace.h b/arch/powerpc/kvm/trace.h
>>>>>> index a088e9a..7d5a136 100644
>>>>>> --- a
Alexander Graf writes:
> On 09/30/2013 02:56 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 27.09.2013, at 15:03, Aneesh Kumar K.V wrote:
>>>
>>>> Alexander Graf writes:
>>>>
>>>>
>>>>>> dif
Alexander Graf writes:
> On 09/30/2013 03:09 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 27.09.2013, at 12:52, Aneesh Kumar K.V wrote:
>>>
>>>> "Aneesh Kumar K.V" writes:
>>>>
>>>>> Hi All,
From: "Aneesh Kumar K.V"
This was introduced by 85a0d845d8bb5df5d2669416212f56cbe1474c6b
arch/powerpc/kvm/book3s_pr.c: In function 'kvmppc_core_vcpu_create':
arch/powerpc/kvm/book3s_pr.c:1182:30: error: 'struct kvmppc_vcpu_book3s' has no
member named 'shad
From: "Aneesh Kumar K.V"
This was introduced by 85a0d845d8 ("KVM: PPC: Book3S PR: Allocate
kvm_vcpu structs from kvm_vcpu_cache").
arch/powerpc/kvm/book3s_pr.c: In function 'kvmppc_core_vcpu_create':
arch/powerpc/kvm/book3s_pr.c:1182:30: error: 'struct kvmpp
From: "Aneesh Kumar K.V"
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
arch/powerpc/platforms/pseries/lpar.c | 5 +++--
2 files
From: "Aneesh Kumar K.V"
Set memory coherence always on hash64 config. If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE.
Signed
Alexander Graf writes:
> On 04.10.2013, at 14:23, Alexander Graf wrote:
>
>>
>> On 03.10.2013, at 06:14, Paul Mackerras wrote:
>>
>>> On Wed, Oct 02, 2013 at 08:08:44PM +0530, Aneesh Kumar K.V wrote:
>>>> From: "An
From: Paul Mackerras
This label is not used now.
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_interrupts.S | 3 ---
arch/powerpc/kvm/book3s_interrupts.S| 3 ---
2 files changed, 6 deletions(-)
diff --git a/arch/powerpc/kvm
EXPORT_SYMBOL_GPL().
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/Makefile | 12
arch/powerpc/kvm/book3s_64_vio_hv.c | 1 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index
From: "Aneesh Kumar K.V"
With later patches supporting PR kvm as a kernel module, the changes
that has to be built into the main kernel binary to enable PR KVM module
is now selected via KVM_BOOK3S_PR_POSSIBLE
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/exception-
From: "Aneesh Kumar K.V"
This patch add a new callback kvmppc_ops. This will help us in enabling
both HV and PR KVM together in the same kernel. The actual change to
enable them together is done in the later patch in the series.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/i
From: "Aneesh Kumar K.V"
This help ups to select the relevant code in the kernel code
when we later move HV and PR bits as seperate modules. The patch
also makes the config options for PR KVM selectable
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s.
From: "Aneesh Kumar K.V"
With this patch if HV is included, interrupts come in to the HV version
of the kvmppc_interrupt code, which then jumps to the PR handler,
renamed to kvmppc_interrupt_pr, if the guest is a PR guest. This helps
in enabling both HV and PR, which we do in later pat
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/booke.c | 4 +-
arch/powerpc/kvm/e500_mmu.c | 2 +-
arch/powerpc/kvm/e500_mmu_host.c | 3 +-
arch/powerpc/kvm/trace.h | 204 ---
arch/p
Hi All,
This patch series support enabling HV and PR KVM together in the same kernel. We
extend machine property with new property "kvm_type". A value of "HV" will
force HV
KVM and "PR" PR KVM. If we don't specify kvm_type we will select the fastest
KVM mode.
ie, HV if that is supported otherwis
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/Kconfig | 6 +++---
arch/powerpc/kvm/Makefile | 11 ---
arch/powerpc/kvm/book3s.c | 12 +++-
arch/powerpc/kvm/book3s_emulate.c | 2 +-
arch/powerpc/kvm/book3s_hv.c
From: "Aneesh Kumar K.V"
We will use that in the later patch to find the kvm ops handler
Signed-off-by: Aneesh Kumar K.V
---
arch/arm/kvm/arm.c | 5 +++--
arch/ia64/kvm/kvm-ia64.c | 5 +++--
arch/mips/kvm/kvm_mips.c | 5 +++--
arch/powerpc/i
From: "Aneesh Kumar K.V"
This moves the kvmppc_ops callbacks to be a per VM entity. This
enables us to select HV and PR mode when creating a VM. We also
allow both kvm-hv and kvm-pr kernel module to be loaded. To
achieve this we move /dev/kvm ownership to kvm.ko module. Depending on
From: "Aneesh Kumar K.V"
drop is_hv_enabled, because that should not be a callback property
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_ppc.h | 6 +-
arch/powerpc/kvm/book3s.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 1 -
arch/powerpc/kvm/b
From: "Aneesh Kumar K.V"
Make required changes to get BOOKE configs to build with
the introduction of kvmppc_ops callback
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_ppc.h | 4 +--
arch/powerpc/kvm/44x.c | 55 +++---
From: "Aneesh Kumar K.V"
This patch moves PR related tracepoints to a separate header. This
enables in converting PR to a kernel module which will be done in
later patches
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_host.c | 2 +-
arch/powerpc/kvm/book3s_
From: "Aneesh Kumar K.V"
This help us to identify whether we are running with hypervisor mode KVM
enabled. The change is needed so that we can have both HV and PR kvm
enabled in the same kernel.
If both HV and PR KVM are included, interrupts come in to the HV version
of the kvmppc
"Aneesh Kumar K.V" writes:
> From: "Aneesh Kumar K.V"
>
> Even though we have same value for linux PTE bits and hash PTE pits
> use the hash pte bits wen updating hash pte
...
> diff --git a/arch/powerpc/platforms/pseries/lpar.c
> b/arch/powerpc/pl
Hi Alex,
Any update on this ?
-aneesh
"Aneesh Kumar K.V" writes:
> Hi All,
>
> This patch series support enabling HV and PR KVM together in the same kernel.
> We
> extend machine property with new property "kvm_type". A value of "HV" will
The below patch fix a compile issue with KVM_XICS. Please fold
diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c
index cef3de9..c3c832b 100644
--- a/arch/powerpc/kvm/book3s_xics.c
+++ b/arch/powerpc/kvm/book3s_xics.c
@@ -840,6 +840,7 @@ int kvmppc_xics_hcall(struct kvm_
Alistair Popple writes:
> PPC44x supports page sizes other than 4K however when 64K page sizes
> are selected compilation fails. This is due to a change in the
> definition of pgtable_t introduced by the following patch:
>
> commit 5c1f6ee9a31cbdac90bbb8ae1ba4475031ac74b4
> Au
Alexander Graf writes:
> On 07.10.2013, at 18:47, Aneesh Kumar K.V
> wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> Make required changes to get BOOKE configs to build with
>> the introduction of kvmppc_ops callback
>>
>> Signed-off-by:
Hi,
This patch series add support for numa faults on ppc64 architecture. We steal
the
_PAGE_COHERENCE bit and use that for indicating _PAGE_NUMA. We clear the
_PAGE_PRESENT bit
and also invalidate the hpte entry on setting _PAGE_NUMA. The next fault on that
page will be considered a numa fault.
From: "Aneesh Kumar K.V"
We want to make sure we don't use these function when updating a pte
or pmd entry that have a valid hpte entry, because these functions
don't invalidate them. So limit the check to _PAGE_PRESENT bit.
Numafault core changes use these functions for upda
From: "Aneesh Kumar K.V"
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
arch/powerpc/platforms/pseries/lpar.c | 3 ++-
2 files
From: "Aneesh Kumar K.V"
change_prot_numa should work even if _PAGE_NUMA != _PAGE_PROTNONE.
On archs like ppc64 that don't use _PAGE_PROTNONE and also have
a separate page table outside linux pagetable, we just need to
make sure that when calling change_prot_numa we flush the
hard
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h
b/arch/powerpc/include/asm/pgtable-ppc64.h
ind
From: "Aneesh Kumar K.V"
Provide numa related functions for updating pmd entries.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/powerpc/i
From: "Aneesh Kumar K.V"
Archs like ppc64 have different layout for pmd entries pointing to PTE
page. Hence add a separate function for modifying them
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 17 +
include/asm-generic/pgtable.h
From: "Aneesh Kumar K.V"
After commit e2b3d202d1dba8f3546ed28224ce485bc50010be we have the
below possible formats for pmd entry
(1) invalid (all zeroes)
(2) pointer to next table, as normal; bottom 6 bits == 0
(3) leaf pte for huge page, bottom two bits != 00
(4) hugepd pointer, botto
From: "Aneesh Kumar K.V"
We steal the _PAGE_COHERENCE bit and use that for indicating NUMA ptes.
This patch still disables the numa hinting using pmd entries. That
require further changes to pmd entry format which is done in later
patches.
Signed-off-by: Aneesh Kumar K.V
---
ar
From: "Aneesh Kumar K.V"
Set memory coherence always on hash64 config. If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE.
Signed
From: "Aneesh Kumar K.V"
We don't use PACATOC for PR. Avoid updating HOST_R2 with PR
KVM mode when both HV and PR are enabled in the kernel. Without this we
get the below crash
(qemu)
Unable to handle kernel paging request for data at address 0x8310
Faulting inst
From: "Aneesh Kumar K.V"
Don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
NOTE: I am not sure why we were originally computing dsisr and dar. So may be
we need a variant of this patch. But with this and the additional patch
"powerpc: book3s: PR: Ena
From: "Aneesh Kumar K.V"
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V
---
This patch depends on the below two changes
1) [PATCH v5 0/6] KVM: PPC: Book3S: MMIO support
From: "Aneesh Kumar K.V"
The ASM version of hash computation function was truncating the upper bit.
Make the ASM version similar to hpt_hash function. Remove masking vsid bits.
Without this patch, we observed hang during bootup due to not satisfying page
fault request correctly.
Hello,
This is the preparatory patchset for supporting THP on powerpc. I am sending
this across
so that we can get review on this change.
For full THP support on powerpc, I have an early version that boots and runs
few test. But
I am still running into few issues, like Firmware NMI etc. Once t
From: "Aneesh Kumar K.V"
USE PTRS_PER_PTE to indicate the size of pte page.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |6 ++
arch/powerpc/mm/hash_low_64.S |4 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/power
From: "Aneesh Kumar K.V"
We now have PTE page consuming only 2K of the 64K page.This is in order to
facilitate transparent huge page support, which works much better if our PMDs
cover 16MB instead of 256MB.
Inorder to reduce the wastage, we now have multiple PTE page fragment
from th
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the huge page and
the range mapped by a single pmd entry should be equal to the huge page size
supported by the hardware.
Phileas Fogg writes:
> Please ignore the previous patch to fix the PACA issue on PS3 arch.
> This is the correct one:
>
> --- a/arch/powerpc/kernel/setup_64.c 2013-02-10 13:56:12.803855673 +0100
> +++ b/arch/powerpc/kernel/setup_64.c 2013-02-10 14:07:22.870561322 +0100
> @@ -186,6 +186,9 @@
>
Phileas Fogg writes:
> And another note.
> I took a look at the MMU chapter in the Cell Architecture handbook and indeed
> the first 15 bits in VA are treated as 0 by the hardware.
>
> Quote:
>
> 1. High-order bits above 65 bits in the 80-bit virtual address (VA[0:14]) are
> not implemented. T
"Aneesh Kumar K.V" writes:
> Phileas Fogg writes:
>
>> And another note.
>> I took a look at the MMU chapter in the Cell Architecture handbook and
>> indeed the first 15 bits in VA are treated as 0 by the hardware.
>>
>> Quote:
>>
>&
From: "Aneesh Kumar K.V"
VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
bits. Make the dependency explicit
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --
From: "Aneesh Kumar K.V"
Different platforms supports different virtual addr size(n bits). We need to
mak sure
0:77-n bits of the VA generated is forced to zero.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 22 +-
1 file c
Benjamin Herrenschmidt writes:
> On Wed, 2013-02-13 at 00:01 +0530, Aneesh Kumar K.V wrote:
>> + * Be careful with this value. This determines the VSID_MODULUS_* and that
>> + * need to be co-prime with VSID_MULTIPLIER*
>> + */
>> +#if defined(CONFIG_POWER6_CPU) |
Benjamin Herrenschmidt writes:
> On Wed, 2013-02-13 at 08:54 +0530, Aneesh Kumar K.V wrote:
>> > A compile option ? Really ? Ugh...
>>
>> I actually wanted that to be done in Kconfig.cputype, but haven't found
>> a nice way to do it. Considering we are swit
David Laight writes:
>> +#define CONTEXT_BITS19
>> +#define USER_ESID_BITS 18
>> +#define USER_ESID_BITS_1T 6
>> +
>> +/*
>> + * 256MB segment
>> + * The proto-VSID space has 2^(CONTEX_BITS + USER_ESID_BITS) - 1 segments
>> + * available for user + kernel mapping. T
"Aneesh Kumar K.V" writes:
> David Laight writes:
>
>>> +#define CONTEXT_BITS 19
>>> +#define USER_ESID_BITS 18
>>> +#define USER_ESID_BITS_1T 6
>>> +
>>> +/*
>>> + * 256MB segment
>>
From: "Aneesh Kumar K.V"
VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
bits. Make the dependency explicit
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --
From: "Aneesh Kumar K.V"
This patch change the kernel VSID range so that we limit VSID_BITS to 37.
This enables us to support 64TB with 65 bit VA (37+28). Without this patch
we have boot hangs on platforms that only support 65 bit VA.
With this patch we now have proto vsid generate
From: "Aneesh Kumar K.V"
We need to make sure that we don't have higher bits of kernel effective
address set. That would result in multiple kernel segments having same
proto vsid. Add debug code to make sure we capture this.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/
From: "Aneesh Kumar K.V"
This enables us to use r10 as scratch in the code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 487f99
"Aneesh Kumar K.V" writes:
> From: "Aneesh Kumar K.V"
>
> This patch change the kernel VSID range so that we limit VSID_BITS to 37.
> This enables us to support 64TB with 65 bit VA (37+28). Without this patch
> we have boot hangs on platforms that only suppor
From: "Aneesh Kumar K.V"
This patch change the kernel VSID range so that we limit VSID_BITS to 37.
This enables us to support 64TB with 65 bit VA (37+28). Without this patch
we have boot hangs on platforms that only support 65 bit VA.
With this patch we now have proto vsid generate
From: "Aneesh Kumar K.V"
VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
bits. Make the dependency explicit
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |3 ++-
arch/powerpc/mm/hash_utils_64.c | 12 +++-
arch/powerpc/mm/hugetlbpage-hash64.c |2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --
From: "Aneesh Kumar K.V"
As per ISA doc, we encode base and actual page size in the LP bits of
PTE. The number of bit used to encode the page sizes depend on actual
page size. ISA doc lists this as
PTE LP actual page size
rrrz ≥8KB
rrzz ≥16KB
rzzz
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [
From: "Aneesh Kumar K.V"
Need changes to other archs. This need to be fixed further
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |3 ++-
arch/powerpc/mm/pgtable.c | 11 ---
mm/huge_memory.c | 18 -
From: "Aneesh Kumar K.V"
This will be later used by powerpc THP support. In powerpc we want to use
pgtable for storing the hash index values. So instead of adding them to
mm_context list, we would like to store them in the second half of pmd
Signed-off-by: Aneesh Kumar K.V
---
From: "Aneesh Kumar K.V"
This make sure we handle Multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 52 +-
1 file changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the huge page and
the range mapped by a single pmd entry should be equal to the huge page size
supported by the hardware.
From: "Aneesh Kumar K.V"
We look at both the segment base page size and actual page size and store
the pte-lp-encodings in an array per base page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h|3 +-
arch/powerpc/include/asm/mmu-hash64.h | 12
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |8
arch/powerpc/mm/hash_native_64.c | 10 +-
arch/powerpc/platforms/pseries/lpar.c |2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --
From: "Aneesh Kumar K.V"
We will use this later with THP changes. With THP we want to create PMD with
twice the size. The second half will be used to depoist pgtable, which will
carry the hpte hash index value
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc6
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