Re: lanana: Add major/minor entries for PPC QE UART devices

2007-02-28 Thread Segher Boessenkool
46 = /dev/ttyCPM0PPC CPM (SCC or SMC) - port 0 ... - 47 = /dev/ttyCPM5PPC CPM (SCC or SMC) - port 5 + 49 = /dev/ttyCPM5PPC CPM (SCC or SMC) - port 5 If CPM0 is 46, then CPM5 is not 47, but not 49 either. Unless it's not CPM5 but

Re: lanana: Add major/minor entries for PPC QE UART devices

2007-02-28 Thread Segher Boessenkool
Just allocate the four slots and we'll deal with anything above this in custom products. Another option is to use 46..49 for UARTs #0..3, and 192..195 for UARTs #4..7. Or, perhaps better, use 46..49 for #0..3, and 192..199 for #0..7, handling the duplication in the driver; and deprecate the

Re: lanana: Add major/minor entries for PPC QE UART devices

2007-02-28 Thread Segher Boessenkool
Please, let's just leave the four we have No one is suggesting otherwise. and let the driver just allocate increasing minor numbers. If anyone has a product with more than 4 UARTs, they will have to figure out what to do with the additional minors. Since you say no one has ever used more

Re: lanana: Add major/minor entries for PPC QE UART devices

2007-03-01 Thread Segher Boessenkool
- Cap the driver at 4 UARTs; Let's do this, but design the code to allow more by just changing a #define. Just randomly using some extra minors that aren't assigned to you isn't such a great idea. Maybe for a desktop or generic server where you don't know what's going to be configured,

Possible bug in flush_dcache_all on 440GP

2003-02-26 Thread Segher Boessenkool
Eugene Surovegin wrote: I believe there is a bug in flush_dcache_all implementation for not cache coherent processors. This function uses simple algorithm to force dcache flush by reading enough data to completely reload the cache: [snip] So you're saying it doesn't use an LRU replacement

[RFC] Adding MTD to device tree

2006-08-12 Thread Segher Boessenkool
Required properties: - device_type : one of nand-flash, nor-flash, or rom. There are more than just those kinds of MTDs. There's dataflash, AG-AND, NVRAM, ioremappable DRAM, etc. I'd prefer it to just be called flash. See more below. Existing firmwares call it rom, nvram,

__switch_to test-and-branch ALTIVEC specific?

2005-09-15 Thread Segher Boessenkool
This probably has to due with what happens on a G4 system with a kernel not build with Altivec.. However, I dont remember exactly what behavior is desired. A kernel not build with AltiVec support will just SIGILL any user process that tries to use it (and MSR[VEC] = 0). The code here can

[PATCH] ppc32: emulate load/store string instructions

2005-03-19 Thread Segher Boessenkool
+ /* Early out if we are an invalid form of lswi */ + if ((instword INST_STRING_MASK) == INST_LSWX) Typo ^ Segher

SV: New invalidate/clean/flush_dcache functions

2002-12-27 Thread Segher Boessenkool
Joakim Tjernlund wrote: Only the invalidate function is missing the sync instruction. It's not needed. Invalidating the cache does not touch the memory so there is no need to sync the memory. I have been running my system sync is not a sync the memory instruction, whatever that should mean.

SV: SV: New invalidate/clean/flush_dcache functions

2002-12-28 Thread Segher Boessenkool
Joakim Tjernlund wrote: In my typical example I need to invalidate a buffer before I give it to the CPM to be used as a receive buffer. Once given to the CPM there must be no more writes to that buffer memory. When the CPM has received data and written the data into the buffer and hands it

[JOB] Senior Embedded Linux Video Engineer

2006-07-14 Thread Segher Boessenkool
On the other hand, a couple weeks ago, proclus at gnu-darwin.org posted a very long, meandering political statement, most of which seemed to have very little to do with PowerPC Linux and I didn't notice anyone complain on these lists. I complained on another list -- he sent it _everywhere_.

Re: printk/console_init - baud rate setting

2007-11-14 Thread Segher Boessenkool
I am getting garbage on the screen. So, I presume this must be some sort of baud rate issue. Can some one help me out understand how this baud is set for serial drivers? I want to run at 115200. console=ttyS0,115200 See Documentation/kernel-parameters.txt; depending on exactly what early

Re: [PATCH] Add AMCC Arches 460GT eval board support to platforms/44x

2008-07-16 Thread Segher Boessenkool
Shouldn't it be enough to have a common compatible value in each of these boards, e.g. amcc,generic-ppc44x and then just ignore the specific type unless you need to do something special? This is bad for the same reason that amcc,44x-blah compatible values are bad in device nodes. The

Re: [PATCH] Add AMCC Arches 460GT eval board support to platforms/44x

2008-07-16 Thread Segher Boessenkool
And then you don't need this file at all. Just add a amcc,canyonlands string to your root node compatible property. No! Don't do this because it is not true! If the board actually _is_ compatible to the canyonlands board (it only _adds_ stuff, doesn't change things or takes away things), it

Re: [PATCH] Add AMCC Arches 460GT eval board support to platforms/44x

2008-07-16 Thread Segher Boessenkool
Shouldn't it be enough to have a common compatible value in each of these boards, e.g. amcc,generic-ppc44x and then just ignore the specific type unless you need to do something special? This is bad for the same reason that amcc,44x-blah compatible values are bad in device nodes.  The