from:"Valentina Giusti via lldb\-commits"

[Lldb-commits] [lldb] r293660 - Add a command to access and manipulate the Intel(R) MPX Boundary Tables.

2017-01-31 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Tue Jan 31 12:02:54 2017
New Revision: 293660

URL: http://llvm.org/viewvc/llvm-project?rev=293660=rev
Log:
Add a command to access and manipulate the Intel(R) MPX Boundary Tables.

Summary:
The Boundary Table Entries are stored in the application memory and allow
to store boundary info for all the pointers of the program, also those that
otherwise wouldn't fit in the 4 bound registers provided by the HW.

Here is an example of how it works:
 * mpx-table show 
lbound = 0x..., ubound = 0x..., (pointer value = 0x..., metadata = 
0x...)
 * mpx-table set 

Signed-off-by: Valentina Giusti 

Reviewers: labath, clayborg

Reviewed By: clayborg

Subscribers: lldb-commits, mgorny

Differential Revision: https://reviews.llvm.org/D29078

Added:
lldb/trunk/tools/intel-mpx/
lldb/trunk/tools/intel-mpx/CMakeLists.txt
lldb/trunk/tools/intel-mpx/IntelMPXTablePlugin.cpp
lldb/trunk/tools/intel-mpx/test/
lldb/trunk/tools/intel-mpx/test/Makefile
lldb/trunk/tools/intel-mpx/test/README.txt
lldb/trunk/tools/intel-mpx/test/TestMPXTable.py
lldb/trunk/tools/intel-mpx/test/main.cpp
Modified:
lldb/trunk/tools/CMakeLists.txt

Modified: lldb/trunk/tools/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/CMakeLists.txt?rev=293660=293659=293660=diff
==
--- lldb/trunk/tools/CMakeLists.txt (original)
+++ lldb/trunk/tools/CMakeLists.txt Tue Jan 31 12:02:54 2017
@@ -8,3 +8,4 @@ add_subdirectory(lldb-mi)
 if (LLDB_CAN_USE_LLDB_SERVER)
   add_subdirectory(lldb-server)
 endif()
+add_subdirectory(intel-mpx)

Added: lldb/trunk/tools/intel-mpx/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/intel-mpx/CMakeLists.txt?rev=293660=auto
==
--- lldb/trunk/tools/intel-mpx/CMakeLists.txt (added)
+++ lldb/trunk/tools/intel-mpx/CMakeLists.txt Tue Jan 31 12:02:54 2017
@@ -0,0 +1,23 @@
+if (NOT CMAKE_SYSTEM_NAME MATCHES "Linux")
+  return ()
+endif ()
+
+include(${LLDB_PROJECT_ROOT}/cmake/LLDBDependencies.cmake)
+
+add_library(lldb-intel-mpxtable SHARED
+  IntelMPXTablePlugin.cpp
+  )
+
+target_link_libraries(lldb-intel-mpxtable PUBLIC liblldb)
+
+if (LLDB_LINKER_SUPPORTS_GROUPS)
+  target_link_libraries(lldb-intel-mpxtable PUBLIC
+-Wl,--start-group ${LLDB_USED_LIBS} -Wl,--end-group)
+else()
+  target_link_libraries(lldb-intel-mpxtable PUBLIC ${LLDB_USED_LIBS})
+endif()
+llvm_config(lldb-intel-mpxtable ${LLVM_LINK_COMPONENTS})
+
+
+install(TARGETS lldb-intel-mpxtable
+  LIBRARY DESTINATION bin)

Added: lldb/trunk/tools/intel-mpx/IntelMPXTablePlugin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/intel-mpx/IntelMPXTablePlugin.cpp?rev=293660=auto
==
--- lldb/trunk/tools/intel-mpx/IntelMPXTablePlugin.cpp (added)
+++ lldb/trunk/tools/intel-mpx/IntelMPXTablePlugin.cpp Tue Jan 31 12:02:54 2017
@@ -0,0 +1,426 @@
+//===-- IntelMPXTablePlugin.cpp--*- C++ 
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+
+// C++ includes
+#include 
+
+// Project includes
+#include "lldb/API/SBCommandInterpreter.h"
+#include "lldb/API/SBCommandReturnObject.h"
+#include "lldb/API/SBMemoryRegionInfo.h"
+#include "lldb/API/SBProcess.h"
+#include "lldb/API/SBTarget.h"
+#include "lldb/API/SBThread.h"
+
+#include "llvm/ADT/Triple.h"
+
+namespace lldb {
+bool PluginInitialize(lldb::SBDebugger debugger);
+}
+
+static bool GetPtr(char *cptr, uint64_t , lldb::SBFrame ,
+   lldb::SBCommandReturnObject ) {
+  if (!cptr) {
+result.SetError("Bad argument.");
+result.SetStatus(lldb::eReturnStatusFailed);
+return false;
+  }
+
+  lldb::SBValue ptr_addr = frame.GetValueForVariablePath(cptr);
+  if (!ptr_addr.IsValid()) {
+result.SetError("Invalid pointer.");
+result.SetStatus(lldb::eReturnStatusFailed);
+return false;
+  }
+  ptr = ptr_addr.GetLoadAddress();
+  return true;
+}
+
+enum {
+  mpx_base_mask_64 = ~(uint64_t)0xFFFULL,
+  mpx_bd_mask_64 = 0xFFF0ULL,
+  bd_r_shift_64 = 20,
+  bd_l_shift_64 = 3,
+  bt_r_shift_64 = 3,
+  bt_l_shift_64 = 5,
+  bt_mask_64 = 0x0008ULL,
+
+  mpx_base_mask_32 = 0xF000ULL,
+  mpx_bd_mask_32 = 0xF000ULL,
+  bd_r_shift_32 = 12,
+  bd_l_shift_32 = 2,
+  bt_r_shift_32 = 2,
+  bt_l_shift_32 = 4,
+  bt_mask_32 = 0x0FFCULL,
+};
+
+static void PrintBTEntry(lldb::addr_t lbound, lldb::addr_t ubound,
+ uint64_t value, uint64_t meta,
+ lldb::SBCommandReturnObject ) {
+  const lldb::addr_t

[Lldb-commits] [lldb] r280668 - Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-05 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Mon Sep  5 12:43:10 2016
New Revision: 280668

URL: http://llvm.org/viewvc/llvm-project?rev=280668=rev
Log:
Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

Summary:

The Intel(R) Memory Protection Extensions (Intel(R) MPX) associates pointers
to bounds, against which the software can check memory references to
prevent out of bound memory access.

This patch allows accessing the MPX registers:
  * bnd0-3: 128-bit registers to hold the bound values,
  * bndcfgu, bndstatus: 64-bit configuration registers,

This patch also adds read/write tests for the MPX registers in the register
command tests and adds a new subdirectory for MPX specific tests.

Signed-off-by: Valentina Giusti 

Reviewers: labath, granata.enrico, lldb-commits, clayborg

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D24187

Added:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile
  - copied, changed from r280662, 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
  - copied, changed from r280662, 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
  - copied, changed from r280662, 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/a.cpp

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
  - copied, changed from r280662, 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/main.cpp
Removed:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/a.cpp
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/main.cpp
Modified:
lldb/trunk/source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp
lldb/trunk/source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
lldb/trunk/source/Plugins/Process/Utility/RegisterContext_x86.h
lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_x86_64.h
lldb/trunk/source/Plugins/Process/Utility/lldb-x86-register-enums.h

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Removed: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile?rev=280667=auto
==
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile 
(original)
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile 
(removed)
@@ -1,5 +0,0 @@
-LEVEL = ../../make
-
-CXX_SOURCES := main.cpp a.cpp
-
-include $(LEVEL)/Makefile.rules

Removed: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py?rev=280667=auto
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
 (removed)
@@ -1,350 +0,0 @@
-"""
-Test the 'register' command.
-"""
-
-from __future__ import print_function
-
-
-
-import os, sys, time
-import re
-import lldb
-from lldbsuite.test.decorators import *
-from lldbsuite.test.lldbtest import *
-from lldbsuite.test import lldbutil
-
-class RegisterCommandsTestCase(TestBase):
-
-mydir = TestBase.compute_mydir(__file__)
-
-def setUp(self):
-TestBase.setUp(self)
-self.has_teardown = False
-
-def tearDown(self):
-self.dbg.GetSelectedTarget().GetProcess().Destroy()
-

Re: [Lldb-commits] [PATCH] D24187: Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-05 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL280668: Intel(R) Memory Protection Extensions (Intel(R) MPX) 
support. (authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D24187?vs=70152=70342#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24187

Files:
  lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
  lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/a.cpp
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
  lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/main.cpp
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
  lldb/trunk/source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp
  lldb/trunk/source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterContext_x86.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_x86_64.h
  lldb/trunk/source/Plugins/Process/Utility/lldb-x86-register-enums.h
  
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
===
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
@@ -0,0 +1,36 @@
+//===-- main.cpp *- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+#include 
+
+#include 
+#include 
+
+long double outermost_return_long_double (long double my_long_double);
+
+int main (int argc, char const *argv[])
+{
+lldb_enable_attach();
+
+char my_string[] = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 0};
+double my_double = 1234.5678;
+long double my_long_double = 1234.5678;
+
+// For simplicity assume that any cmdline argument means wait for attach.
+if (argc > 1)
+{
+volatile int wait_for_attach=1;
+while (wait_for_attach)
+std::this_thread::sleep_for(std::chrono::microseconds(1));
+}
+
+printf("my_string=%s\n", my_string);
+printf("my_double=%g\n", my_double);
+outermost_return_long_double (my_long_double);
+return 0;
+}
Index: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
===
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
@@ -0,0 +1,44 @@
+//===-- a.cpp *- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+#include 
+
+long double
+return_long_double (long double value)
+{
+#if defined (__i386__) || defined (__x86_64__)
+float a=2, b=4,c=8, d=16, e=32, f=64, k=128, l=256, add=0;
+__asm__ (
+"int3 ;"
+"flds %1 ;"
+"flds %2 ;"
+"flds %3 ;"
+"flds %4 ;"
+"flds %5 ;"
+"flds %6 ;"
+"flds %7 ;"
+"faddp ;" : "=g" (add) : "g" (a), "g" (b), "g" (c), "g" (d), "g" (e), "g" (f), "g" (k), "g" (l) );  // Set break point at this line.
+#endif// #if defined (__i386__) || defined (__x86_64__)
+return value;
+}
+
+long double
+outer_return_long_double (long double value)
+{
+long double val = return_long_double(value);
+val *= 2 ;
+return val;
+}
+
+long

[Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-06 Thread Valentina Giusti via lldb-commits

valentinagiusti created this revision.
valentinagiusti added a subscriber: lldb-commits.

Signed-off-by: Valentina Giusti 

https://reviews.llvm.org/D24255

Files:
  packages/Python/lldbsuite/test/functionalities/register/Makefile
  packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
  packages/Python/lldbsuite/test/functionalities/register/a.cpp
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
  packages/Python/lldbsuite/test/functionalities/register/main.cpp
  
packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
  packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
  
packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
  source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp
  source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  source/Plugins/Process/Utility/RegisterContext_x86.h
  source/Plugins/Process/Utility/RegisterInfos_i386.h
  source/Plugins/Process/Utility/RegisterInfos_x86_64.h
  source/Plugins/Process/Utility/lldb-x86-register-enums.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -610,6 +610,7 @@
   .Case("vector-sint32", eFormatVectorOfSInt32)
   .Case("vector-uint32", eFormatVectorOfUInt32)
   .Case("vector-float32", eFormatVectorOfFloat32)
+  .Case("vector-uint64", eFormatVectorOfUInt64)
   .Case("vector-uint128", eFormatVectorOfUInt128)
   .Default(eFormatInvalid);
 }
@@ -4545,6 +4546,8 @@
 reg_info.format = eFormatVectorOfUInt32;
 else if (value == "vector-float32")
 reg_info.format = eFormatVectorOfFloat32;
+else if (value == "vector-uint64")
+reg_info.format = eFormatVectorOfUInt64;
 else if (value == "vector-uint128")
 reg_info.format = eFormatVectorOfUInt128;
 }
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -1566,6 +1566,7 @@
 case eFormatVectorOfSInt32:  response.PutCString ("format:vector-sint32;"); break;
 case eFormatVectorOfUInt32:  response.PutCString ("format:vector-uint32;"); break;
 case eFormatVectorOfFloat32: response.PutCString ("format:vector-float32;"); break;
+case eFormatVectorOfUInt64:  response.PutCString ("format:vector-uint64;"); break;
 case eFormatVectorOfUInt128: response.PutCString ("format:vector-uint128;"); break;
 default: break;
 };
Index: source/Plugins/Process/Utility/lldb-x86-register-enums.h
===
--- source/Plugins/Process/Utility/lldb-x86-register-enums.h
+++ source/Plugins/Process/Utility/lldb-x86-register-enums.h
@@ -106,6 +106,18 @@
 lldb_ymm7_i386,
 k_last_avx_i386 = lldb_ymm7_i386,
 
+k_first_mpxr_i386,
+lldb_bnd0_i386 = k_first_mpxr_i386,
+lldb_bnd1_i386,
+lldb_bnd2_i386,
+lldb_bnd3_i386,
+k_last_mpxr = lldb_bnd3_i386,
+
+k_first_mpxc_i386,
+lldb_bndcfgu_i386 = k_first_mpxc_i386,
+lldb_bndstatus_i386,
+k_last_mpxc_i386 = lldb_bndstatus_i386,
+
 lldb_dr0_i386,
 lldb_dr1_i386,
 lldb_dr2_i386,
@@ -119,7 +131,8 @@
 k_num_gpr_registers_i386 = k_last_gpr_i386 - k_first_gpr_i386 + 1,
 k_num_fpr_registers_i386 = k_last_fpr_i386 - k_first_fpr_i386 + 1,
 k_num_avx_registers_i386 = k_last_avx_i386 - k_first_avx_i386 + 1,
-k_num_user_registers_i386 = k_num_gpr_registers_i386 + k_num_fpr_registers_i386 + k_num_avx_registers_i386,
+k_num_mpx_registers_i386 = k_last_mpxc_i386 -

Re: [Lldb-commits] [PATCH] D24187: Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-06 Thread Valentina Giusti via lldb-commits

valentinagiusti added a comment.

Thanks for the review! You can find my replies inline.



Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py:27
@@ +26,3 @@
+
+@skipIfiOSSimulator
+@skipIf(compiler="clang")

labath wrote:
> Do we really need the ios simulator decorator here?
Is this naturally skipped if all OSs are skipped except for linux?


Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py:29
@@ +28,3 @@
+@skipIf(compiler="clang")
+@expectedFailureAll(oslist=["linux"], compiler="gcc", 
compiler_version=["<", "5"])
+@skipIf(archs=no_match(['amd64', 'i386', 'x86_64']))

labath wrote:
> I presume this is XFAIL because the compiler does not have the required 
> features. If that is true then a "skip" result would be more appropriate.
True, here a skip would be better.


Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py:30
@@ +29,3 @@
+@expectedFailureAll(oslist=["linux"], compiler="gcc", 
compiler_version=["<", "5"])
+@skipIf(archs=no_match(['amd64', 'i386', 'x86_64']))
+def test_mpx_registers_with_example_code(self):

labath wrote:
> It shouldn't be necessary to specify `amd64` here. I know some old code does 
> that, but now we have code in `lldbtest.py` which automatically remaps it to 
> `x86_64`.
ok, I'll remove it then!


Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py:43
@@ +42,3 @@
+
+self.runCmd('settings set target.inline-breakpoint-strategy always')
+self.addTearDownHook(

labath wrote:
> Why is this necessary? (Also it looks like your cleanup function is the same 
> as the setup)
Sorry this is something I should have cleaned up.


Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py:50
@@ +49,3 @@
+
+self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
+substrs = ["stop reason = breakpoint 1."])

labath wrote:
> So, this test will fail if run on hardware which does not have the registers 
> you are testing now (as far as I can tell, that's pretty much all of it). We 
> should detect that situation (the inferior already has code for that, 
> apparently), and skip the test. Something like:
> ```
> if inferior_exited_with_minus_1:
>   self.skipTest("blah blah")
> ```
> 
> 
Good point! I will add this


Repository:
  rL LLVM

https://reviews.llvm.org/D24187



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Re: [Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-06 Thread Valentina Giusti via lldb-commits

valentinagiusti added a comment.

Hi, inline there are my other replies.



Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile:5
@@ +4,3 @@
+
+ifeq "$(ARCH)" "i386"
+   CXXFLAGS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd -m32

labath wrote:
> This should not be necessary. Makefile.rules already correctly appends -m32 
> when needed. Maybe CFLAGS_EXTRAS would work instead (?)
Unfortunately it doesn't append -m32 to all the instances when also a linker is 
needed in the build process. In fact, in the test logs it shows that only the 
first call of the g++ command has such a flag, and therefore the inferior code 
build ends with an error.
If there is a better way to do the same with CFLAGS_EXTRAS please let me know!



Comment at: 
packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py:297
@@ -294,4 +296,3 @@
 for registerSet in registerSets:
-if 'advanced vector extensions' in 
registerSet.GetName().lower():
-has_avx = True
-break
+if registerSet.GetName():
+if 'advanced vector extensions' in 
registerSet.GetName().lower():

labath wrote:
> Do we want to allow a register set with no name? It looks like the root of 
> the problem is elsewhere.
These lines of code are just to detect if there are AVX or MPX register sets, 
so I don't think there is the need to do anything about nameless sets here. If 
you don't like this solution, I think an alternative is to just check if there 
are the register names that belong to one set or the other, it just takes a bit 
longer - or I could just look for the first register in the set.


https://reviews.llvm.org/D24255



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Re: [Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-07 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 70507.
valentinagiusti added a comment.

Improved TestMPXRegisters.py and Makefile according to review.


https://reviews.llvm.org/D24255

Files:
  packages/Python/lldbsuite/test/functionalities/register/Makefile
  packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
  packages/Python/lldbsuite/test/functionalities/register/a.cpp
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
  packages/Python/lldbsuite/test/functionalities/register/main.cpp
  
packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
  packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
  
packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
  source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp
  source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  source/Plugins/Process/Utility/RegisterContext_x86.h
  source/Plugins/Process/Utility/RegisterInfos_i386.h
  source/Plugins/Process/Utility/RegisterInfos_x86_64.h
  source/Plugins/Process/Utility/lldb-x86-register-enums.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -610,6 +610,7 @@
   .Case("vector-sint32", eFormatVectorOfSInt32)
   .Case("vector-uint32", eFormatVectorOfUInt32)
   .Case("vector-float32", eFormatVectorOfFloat32)
+  .Case("vector-uint64", eFormatVectorOfUInt64)
   .Case("vector-uint128", eFormatVectorOfUInt128)
   .Default(eFormatInvalid);
 }
@@ -4545,6 +4546,8 @@
 reg_info.format = eFormatVectorOfUInt32;
 else if (value == "vector-float32")
 reg_info.format = eFormatVectorOfFloat32;
+else if (value == "vector-uint64")
+reg_info.format = eFormatVectorOfUInt64;
 else if (value == "vector-uint128")
 reg_info.format = eFormatVectorOfUInt128;
 }
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -1566,6 +1566,7 @@
 case eFormatVectorOfSInt32:  response.PutCString ("format:vector-sint32;"); break;
 case eFormatVectorOfUInt32:  response.PutCString ("format:vector-uint32;"); break;
 case eFormatVectorOfFloat32: response.PutCString ("format:vector-float32;"); break;
+case eFormatVectorOfUInt64:  response.PutCString ("format:vector-uint64;"); break;
 case eFormatVectorOfUInt128: response.PutCString ("format:vector-uint128;"); break;
 default: break;
 };
Index: source/Plugins/Process/Utility/lldb-x86-register-enums.h
===
--- source/Plugins/Process/Utility/lldb-x86-register-enums.h
+++ source/Plugins/Process/Utility/lldb-x86-register-enums.h
@@ -106,6 +106,18 @@
 lldb_ymm7_i386,
 k_last_avx_i386 = lldb_ymm7_i386,
 
+k_first_mpxr_i386,
+lldb_bnd0_i386 = k_first_mpxr_i386,
+lldb_bnd1_i386,
+lldb_bnd2_i386,
+lldb_bnd3_i386,
+k_last_mpxr = lldb_bnd3_i386,
+
+k_first_mpxc_i386,
+lldb_bndcfgu_i386 = k_first_mpxc_i386,
+lldb_bndstatus_i386,
+k_last_mpxc_i386 = lldb_bndstatus_i386,
+
 lldb_dr0_i386,
 lldb_dr1_i386,
 lldb_dr2_i386,
@@ -119,7 +131,8 @@
 k_num_gpr_registers_i386 = k_last_gpr_i386 - k_first_gpr_i386 + 1,
 k_num_fpr_registers_i386 = k_last_fpr_i386 - k_first_fpr_i386 + 1,
 k_num_avx_registers_i386 = k_last_avx_i386 - k_first_avx_i386 + 1,
-k_num_user_registers_i386 = k_num_gpr_registers_i386 + k_num_fpr_registers_i386 + k_num_avx_registers_i386,
+k_num_mpx_registers_i386 = k_last_mpxc_i386 -

Re: [Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-08 Thread Valentina Giusti via lldb-commits

valentinagiusti added inline comments.


Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile:7
@@ +6,2 @@
+
+include $(LEVEL)/Makefile.rules

Np, thanks for the review and explanations ;)


https://reviews.llvm.org/D24255



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Re: [Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-08 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 70695.
valentinagiusti added a comment.

Improved MPX test Makefile and removed workaround for unnamed register sets, 
and rebased according to the new coding style.


https://reviews.llvm.org/D24255

Files:
  packages/Python/lldbsuite/test/functionalities/register/Makefile
  packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
  packages/Python/lldbsuite/test/functionalities/register/a.cpp
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
  packages/Python/lldbsuite/test/functionalities/register/main.cpp
  
packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
  packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
  
packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
  source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp
  source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  source/Plugins/Process/Utility/RegisterContext_x86.h
  source/Plugins/Process/Utility/RegisterInfos_i386.h
  source/Plugins/Process/Utility/RegisterInfos_x86_64.h
  source/Plugins/Process/Utility/lldb-x86-register-enums.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -547,6 +547,7 @@
   .Case("vector-sint32", eFormatVectorOfSInt32)
   .Case("vector-uint32", eFormatVectorOfUInt32)
   .Case("vector-float32", eFormatVectorOfFloat32)
+  .Case("vector-uint64", eFormatVectorOfUInt64)
   .Case("vector-uint128", eFormatVectorOfUInt128)
   .Default(eFormatInvalid);
 }
@@ -4178,6 +4179,8 @@
   reg_info.format = eFormatVectorOfUInt32;
 else if (value == "vector-float32")
   reg_info.format = eFormatVectorOfFloat32;
+else if (value == "vector-uint64")
+  reg_info.format = eFormatVectorOfUInt64;
 else if (value == "vector-uint128")
   reg_info.format = eFormatVectorOfUInt128;
   } else if (name == "group_id") {
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -1592,6 +1592,9 @@
   case eFormatVectorOfFloat32:
 response.PutCString("format:vector-float32;");
 break;
+  case eFormatVectorOfUInt64:
+response.PutCString("format:vector-uint64;");
+break;
   case eFormatVectorOfUInt128:
 response.PutCString("format:vector-uint128;");
 break;
Index: source/Plugins/Process/Utility/lldb-x86-register-enums.h
===
--- source/Plugins/Process/Utility/lldb-x86-register-enums.h
+++ source/Plugins/Process/Utility/lldb-x86-register-enums.h
@@ -104,6 +104,18 @@
   lldb_ymm7_i386,
   k_last_avx_i386 = lldb_ymm7_i386,
 
+  k_first_mpxr_i386,
+  lldb_bnd0_i386 = k_first_mpxr_i386,
+  lldb_bnd1_i386,
+  lldb_bnd2_i386,
+  lldb_bnd3_i386,
+  k_last_mpxr = lldb_bnd3_i386,
+
+  k_first_mpxc_i386,
+  lldb_bndcfgu_i386 = k_first_mpxc_i386,
+  lldb_bndstatus_i386,
+  k_last_mpxc_i386 = lldb_bndstatus_i386,
+
   lldb_dr0_i386,
   lldb_dr1_i386,
   lldb_dr2_i386,
@@ -117,9 +129,11 @@
   k_num_gpr_registers_i386 = k_last_gpr_i386 - k_first_gpr_i386 + 1,
   k_num_fpr_registers_i386 = k_last_fpr_i386 - k_first_fpr_i386 + 1,
   k_num_avx_registers_i386 = k_last_avx_i386 - k_first_avx_i386 + 1,
+  k_num_mpx_registers_i386 = k_last_mpxc_i386 - k_first_mpxr_i386 + 1,
   k_num_user_registers_i386 = k_num_gpr_registers_i386 +
   k_num_fpr_registers_i386 +
-  k_num_avx_registers_i386,
+  k_num_avx_registers_i386 +
+  k_num_mpx_registers_i386,
 };
 
 //---
@@ -273,6 +287,18 @@
   lldb_ymm15_x86_64,
   k_last_avx_x86_64 = lldb_ymm15_x86_64,
 
+  k_first_mpxr_x86_64,
+  lldb_bnd0_x86_64 = k_first_mpxr_x86_64,
+  lldb_bnd1_x86_64,
+

Re: [Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-08 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL280942: Fix for rL280668, Intel(R) Memory Protection 
Extensions (Intel(R) MPX) support. (authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D24255?vs=70695=70698#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24255

Files:
  lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py
  lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/a.cpp
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
  lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/main.cpp
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp
  lldb/trunk/source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp
  lldb/trunk/source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterContext_x86.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_x86_64.h
  lldb/trunk/source/Plugins/Process/Utility/lldb-x86-register-enums.h
  
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
===
--- lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -1592,6 +1592,9 @@
   case eFormatVectorOfFloat32:
 response.PutCString("format:vector-float32;");
 break;
+  case eFormatVectorOfUInt64:
+response.PutCString("format:vector-uint64;");
+break;
   case eFormatVectorOfUInt128:
 response.PutCString("format:vector-uint128;");
 break;
Index: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -547,6 +547,7 @@
   .Case("vector-sint32", eFormatVectorOfSInt32)
   .Case("vector-uint32", eFormatVectorOfUInt32)
   .Case("vector-float32", eFormatVectorOfFloat32)
+  .Case("vector-uint64", eFormatVectorOfUInt64)
   .Case("vector-uint128", eFormatVectorOfUInt128)
   .Default(eFormatInvalid);
 }
@@ -4178,6 +4179,8 @@
   reg_info.format = eFormatVectorOfUInt32;
 else if (value == "vector-float32")
   reg_info.format = eFormatVectorOfFloat32;
+else if (value == "vector-uint64")
+  reg_info.format = eFormatVectorOfUInt64;
 else if (value == "vector-uint128")
   reg_info.format = eFormatVectorOfUInt128;
   } else if (name == "group_id") {
Index: lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
===
--- lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
+++ lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
@@ -34,6 +34,16 @@
LLVM_EXTENSION offsetof(FXSAVE, xmm[7]) + sizeof(XMMReg) +  \
(32 * reg_index))
 
+#define BNDR_OFFSET(reg_index) \
+(LLVM_EXTENSION offsetof(UserArea, i387) + \
+ LLVM_EXTENSION offsetof(FPR, xstate) + \
+ LLVM_EXTENSION offsetof(XSAVE, mpxr[reg_index]))
+
+#define BNDC_OFFSET(reg_index) \
+(LLVM_EXTENSION offsetof(UserArea, i387) + \
+ LLVM_EXTENSION offsetof(FPR, xstate) + \
+ LLVM_EXTENSION offsetof(XSAVE, mpxc[reg_index]))
+
 // Number of bytes needed to represent a FPR.
 #if !defined(FPR_SIZE)
 #define FPR_SIZE(reg) sizeof(((FXSAVE *)NULL)->reg)
@@ -48,6 +58,10 @@
 // Number of bytes needed to represent a YMM register.
 #define YMM_SIZE sizeof(YMMReg)
 
+// Number of bytes needed to represent MPX registers.
+#define BNDR_SIZE sizeof(MPXReg)
+#define BNDC_SIZE

Re: [Lldb-commits] [PATCH] D24255: Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

2016-09-07 Thread Valentina Giusti via lldb-commits

valentinagiusti marked an inline comment as done.


Comment at: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile:6
@@ +5,3 @@
+ifeq "$(ARCH)" "i386"
+   CFLAGS_EXTRAS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd -m32
+   LD_EXTRAS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd -m32

You are right, if I use CFLAGS_EXTRAS I don't have to check for the arch or use 
LD_EXTRAS. I wish I knew this from the beginning...


https://reviews.llvm.org/D24255



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Re: [Lldb-commits] [PATCH] D24559: Use Intel CPU flags to determine target supported features.

2016-09-14 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 71371.
valentinagiusti added a comment.

moved header to the bottom and moved enum into header file


https://reviews.llvm.org/D24559

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  source/Plugins/Process/Utility/RegisterContext_x86.h

Index: source/Plugins/Process/Utility/RegisterContext_x86.h
===
--- source/Plugins/Process/Utility/RegisterContext_x86.h
+++ source/Plugins/Process/Utility/RegisterContext_x86.h
@@ -277,7 +277,9 @@
   uint32_t mxcsrmask; // MXCSR Mask
   MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
   XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes
-  uint32_t padding[24];
+  uint8_t padding1[48];
+  uint64_t xcr0;
+  uint8_t padding2[40];
 };
 
 //---
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
@@ -77,7 +77,8 @@
 
 private:
   // Private member types.
-  enum FPRType { eFPRTypeNotValid = 0, eFPRTypeFXSAVE, eFPRTypeXSAVE };
+  enum XStateType { eXStateTypeNotValid = 0, eXStateTypeFXSAVE, eXStateTypeXSAVE };
+  enum RegSet { gpr, fpu, avx, mpx };
 
   // Info about register ranges.
   struct RegInfo {
@@ -106,26 +107,30 @@
   };
 
   // Private member variables.
-  mutable FPRType m_fpr_type;
-  FPR m_fpr;
+  mutable XStateType m_xstate_type;
+  FPR m_fpr; // Extended States Area, named FPR for historical reasons.
   IOVEC m_iovec;
   YMM m_ymm_set;
   MPX m_mpx_set;
   RegInfo m_reg_info;
   uint64_t m_gpr_x86_64[k_num_gpr_registers_x86_64];
   uint32_t m_fctrl_offset_in_userarea;
 
   // Private member methods.
+  bool HasFXSAVE() const;
+
+  bool HasXSAVE() const;
+
+  bool IsCPUFeatureAvailable(RegSet feature_code) const;
+
   bool IsRegisterSetAvailable(uint32_t set_index) const;
 
   bool IsGPR(uint32_t reg_index) const;
 
-  FPRType GetFPRType() const;
+  XStateType GetXStateType() const;
 
   bool IsFPR(uint32_t reg_index) const;
 
-  bool IsFPR(uint32_t reg_index, FPRType fpr_type) const;
-
   bool CopyXSTATEtoYMM(uint32_t reg_index, lldb::ByteOrder byte_order);
 
   bool CopyYMMtoXSTATE(uint32_t reg, lldb::ByteOrder byte_order);
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
@@ -20,6 +20,8 @@
 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
 
+#include 
+
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
@@ -218,6 +220,23 @@
 #define NT_PRXFPREG 0x46e62b7f
 #endif
 
+// 
+// Required MPX define.
+// 
+
+// Support MPX extensions also if compiled with compiler without MPX support.
+#ifndef bit_MPX
+#define bit_MPX 0x4000
+#endif
+
+// 
+// XCR0 extended register sets masks.
+// 
+#define mask_XSTATE_AVX (1ULL << 2)
+#define mask_XSTATE_BNDREGS (1ULL << 3)
+#define mask_XSTATE_BNDCFG (1ULL << 4)
+#define mask_XSTATE_MPX (mask_XSTATE_BNDREGS | mask_XSTATE_BNDCFG)
+
 NativeRegisterContextLinux *
 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
 const ArchSpec _arch, NativeThreadProtocol _thread,
@@ -249,7 +268,7 @@
 uint32_t concrete_frame_idx)
 : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
  CreateRegisterInfoInterface(target_arch)),
-  m_fpr_type(eFPRTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
+  m_xstate_type(eXStateTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
   m_mpx_set(), m_reg_info(), m_gpr_x86_64() {
   // Set up data about ranges of valid registers.
   switch (target_arch.GetMachine()) {
@@ -379,7 +398,7 @@
 return error;
   }
 
-  if (IsFPR(reg, GetFPRType())) {
+  if (IsFPR(reg) || IsAVX(reg) || IsMPX(reg)) {
 error = ReadFPR();
 if (error.Fail())
   return error;
@@ -428,25 +447,25 @@
 reg_info->byte_size, byte_order);
   if (reg >= m_reg_info.first_ymm && reg <= m_reg_info.last_ymm) {
 // Concatenate ymm using the register halves in xmm.bytes and ymmh.bytes
-if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoYMM(reg, byte_order))
+if

Re: [Lldb-commits] [PATCH] D24559: Use Intel CPU flags to determine target supported features.

2016-09-14 Thread Valentina Giusti via lldb-commits

valentinagiusti marked 2 inline comments as done.
valentinagiusti added a comment.

This fixes the fact that there is no proper check that the kernel or the 
hardware are actually supporting either AVX or MPX. Before this patch, the code 
only relied on a "hack" that checks if it's possible to do a ptrace to retrieve 
the XSAVE or FXSAVE areas: the assumption was that if XSAVE is there, then 
there must be also AVX and MPX, which obviously is not the correct thing to do.
The 'cpuid' calls (wrappers for the CPUID instruction) get the info directly 
from the hardware, and then the ptrace call is made to actually get either 
FXSAVE or XSAVE. If XSAVE is there, then 'cpuid' is used again to check the 
hardware for AVX and MPX, and then if this step is also successful, the XSAVE 
memory region is further checked to verify that the kernel is properly handling 
these features.
Basically it's both a refactoring and a fix, and it doesn't require a dedicated 
test: the fact that the current register tests succeed is proof enough.


https://reviews.llvm.org/D24559



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Re: [Lldb-commits] [PATCH] D24559: Use Intel CPU flags to determine target supported features.

2016-09-14 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL281507: Use Intel CPU flags to determine target supported 
features. (authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D24559?vs=71371=71390#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24559

Files:
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterContext_x86.h

Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
@@ -77,7 +77,8 @@
 
 private:
   // Private member types.
-  enum FPRType { eFPRTypeNotValid = 0, eFPRTypeFXSAVE, eFPRTypeXSAVE };
+  enum XStateType { eXStateTypeNotValid = 0, eXStateTypeFXSAVE, eXStateTypeXSAVE };
+  enum RegSet { gpr, fpu, avx, mpx };
 
   // Info about register ranges.
   struct RegInfo {
@@ -106,26 +107,30 @@
   };
 
   // Private member variables.
-  mutable FPRType m_fpr_type;
-  FPR m_fpr;
+  mutable XStateType m_xstate_type;
+  FPR m_fpr; // Extended States Area, named FPR for historical reasons.
   IOVEC m_iovec;
   YMM m_ymm_set;
   MPX m_mpx_set;
   RegInfo m_reg_info;
   uint64_t m_gpr_x86_64[k_num_gpr_registers_x86_64];
   uint32_t m_fctrl_offset_in_userarea;
 
   // Private member methods.
+  bool HasFXSAVE() const;
+
+  bool HasXSAVE() const;
+
+  bool IsCPUFeatureAvailable(RegSet feature_code) const;
+
   bool IsRegisterSetAvailable(uint32_t set_index) const;
 
   bool IsGPR(uint32_t reg_index) const;
 
-  FPRType GetFPRType() const;
+  XStateType GetXStateType() const;
 
   bool IsFPR(uint32_t reg_index) const;
 
-  bool IsFPR(uint32_t reg_index, FPRType fpr_type) const;
-
   bool CopyXSTATEtoYMM(uint32_t reg_index, lldb::ByteOrder byte_order);
 
   bool CopyYMMtoXSTATE(uint32_t reg, lldb::ByteOrder byte_order);
Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
@@ -20,6 +20,8 @@
 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
 
+#include 
+
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
@@ -218,6 +220,23 @@
 #define NT_PRXFPREG 0x46e62b7f
 #endif
 
+// 
+// Required MPX define.
+// 
+
+// Support MPX extensions also if compiled with compiler without MPX support.
+#ifndef bit_MPX
+#define bit_MPX 0x4000
+#endif
+
+// 
+// XCR0 extended register sets masks.
+// 
+#define mask_XSTATE_AVX (1ULL << 2)
+#define mask_XSTATE_BNDREGS (1ULL << 3)
+#define mask_XSTATE_BNDCFG (1ULL << 4)
+#define mask_XSTATE_MPX (mask_XSTATE_BNDREGS | mask_XSTATE_BNDCFG)
+
 NativeRegisterContextLinux *
 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
 const ArchSpec _arch, NativeThreadProtocol _thread,
@@ -249,7 +268,7 @@
 uint32_t concrete_frame_idx)
 : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
  CreateRegisterInfoInterface(target_arch)),
-  m_fpr_type(eFPRTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
+  m_xstate_type(eXStateTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
   m_mpx_set(), m_reg_info(), m_gpr_x86_64() {
   // Set up data about ranges of valid registers.
   switch (target_arch.GetMachine()) {
@@ -379,7 +398,7 @@
 return error;
   }
 
-  if (IsFPR(reg, GetFPRType())) {
+  if (IsFPR(reg) || IsAVX(reg) || IsMPX(reg)) {
 error = ReadFPR();
 if (error.Fail())
   return error;
@@ -428,25 +447,25 @@
 reg_info->byte_size, byte_order);
   if (reg >= m_reg_info.first_ymm && reg <= m_reg_info.last_ymm) {
 // Concatenate ymm using the register halves in xmm.bytes and ymmh.bytes
-if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoYMM(reg, byte_order))
+if (CopyXSTATEtoYMM(reg, byte_order))
   reg_value.SetBytes(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes,
  reg_info->byte_size, byte_order);
 else {
   error.SetErrorString("failed to copy ymm register value");
   return error;
 }
   }
   if (reg >= m_reg_info.first_mpxr && reg <=

[Lldb-commits] [lldb] r281507 - Use Intel CPU flags to determine target supported features.

2016-09-14 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Wed Sep 14 12:27:48 2016
New Revision: 281507

URL: http://llvm.org/viewvc/llvm-project?rev=281507=rev
Log:
Use Intel CPU flags to determine target supported features.

Summary:
This patch uses the instruction CPUID to verify that FXSAVE, XSAVE, AVX
and MPX are supported by the target hardware. In case the HW supports XSAVE,
and at least one of the extended register sets, it further checks if the
target software has the kernel support for such features, by verifying that
their XSAVE part is correctly managed.

Differential Revision: https://reviews.llvm.org/D24559

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
lldb/trunk/source/Plugins/Process/Utility/RegisterContext_x86.h

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp?rev=281507=281506=281507=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp 
Wed Sep 14 12:27:48 2016
@@ -20,6 +20,8 @@
 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
 
+#include 
+
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
@@ -218,6 +220,23 @@ static const RegisterSet g_reg_sets_x86_
 #define NT_PRXFPREG 0x46e62b7f
 #endif
 
+// 
+// Required MPX define.
+// 
+
+// Support MPX extensions also if compiled with compiler without MPX support.
+#ifndef bit_MPX
+#define bit_MPX 0x4000
+#endif
+
+// 
+// XCR0 extended register sets masks.
+// 
+#define mask_XSTATE_AVX (1ULL << 2)
+#define mask_XSTATE_BNDREGS (1ULL << 3)
+#define mask_XSTATE_BNDCFG (1ULL << 4)
+#define mask_XSTATE_MPX (mask_XSTATE_BNDREGS | mask_XSTATE_BNDCFG)
+
 NativeRegisterContextLinux *
 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
 const ArchSpec _arch, NativeThreadProtocol _thread,
@@ -249,7 +268,7 @@ NativeRegisterContextLinux_x86_64::Nativ
 uint32_t concrete_frame_idx)
 : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
  CreateRegisterInfoInterface(target_arch)),
-  m_fpr_type(eFPRTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
+  m_xstate_type(eXStateTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
   m_mpx_set(), m_reg_info(), m_gpr_x86_64() {
   // Set up data about ranges of valid registers.
   switch (target_arch.GetMachine()) {
@@ -379,7 +398,7 @@ Error NativeRegisterContextLinux_x86_64:
 return error;
   }
 
-  if (IsFPR(reg, GetFPRType())) {
+  if (IsFPR(reg) || IsAVX(reg) || IsMPX(reg)) {
 error = ReadFPR();
 if (error.Fail())
   return error;
@@ -428,7 +447,7 @@ Error NativeRegisterContextLinux_x86_64:
 reg_info->byte_size, byte_order);
   if (reg >= m_reg_info.first_ymm && reg <= m_reg_info.last_ymm) {
 // Concatenate ymm using the register halves in xmm.bytes and 
ymmh.bytes
-if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoYMM(reg, byte_order))
+if (CopyXSTATEtoYMM(reg, byte_order))
   reg_value.SetBytes(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes,
  reg_info->byte_size, byte_order);
 else {
@@ -437,7 +456,7 @@ Error NativeRegisterContextLinux_x86_64:
 }
   }
   if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) {
-if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoMPX(reg))
+if (CopyXSTATEtoMPX(reg))
   reg_value.SetBytes(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes,
  reg_info->byte_size, byte_order);
 else {
@@ -446,7 +465,7 @@ Error NativeRegisterContextLinux_x86_64:
 }
   }
   if (reg >= m_reg_info.first_mpxc && reg <= m_reg_info.last_mpxc) {
-if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoMPX(reg))
+if (CopyXSTATEtoMPX(reg))
   reg_value.SetBytes(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes,
  reg_info->byte_size, byte_order);
 else {
@@ -517,7 +536,7 @@ Error NativeRegisterContextLinux_x86_64:
   if (IsGPR(reg_index))
 return WriteRegisterRaw(reg_index, reg_value);
 
-  if (IsFPR(reg_index, GetFPRType())) {
+  if (IsFPR(reg_index) || IsAVX(reg_index) || IsMPX(reg_index)) {
 if

[Lldb-commits] [lldb] r281528 - Use 'enum class' instead of 'enum' in NativeRegisterContextLinux_x86_x64.

2016-09-14 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Wed Sep 14 15:12:12 2016
New Revision: 281528

URL: http://llvm.org/viewvc/llvm-project?rev=281528=rev
Log:
Use 'enum class' instead of 'enum' in NativeRegisterContextLinux_x86_x64.

Reviewers: labath, clayborg, zturner

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D24578

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp?rev=281528=281527=281528=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp 
Wed Sep 14 15:12:12 2016
@@ -268,7 +268,7 @@ NativeRegisterContextLinux_x86_64::Nativ
 uint32_t concrete_frame_idx)
 : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
  CreateRegisterInfoInterface(target_arch)),
-  m_xstate_type(eXStateTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
+  m_xstate_type(XStateType::Invalid), m_fpr(), m_iovec(), m_ymm_set(),
   m_mpx_set(), m_reg_info(), m_gpr_x86_64() {
   // Set up data about ranges of valid registers.
   switch (target_arch.GetMachine()) {
@@ -664,12 +664,12 @@ Error NativeRegisterContextLinux_x86_64:
 
   ::memcpy(dst, _gpr_x86_64, GetRegisterInfoInterface().GetGPRSize());
   dst += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == eXStateTypeFXSAVE)
+  if (GetXStateType() == XStateType::FXSAVE)
 ::memcpy(dst, _fpr.xstate.fxsave, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == eXStateTypeXSAVE) {
+  else if (GetXStateType() == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
-if (IsCPUFeatureAvailable(avx)) {
+if (IsCPUFeatureAvailable(RegSet::avx)) {
   // Assemble the YMM register content from the register halves.
   for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm;
++reg) {
@@ -684,7 +684,7 @@ Error NativeRegisterContextLinux_x86_64:
   }
 }
 
-if (IsCPUFeatureAvailable(mpx)) {
+if (IsCPUFeatureAvailable(RegSet::mpx)) {
   for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc;
++reg) {
 if (!CopyXSTATEtoMPX(reg)) {
@@ -756,19 +756,19 @@ Error NativeRegisterContextLinux_x86_64:
 return error;
 
   src += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == eXStateTypeFXSAVE)
+  if (GetXStateType() == XStateType::FXSAVE)
 ::memcpy(_fpr.xstate.fxsave, src, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == eXStateTypeXSAVE)
+  else if (GetXStateType() == XStateType::XSAVE)
 ::memcpy(_fpr.xstate.xsave, src, sizeof(m_fpr.xstate.xsave));
 
   error = WriteFPR();
   if (error.Fail())
 return error;
 
-  if (GetXStateType() == eXStateTypeXSAVE) {
+  if (GetXStateType() == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
-if (IsCPUFeatureAvailable(avx)) {
+if (IsCPUFeatureAvailable(RegSet::avx)) {
   // Parse the YMM register content from the register halves.
   for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm;
++reg) {
@@ -783,7 +783,7 @@ Error NativeRegisterContextLinux_x86_64:
   }
 }
 
-if (IsCPUFeatureAvailable(mpx)) {
+if (IsCPUFeatureAvailable(RegSet::mpx)) {
   for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc;
++reg) {
 if (!CopyMPXtoXSTATE(reg)) {
@@ -808,7 +808,7 @@ bool NativeRegisterContextLinux_x86_64::
   if (!__get_cpuid(1, , , , ))
 return false;
   if ((rdx & bit_FXSAVE) == bit_FXSAVE) {
-m_xstate_type = eXStateTypeFXSAVE;
+m_xstate_type = XStateType::FXSAVE;
 if (const_cast(this)->ReadFPR().Fail())
   return false;
 return true;
@@ -823,7 +823,7 @@ bool NativeRegisterContextLinux_x86_64::
   if (!__get_cpuid(1, , , , ))
 return false;
   if ((rcx & bit_OSXSAVE) == bit_OSXSAVE) {
-m_xstate_type = eXStateTypeXSAVE;
+m_xstate_type = XStateType::XSAVE;
 if (const_cast(this)->ReadFPR().Fail())
   return false;
 return true;
@@ -841,10 +841,10 @@ bool NativeRegisterContextLinux_x86_64::
 
   __get_cpuid(1, , , , );
   switch (feature_code) {
-  case avx: // Check if CPU has AVX and if there is kernel support, by reading 
in the XCR0 area of XSAVE.
+  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by 
reading in the XCR0 area of XSAVE.
 if (((rcx & bit_AVX) != 0) && ((m_fpr.xstate.xsave.i387.xcr0 & 
mask_XSTATE_AVX) == mask_XSTATE_AVX))
   return true;
-  case mpx: // Check if CPU has MPX

Re: [Lldb-commits] [PATCH] D24578: Use 'enum class' instead of 'enum' in NativeRegisterContextLinux_x86_x64.

2016-09-14 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL281528: Use 'enum class' instead of 'enum' in 
NativeRegisterContextLinux_x86_x64. (authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D24578?vs=71412=71418#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24578

Files:
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h

Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
@@ -77,8 +77,8 @@
 
 private:
   // Private member types.
-  enum XStateType { eXStateTypeNotValid = 0, eXStateTypeFXSAVE, eXStateTypeXSAVE };
-  enum RegSet { gpr, fpu, avx, mpx };
+  enum class XStateType { Invalid, FXSAVE, XSAVE };
+  enum class RegSet { gpr, fpu, avx, mpx };
 
   // Info about register ranges.
   struct RegInfo {
Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
@@ -268,7 +268,7 @@
 uint32_t concrete_frame_idx)
 : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
  CreateRegisterInfoInterface(target_arch)),
-  m_xstate_type(eXStateTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
+  m_xstate_type(XStateType::Invalid), m_fpr(), m_iovec(), m_ymm_set(),
   m_mpx_set(), m_reg_info(), m_gpr_x86_64() {
   // Set up data about ranges of valid registers.
   switch (target_arch.GetMachine()) {
@@ -664,12 +664,12 @@
 
   ::memcpy(dst, _gpr_x86_64, GetRegisterInfoInterface().GetGPRSize());
   dst += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == eXStateTypeFXSAVE)
+  if (GetXStateType() == XStateType::FXSAVE)
 ::memcpy(dst, _fpr.xstate.fxsave, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == eXStateTypeXSAVE) {
+  else if (GetXStateType() == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
-if (IsCPUFeatureAvailable(avx)) {
+if (IsCPUFeatureAvailable(RegSet::avx)) {
   // Assemble the YMM register content from the register halves.
   for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm;
++reg) {
@@ -684,7 +684,7 @@
   }
 }
 
-if (IsCPUFeatureAvailable(mpx)) {
+if (IsCPUFeatureAvailable(RegSet::mpx)) {
   for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc;
++reg) {
 if (!CopyXSTATEtoMPX(reg)) {
@@ -756,19 +756,19 @@
 return error;
 
   src += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == eXStateTypeFXSAVE)
+  if (GetXStateType() == XStateType::FXSAVE)
 ::memcpy(_fpr.xstate.fxsave, src, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == eXStateTypeXSAVE)
+  else if (GetXStateType() == XStateType::XSAVE)
 ::memcpy(_fpr.xstate.xsave, src, sizeof(m_fpr.xstate.xsave));
 
   error = WriteFPR();
   if (error.Fail())
 return error;
 
-  if (GetXStateType() == eXStateTypeXSAVE) {
+  if (GetXStateType() == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
-if (IsCPUFeatureAvailable(avx)) {
+if (IsCPUFeatureAvailable(RegSet::avx)) {
   // Parse the YMM register content from the register halves.
   for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm;
++reg) {
@@ -783,7 +783,7 @@
   }
 }
 
-if (IsCPUFeatureAvailable(mpx)) {
+if (IsCPUFeatureAvailable(RegSet::mpx)) {
   for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc;
++reg) {
 if (!CopyMPXtoXSTATE(reg)) {
@@ -808,7 +808,7 @@
   if (!__get_cpuid(1, , , , ))
 return false;
   if ((rdx & bit_FXSAVE) == bit_FXSAVE) {
-m_xstate_type = eXStateTypeFXSAVE;
+m_xstate_type = XStateType::FXSAVE;
 if (const_cast(this)->ReadFPR().Fail())
   return false;
 return true;
@@ -823,7 +823,7 @@
   if (!__get_cpuid(1, , , , ))
 return false;
   if ((rcx & bit_OSXSAVE) == bit_OSXSAVE) {
-m_xstate_type = eXStateTypeXSAVE;
+m_xstate_type = XStateType::XSAVE;
 if (const_cast(this)->ReadFPR().Fail())
   return false;
 return true;
@@ -841,10 +841,10 @@
 
   __get_cpuid(1, , , , );
   switch (feature_code) {
-  case avx: // Check if CPU has AVX and if there is kernel support, by reading in the XCR0 area of XSAVE.
+  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by reading in the XCR0 area of XSAVE.
 if (((rcx & bit_AVX) != 0) &&

[Lldb-commits] [lldb] r283548 - Fix build failure on lldb-amd64-ninja-freebsd11 error caused by rL283474

2016-10-07 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Fri Oct  7 08:21:59 2016
New Revision: 283548

URL: http://llvm.org/viewvc/llvm-project?rev=283548=rev
Log:
Fix build failure on lldb-amd64-ninja-freebsd11 error caused by rL283474

Differential Revision: https://reviews.llvm.org/D25362

Modified:
lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h

Modified: lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp?rev=283548=283547=283548=diff
==
--- lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp (original)
+++ lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp Fri Oct  7 08:21:59 
2016
@@ -136,6 +136,24 @@ CrashReason GetCrashReasonForSIGBUS(cons
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+  if (reason == CrashReason::eBoundViolation) {
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+return str;
+  }
+#endif
+
+  return GetCrashReasonString(reason,
+  reinterpret_cast(info.si_addr));
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
@@ -143,20 +161,14 @@ std::string GetCrashReasonString(CrashRe
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";

Modified: lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h?rev=283548=283547=283548=diff
==
--- lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h (original)
+++ lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h Fri Oct  7 08:21:59 
2016
@@ -50,6 +50,7 @@ enum class CrashReason {
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D25362: Fix build failure on lldb-amd64-ninja-freebsd11 error caused by rL283474

2016-10-07 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL283548: Fix build failure on lldb-amd64-ninja-freebsd11 
error caused by rL283474 (authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D25362?vs=73909=73945#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25362

Files:
  lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
  lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h


Index: lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
===
--- lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
+++ lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,39 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+  if (reason == CrashReason::eBoundViolation) {
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+return str;
+  }
+#endif
+
+  return GetCrashReasonString(reason,
+  reinterpret_cast(info.si_addr));
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";
Index: lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h
===
--- lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h
+++ lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);


Index: lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
===
--- lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
+++ lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,39 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+  if (reason == CrashReason::eBoundViolation) {
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+return str;
+  }
+#endif
+
+  return GetCrashReasonString(reason,
+  reinterpret_cast(info.si_addr));
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";
Index: lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h
===
---

[Lldb-commits] [PATCH] D25329: Add bound violation handling for Intel(R) Memory Protection Extensions (Intel(R) MPX)

2016-10-06 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL283474: Add bound violation handling for Intel(R) Memory 
Protection Extensions (Intel… (authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D25329?vs=73823=73826#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25329

Files:
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeThreadLinux.cpp
  lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
  lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h

Index: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
===
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
@@ -0,0 +1,7 @@
+LEVEL = ../../../../make
+
+CXX_SOURCES := main.cpp
+
+CFLAGS_EXTRAS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd
+
+include $(LEVEL)/Makefile.rules
Index: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
===
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
@@ -0,0 +1,40 @@
+//===-- main.cpp *- C++ -*-===//
+
+ The LLVM Compiler Infrastructure
+
+ This file is distributed under the University of Illinois Open Source
+ License. See LICENSE.TXT for details.
+
+===--===//
+//
+
+#include 
+#include 
+
+static void violate_upper_bound(int *ptr, int size)
+{
+  int i;
+  i = *(ptr + size);
+}
+
+static void violate_lower_bound (int *ptr, int size)
+{
+  int i;
+  i = *(ptr - size);
+}
+
+int
+main(int argc, char const *argv[])
+{
+  unsigned int rax, rbx, rcx, rdx;
+  int array[5];
+
+  // This call returns 0 only if the CPU and the kernel support Intel(R) MPX.
+  if (prctl(PR_MPX_ENABLE_MANAGEMENT, 0, 0, 0, 0) != 0)
+return -1;
+
+  violate_upper_bound(array, 5);
+  violate_lower_bound(array, 5);
+
+  return 0;
+}
Index: lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
===
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
@@ -0,0 +1,57 @@
+"""
+Test the Intel(R) MPX bound violation signal.
+"""
+
+from __future__ import print_function
+
+
+import os
+import sys
+import time
+import re
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipIf(compiler="clang")
+@skipIf(oslist=no_match(['linux']))
+@skipIf(archs=no_match(['i386', 'x86_64']))
+@skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) #GCC version >= 5 supports Intel(R) MPX.
+def test_mpx_boundary_violation(self):
+"""Test Intel(R) MPX bound violation signal."""
+self.build()
+self.mpx_boundary_violation()
+
+def mpx_boundary_violation(self):
+exe = os.path.join(os.getcwd(), "a.out")
+self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+self.runCmd("run", RUN_SUCCEEDED)
+
+target = self.dbg.GetSelectedTarget()
+process = target.GetProcess()
+
+if (process.GetState() == lldb.eStateExited):
+self.skipTest("Intel(R) MPX is not supported.")
+
+if (process.GetState() == lldb.eStateStopped):
+self.expect("thread backtrace", STOPPED_DUE_TO_SIGNAL,
+substrs = ['stop reason = signal SIGSEGV: upper bound violation',
+   'fault address:', 'lower bound:', 'upper bound:'])
+
+self.runCmd("continue")
+
+if (process.GetState() == lldb.eStateStopped):
+

[Lldb-commits] [PATCH] D25329: Add bound violation handling for Intel(R) Memory Protection Extensions (Intel(R) MPX)

2016-10-06 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 73823.
valentinagiusti added a comment.

fixed usage of llvm:raw_string_ostream


https://reviews.llvm.org/D25329

Files:
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
  source/Plugins/Process/Linux/NativeThreadLinux.cpp
  source/Plugins/Process/POSIX/CrashReason.cpp
  source/Plugins/Process/POSIX/CrashReason.h

Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -22,6 +22,7 @@
   // SIGSEGV crash reasons.
   eInvalidAddress,
   ePrivilegedAddress,
+  eBoundViolation,
 
   // SIGILL crash reasons.
   eIllegalOpcode,
@@ -49,7 +50,7 @@
   eFloatSubscriptRange
 };
 
-std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
+std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
 
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -9,6 +9,8 @@
 
 #include "CrashReason.h"
 
+#include "llvm/Support/raw_ostream.h"
+
 #include 
 
 namespace {
@@ -19,6 +21,23 @@
   str += ss.str();
 }
 
+void AppendBounds(std::string , lldb::addr_t lower_bound,
+  lldb::addr_t upper_bound, lldb::addr_t addr) {
+  llvm::raw_string_ostream stream(str);
+  if ((unsigned long)addr < lower_bound)
+stream << ": lower bound violation ";
+  else
+stream << ": upper bound violation ";
+  stream << "(fault address: 0x";
+  stream.write_hex(addr);
+  stream << ", lower bound: 0x";
+  stream.write_hex(lower_bound);
+  stream << ", upper bound: 0x";
+  stream.write_hex(upper_bound);
+  stream << ")";
+  stream.flush();
+}
+
 CrashReason GetCrashReasonForSIGSEGV(const siginfo_t ) {
   assert(info.si_signo == SIGSEGV);
 
@@ -34,6 +53,11 @@
 return CrashReason::eInvalidAddress;
   case SEGV_ACCERR:
 return CrashReason::ePrivilegedAddress;
+#ifndef SEGV_BNDERR
+#define SEGV_BNDERR 3
+#endif
+  case SEGV_BNDERR:
+return CrashReason::eBoundViolation;
   }
 
   assert(false && "unexpected si_code for SIGSEGV");
@@ -109,7 +133,7 @@
 }
 }
 
-std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
   switch (reason) {
@@ -119,11 +143,20 @@
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, fault_addr);
+AppendFaultAddr(str, reinterpret_cast(info.si_addr));
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, fault_addr);
+AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+break;
+  case CrashReason::eBoundViolation:
+str = "signal SIGSEGV";
+// Make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#endif
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";
@@ -207,6 +240,9 @@
   case CrashReason::ePrivilegedAddress:
 str = "ePrivilegedAddress";
 break;
+  case CrashReason::eBoundViolation:
+str = "eBoundViolation";
+break;
 
   // SIGILL crash reasons.
   case CrashReason::eIllegalOpcode:
Index: source/Plugins/Process/Linux/NativeThreadLinux.cpp
===
--- source/Plugins/Process/Linux/NativeThreadLinux.cpp
+++ source/Plugins/Process/Linux/NativeThreadLinux.cpp
@@ -316,8 +316,7 @@
   (info->si_signo == SIGBUS && info->si_code == SI_KERNEL)
   ? CrashReason::eInvalidAddress
   : GetCrashReason(*info);
-  m_stop_description = GetCrashReasonString(
-  reason, reinterpret_cast(info->si_addr));
+  m_stop_description = GetCrashReasonString(reason, *info);
   break;
 }
   }
Index: packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
@@ -0,0 +1,40 @@
+//===-- main.cpp *- C++ -*-===//
+
+

[Lldb-commits] [lldb] r283474 - Add bound violation handling for Intel(R) Memory Protection Extensions (Intel(R) MPX)

2016-10-06 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Thu Oct  6 13:05:12 2016
New Revision: 283474

URL: http://llvm.org/viewvc/llvm-project?rev=283474=rev
Log:
Add bound violation handling for Intel(R) Memory Protection Extensions 
(Intel(R) MPX)

Summary:
This patch adds support for handling the SIGSEGV signal with 'si_code ==
SEGV_BNDERR', which is thrown when a bound violation is caught by the
Intel(R) MPX technology.

Differential Revision: https://reviews.llvm.org/D25329

Added:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
Modified:
lldb/trunk/source/Plugins/Process/Linux/NativeThreadLinux.cpp
lldb/trunk/source/Plugins/Process/POSIX/CrashReason.cpp
lldb/trunk/source/Plugins/Process/POSIX/CrashReason.h

Added: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile?rev=283474=auto
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
 (added)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
 Thu Oct  6 13:05:12 2016
@@ -0,0 +1,7 @@
+LEVEL = ../../../../make
+
+CXX_SOURCES := main.cpp
+
+CFLAGS_EXTRAS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd
+
+include $(LEVEL)/Makefile.rules

Added: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py?rev=283474=auto
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
 (added)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
 Thu Oct  6 13:05:12 2016
@@ -0,0 +1,57 @@
+"""
+Test the Intel(R) MPX bound violation signal.
+"""
+
+from __future__ import print_function
+
+
+import os
+import sys
+import time
+import re
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipIf(compiler="clang")
+@skipIf(oslist=no_match(['linux']))
+@skipIf(archs=no_match(['i386', 'x86_64']))
+@skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) 
#GCC version >= 5 supports Intel(R) MPX.
+def test_mpx_boundary_violation(self):
+"""Test Intel(R) MPX bound violation signal."""
+self.build()
+self.mpx_boundary_violation()
+
+def mpx_boundary_violation(self):
+exe = os.path.join(os.getcwd(), "a.out")
+self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+self.runCmd("run", RUN_SUCCEEDED)
+
+target = self.dbg.GetSelectedTarget()
+process = target.GetProcess()
+
+if (process.GetState() == lldb.eStateExited):
+self.skipTest("Intel(R) MPX is not supported.")
+
+if (process.GetState() == lldb.eStateStopped):
+self.expect("thread backtrace", STOPPED_DUE_TO_SIGNAL,
+substrs = ['stop reason = signal SIGSEGV: upper bound 
violation',
+   'fault address:', 'lower bound:', 'upper 
bound:'])
+
+self.runCmd("continue")
+
+if (process.GetState() == lldb.eStateStopped):
+self.expect("thread backtrace", STOPPED_DUE_TO_SIGNAL,
+substrs = ['stop reason = signal SIGSEGV: lower bound 
violation',
+   'fault address:', 'lower bound:', 'upper 
bound:'])
+
+self.runCmd("continue")
+self.assertTrue(process.GetState() == lldb.eStateExited,
+PROCESS_EXITED)

Added: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
URL:

[Lldb-commits] [PATCH] D25329: Add bound violation handling for Intel(R) Memory Protection Extensions (Intel(R) MPX)

2016-10-06 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 73811.
valentinagiusti added a comment.

used llvm:raw_string_ostream instead of std::stringstream


https://reviews.llvm.org/D25329

Files:
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
  source/Plugins/Process/Linux/NativeThreadLinux.cpp
  source/Plugins/Process/POSIX/CrashReason.cpp
  source/Plugins/Process/POSIX/CrashReason.h

Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -22,6 +22,7 @@
   // SIGSEGV crash reasons.
   eInvalidAddress,
   ePrivilegedAddress,
+  eBoundViolation,
 
   // SIGILL crash reasons.
   eIllegalOpcode,
@@ -49,7 +50,7 @@
   eFloatSubscriptRange
 };
 
-std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
+std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
 
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -9,6 +9,8 @@
 
 #include "CrashReason.h"
 
+#include "llvm/Support/raw_ostream.h"
+
 #include 
 
 namespace {
@@ -19,6 +21,23 @@
   str += ss.str();
 }
 
+void AppendBounds(std::string , lldb::addr_t lower_bound,
+  lldb::addr_t upper_bound, lldb::addr_t addr) {
+  llvm::raw_string_ostream stream(str);
+  if ((unsigned long)addr < lower_bound)
+stream << ": lower bound violation ";
+  else
+stream << ": upper bound violation ";
+  stream << "(fault address: 0x";
+  stream.write_hex(addr);
+  stream << ", lower bound: 0x";
+  stream.write_hex(lower_bound);
+  stream << ", upper bound: 0x";
+  stream.write_hex(upper_bound);
+  stream << ")";
+  str += stream.str();
+}
+
 CrashReason GetCrashReasonForSIGSEGV(const siginfo_t ) {
   assert(info.si_signo == SIGSEGV);
 
@@ -34,6 +53,11 @@
 return CrashReason::eInvalidAddress;
   case SEGV_ACCERR:
 return CrashReason::ePrivilegedAddress;
+#ifndef SEGV_BNDERR
+#define SEGV_BNDERR 3
+#endif
+  case SEGV_BNDERR:
+return CrashReason::eBoundViolation;
   }
 
   assert(false && "unexpected si_code for SIGSEGV");
@@ -109,7 +133,7 @@
 }
 }
 
-std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
   switch (reason) {
@@ -119,11 +143,20 @@
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, fault_addr);
+AppendFaultAddr(str, reinterpret_cast(info.si_addr));
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, fault_addr);
+AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+break;
+  case CrashReason::eBoundViolation:
+str = "signal SIGSEGV";
+// Make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#endif
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";
@@ -207,6 +240,9 @@
   case CrashReason::ePrivilegedAddress:
 str = "ePrivilegedAddress";
 break;
+  case CrashReason::eBoundViolation:
+str = "eBoundViolation";
+break;
 
   // SIGILL crash reasons.
   case CrashReason::eIllegalOpcode:
Index: source/Plugins/Process/Linux/NativeThreadLinux.cpp
===
--- source/Plugins/Process/Linux/NativeThreadLinux.cpp
+++ source/Plugins/Process/Linux/NativeThreadLinux.cpp
@@ -316,8 +316,7 @@
   (info->si_signo == SIGBUS && info->si_code == SI_KERNEL)
   ? CrashReason::eInvalidAddress
   : GetCrashReason(*info);
-  m_stop_description = GetCrashReasonString(
-  reason, reinterpret_cast(info->si_addr));
+  m_stop_description = GetCrashReasonString(reason, *info);
   break;
 }
   }
Index: packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
@@ -0,0 +1,40 @@
+//===-- main.cpp *- C++ -*-===//

[Lldb-commits] [PATCH] D25362: Fix build failure on lldb-amd64-ninja-freebsd11 error caused by rL283474

2016-10-07 Thread Valentina Giusti via lldb-commits

valentinagiusti created this revision.
valentinagiusti added reviewers: zturner, labath.
valentinagiusti added subscribers: lldb-commits, emaste.

https://reviews.llvm.org/D25362

Files:
  source/Plugins/Process/POSIX/CrashReason.cpp
  source/Plugins/Process/POSIX/CrashReason.h


Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,40 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+  if (reason == CrashReason::eBoundViolation) {
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#else
+str = GetCrashReasonString(reason, 
reinterpret_cast(info.si_addr));
+#endif
+  } else {
+str = GetCrashReasonString(reason, 
reinterpret_cast(info.si_addr));
+  }
+  return str;
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";


Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,40 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+  if (reason == CrashReason::eBoundViolation) {
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#else
+str = GetCrashReasonString(reason, reinterpret_cast(info.si_addr));
+#endif
+  } else {
+str = GetCrashReasonString(reason, reinterpret_cast(info.si_addr));
+  }
+  return str;
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
-

[Lldb-commits] [PATCH] D25362: Fix build failure on lldb-amd64-ninja-freebsd11 error caused by rL283474

2016-10-07 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 73907.
valentinagiusti added a comment.

applied clang-format


https://reviews.llvm.org/D25362

Files:
  source/Plugins/Process/POSIX/CrashReason.cpp
  source/Plugins/Process/POSIX/CrashReason.h


Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,42 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+  if (reason == CrashReason::eBoundViolation) {
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#else
+str = GetCrashReasonString(reason,
+   reinterpret_cast(info.si_addr));
+#endif
+  } else {
+str = GetCrashReasonString(reason,
+   reinterpret_cast(info.si_addr));
+  }
+  return str;
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";


Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,42 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+  if (reason == CrashReason::eBoundViolation) {
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#else
+str = GetCrashReasonString(reason,
+   reinterpret_cast(info.si_addr));
+#endif
+  } else {
+str = GetCrashReasonString(reason,
+   reinterpret_cast(info.si_addr));
+  }
+  return str;
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
-

[Lldb-commits] [PATCH] D25362: Fix build failure on lldb-amd64-ninja-freebsd11 error caused by rL283474

2016-10-07 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 73909.
valentinagiusti added a comment.

cleaned up code


https://reviews.llvm.org/D25362

Files:
  source/Plugins/Process/POSIX/CrashReason.cpp
  source/Plugins/Process/POSIX/CrashReason.h


Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,39 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+  if (reason == CrashReason::eBoundViolation) {
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+return str;
+  }
+#endif
+
+  return GetCrashReasonString(reason,
+  reinterpret_cast(info.si_addr));
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";


Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -50,6 +50,7 @@
   eFloatSubscriptRange
 };
 
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -136,27 +136,39 @@
 std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
+// make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+  if (reason == CrashReason::eBoundViolation) {
+str = "signal SIGSEGV";
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+return str;
+  }
+#endif
+
+  return GetCrashReasonString(reason,
+  reinterpret_cast(info.si_addr));
+}
+
+std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+  std::string str;
+
   switch (reason) {
   default:
 assert(false && "invalid CrashReason");
 break;
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+AppendFaultAddr(str, fault_addr);
 break;
   case CrashReason::eBoundViolation:
-str = "signal SIGSEGV";
-// Make sure that siginfo_t has the bound fields available.
-#if defined(si_lower) && defined(si_upper)
-AppendBounds(str, reinterpret_cast(info.si_lower),
- reinterpret_cast(info.si_upper),
- reinterpret_cast(info.si_addr));
-#endif
+str = "signal SIGSEGV: bound violation";
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";

[Lldb-commits] [PATCH] D25329: Add bound violation handling for Intel(R) Memory Protection Extensions (Intel(R) MPX)

2016-10-06 Thread Valentina Giusti via lldb-commits

valentinagiusti created this revision.
valentinagiusti added reviewers: zturner, labath.
valentinagiusti added subscribers: emaste, lldb-commits.

This patch adds support for handling the SIGSEGV signal with 'si_code ==
SEGV_BNDERR', which is thrown when a bound violation is caught by the
Intel(R) MPX technology.

Signed-off-by: Valentina Giusti 


https://reviews.llvm.org/D25329

Files:
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/Makefile
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/TestBoundViolation.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
  source/Plugins/Process/Linux/NativeThreadLinux.cpp
  source/Plugins/Process/POSIX/CrashReason.cpp
  source/Plugins/Process/POSIX/CrashReason.h

Index: source/Plugins/Process/POSIX/CrashReason.h
===
--- source/Plugins/Process/POSIX/CrashReason.h
+++ source/Plugins/Process/POSIX/CrashReason.h
@@ -22,6 +22,7 @@
   // SIGSEGV crash reasons.
   eInvalidAddress,
   ePrivilegedAddress,
+  eBoundViolation,
 
   // SIGILL crash reasons.
   eIllegalOpcode,
@@ -49,7 +50,7 @@
   eFloatSubscriptRange
 };
 
-std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr);
+std::string GetCrashReasonString(CrashReason reason, const siginfo_t );
 
 const char *CrashReasonAsString(CrashReason reason);
 
Index: source/Plugins/Process/POSIX/CrashReason.cpp
===
--- source/Plugins/Process/POSIX/CrashReason.cpp
+++ source/Plugins/Process/POSIX/CrashReason.cpp
@@ -19,6 +19,19 @@
   str += ss.str();
 }
 
+void AppendBounds(std::string , lldb::addr_t lower_bound,
+  lldb::addr_t upper_bound, lldb::addr_t addr) {
+  std::stringstream ss;
+  if ((unsigned long)addr < lower_bound)
+ss << ": lower bound violation ";
+  else
+ss << ": upper bound violation ";
+  ss << "(fault address: 0x" << std::hex << addr << ",";
+  ss << " lower bound: 0x" << std::hex << lower_bound << ",";
+  ss << " upper bound: 0x" << std::hex << upper_bound << ")";
+  str += ss.str();
+}
+
 CrashReason GetCrashReasonForSIGSEGV(const siginfo_t ) {
   assert(info.si_signo == SIGSEGV);
 
@@ -34,6 +47,11 @@
 return CrashReason::eInvalidAddress;
   case SEGV_ACCERR:
 return CrashReason::ePrivilegedAddress;
+#ifndef SEGV_BNDERR
+#define SEGV_BNDERR 3
+#endif
+  case SEGV_BNDERR:
+return CrashReason::eBoundViolation;
   }
 
   assert(false && "unexpected si_code for SIGSEGV");
@@ -109,7 +127,7 @@
 }
 }
 
-std::string GetCrashReasonString(CrashReason reason, lldb::addr_t fault_addr) {
+std::string GetCrashReasonString(CrashReason reason, const siginfo_t ) {
   std::string str;
 
   switch (reason) {
@@ -119,11 +137,20 @@
 
   case CrashReason::eInvalidAddress:
 str = "signal SIGSEGV: invalid address";
-AppendFaultAddr(str, fault_addr);
+AppendFaultAddr(str, reinterpret_cast(info.si_addr));
 break;
   case CrashReason::ePrivilegedAddress:
 str = "signal SIGSEGV: address access protected";
-AppendFaultAddr(str, fault_addr);
+AppendFaultAddr(str, reinterpret_cast(info.si_addr));
+break;
+  case CrashReason::eBoundViolation:
+str = "signal SIGSEGV";
+// Make sure that siginfo_t has the bound fields available.
+#if defined(si_lower) && defined(si_upper)
+AppendBounds(str, reinterpret_cast(info.si_lower),
+ reinterpret_cast(info.si_upper),
+ reinterpret_cast(info.si_addr));
+#endif
 break;
   case CrashReason::eIllegalOpcode:
 str = "signal SIGILL: illegal instruction";
@@ -207,6 +234,9 @@
   case CrashReason::ePrivilegedAddress:
 str = "ePrivilegedAddress";
 break;
+  case CrashReason::eBoundViolation:
+str = "eBoundViolation";
+break;
 
   // SIGILL crash reasons.
   case CrashReason::eIllegalOpcode:
Index: source/Plugins/Process/Linux/NativeThreadLinux.cpp
===
--- source/Plugins/Process/Linux/NativeThreadLinux.cpp
+++ source/Plugins/Process/Linux/NativeThreadLinux.cpp
@@ -316,8 +316,7 @@
   (info->si_signo == SIGBUS && info->si_code == SI_KERNEL)
   ? CrashReason::eInvalidAddress
   : GetCrashReason(*info);
-  m_stop_description = GetCrashReasonString(
-  reason, reinterpret_cast(info->si_addr));
+  m_stop_description = GetCrashReasonString(reason, *info);
   break;
 }
   }
Index: packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/mpx_bound_violation/main.cpp
@@ -0,0 +1,40 @@
+//===-- main.cpp

[Lldb-commits] [PATCH] D25328: Improve test for Intel(R) MPX registers.

2016-10-06 Thread Valentina Giusti via lldb-commits

valentinagiusti created this revision.
valentinagiusti added a reviewer: zturner.
valentinagiusti added a subscriber: lldb-commits.

Let the inferior test code determine if CPU and kernel support Intel(R)
MPX and cleanup test script.

Signed-off-by: Valentina Giusti 


https://reviews.llvm.org/D25328

Files:
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
  
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp


Index: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
===
--- 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
+++ 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
@@ -14,23 +14,11 @@
 int
 main(int argc, char const *argv[])
 {
-unsigned int rax, rbx, rcx, rdx;
-
-// Check if XSAVE is enabled.
-if (!__get_cpuid(1, , , , ) || (rcx & bit_OSXSAVE) != 
bit_OSXSAVE)
-return -1;
-
-// Check if MPX is enabled.
-if (__get_cpuid_max(0, NULL) > 7)
-{
-__cpuid_count(7, 0, rax, rbx, rcx, rdx);
-if ((rbx & bit_MPX) != bit_MPX)
-return -1;
-}
-else
+// This call returns 0 only if the CPU and the kernel support Intel(R) MPX.
+if (prctl(PR_MPX_ENABLE_MANAGEMENT, 0, 0, 0, 0) != 0)
 return -1;
 
-// Run MPX test code.
+// Run Intel(R) MPX test code.
 #if defined(__x86_64__)
 asm("mov $16, %rax\n\t"
 "mov $9, %rdx\n\t"
Index: 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
===
--- 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
+++ 
packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
@@ -1,5 +1,5 @@
 """
-Test the MPX registers.
+Test the Intel(R) MPX registers.
 """
 
 from __future__ import print_function
@@ -21,23 +21,18 @@
 
 def setUp(self):
 TestBase.setUp(self)
-self.has_teardown = False
-
-def tearDown(self):
-self.dbg.GetSelectedTarget().GetProcess().Destroy()
-TestBase.tearDown(self)
 
 @skipIf(compiler="clang")
-@skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) 
#GCC version >= 5 supports MPX.
 @skipIf(oslist=no_match(['linux']))
 @skipIf(archs=no_match(['i386', 'x86_64']))
+@skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) 
#GCC version >= 5 supports Intel(R) MPX.
 def test_mpx_registers_with_example_code(self):
-"""Test MPX registers with example code."""
+"""Test Intel(R) MPX registers with example code."""
 self.build()
 self.mpx_registers_with_example_code()
 
 def mpx_registers_with_example_code(self):
-"""Test MPX registers after running example code."""
+"""Test Intel(R) MPX registers after running example code."""
 self.line = line_number('main.cpp', '// Set a break point here.')
 
 exe = os.path.join(os.getcwd(), "a.out")
@@ -50,7 +45,7 @@
 process = target.GetProcess()
 
 if (process.GetState() == lldb.eStateExited):
-self.skipTest("HW doesn't support MPX feature.")
+self.skipTest("Intel(R) MPX is not supported.")
 else:
 self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
 substrs = ["stop reason = breakpoint 1."])


Index: packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
===
--- packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
+++ packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
@@ -14,23 +14,11 @@
 int
 main(int argc, char const *argv[])
 {
-unsigned int rax, rbx, rcx, rdx;
-
-// Check if XSAVE is enabled.
-if (!__get_cpuid(1, , , , ) || (rcx & bit_OSXSAVE) != bit_OSXSAVE)
-return -1;
-
-// Check if MPX is enabled.
-if (__get_cpuid_max(0, NULL) > 7)
-{
-__cpuid_count(7, 0, rax, rbx, rcx, rdx);
-if ((rbx & bit_MPX) != bit_MPX)
-return -1;
-}
-else
+// This call returns 0 only if the CPU and the kernel support Intel(R) MPX.
+if (prctl(PR_MPX_ENABLE_MANAGEMENT, 0, 0, 0, 0) != 0)
 return -1;
 
-// Run MPX test code.
+// Run Intel(R) MPX test code.
 #if defined(__x86_64__)
 asm("mov $16, %rax\n\t"
 "mov $9, %rdx\n\t"
Index: packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
===
---

[Lldb-commits] [lldb] r283461 - Improve test for Intel(R) MPX registers.

2016-10-06 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Thu Oct  6 10:49:10 2016
New Revision: 283461

URL: http://llvm.org/viewvc/llvm-project?rev=283461=rev
Log:
Improve test for Intel(R) MPX registers.

Summary:
Let the inferior test code determine if CPU and kernel support Intel(R)
MPX and cleanup test script.

Differential Revision: https://reviews.llvm.org/D25328

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py?rev=283461=283460=283461=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py
 Thu Oct  6 10:49:10 2016
@@ -1,5 +1,5 @@
 """
-Test the MPX registers.
+Test the Intel(R) MPX registers.
 """
 
 from __future__ import print_function
@@ -21,23 +21,18 @@ class RegisterCommandsTestCase(TestBase)
 
 def setUp(self):
 TestBase.setUp(self)
-self.has_teardown = False
-
-def tearDown(self):
-self.dbg.GetSelectedTarget().GetProcess().Destroy()
-TestBase.tearDown(self)
 
 @skipIf(compiler="clang")
-@skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) 
#GCC version >= 5 supports MPX.
 @skipIf(oslist=no_match(['linux']))
 @skipIf(archs=no_match(['i386', 'x86_64']))
+@skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) 
#GCC version >= 5 supports Intel(R) MPX.
 def test_mpx_registers_with_example_code(self):
-"""Test MPX registers with example code."""
+"""Test Intel(R) MPX registers with example code."""
 self.build()
 self.mpx_registers_with_example_code()
 
 def mpx_registers_with_example_code(self):
-"""Test MPX registers after running example code."""
+"""Test Intel(R) MPX registers after running example code."""
 self.line = line_number('main.cpp', '// Set a break point here.')
 
 exe = os.path.join(os.getcwd(), "a.out")
@@ -50,7 +45,7 @@ class RegisterCommandsTestCase(TestBase)
 process = target.GetProcess()
 
 if (process.GetState() == lldb.eStateExited):
-self.skipTest("HW doesn't support MPX feature.")
+self.skipTest("Intel(R) MPX is not supported.")
 else:
 self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
 substrs = ["stop reason = breakpoint 1."])

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp?rev=283461=283460=283461=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp
 Thu Oct  6 10:49:10 2016
@@ -14,23 +14,11 @@
 int
 main(int argc, char const *argv[])
 {
-unsigned int rax, rbx, rcx, rdx;
-
-// Check if XSAVE is enabled.
-if (!__get_cpuid(1, , , , ) || (rcx & bit_OSXSAVE) != 
bit_OSXSAVE)
-return -1;
-
-// Check if MPX is enabled.
-if (__get_cpuid_max(0, NULL) > 7)
-{
-__cpuid_count(7, 0, rax, rbx, rcx, rdx);
-if ((rbx & bit_MPX) != bit_MPX)
-return -1;
-}
-else
+// This call returns 0 only if the CPU and the kernel support Intel(R) MPX.
+if (prctl(PR_MPX_ENABLE_MANAGEMENT, 0, 0, 0, 0) != 0)
 return -1;
 
-// Run MPX test code.
+// Run Intel(R) MPX test code.
 #if defined(__x86_64__)
 asm("mov $16, %rax\n\t"
 "mov $9, %rdx\n\t"


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Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

valentinagiusti added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp:805
@@ -827,2 +804,3 @@
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;

valentinagiusti wrote:
> valentinagiusti wrote:
> > labath wrote:
> > > Then I think we should make that non-const as well. I mean, what's the 
> > > point of making it const if it does actually modify the state of the 
> > > object. Either that, or implement it in a way that does not modify the 
> > > state.
> > This involves changing the interface of NativeRegisterContextLinux just 
> > because NativeRegisterContextLinux_x86_64 has some specific needs that make 
> > GetRegisterCount use a non-const function. Also, I don't have all the 
> > hardware to test such a cross-platform change.
> Anyway I guess I can submit a follow-up patch with this, I will do it today ;)
So I have looked into this and actually in 
"source/Host/common/NativeRegisterContextRegisterInfo.cpp" the method 
GetRegisterCount() is implemented as const (and the pure virtual method is 
defined in "include/lldb/Host/common/NativeRegisterContext.h"). Unfortunately I 
don't see an easy way 1. to make the method non-const or 2. to avoid that 
GetRegisterSetCount() in NativeRegisterContextLinux_x86_64 needs to call a non 
const function: in order to get the register set count, it must know if the 
XState type is XSAVE, and in order to do that it must call ReadFPR(), or 
directly PtraceWrapper(), which are both non-const.
Could you please tell me what you think is best?
Imho, it would be better to first merge this patch and then clean up the 
NativeRegisterContext code, but I am open to suggestions.


https://reviews.llvm.org/D24764



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Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

valentinagiusti added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp:805
@@ -827,2 +804,3 @@
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;

valentinagiusti wrote:
> labath wrote:
> > Then I think we should make that non-const as well. I mean, what's the 
> > point of making it const if it does actually modify the state of the 
> > object. Either that, or implement it in a way that does not modify the 
> > state.
> This involves changing the interface of NativeRegisterContextLinux just 
> because NativeRegisterContextLinux_x86_64 has some specific needs that make 
> GetRegisterCount use a non-const function. Also, I don't have all the 
> hardware to test such a cross-platform change.
Anyway I guess I can submit a follow-up patch with this, I will do it today ;)


https://reviews.llvm.org/D24764



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Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-20 Thread Valentina Giusti via lldb-commits

valentinagiusti marked an inline comment as done.
valentinagiusti added a comment.

Thanks for your review! Please find my answers inline.



Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp:807
@@ -827,2 +806,3 @@
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;

labath wrote:
> I don't think the `const_cast` here is a good idea. How about we just make 
> this functions non-const ?
IsCPUFeatureAvailable must also be called by IsRegisterSetAvailable, which is 
also const...


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp:818
@@ +817,3 @@
+  return true;
+  case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by
+// reading in the XCR0 area of XSAVE.

zturner wrote:
> Is the AVX case supposed to fall-through to the mpx case?
good catch, it's not supposed to fall-through


https://reviews.llvm.org/D24764



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Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-20 Thread Valentina Giusti via lldb-commits

valentinagiusti updated this revision to Diff 71949.
valentinagiusti added a comment.

Removed unnecessary header, corrected switch-case.


https://reviews.llvm.org/D24764

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
@@ -117,18 +117,12 @@
   uint32_t m_fctrl_offset_in_userarea;
 
   // Private member methods.
-  bool HasFXSAVE() const;
-
-  bool HasXSAVE() const;
-
   bool IsCPUFeatureAvailable(RegSet feature_code) const;
 
   bool IsRegisterSetAvailable(uint32_t set_index) const;
 
   bool IsGPR(uint32_t reg_index) const;
 
-  XStateType GetXStateType() const;
-
   bool IsFPR(uint32_t reg_index) const;
 
   bool CopyXSTATEtoYMM(uint32_t reg_index, lldb::ByteOrder byte_order);
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
@@ -20,8 +20,6 @@
 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
 
-#include 
-
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
@@ -664,9 +662,9 @@
 
   ::memcpy(dst, _gpr_x86_64, GetRegisterInfoInterface().GetGPRSize());
   dst += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == XStateType::FXSAVE)
+  if (m_xstate_type == XStateType::FXSAVE)
 ::memcpy(dst, _fpr.xstate.fxsave, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == XStateType::XSAVE) {
+  else if (m_xstate_type == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
 if (IsCPUFeatureAvailable(RegSet::avx)) {
@@ -756,16 +754,16 @@
 return error;
 
   src += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == XStateType::FXSAVE)
+  if (m_xstate_type == XStateType::FXSAVE)
 ::memcpy(_fpr.xstate.fxsave, src, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == XStateType::XSAVE)
+  else if (m_xstate_type == XStateType::XSAVE)
 ::memcpy(_fpr.xstate.xsave, src, sizeof(m_fpr.xstate.xsave));
 
   error = WriteFPR();
   if (error.Fail())
 return error;
 
-  if (GetXStateType() == XStateType::XSAVE) {
+  if (m_xstate_type == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
 if (IsCPUFeatureAvailable(RegSet::avx)) {
@@ -801,58 +799,28 @@
   return error;
 }
 
-bool NativeRegisterContextLinux_x86_64::HasFXSAVE() const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if FXSAVE is enabled.
-  if (!__get_cpuid(1, , , , ))
-return false;
-  if ((rdx & bit_FXSAVE) == bit_FXSAVE) {
-m_xstate_type = XStateType::FXSAVE;
-if (const_cast(this)->ReadFPR().Fail())
-  return false;
-return true;
-  }
-  return false;
-}
-
-bool NativeRegisterContextLinux_x86_64::HasXSAVE() const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if XSAVE is enabled.
-  if (!__get_cpuid(1, , , , ))
-return false;
-  if ((rcx & bit_OSXSAVE) == bit_OSXSAVE) {
-m_xstate_type = XStateType::XSAVE;
+bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable(
+RegSet feature_code) const {
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;
-return true;
   }
-  return false;
-}
-
-bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable(
-RegSet feature_code) const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if XSAVE is enabled.
-  if (!HasXSAVE())
-return false;
-
-  __get_cpuid(1, , , , );
   switch (feature_code) {
-  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by reading in the XCR0 area of XSAVE.
-if (((rcx & bit_AVX) != 0) && ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_AVX) == mask_XSTATE_AVX))
+  case RegSet::gpr:
+  case RegSet::fpu:
+return true;
+  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by
+// reading in the XCR0 area of XSAVE.
+if ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_AVX) == mask_XSTATE_AVX)
   return true;
-  case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by reading in the XCR0 area of XSAVE.
-if (__get_cpuid_max(0, NULL) > 7) {
-  __cpuid_count(7, 0, rax, rbx, rcx, rdx);
-  if (((rbx & bit_MPX) != 0) && ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_MPX) == mask_XSTATE_MPX))
-return true;
-}
-  default:
-return false;
+ break;
+  case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by
+// reading in

[Lldb-commits] [lldb] r282072 - Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

Author: valentinagiusti
Date: Wed Sep 21 08:33:01 2016
New Revision: 282072

URL: http://llvm.org/viewvc/llvm-project?rev=282072=rev
Log:
Refactor NativeRegisterContextLinux_x86_64 code.

This patch refactors the way the XState type is checked and, in order to
simplify the code, it removes the usage of the 'cpuid' instruction: just 
checking
if the ptrace calls done throuhg ReadFPR is enough to verify both if there is
HW support and if there is kernel support. Also the XCR0 bits are enough to 
check if
there is both HW and kernel support for AVX and MPX.

Differential Revision: https://reviews.llvm.org/D24764

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp?rev=282072=282071=282072=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp 
Wed Sep 21 08:33:01 2016
@@ -20,8 +20,6 @@
 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
 
-#include 
-
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
@@ -664,9 +662,9 @@ Error NativeRegisterContextLinux_x86_64:
 
   ::memcpy(dst, _gpr_x86_64, GetRegisterInfoInterface().GetGPRSize());
   dst += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == XStateType::FXSAVE)
+  if (m_xstate_type == XStateType::FXSAVE)
 ::memcpy(dst, _fpr.xstate.fxsave, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == XStateType::XSAVE) {
+  else if (m_xstate_type == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
 if (IsCPUFeatureAvailable(RegSet::avx)) {
@@ -756,16 +754,16 @@ Error NativeRegisterContextLinux_x86_64:
 return error;
 
   src += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == XStateType::FXSAVE)
+  if (m_xstate_type == XStateType::FXSAVE)
 ::memcpy(_fpr.xstate.fxsave, src, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == XStateType::XSAVE)
+  else if (m_xstate_type == XStateType::XSAVE)
 ::memcpy(_fpr.xstate.xsave, src, sizeof(m_fpr.xstate.xsave));
 
   error = WriteFPR();
   if (error.Fail())
 return error;
 
-  if (GetXStateType() == XStateType::XSAVE) {
+  if (m_xstate_type == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
 if (IsCPUFeatureAvailable(RegSet::avx)) {
@@ -801,58 +799,28 @@ Error NativeRegisterContextLinux_x86_64:
   return error;
 }
 
-bool NativeRegisterContextLinux_x86_64::HasFXSAVE() const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if FXSAVE is enabled.
-  if (!__get_cpuid(1, , , , ))
-return false;
-  if ((rdx & bit_FXSAVE) == bit_FXSAVE) {
-m_xstate_type = XStateType::FXSAVE;
-if (const_cast(this)->ReadFPR().Fail())
-  return false;
-return true;
-  }
-  return false;
-}
-
-bool NativeRegisterContextLinux_x86_64::HasXSAVE() const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if XSAVE is enabled.
-  if (!__get_cpuid(1, , , , ))
-return false;
-  if ((rcx & bit_OSXSAVE) == bit_OSXSAVE) {
-m_xstate_type = XStateType::XSAVE;
+bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable(
+RegSet feature_code) const {
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;
-return true;
   }
-  return false;
-}
-
-bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable(
-RegSet feature_code) const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if XSAVE is enabled.
-  if (!HasXSAVE())
-return false;
-
-  __get_cpuid(1, , , , );
   switch (feature_code) {
-  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by 
reading in the XCR0 area of XSAVE.
-if (((rcx & bit_AVX) != 0) && ((m_fpr.xstate.xsave.i387.xcr0 & 
mask_XSTATE_AVX) == mask_XSTATE_AVX))
+  case RegSet::gpr:
+  case RegSet::fpu:
+return true;
+  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by
+// reading in the XCR0 area of XSAVE.
+if ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_AVX) == mask_XSTATE_AVX)
   return true;
-  case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by 
reading in the XCR0 area of XSAVE.
-if (__get_cpuid_max(0, NULL) > 7) {
-  __cpuid_count(7, 0, rax, rbx, rcx, rdx);
-  if (((rbx & bit_MPX) != 0) && ((m_fpr.xstate.xsave.i387.xcr0 & 
mask_XSTATE_MPX) == mask_XSTATE_MPX))
-return true;
-}
-  default:
-return false;
+ break;
+  case RegSet::mpx:

Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

valentinagiusti added a comment.

ok, I will keep it in mind for some further refactoring, thanks!


Repository:
  rL LLVM

https://reviews.llvm.org/D24764



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Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL282072: Refactor NativeRegisterContextLinux_x86_64 code. 
(authored by valentinagiusti).

Changed prior to commit:
  https://reviews.llvm.org/D24764?vs=71949=72036#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24764

Files:
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h

Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h
@@ -117,18 +117,12 @@
   uint32_t m_fctrl_offset_in_userarea;
 
   // Private member methods.
-  bool HasFXSAVE() const;
-
-  bool HasXSAVE() const;
-
   bool IsCPUFeatureAvailable(RegSet feature_code) const;
 
   bool IsRegisterSetAvailable(uint32_t set_index) const;
 
   bool IsGPR(uint32_t reg_index) const;
 
-  XStateType GetXStateType() const;
-
   bool IsFPR(uint32_t reg_index) const;
 
   bool CopyXSTATEtoYMM(uint32_t reg_index, lldb::ByteOrder byte_order);
Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
@@ -20,8 +20,6 @@
 #include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
 
-#include 
-
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
@@ -664,9 +662,9 @@
 
   ::memcpy(dst, _gpr_x86_64, GetRegisterInfoInterface().GetGPRSize());
   dst += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == XStateType::FXSAVE)
+  if (m_xstate_type == XStateType::FXSAVE)
 ::memcpy(dst, _fpr.xstate.fxsave, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == XStateType::XSAVE) {
+  else if (m_xstate_type == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
 if (IsCPUFeatureAvailable(RegSet::avx)) {
@@ -756,16 +754,16 @@
 return error;
 
   src += GetRegisterInfoInterface().GetGPRSize();
-  if (GetXStateType() == XStateType::FXSAVE)
+  if (m_xstate_type == XStateType::FXSAVE)
 ::memcpy(_fpr.xstate.fxsave, src, sizeof(m_fpr.xstate.fxsave));
-  else if (GetXStateType() == XStateType::XSAVE)
+  else if (m_xstate_type == XStateType::XSAVE)
 ::memcpy(_fpr.xstate.xsave, src, sizeof(m_fpr.xstate.xsave));
 
   error = WriteFPR();
   if (error.Fail())
 return error;
 
-  if (GetXStateType() == XStateType::XSAVE) {
+  if (m_xstate_type == XStateType::XSAVE) {
 lldb::ByteOrder byte_order = GetByteOrder();
 
 if (IsCPUFeatureAvailable(RegSet::avx)) {
@@ -801,58 +799,28 @@
   return error;
 }
 
-bool NativeRegisterContextLinux_x86_64::HasFXSAVE() const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if FXSAVE is enabled.
-  if (!__get_cpuid(1, , , , ))
-return false;
-  if ((rdx & bit_FXSAVE) == bit_FXSAVE) {
-m_xstate_type = XStateType::FXSAVE;
-if (const_cast(this)->ReadFPR().Fail())
-  return false;
-return true;
-  }
-  return false;
-}
-
-bool NativeRegisterContextLinux_x86_64::HasXSAVE() const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if XSAVE is enabled.
-  if (!__get_cpuid(1, , , , ))
-return false;
-  if ((rcx & bit_OSXSAVE) == bit_OSXSAVE) {
-m_xstate_type = XStateType::XSAVE;
+bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable(
+RegSet feature_code) const {
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;
-return true;
   }
-  return false;
-}
-
-bool NativeRegisterContextLinux_x86_64::IsCPUFeatureAvailable(
-RegSet feature_code) const {
-  unsigned int rax, rbx, rcx, rdx;
-
-  // Check if XSAVE is enabled.
-  if (!HasXSAVE())
-return false;
-
-  __get_cpuid(1, , , , );
   switch (feature_code) {
-  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by reading in the XCR0 area of XSAVE.
-if (((rcx & bit_AVX) != 0) && ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_AVX) == mask_XSTATE_AVX))
+  case RegSet::gpr:
+  case RegSet::fpu:
+return true;
+  case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by
+// reading in the XCR0 area of XSAVE.
+if ((m_fpr.xstate.xsave.i387.xcr0 & mask_XSTATE_AVX) == mask_XSTATE_AVX)
   return true;
-  case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by reading in the XCR0 area of XSAVE.
-if (__get_cpuid_max(0, NULL) > 7) {
-  __cpuid_count(7, 0, rax, rbx, rcx, rdx);
-  if (((rbx & bit_MPX) != 0) &&

Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

valentinagiusti added a comment.

Thechnically it's not correct that I am introducing this issue, because the old 
code already used a cast. It was done in the old and now not existing method 
"GetFPRType()", long before I introduced the MPX changes, and then I later 
moved it into HasXSave()/HasXSave() and now with this current refactoring patch 
I am moving it into IsCPUFeatureAvailable().


https://reviews.llvm.org/D24764



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Re: [Lldb-commits] [PATCH] D24764: Refactor NativeRegisterContextLinux_x86_64 code.

2016-09-21 Thread Valentina Giusti via lldb-commits

valentinagiusti added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp:805
@@ -827,2 +804,3 @@
+  if (m_xstate_type == XStateType::Invalid) {
 if (const_cast(this)->ReadFPR().Fail())
   return false;

labath wrote:
> Then I think we should make that non-const as well. I mean, what's the point 
> of making it const if it does actually modify the state of the object. Either 
> that, or implement it in a way that does not modify the state.
This involves changing the interface of NativeRegisterContextLinux just because 
NativeRegisterContextLinux_x86_64 has some specific needs that make 
GetRegisterCount use a non-const function. Also, I don't have all the hardware 
to test such a cross-platform change.


https://reviews.llvm.org/D24764



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