[llvm-branch-commits] [llvm] [profcheck] Update exclusion list to reflect fixes (PR #161943)

https://github.com/mtrofin ready_for_review https://github.com/llvm/llvm-project/pull/161943 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [PowerPC] Implement paddis (PR #161572)

https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/161572 >From 012b638031fb72d36525234115f9d7b87d8c98e3 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 30 Sep 2025 18:09:31 + Subject: [PATCH 1/5] [PowerPC] Implement paddis --- .../Target/PowerPC/AsmParser/PPC

[llvm-branch-commits] [llvm] release/21.x: [SPARC] Prevent meta instructions from being inserted into delay slots (#161111) (PR #161937)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/161937 Backport 2e1fab93467ec8c37a236ae6e059300ebaa0c986 Requested by: @brad0 >From 4cb5d998e732df6a28462288ffae97d3bd16 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Fri, 3 Oct 2025 19:25:08 +0700 Subject: [PATCH

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/161739 >From d1ddd8929f07ddbbcaea73ee99d788a6cd623110 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Wed, 1 Oct 2025 17:08:48 -0700 Subject: [PATCH] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitc

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Profile propagation for `indirectbr` (PR #161747)

https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/161747 >From a55a7e2f13a6606f9660fdacc3287f741d3f2ac2 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Thu, 2 Oct 2025 15:56:16 -0700 Subject: [PATCH] [SimplifyCFG][profcheck] Profile propagation for `indirectbr` --

[llvm-branch-commits] [llvm] release/21.x: [SPARC] Prevent meta instructions from being inserted into delay slots (#161111) (PR #161937)

llvmbot wrote: @llvm/pr-subscribers-backend-sparc Author: None (llvmbot) Changes Backport 2e1fab93467ec8c37a236ae6e059300ebaa0c986 Requested by: @brad0 --- Full diff: https://github.com/llvm/llvm-project/pull/161937.diff 2 Files Affected: - (modified) llvm/lib/Target/Sparc/DelaySlotFi

[llvm-branch-commits] [llvm] release/21.x: [SPARC] Prevent meta instructions from being inserted into delay slots (#161111) (PR #161937)

llvmbot wrote: @arsenm What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/161937 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listin

[llvm-branch-commits] [llvm] AMDGPU: Stop using the wavemask register class for SCC cross class copies (PR #161801)

arsenm wrote: > Are there any codegen changes? I don't think so. There could maybe be dag scheduling changes but I haven't found them https://github.com/llvm/llvm-project/pull/161801 ___ llvm-branch-commits mailing list [email protected]

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/161762 >From 53a6a5b9e3adcabc51e7eff0a21642f33859b946 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 3 Oct 2025 10:21:10 +0900 Subject: [PATCH] AMDGPU: Remove LDS_DIRECT_CLASS register class This is a singlet

[llvm-branch-commits] [clang] [llvm] [HLSL] GetDimensions methods for buffer resources (PR #161929)

https://github.com/hekota updated https://github.com/llvm/llvm-project/pull/161929 >From e50918910a0ce590228c6ecacd4ff2a578da6f58 Mon Sep 17 00:00:00 2001 From: Helena Kotas Date: Fri, 3 Oct 2025 17:33:19 -0700 Subject: [PATCH] [HLSL] GetDimensions methods for buffer resources Adds GetDimensio

[llvm-branch-commits] [llvm] [PowerPC] Implement paddis (PR #161572)

https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/161572 >From 012b638031fb72d36525234115f9d7b87d8c98e3 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 30 Sep 2025 18:09:31 + Subject: [PATCH 1/4] [PowerPC] Implement paddis --- .../Target/PowerPC/AsmParser/PPC

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (#155829) (PR #161766)

https://github.com/efriedma-quic approved this pull request. LGTM. This is an ABI fix which is important for the active SPARC developers. and it very obviously only affects SPARC targets. https://github.com/llvm/llvm-project/pull/161766 ___ llvm-bran

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/161739 >From 4979ae9e8486f51e124fe94471fec97ff93698c8 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Wed, 1 Oct 2025 17:08:48 -0700 Subject: [PATCH] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitc

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

bcardosolopes wrote: > I made a change tn the function: `performAddrSpaceCast` and I opted for > getting rid of the `LangAS` parameters for both source and destination Sounds legit, thanks! https://github.com/llvm/llvm-project/pull/161212 ___ llvm-b

[llvm-branch-commits] [llvm] [mlir] [MLIR][OpenMP][OMPIRBuilder] Improve shared memory checks (PR #161864)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder

[llvm-branch-commits] [llvm] [mlir] [MLIR][OpenMP][OMPIRBuilder] Improve shared memory checks (PR #161864)

llvmbot wrote: @llvm/pr-subscribers-offload Author: Sergio Afonso (skatrak) Changes This patch refines checks to decide whether to use device shared memory or regular stack allocations. In particular, it adds support for parallel regions residing on standalone target device functions. T

[llvm-branch-commits] [mlir] [MLIR][OpenMP] Refactor omp.target_allocmem to allow reuse, NFC (PR #161861)

skatrak wrote: PR stack: - #150922 - #150923 - #150924 - #150925 - #150926 - #150927 - #154752 - #161861 ◀️ - #161862 - #161863 - #161864 https://github.com/llvm/llvm-project/pull/161861 ___ llvm-branch-commits mailing list [email protected]

[llvm-branch-commits] [llvm] [mlir] [MLIR][OpenMP][OMPIRBuilder] Improve shared memory checks (PR #161864)

llvmbot wrote: @llvm/pr-subscribers-mlir-llvm Author: Sergio Afonso (skatrak) Changes This patch refines checks to decide whether to use device shared memory or regular stack allocations. In particular, it adds support for parallel regions residing on standalone target device functions.

[llvm-branch-commits] [llvm] [mlir] [MLIR][OpenMP][OMPIRBuilder] Improve shared memory checks (PR #161864)

llvmbot wrote: @llvm/pr-subscribers-mlir-openmp Author: Sergio Afonso (skatrak) Changes This patch refines checks to decide whether to use device shared memory or regular stack allocations. In particular, it adds support for parallel regions residing on standalone target device functions

[llvm-branch-commits] [llvm] [mlir] [MLIR][OpenMP][OMPIRBuilder] Improve shared memory checks (PR #161864)

https://github.com/skatrak created https://github.com/llvm/llvm-project/pull/161864 This patch refines checks to decide whether to use device shared memory or regular stack allocations. In particular, it adds support for parallel regions residing on standalone target device functions. The cha

[llvm-branch-commits] [llvm] [OpenMPOpt] Make parallel regions reachable from new DeviceRTL loop functions (PR #150927)

skatrak wrote: Moving to draft because I've noticed this doesn't currently work whenever there are different calls to new DeviceRTL loop functions. The state machine rewrite optimization of OpenMPOpt causes the following code to not run properly, whereas the same code without the `unused_probl

[llvm-branch-commits] [llvm] [mlir] [OpenMP][OMPIRBuilder] Support parallel in Generic kernels (PR #150926)

https://github.com/skatrak updated https://github.com/llvm/llvm-project/pull/150926 >From 9533653e89c7d9abf065a62c7c880cc012886be4 Mon Sep 17 00:00:00 2001 From: Sergio Afonso Date: Fri, 4 Jul 2025 16:32:03 +0100 Subject: [PATCH 1/2] [OpenMP][OMPIRBuilder] Support parallel in Generic kernels

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Profile propagation for `indirectbr` (PR #161747)

https://github.com/mtrofin edited https://github.com/llvm/llvm-project/pull/161747 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Profile propagation for `indirectbr` (PR #161747)

https://github.com/mtrofin ready_for_review https://github.com/llvm/llvm-project/pull/161747 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Profile propagation for `indirectbr` (PR #161747)

https://github.com/mtrofin edited https://github.com/llvm/llvm-project/pull/161747 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp ``

[llvm-branch-commits] [clang] [llvm] [openmp] [OpenMP] Taskgraph Clang 'record and replay' frontend support (PR #159774)

jtb20 wrote: This rebased version mentions partial taskgraph support in `clang/docs/ReleaseNotes.rst`. There's already a table entry regarding record-and-replay taskgraph support's in-progress status in `clang/docs/OpenMPSupport.rst`. https://github.com/llvm/llvm-project/pull/159774 _

[llvm-branch-commits] [llvm] CodeGen: Stop checking for physregs in constrainRegClass (PR #161795)

@@ -83,8 +83,6 @@ constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { - if (Reg.isPhysical()) arsenm wrote: It wi

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/161762 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

llvmbot wrote: @llvm/pr-subscribers-backend-x86 Author: None (llvmbot) Changes Backport 3c5c82d09c691a83fec5d09df2f6a308a789ead1 Requested by: @mstorsjo --- Full diff: https://github.com/llvm/llvm-project/pull/161836.diff 1 Files Affected: - (modified) clang/lib/Headers/avx10_2bf16int

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/161836 Backport 3c5c82d09c691a83fec5d09df2f6a308a789ead1 Requested by: @mstorsjo >From 290ad0a527af6e28eb53782226af41b682be721c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Fri, 3 Oct 2025 1

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

https://github.com/phoebewang approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/161836 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

llvmbot wrote: @RKSimon What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/161836 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listi

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

https://github.com/easyonaadit created https://github.com/llvm/llvm-project/pull/161816 None >From 6cd1510d1ca606a5d08e4bbdb3c77d17d93447d8 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Tue, 30 Sep 2025 11:37:42 +0530 Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics --- cl

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

llvmbot wrote: @llvm/pr-subscribers-clang Author: None (llvmbot) Changes Backport 3c5c82d09c691a83fec5d09df2f6a308a789ead1 Requested by: @mstorsjo --- Full diff: https://github.com/llvm/llvm-project/pull/161836.diff 1 Files Affected: - (modified) clang/lib/Headers/avx10_2bf16intrin.h

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/161836 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/21.x: [clang] [Headers] Don't use unreserved names in avx10_2bf16intrin.h (#161824) (PR #161836)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/161836 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Stop trying to constrain register class of post-RA-pseudos (PR #161792)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes This is trying to constrain the register class of a physical register, which makes no sense. --- Full diff: https://github.com/llvm/llvm-project/pull/161792.diff 1 Files Affected: - (modified) ll

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161815 >From 2e8024c70b755a3b309ec8b2965333e61a91af69 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Mon, 29 Sep 2025 18:58:10 +0530 Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 2 Supported

[llvm-branch-commits] [llvm] AMDGPU: Stop using the wavemask register class for SCC cross class copies (PR #161801)

@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const { const TargetRegisterClass * SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { - if (RC == &AMDGPU::SCC_CLASSRegClass) -return getWaveMaskRegClass(); - return RC; +

[llvm-branch-commits] [llvm] AMDGPU: Stop using the wavemask register class for SCC cross class copies (PR #161801)

@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const { const TargetRegisterClass * SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { - if (RC == &AMDGPU::SCC_CLASSRegClass) -return getWaveMaskRegClass(); - return RC; +

[llvm-branch-commits] [llvm] CodeGen: Stop checking for physregs in constrainRegClass (PR #161795)

https://github.com/cdevadas approved this pull request. https://github.com/llvm/llvm-project/pull/161795 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

arsenm wrote: > Same here: drop mir tests which test what tablegen has generated. Same, the MIR tests are completely unrelated and not related to this pr. We cannot simply drop these https://github.com/llvm/llvm-project/pull/161762 ___ llvm-branch-c

[llvm-branch-commits] [llvm] AMDGPU: Fix constrain register logic for physregs (PR #161794)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161794?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Fix trying to constrain physical registers in spill handling (PR #161793)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161793?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

easyonaadit wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161816?utm_source=stack-comment-downstack-mergeability-warni

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

https://github.com/zmodem approved this pull request. lgtm https://github.com/llvm/llvm-project/pull/156840 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161816 >From feaf31184bc20619448c87f3c38a1bbc3ec21719 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Tue, 30 Sep 2025 11:37:42 +0530 Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics --- clang/in

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161815 >From 2e8024c70b755a3b309ec8b2965333e61a91af69 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Mon, 29 Sep 2025 18:58:10 +0530 Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 2 Supported

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161816 >From feaf31184bc20619448c87f3c38a1bbc3ec21719 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Tue, 30 Sep 2025 11:37:42 +0530 Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics --- clang/in

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

easyonaadit wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161815?utm_source=stack-comment-downstack-mergeability-warni

[llvm-branch-commits] [llvm] CodeGen: Stop checking for physregs in constrainRegClass (PR #161795)

@@ -83,8 +83,6 @@ constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { - if (Reg.isPhysical()) cdevadas wrote: Wha

[llvm-branch-commits] [llvm] AMDGPU: Fix trying to constrain physical registers in spill handling (PR #161793)

https://github.com/cdevadas approved this pull request. https://github.com/llvm/llvm-project/pull/161793 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

https://github.com/zmodem approved this pull request. lgtm https://github.com/llvm/llvm-project/pull/156839 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)

@@ -1353,6 +1354,92 @@ void CodeGenFunction::EmitAllocToken(llvm::CallBase *CB, QualType AllocType) { CB->setMetadata(llvm::LLVMContext::MD_alloc_token, MDN); } +/// Infer type from a simple sizeof expression. +static QualType inferTypeFromSizeofExpr(const Expr *E) { + con

[llvm-branch-commits] [llvm] AMDGPU: Stop using the wavemask register class for SCC cross class copies (PR #161801)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make sense. --- Full diff: https://github.com/llvm/llvm-project/pull/161801.diff 1 Files Affected: - (modified) llvm/lib/Target/AM

[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)

@@ -10,7 +10,7 @@ typedef __typeof(sizeof(int)) size_t; void *malloc(size_t size); // CHECK-LABEL: @test_malloc( -// CHECK: call{{.*}} ptr @__alloc_token_malloc(i64 noundef 4, i64 0) +// CHECK: call{{.*}} ptr @__alloc_token_malloc(i64 noundef 4, i64 2689373973731826898){{.*}}

[llvm-branch-commits] [llvm] AMDGPU: Stop using the wavemask register class for SCC cross class copies (PR #161801)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161801 SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make sense. >From 04a448a4f8da85d879ffb61618a824bd2ab5a62a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 3 Oct 2025 15:53:00 +0900 Subj