@@ -478,146 +890,232 @@ entry:
}
define i1 @bcmp_eq_zero(ptr %s1, ptr %s2) nounwind {
-; LA32-LABEL: bcmp_eq_zero:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT:addi.w $sp, $sp, -16
-; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:ori $a2, $zero, 1
@@ -478,146 +890,232 @@ entry:
}
define i1 @bcmp_eq_zero(ptr %s1, ptr %s2) nounwind {
-; LA32-LABEL: bcmp_eq_zero:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT:addi.w $sp, $sp, -16
-; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:ori $a2, $zero, 1
https://github.com/easyonaadit updated
https://github.com/llvm/llvm-project/pull/161815
>From ba56c4728ccc10087770ec2d59576e1d2f529516 Mon Sep 17 00:00:00 2001
From: Aaditya
Date: Mon, 29 Sep 2025 18:58:10 +0530
Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 2
Supported
https://github.com/easyonaadit updated
https://github.com/llvm/llvm-project/pull/161815
>From ba56c4728ccc10087770ec2d59576e1d2f529516 Mon Sep 17 00:00:00 2001
From: Aaditya
Date: Mon, 29 Sep 2025 18:58:10 +0530
Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 2
Supported
https://github.com/easyonaadit updated
https://github.com/llvm/llvm-project/pull/161816
>From 1e3a049f679683944d9aec18b710deec8f798bec Mon Sep 17 00:00:00 2001
From: Aaditya
Date: Tue, 30 Sep 2025 11:37:42 +0530
Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics
---
clang/in
https://github.com/easyonaadit updated
https://github.com/llvm/llvm-project/pull/161816
>From 1e3a049f679683944d9aec18b710deec8f798bec Mon Sep 17 00:00:00 2001
From: Aaditya
Date: Tue, 30 Sep 2025 11:37:42 +0530
Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics
---
clang/in
@@ -5330,11 +5330,13 @@ static uint32_t
getIdentityValueFor32BitWaveReduction(unsigned Opc) {
case AMDGPU::S_MAX_U32:
return std::numeric_limits::min();
case AMDGPU::S_MAX_I32:
+ case AMDGPU::V_SUB_F32_e64: // +0.0
easyonaadit wrote:
Sorry, I think I
@@ -1,12 +1,13 @@
; RUN: llc -dwarf-version=5 -split-dwarf-file=foo.dwo -O0 %s
-mtriple=riscv64-unknown-linux-gnu -filetype=obj -o %t
; RUN: llvm-dwarfdump -v %t | FileCheck --check-prefix=DWARF5 %s
; RUN: llvm-dwarfdump --debug-info %t 2> %t.txt
-; RUN: FileCheck --input-file
@@ -478,146 +890,232 @@ entry:
}
define i1 @bcmp_eq_zero(ptr %s1, ptr %s2) nounwind {
-; LA32-LABEL: bcmp_eq_zero:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT:addi.w $sp, $sp, -16
-; LA32-NEXT:st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:ori $a2, $zero, 1
ChuanqiXu9 wrote:
> > > @ChuanqiXu9 What do you think about merging this PR to the release branch?
> >
> >
> > This is a simple fix. I think there is no risks.
>
> Could you approve the port request as a formality if it is okay with you?
Done
https://github.com/llvm/llvm-project/pull/166701
https://github.com/ChuanqiXu9 approved this pull request.
https://github.com/llvm/llvm-project/pull/166701
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https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/165963
>From e177f8d15c9efc4eba953f5aa5f7099bfc35877e Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sat, 1 Nov 2025 03:16:20 +
Subject: [PATCH] Avoid using DenseMap for CFGBlock and program points
---
.../Ana
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/165963
>From e177f8d15c9efc4eba953f5aa5f7099bfc35877e Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sat, 1 Nov 2025 03:16:20 +
Subject: [PATCH] Avoid using DenseMap for CFGBlock and program points
---
.../Ana
dyung wrote:
At this time we are only accepting release branch patches for major bugs or
regressions, and this does not seem to be either to me (although admittedly I'm
not very familiar with this area). @dsandersllvm can you explain why this meets
the criteria for inclusion in the release bra
dyung wrote:
> > @ChuanqiXu9 What do you think about merging this PR to the release branch?
>
> This is a simple fix. I think there is no risks.
Could you approve the port request as a formality if it is okay with you?
https://github.com/llvm/llvm-project/pull/166701
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https://github.com/llvm/llvm-project/pull/166880
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https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/166880
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llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Helena Kotas (hekota)
Changes
This change fixes couple of issues with static resources:
- Enables assignment to static resource and resource array variables (fixes
#166458)
- Initializes static resources and resource arrays with default con
llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-clang-codegen
Author: Helena Kotas (hekota)
Changes
This change fixes couple of issues with static resources:
- Enables assignment to static resource and resource array variables (fixes
#166458)
- Initializes static resources
https://github.com/hekota created
https://github.com/llvm/llvm-project/pull/166880
This change fixes couple of issues with static resources:
- Enables assignment to static resource and resource array variables (fixes
#166458)
- Initializes static resources and resource arrays with default const
https://github.com/makslevental updated
https://github.com/llvm/llvm-project/pull/166618
>From 186a5f9dd5545db6e3ccb228174e9f6edbce95d5 Mon Sep 17 00:00:00 2001
From: makslevental
Date: Wed, 5 Nov 2025 11:13:09 -0800
Subject: [PATCH 1/5] check float cast
---
mlir/lib/Conversion/ArithToLLVM/Ar
https://github.com/makslevental updated
https://github.com/llvm/llvm-project/pull/166618
>From 186a5f9dd5545db6e3ccb228174e9f6edbce95d5 Mon Sep 17 00:00:00 2001
From: makslevental
Date: Wed, 5 Nov 2025 11:13:09 -0800
Subject: [PATCH 1/5] check float cast
---
mlir/lib/Conversion/ArithToLLVM/Ar
https://github.com/dlav-sc updated
https://github.com/llvm/llvm-project/pull/164813
>From 2d238393e9b59f8e90f0f1e49ad65e6271cb1f42 Mon Sep 17 00:00:00 2001
From: Daniil Avdeev
Date: Thu, 18 Sep 2025 02:05:39 +
Subject: [PATCH 1/3] [dwarf] make dwarf fission compatible with RISCV
relaxation
https://github.com/dlav-sc updated
https://github.com/llvm/llvm-project/pull/164813
>From 833329169cadc9a1223a19dd5a50faff0501f92b Mon Sep 17 00:00:00 2001
From: Daniil Avdeev
Date: Thu, 18 Sep 2025 02:05:39 +
Subject: [PATCH 1/3] [dwarf] make dwarf fission compatible with RISCV
relaxation
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/165818
>From 8466578444bc27c0d8c5dc2ee95f074a96b5e47f Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 30 Oct 2025 12:19:59 -0400
Subject: [PATCH 1/2] [SelectionDAG] Split vector types for atomic load
Vector types that a
@@ -3494,6 +3494,95 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl,
unsigned BuiltinID,
if (BuiltinCountedByRef(TheCall))
return ExprError();
break;
+
+ case Builtin::BI__builtin_ct_select: {
+if (TheCall->getNumArgs() != 3) {
+ // Simple argumen
@@ -6450,6 +6451,40 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
auto Str = CGM.GetAddrOfConstantCString(Name, "");
return RValue::get(Str.getPointer());
}
+ case Builtin::BI__builtin_ct_select: {
+if (E->getNumArgs() != 3)
@@ -3494,6 +3494,95 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl,
unsigned BuiltinID,
if (BuiltinCountedByRef(TheCall))
return ExprError();
break;
+
+ case Builtin::BI__builtin_ct_select: {
+if (TheCall->getNumArgs() != 3) {
+ // Simple argumen
@@ -3494,6 +3494,95 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl,
unsigned BuiltinID,
if (BuiltinCountedByRef(TheCall))
return ExprError();
break;
+
+ case Builtin::BI__builtin_ct_select: {
+if (TheCall->getNumArgs() != 3) {
+ // Simple argumen
https://github.com/efriedma-quic edited
https://github.com/llvm/llvm-project/pull/166703
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https://github.com/efriedma-quic commented:
Needs documentation in clang/docs/LanguageExtensions.rst. Needs a release note.
I'm still generally skeptical of this approach, but I don't think have anything
to say that hasn't already been said on the RFC thread.
https://github.com/llvm/llvm-proj
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Julius Alexandre (wizardengineer)
Changes
---
Patch is 49.36 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/166703.diff
5 Files Affected:
- (modified) clang/include/clang/Basic/Builtins.td
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Julius Alexandre (wizardengineer)
Changes
This patch implements architecture-specific lowering for ct.select on AArch64
using CSEL (conditional select) instructions for constant-time selection.
Implementation details:
- Uses CSEL
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Julius Alexandre (wizardengineer)
Changes
Add comprehensive test suite for RISC-V fallback implementation:
- Edge cases (zero conditions, large integers, sign extension)
- Pattern matching (nested selects, chains)
- Vector support
llvmbot wrote:
@llvm/pr-subscribers-backend-webassembly
Author: Julius Alexandre (wizardengineer)
Changes
---
Patch is 79.36 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/166709.diff
5 Files Affected:
- (added) llvm/test/CodeGen/WebAssemb
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Julius Alexandre (wizardengineer)
Changes
---
Patch is 49.36 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/166703.diff
5 Files Affected:
- (modified) clang/include/clang/Basic/Buil
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Julius Alexandre (wizardengineer)
Changes
[LLVM][X86] Add native ct.select support for X86 and i386
Add native X86 implementation with CMOV instructions and comprehensive tests:
- X86 ISelLowering with CMOV for x86_64 and i386
- Fall
llvmbot wrote:
@llvm/pr-subscribers-backend-mips
Author: Julius Alexandre (wizardengineer)
Changes
---
Patch is 70.17 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/166705.diff
5 Files Affected:
- (added) llvm/test/CodeGen/Mips/ctselect-fa
llvmbot wrote:
@llvm/pr-subscribers-backend-arm
Author: Julius Alexandre (wizardengineer)
Changes
This patch implements architecture-specific lowering for ct.select on ARM
(both ARM32 and Thumb modes) using conditional move instructions and
bitwise operations for constant-time selection.
https://github.com/wizardengineer ready_for_review
https://github.com/llvm/llvm-project/pull/166709
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https://github.com/wizardengineer ready_for_review
https://github.com/llvm/llvm-project/pull/166704
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https://github.com/wizardengineer ready_for_review
https://github.com/llvm/llvm-project/pull/166705
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https://github.com/llvm/llvm-project/pull/166706
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https://github.com/llvm/llvm-project/pull/166707
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https://github.com/llvm/llvm-project/pull/166703
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https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166708
>From 7aec58aa6f8029c514857a755b5a381e6a6b22af Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 11:01:00 -0500
Subject: [PATCH] [ConstantTime][RISCV] Add comprehensive tests for ct.sele
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/166828
>From bc870644188ae13da4141efdf75eab0137ddcc30 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Thu, 6 Nov 2025 19:05:09 +
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/166828
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boomanaiden154 wrote:
> This thing is a perennial PITA. I'm stamping to unblock but can you can also
> try https://github.com/wjakob/nanobind/pull/868.
Yeah, looks like it. Very interesting to see a project that is pretty against
disabling warnings, but also against accepting patches to fix wa
makslevental wrote:
PS also this https://github.com/wjakob/nanobind/issues/994 🙂
https://github.com/llvm/llvm-project/pull/166828
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https://github.com/makslevental approved this pull request.
This thing is a perennial PITA. I'm stamping to unblock but can you can also
try [NB_SUPPRESS_WARNINGS](https://github.com/wjakob/nanobind/pull/868).
https://github.com/llvm/llvm-project/pull/166828
llvmbot wrote:
@llvm/pr-subscribers-mlir
Author: Aiden Grossman (boomanaiden154)
Changes
We recently moved over to compiling with clang-cl on Windows. This ended
up causing a large increase in warnings, particularly due to how
warnings are handled in nanobind. cd91d0fff9293a904704784c92c28
https://github.com/boomanaiden154 created
https://github.com/llvm/llvm-project/pull/166828
We recently moved over to compiling with clang-cl on Windows. This ended
up causing a large increase in warnings, particularly due to how
warnings are handled in nanobind. cd91d0fff9293a904704784c92c28637b
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148899
>From 23fb9283f42bd418afb4d478dfaa7215c4d16093 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:02:04 -0400
Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats
This commit casts float
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148900
>From 242cf54a6b527e573c4d30a3bea47e3a458fb8c1 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:03:15 -0400
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148899
>From 23fb9283f42bd418afb4d478dfaa7215c4d16093 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:02:04 -0400
Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats
This commit casts float
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148900
>From 242cf54a6b527e573c4d30a3bea47e3a458fb8c1 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:03:15 -0400
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/165818
>From 8466578444bc27c0d8c5dc2ee95f074a96b5e47f Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 30 Oct 2025 12:19:59 -0400
Subject: [PATCH] [SelectionDAG] Split vector types for atomic load
Vector types that aren'
https://github.com/RKSimon approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/148898
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https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From cc06ca25470188cc8e767eab72fcfe83958cf4b2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
@@ -4088,7 +4107,20 @@ MachineInstr
*SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
LV->getVarInfo(DefReg).AliveBlocks.clear();
}
-if (LIS) {
+if (MI.isBundle()) {
+ VirtRegInfo VRI = AnalyzeVirtRegInBundle(MI, DefReg);
+ if (!VRI.Reads &&
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From cc06ca25470188cc8e767eab72fcfe83958cf4b2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From dd8c2ece4a1287580cec17fff56e8eaa314ffef7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148900
>From a657bd946e7be59892a00a447ca7018d0715c6a5 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:03:15 -0400
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148899
>From f9b99b992450687c7da5048c82e9ce38efc3ff1d Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:02:04 -0400
Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats
This commit casts float
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148900
>From a657bd946e7be59892a00a447ca7018d0715c6a5 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:03:15 -0400
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/165818
>From 1434bcf8d9be03eeabce92430d00e02b0e434069 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 30 Oct 2025 12:19:59 -0400
Subject: [PATCH] [SelectionDAG] Split vector types for atomic load
Vector types that aren'
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148899
>From f9b99b992450687c7da5048c82e9ce38efc3ff1d Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:02:04 -0400
Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats
This commit casts float
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148898
>From b92b6dac8913654dc0ba987ce328c47fa7330778 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:01:24 -0400
Subject: [PATCH] [X86] Remove extra MOV after widening atomic load
This change adds patter
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/165818
>From 1434bcf8d9be03eeabce92430d00e02b0e434069 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 30 Oct 2025 12:19:59 -0400
Subject: [PATCH] [SelectionDAG] Split vector types for atomic load
Vector types that aren'
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/148898
>From b92b6dac8913654dc0ba987ce328c47fa7330778 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Tue, 15 Jul 2025 13:01:24 -0400
Subject: [PATCH] [X86] Remove extra MOV after widening atomic load
This change adds patter
https://github.com/aaupov closed
https://github.com/llvm/llvm-project/pull/165490
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https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166706
>From 7de2b8134fa87b1f113834b5ab0b218cbde5a821 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 17:09:45 -0500
Subject: [PATCH] [LLVM][AArch64] Add native ct.select support for ARM64
T
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166709
>From 046e875568de9a6a794725bc69572151be8b8b9f Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 11:03:23 -0500
Subject: [PATCH] [ConstantTime][WebAssembly] Add comprehensive tests for
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166708
>From 9ed3c7d206aa6d9dcba0fdbc3afe773b431bf597 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 11:01:00 -0500
Subject: [PATCH] [ConstantTime][RISCV] Add comprehensive tests for ct.sele
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166705
>From 9dac6cad69ae839442c551be1e0a03617f8579d8 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 11:01:26 -0500
Subject: [PATCH] [LLVM][MIPS] Add comprehensive tests for ct.select
---
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166706
>From 7de2b8134fa87b1f113834b5ab0b218cbde5a821 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 17:09:45 -0500
Subject: [PATCH] [LLVM][AArch64] Add native ct.select support for ARM64
T
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166709
>From 046e875568de9a6a794725bc69572151be8b8b9f Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 11:03:23 -0500
Subject: [PATCH] [ConstantTime][WebAssembly] Add comprehensive tests for
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166703
>From 6ac8221eef92f3e8c615c2218b8db2e3d26cf692 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 10:56:34 -0500
Subject: [PATCH] [ConstantTime][Clang] Add __builtin_ct_select for
consta
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166703
>From 6ac8221eef92f3e8c615c2218b8db2e3d26cf692 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 10:56:34 -0500
Subject: [PATCH] [ConstantTime][Clang] Add __builtin_ct_select for
consta
https://github.com/wizardengineer updated
https://github.com/llvm/llvm-project/pull/166708
>From 9ed3c7d206aa6d9dcba0fdbc3afe773b431bf597 Mon Sep 17 00:00:00 2001
From: wizardengineer
Date: Wed, 5 Nov 2025 11:01:00 -0500
Subject: [PATCH] [ConstantTime][RISCV] Add comprehensive tests for ct.sele
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From 856bcd31258066731b367e0fadfa44b7c8de35ab Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From 856bcd31258066731b367e0fadfa44b7c8de35ab Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From 856bcd31258066731b367e0fadfa44b7c8de35ab Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/jayfoad approved this pull request.
Seems OK on the understanding that it is slightly experimental, and after some
more experience we may need to change things and/or nail down the exact rules
for what cases are and are not supported.
https://github.com/llvm/llvm-project/pul
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff origin/main HEAD --extensions cpp --
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp -
@@ -1665,6 +1665,22 @@ void
TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,
// by SubRegB is compatible with RegA with no subregister. So regardless of
// whether the dest oper writes a subreg, the source oper should not.
MO.setSubReg(0);
+
+// Up
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From 69ff9c0f0dd1af8333d4b160003d7f8a6eea61aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From 69ff9c0f0dd1af8333d4b160003d7f8a6eea61aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166213
From 69ff9c0f0dd1af8333d4b160003d7f8a6eea61aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 7 Oct 2025 12:17:02 -0700
Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166212
From b6bf0c47fd34efff8a4df14df69eb1f06785 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 23 Sep 2025 19:08:52 -0700
Subject: [PATCH] CodeGen: Handle bundled instructions in
two
https://github.com/nhaehnle updated
https://github.com/llvm/llvm-project/pull/166212
From b6bf0c47fd34efff8a4df14df69eb1f06785 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?=
Date: Tue, 23 Sep 2025 19:08:52 -0700
Subject: [PATCH] CodeGen: Handle bundled instructions in
two
@@ -1665,6 +1665,22 @@ void
TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,
// by SubRegB is compatible with RegA with no subregister. So regardless of
// whether the dest oper writes a subreg, the source oper should not.
MO.setSubReg(0);
+
+// Up
nhaehnle wrote:
> Have you considered the case where the instructions inside the bundle have
> two uses of RegB, but only one of them is tied with RegA? I think it is
> almost impossible to handle that optimally given only the summarised
> information that you get from the operands of the BUND
@@ -4,20 +4,58 @@
"""Script for getting explanations from the premerge advisor."""
import argparse
-import os
import platform
import sys
+import json
import requests
+import github
+import github.PullRequest
import generate_test_report_lib
PREMERGE_ADVISOR_URL = (
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/166605
>From 06c030dcb4ee57be287beffd96d1b21ef1697dd4 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 5 Nov 2025 18:23:46 +
Subject: [PATCH 1/2] fix
Created using spr 1.3.7
---
.ci/premerge_adviso
@@ -33,17 +33,18 @@ function at-exit {
# If building fails there will be no results files.
shopt -s nullglob
- if [[ "$GITHUB_STEP_SUMMARY" != "" ]]; then
+ if [[ "$GITHUB_ACTIONS" != "" ]]; then
boomanaiden154 wrote:
This checks that we are running in
@@ -45,13 +83,31 @@ def main(commit_sha: str, build_log_files: list[str]):
)
if advisor_response.status_code == 200:
print(advisor_response.json())
+comments = [
+get_comment(
+github_token,
+pr_number,
+
https://github.com/rafaelauler approved this pull request.
https://github.com/llvm/llvm-project/pull/165490
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