[llvm-branch-commits] [llvm] [DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold. (PR #133915)

davemgreen wrote: Did you have a reason to need this change? https://github.com/llvm/llvm-project/pull/133915 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/20.x: [AArch64] Fix feature list for FUJITSU-MONAKA processor (#139212) (PR #139222)

https://github.com/davemgreen approved this pull request. https://github.com/llvm/llvm-project/pull/139222 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/20.x: [AArch64] Fix feature list for FUJITSU-MONAKA processor (#139212) (PR #139222)

davemgreen wrote: LGTM - changes look small and correct a regression since the previous release. https://github.com/llvm/llvm-project/pull/139222 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[llvm-branch-commits] [llvm] [GlobalISel] Add computeNumSignBits for G_BUILD_VECTOR. (PR #139506)

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/139506 The code is similar to SelectionDAG::ComputeNumSignBits, but does not deal with truncating buildvectors. >From c1286744212c2b2f09e923161a6e6fc4d894e216 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon,

[llvm-branch-commits] [llvm] [GlobalISel] Add computeKnownBits for G_SHUFFLE_VECTOR (PR #139505)

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/139505 The code is similar to computeKnownBits and the code in SelectionDAG::ComputeNumSignBits. >From 68fc0c493331eaa56ebc862ef7dfb7106cabad82 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 12 May 2025 07:

[llvm-branch-commits] [llvm] [GlobalISel] Add computeNumSignBits for ASHR (PR #139503)

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/139503 None Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Ari

[llvm-branch-commits] [llvm] [AArch64AsmPrinter]Place jump tables into hot/unlikely-prefixed data sections for aarch64 (PR #126018)

https://github.com/davemgreen approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/126018 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold. (PR #133915)

https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/133915 >From 35f44f31a41e485c7098a66bff99c4dfc424bb8d Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 1 Apr 2025 15:15:08 +0100 Subject: [PATCH 1/2] [DAG][AArch64] Handle truncated buildvectors to allow and(s

[llvm-branch-commits] [llvm] [DAG][AArch64] Handle truncated buildvectors to allow and(subvector(anyext)) fold. (PR #133915)

@@ -7166,7 +7166,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // if (and x, c) is known to be zero, return 0 unsigned BitWidth = VT.getScalarSizeInBits(); - ConstantSDNode *N1C = isConstOrConstSplat(N1); + ConstantSDNode *N1C = + isConstOrConstSplat(N1, /*AllowUn

[llvm-branch-commits] [llvm] [SDAG] Introduce inbounds flag for pointer arithmetic (PR #131862)

davemgreen wrote: There is a ISD::PTRADD in https://github.com/llvm/llvm-project/pull/105669, which still has some open questions about whether the AMDGPU use of the tablegen `ptradd` can be redefined. https://github.com/llvm/llvm-project/pull/131862 ___

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Fix legalization for <4 x i1> vector stores. (PR #121185)

https://github.com/davemgreen approved this pull request. I think this sounds OK. LGTM (Which of bitcast or load/store is considered the most fundamental for v4i1/v8i1? I think I would have expected in GISel the loads to be converted to a i4/i8 load with bitcast, and the bitcast legalizes howe

[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)

davemgreen wrote: It did look like the abs/shuffle was being optimized differently in the rest of vector combine. https://github.com/llvm/llvm-project/pull/111796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.ll

[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)

https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/111796 >From b64f2902d1b01234f57888fcf78282bc7cddb293 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 9 Oct 2024 16:20:03 +0100 Subject: [PATCH 1/2] [VectorCombine] Do not try to operate on OperandBundles. (#

[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)

https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/111796 >From b64f2902d1b01234f57888fcf78282bc7cddb293 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 9 Oct 2024 16:20:03 +0100 Subject: [PATCH 1/2] [VectorCombine] Do not try to operate on OperandBundles. (#

[llvm-branch-commits] [llvm] release/19.x: [VectorCombine] Do not try to operate on OperandBundles. (#111635) (PR #111796)

davemgreen wrote: I must admit OperandBundles are a new one for me. It has apparently been around for a while, and I had assumed from https://github.com/JuliaPackaging/Yggdrasil/pull/9204 that this was related to pulling clang-19 into Julia. I will have to have a look at what is behaving diff

[llvm-branch-commits] [llvm] [AArch64] Generalize the instruction size checking in AsmPrinter (PR #110108)

@@ -2546,6 +2510,7 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) { TLSDescCall.setOpcode(AArch64::TLSDESCCALL); TLSDescCall.addOperand(Sym); EmitToStreamer(*OutStreamer, TLSDescCall); +--InstsEmitted; // no code emitted dav

[llvm-branch-commits] [llvm] release/19.x: [AArch64] Add streaming-mode stack hazard optimization remarks (#101695) (PR #102168)

davemgreen wrote: Thanks @tru https://github.com/llvm/llvm-project/pull/102168 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [AArch64] Add streaming-mode stack hazard optimization remarks (#101695) (PR #102168)

davemgreen wrote: > The patch here is pretty big in size, but it seems to only affects the > remarks, on the other hand it doesn't seem to really fix anything and in that > case I feel like RC3 might be the wrong time to merge this. Is there a huge > upside to take this this late in the proces

[llvm-branch-commits] [llvm] release/19.x: [AArch64] Add streaming-mode stack hazard optimization remarks (#101695) (PR #102168)

https://github.com/davemgreen approved this pull request. https://github.com/llvm/llvm-project/pull/102168 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [AArch64] Add streaming-mode stack hazard optimization remarks (#101695) (PR #102168)

davemgreen wrote: The changes looks OK to me - they should only alter the (doublely) opt-in optimization remarks so should be pretty safe. @tru does that sounds OK to you, for it to go onto the branch? https://github.com/llvm/llvm-project/pull/102168 ___

[llvm-branch-commits] [llvm] release/19.x: [SLP] Order clustered load base pointers by ascending offsets (#100653) (PR #101033)

davemgreen wrote: It is fixing a performance regression introduced in #98025 under AArch64. My only worry in it is the sorting algorithm, where there is a chance it isn't quite strict-weak. The regression wasn't huge, lets leave this one and we can pick it up in the next release. It's a bit of

[llvm-branch-commits] [llvm] release/19.x: [SLP] Order clustered load base pointers by ascending offsets (#100653) (PR #101033)

https://github.com/davemgreen closed https://github.com/llvm/llvm-project/pull/101033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [SLP] Order clustered load base pointers by ascending offsets (#100653) (PR #101033)

davemgreen wrote: Hi - What stage are we in for backports? Is it still OK to get this in if I add #101144 to it? https://github.com/llvm/llvm-project/pull/101033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llv

[llvm-branch-commits] [llvm] release/19.x: [SLP] Order clustered load base pointers by ascending offsets (#100653) (PR #101033)

https://github.com/davemgreen requested changes to this pull request. The strict-weak ordering is unfortunately causing problems. https://github.com/llvm/llvm-project/pull/101033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org h

[llvm-branch-commits] [llvm] release/19.x: [StackFrameLayoutAnalysis] Support more SlotTypes (#100562) (PR #101042)

davemgreen wrote: @ilovepi Does porting these to the branch sounds OK to you? Thanks https://github.com/llvm/llvm-project/pull/101042 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinf

[llvm-branch-commits] [llvm] release/19.x: [SLP] Order clustered load base pointers by ascending offsets (#100653) (PR #101033)

https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/101033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

davemgreen wrote: I think it would be better if the generic model produced better results for custom nodes, but I have extended the existing costs for Arm/AArch64 to hopefully give a better cost in more cases. It just extended what was already there to handle more cases. https://github.com/ll

[llvm-branch-commits] [llvm] TTI: Check legalization cost of add/sub overflow ISD nodes (PR #100518)

https://github.com/davemgreen commented: I think all these cost changes are OK. https://github.com/llvm/llvm-project/pull/100518 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llv

[llvm-branch-commits] [llvm] TTI: Check legalization cost of min/max ISD nodes (PR #100514)

https://github.com/davemgreen commented: The Arm costs look OK to me. https://github.com/llvm/llvm-project/pull/100514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-c

[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)

davemgreen wrote: LGTM, I believe this should be safe to merge, if there are people asking for it. https://github.com/llvm/llvm-project/pull/91151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[llvm-branch-commits] [llvm] release/18.x: [AArch64] Remove invalid uabdl patterns. (#89272) (PR #89380)

https://github.com/davemgreen approved this pull request. I think this should be OK for the branch, if it is wanted. It should be a safe commit to backport, considering it just removes some invalid patterns. LGTM. https://github.com/llvm/llvm-project/pull/89380 _

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

https://github.com/davemgreen approved this pull request. Thanks. LGTM https://github.com/llvm/llvm-project/pull/85042 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-c

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

https://github.com/davemgreen commented: It looks like this comes from the lowerIfMemSizeNotByteSizePow2. Custom is often best avoided unless there is not anther way, or the change is quite target-dependant. Can we try something like this instead? ``` .clampMaxNumElements(0, s8, 16)

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

davemgreen wrote: See https://github.com/llvm/llvm-project/pull/83017, about it fixing the bug in a recent RISCV issue. I think the "Requested by" comes from the git committer. @lukel97 i'm not sure if you have already or not, but it might be good to include the recent test you added too. htt

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64] Backport Ampere1B support (#81297 , #81341, and #81744) (PR #81857)

davemgreen wrote: > Is this fixing a regression introduced in Clang 18? I'm wondering why the > backport is needed in the first place, as this seems to be making potentially > significant changes during the RC ("Make +pauth enabled in Armv8.3-a by > default"). It is adding new CPU support to

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64] Backport Ampere1B support (#81297 , #81341, and #81744) (PR #81857)

https://github.com/davemgreen approved this pull request. I believe considering what this changes it should be OK. LGTM https://github.com/llvm/llvm-project/pull/81857 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://list

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64] Backport Ampere1B support (#81297 , #81341, and #81744) (PR #81857)

davemgreen wrote: This is a fairly big patch to backport. The ampere1b changes should be safe enough considering as it just adds support for an extra CPU. There is also the change from #78027 added for changing how PAUTH is enabled. @atrosinenko @DavidSpickett do you think that is OK to backpo

[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

@@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {s16, v8s16}, {s32, v2s32}, {s32, v4s32}}) + .moreElementsIf( davemgreen wrote: I think this can happen for m

[llvm-branch-commits] [llvm] release/18.x: [AArch64] Only apply bool vector bitcast opt if result is scalar (#81256) (PR #81454)

https://github.com/davemgreen approved this pull request. Looks good to get onto the branch to me https://github.com/llvm/llvm-project/pull/81454 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[llvm-branch-commits] [libcxx] [libc] [flang] [llvm] [clang] [compiler-rt] [SelectOpt] Print instruction instead of pointer (PR #80125)

https://github.com/davemgreen approved this pull request. Thanks. LGTM https://github.com/llvm/llvm-project/pull/80125 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-c

[llvm-branch-commits] [llvm] [clang] PR for llvm/llvm-project#79614 (PR #79870)

https://github.com/davemgreen approved this pull request. Sounds simple enough to me. LGTM https://github.com/llvm/llvm-project/pull/79870 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/li

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#79800 (PR #79813)

https://github.com/davemgreen approved this pull request. The perf regression was fairly significant, so it would be good to get this into the branch. Thanks. https://github.com/llvm/llvm-project/pull/79813 ___ llvm-branch-commits mailing list llvm-br

[llvm-branch-commits] [clang] [llvm] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)

@@ -720,7 +726,7 @@ if(COMPILER_RT_SUPPORTED_ARCH) endif() message(STATUS "Compiler-RT supported architectures: ${COMPILER_RT_SUPPORTED_ARCH}") -set(ALL_SANITIZERS asan;dfsan;msan;hwasan;tsan;safestack;cfi;scudo_standalone;ubsan_minimal;gwp_asan;asan_abi) +set(ALL_SANITIZERS

[llvm-branch-commits] [llvm] e841bd5 - [ARM] Extra MVE unaligned VLDn tests. NFC

Author: David Green Date: 2021-01-24T21:39:00Z New Revision: e841bd5f335864b8c4d81cbf4df08460ef39f2ae URL: https://github.com/llvm/llvm-project/commit/e841bd5f335864b8c4d81cbf4df08460ef39f2ae DIFF: https://github.com/llvm/llvm-project/commit/e841bd5f335864b8c4d81cbf4df08460ef39f2ae.diff LOG: [

[llvm-branch-commits] [llvm] 4cc94b7 - [CostModel] Tests for showing the cost of intrinsics from the vectorizer. NFC

Author: David Green Date: 2021-01-24T14:47:15Z New Revision: 4cc94b731345aa494e0e364846ba9550f5dd5105 URL: https://github.com/llvm/llvm-project/commit/4cc94b731345aa494e0e364846ba9550f5dd5105 DIFF: https://github.com/llvm/llvm-project/commit/4cc94b731345aa494e0e364846ba9550f5dd5105.diff LOG: [

[llvm-branch-commits] [llvm] 06ab795 - [AArch64] Saturating add cost tests. NFC

Author: David Green Date: 2021-01-24T13:49:17Z New Revision: 06ab7953e98222de1ace4520163b4fa53565ead4 URL: https://github.com/llvm/llvm-project/commit/06ab7953e98222de1ace4520163b4fa53565ead4 DIFF: https://github.com/llvm/llvm-project/commit/06ab7953e98222de1ace4520163b4fa53565ead4.diff LOG: [

[llvm-branch-commits] [llvm] af03324 - [ARM] Disable sign extended SSAT pattern recognition.

Author: David Green Date: 2021-01-22T14:07:48Z New Revision: af0332498405b3a4074cef09845bbacfd4fd594f URL: https://github.com/llvm/llvm-project/commit/af0332498405b3a4074cef09845bbacfd4fd594f DIFF: https://github.com/llvm/llvm-project/commit/af0332498405b3a4074cef09845bbacfd4fd594f.diff LOG: [

[llvm-branch-commits] [llvm] 9ae73cd - [ARM] Adjust isSaturatingConditional to return a new SDValue. NFC

Author: David Green Date: 2021-01-22T11:11:36Z New Revision: 9ae73cdbc1e59fd3149e60efd2b96e68e8d1669b URL: https://github.com/llvm/llvm-project/commit/9ae73cdbc1e59fd3149e60efd2b96e68e8d1669b DIFF: https://github.com/llvm/llvm-project/commit/9ae73cdbc1e59fd3149e60efd2b96e68e8d1669b.diff LOG: [

[llvm-branch-commits] [llvm] 39db575 - [LV][ARM] Inloop reduction cost modelling

Author: David Green Date: 2021-01-21T21:03:41Z New Revision: 39db5753f993abcc4289dd165e8297a4e28f4b0a URL: https://github.com/llvm/llvm-project/commit/39db5753f993abcc4289dd165e8297a4e28f4b0a DIFF: https://github.com/llvm/llvm-project/commit/39db5753f993abcc4289dd165e8297a4e28f4b0a.diff LOG: [

[llvm-branch-commits] [llvm] dfac521 - [ARM] Fix vector saddsat costs.

Author: David Green Date: 2021-01-21T15:30:39Z New Revision: dfac521da1b90db6832a0d357f67cb819ea8687f URL: https://github.com/llvm/llvm-project/commit/dfac521da1b90db6832a0d357f67cb819ea8687f DIFF: https://github.com/llvm/llvm-project/commit/dfac521da1b90db6832a0d357f67cb819ea8687f.diff LOG: [

[llvm-branch-commits] [llvm] 045d84f - D94954: Fixes Snapdragon Kryo CPU core detection

Author: Ryan Houdek Date: 2021-01-20T22:23:43Z New Revision: 045d84f4e6d7d6bbccaa6d965669a068fc329809 URL: https://github.com/llvm/llvm-project/commit/045d84f4e6d7d6bbccaa6d965669a068fc329809 DIFF: https://github.com/llvm/llvm-project/commit/045d84f4e6d7d6bbccaa6d965669a068fc329809.diff LOG: D

[llvm-branch-commits] [llvm] 6a563ee - [ARM] Expand vXi1 VSELECT's

Author: David Green Date: 2021-01-19T17:56:50Z New Revision: 6a563eef1321f742fa06482f4536cd41fb8e24c7 URL: https://github.com/llvm/llvm-project/commit/6a563eef1321f742fa06482f4536cd41fb8e24c7 DIFF: https://github.com/llvm/llvm-project/commit/6a563eef1321f742fa06482f4536cd41fb8e24c7.diff LOG: [

[llvm-branch-commits] [llvm] f373b30 - [ARM] Add MVE add.sat costs

Author: David Green Date: 2021-01-19T15:38:46Z New Revision: f373b30923d7a83985e59ec76a566dd889e684d9 URL: https://github.com/llvm/llvm-project/commit/f373b30923d7a83985e59ec76a566dd889e684d9 DIFF: https://github.com/llvm/llvm-project/commit/f373b30923d7a83985e59ec76a566dd889e684d9.diff LOG: [

[llvm-branch-commits] [llvm] 54e3844 - [ARM] Expand add.sat/sub.sat cost checks. NFC

Author: David Green Date: 2021-01-19T15:06:06Z New Revision: 54e38440e74f98ec58a22d7d8f9fc5e550ce65aa URL: https://github.com/llvm/llvm-project/commit/54e38440e74f98ec58a22d7d8f9fc5e550ce65aa DIFF: https://github.com/llvm/llvm-project/commit/54e38440e74f98ec58a22d7d8f9fc5e550ce65aa.diff LOG: [

[llvm-branch-commits] [llvm] e7dc083 - [ARM] Don't handle low overhead branches in AnalyzeBranch

Author: David Green Date: 2021-01-18T17:16:07Z New Revision: e7dc083a410f187e143138b4956993370626268b URL: https://github.com/llvm/llvm-project/commit/e7dc083a410f187e143138b4956993370626268b DIFF: https://github.com/llvm/llvm-project/commit/e7dc083a410f187e143138b4956993370626268b.diff LOG: [

[llvm-branch-commits] [llvm] 6929581 - [ARM] Update test target triple. NFC

Author: David Green Date: 2021-01-18T16:36:00Z New Revision: 69295815ed92cc125f7ae0a0c41c99fd507dad9d URL: https://github.com/llvm/llvm-project/commit/69295815ed92cc125f7ae0a0c41c99fd507dad9d DIFF: https://github.com/llvm/llvm-project/commit/69295815ed92cc125f7ae0a0c41c99fd507dad9d.diff LOG: [

[llvm-branch-commits] [llvm] 2a5b576 - [ARM] Test for aligned blocks. NFC

Author: David Green Date: 2021-01-16T22:04:48Z New Revision: 2a5b576e3ea41c30537435d989a3dce7a409f8e2 URL: https://github.com/llvm/llvm-project/commit/2a5b576e3ea41c30537435d989a3dce7a409f8e2 DIFF: https://github.com/llvm/llvm-project/commit/2a5b576e3ea41c30537435d989a3dce7a409f8e2.diff LOG: [

[llvm-branch-commits] [llvm] 1454724 - [ARM] Align blocks that are not fallthough targets

Author: David Green Date: 2021-01-16T22:19:35Z New Revision: 145472421535c71a9ea60af7e5d012ab69dc85ff URL: https://github.com/llvm/llvm-project/commit/145472421535c71a9ea60af7e5d012ab69dc85ff DIFF: https://github.com/llvm/llvm-project/commit/145472421535c71a9ea60af7e5d012ab69dc85ff.diff LOG: [

[llvm-branch-commits] [llvm] 372eb2b - [ARM] Add low overhead loops terminators to AnalyzeBranch

Author: David Green Date: 2021-01-16T18:30:21Z New Revision: 372eb2bbb6fb903ce76266e659dfefbaee67722b URL: https://github.com/llvm/llvm-project/commit/372eb2bbb6fb903ce76266e659dfefbaee67722b DIFF: https://github.com/llvm/llvm-project/commit/372eb2bbb6fb903ce76266e659dfefbaee67722b.diff LOG: [

[llvm-branch-commits] [llvm] c1ab698 - [ARM] Remove LLC tests from transform/hardware loop tests.

Author: David Green Date: 2021-01-16T18:30:21Z New Revision: c1ab698dce8dd4e751e63142ebb333d5b90bb8dc URL: https://github.com/llvm/llvm-project/commit/c1ab698dce8dd4e751e63142ebb333d5b90bb8dc DIFF: https://github.com/llvm/llvm-project/commit/c1ab698dce8dd4e751e63142ebb333d5b90bb8dc.diff LOG: [

[llvm-branch-commits] [llvm] f5abf0b - [ARM] Tail predication with constant loop bounds

Author: David Green Date: 2021-01-15T18:17:31Z New Revision: f5abf0bd485a1fa7e332f5f8266c25755d385a8a URL: https://github.com/llvm/llvm-project/commit/f5abf0bd485a1fa7e332f5f8266c25755d385a8a DIFF: https://github.com/llvm/llvm-project/commit/f5abf0bd485a1fa7e332f5f8266c25755d385a8a.diff LOG: [

[llvm-branch-commits] [llvm] a0770f9 - [ARM] Constant tripcount tail predication loop tests. NFC

Author: David Green Date: 2021-01-15T18:02:07Z New Revision: a0770f9e4e923292066dd095cf01a28671e40ad6 URL: https://github.com/llvm/llvm-project/commit/a0770f9e4e923292066dd095cf01a28671e40ad6 DIFF: https://github.com/llvm/llvm-project/commit/a0770f9e4e923292066dd095cf01a28671e40ad6.diff LOG: [

[llvm-branch-commits] [llvm] c29ca85 - [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors

Author: David Green Date: 2021-01-13T08:51:28Z New Revision: c29ca8551afff316976c2befcd65eeef53798499 URL: https://github.com/llvm/llvm-project/commit/c29ca8551afff316976c2befcd65eeef53798499 DIFF: https://github.com/llvm/llvm-project/commit/c29ca8551afff316976c2befcd65eeef53798499.diff LOG: [

[llvm-branch-commits] [llvm] 3aeb30d - [ARM] Additional tests for different interleaving patterns. NFC

Author: David Green Date: 2021-01-13T08:31:50Z New Revision: 3aeb30d1a68a76616c699587e07a7d8880c29d1c URL: https://github.com/llvm/llvm-project/commit/3aeb30d1a68a76616c699587e07a7d8880c29d1c DIFF: https://github.com/llvm/llvm-project/commit/3aeb30d1a68a76616c699587e07a7d8880c29d1c.diff LOG: [

[llvm-branch-commits] [llvm] 8165a03 - [ARM] Add debug messages for the load store optimizer. NFC

Author: David Green Date: 2021-01-11T09:24:28Z New Revision: 8165a0342033e58ce6090fbc425ebdc7c455469f URL: https://github.com/llvm/llvm-project/commit/8165a0342033e58ce6090fbc425ebdc7c455469f DIFF: https://github.com/llvm/llvm-project/commit/8165a0342033e58ce6090fbc425ebdc7c455469f.diff LOG: [

[llvm-branch-commits] [llvm] dcefcd5 - [ARM] Update trunc costs

Author: David Green Date: 2021-01-11T08:59:28Z New Revision: dcefcd51e01741c79c9d9a729fe803b13287a372 URL: https://github.com/llvm/llvm-project/commit/dcefcd51e01741c79c9d9a729fe803b13287a372 DIFF: https://github.com/llvm/llvm-project/commit/dcefcd51e01741c79c9d9a729fe803b13287a372.diff LOG: [

[llvm-branch-commits] [llvm] 0c8b748 - [ARM] Additional trunc cost tests. NFC

Author: David Green Date: 2021-01-11T08:35:16Z New Revision: 0c8b748f321736d016da0f6d710778f503a89b51 URL: https://github.com/llvm/llvm-project/commit/0c8b748f321736d016da0f6d710778f503a89b51 DIFF: https://github.com/llvm/llvm-project/commit/0c8b748f321736d016da0f6d710778f503a89b51.diff LOG: [

[llvm-branch-commits] [llvm] 024af42 - [ARM] Custom lower i1 vector truncates

Author: David Green Date: 2021-01-08T18:21:00Z New Revision: 024af42c601063e5f831b3049612321b5629e00a URL: https://github.com/llvm/llvm-project/commit/024af42c601063e5f831b3049612321b5629e00a DIFF: https://github.com/llvm/llvm-project/commit/024af42c601063e5f831b3049612321b5629e00a.diff LOG: [

[llvm-branch-commits] [llvm] e185b1d - [ConstProp] Constant propagation for get.active.lane.mask instrinsics

Author: David Green Date: 2021-01-08T16:10:01Z New Revision: e185b1dd7b34c352167823295281f1bf1df09976 URL: https://github.com/llvm/llvm-project/commit/e185b1dd7b34c352167823295281f1bf1df09976 DIFF: https://github.com/llvm/llvm-project/commit/e185b1dd7b34c352167823295281f1bf1df09976.diff LOG: [

[llvm-branch-commits] [llvm] a36a286 - [ARM][LV] Additional loop invariant reduction test. NFC

Author: David Green Date: 2021-01-08T15:15:08Z New Revision: a36a2864c0d4b89b66e0cdfde0f82d569a293e10 URL: https://github.com/llvm/llvm-project/commit/a36a2864c0d4b89b66e0cdfde0f82d569a293e10 DIFF: https://github.com/llvm/llvm-project/commit/a36a2864c0d4b89b66e0cdfde0f82d569a293e10.diff LOG: [

[llvm-branch-commits] [llvm] 1ae7624 - [ARM] Update and regenerate test checks. NFC

Author: David Green Date: 2021-01-08T14:54:16Z New Revision: 1ae762469fd11be0b5a10353281a8264ab97b166 URL: https://github.com/llvm/llvm-project/commit/1ae762469fd11be0b5a10353281a8264ab97b166 DIFF: https://github.com/llvm/llvm-project/commit/1ae762469fd11be0b5a10353281a8264ab97b166.diff LOG: [

[llvm-branch-commits] [llvm] 72fb5ba - [LV] Don't sink into replication regions

Author: David Green Date: 2021-01-08T09:50:10Z New Revision: 72fb5ba079019c2108d676526b5285b228795e48 URL: https://github.com/llvm/llvm-project/commit/72fb5ba079019c2108d676526b5285b228795e48 DIFF: https://github.com/llvm/llvm-project/commit/72fb5ba079019c2108d676526b5285b228795e48.diff LOG: [

[llvm-branch-commits] [llvm] 63dce70 - [ARM] Handle any extend whilst lowering addw/addl/subw/subl

Author: David Green Date: 2021-01-06T11:26:39Z New Revision: 63dce70b794eb99ebbfdeed3ca9aafca2b8fe5c4 URL: https://github.com/llvm/llvm-project/commit/63dce70b794eb99ebbfdeed3ca9aafca2b8fe5c4 DIFF: https://github.com/llvm/llvm-project/commit/63dce70b794eb99ebbfdeed3ca9aafca2b8fe5c4.diff LOG: [

[llvm-branch-commits] [llvm] ddb82fc - [ARM] Handle any extend whilst lowering mull

Author: David Green Date: 2021-01-06T10:51:12Z New Revision: ddb82fc76ceb92e6f361d35f1ee8dedaee756854 URL: https://github.com/llvm/llvm-project/commit/ddb82fc76ceb92e6f361d35f1ee8dedaee756854 DIFF: https://github.com/llvm/llvm-project/commit/ddb82fc76ceb92e6f361d35f1ee8dedaee756854.diff LOG: [

[llvm-branch-commits] [llvm] a9b6440 - [AArch64] Handle any extend whilst lowering addw/addl/subw/subl

Author: David Green Date: 2021-01-06T10:35:23Z New Revision: a9b6440eddde920920141d8ade9090273271a79b URL: https://github.com/llvm/llvm-project/commit/a9b6440eddde920920141d8ade9090273271a79b DIFF: https://github.com/llvm/llvm-project/commit/a9b6440eddde920920141d8ade9090273271a79b.diff LOG: [

[llvm-branch-commits] [llvm] 78d8a82 - [AArch64] Handle any extend whilst lowering mull

Author: David Green Date: 2021-01-06T10:08:43Z New Revision: 78d8a821e23e42d13dcbb3467747e480fb889b8a URL: https://github.com/llvm/llvm-project/commit/78d8a821e23e42d13dcbb3467747e480fb889b8a DIFF: https://github.com/llvm/llvm-project/commit/78d8a821e23e42d13dcbb3467747e480fb889b8a.diff LOG: [

[llvm-branch-commits] [llvm] 0c59a4d - [ARM][AArch64] Some extra test to show anyextend lowering. NFC

Author: David Green Date: 2021-01-05T17:34:23Z New Revision: 0c59a4da59a42f04ba932fdab806fc4473d4e0b5 URL: https://github.com/llvm/llvm-project/commit/0c59a4da59a42f04ba932fdab806fc4473d4e0b5 DIFF: https://github.com/llvm/llvm-project/commit/0c59a4da59a42f04ba932fdab806fc4473d4e0b5.diff LOG: [

[llvm-branch-commits] [llvm] 901cc9b - [ARM] Extend lowering for i64 reductions

Author: David Green Date: 2021-01-04T12:44:43Z New Revision: 901cc9b6f30f120f2fbdc01f9eec3708c512186b URL: https://github.com/llvm/llvm-project/commit/901cc9b6f30f120f2fbdc01f9eec3708c512186b DIFF: https://github.com/llvm/llvm-project/commit/901cc9b6f30f120f2fbdc01f9eec3708c512186b.diff LOG: [

[llvm-branch-commits] [llvm] 6c89f6f - [AArch64] Attempt to fix Mac tests with a more specific triple. NFC

Author: David Green Date: 2021-01-04T11:29:18Z New Revision: 6c89f6fae4913eba07093fe7c268e828f801c78b URL: https://github.com/llvm/llvm-project/commit/6c89f6fae4913eba07093fe7c268e828f801c78b DIFF: https://github.com/llvm/llvm-project/commit/6c89f6fae4913eba07093fe7c268e828f801c78b.diff LOG: [

[llvm-branch-commits] [llvm] 685c8b5 - [AARCH64] Improve accumulator forwarding for Cortex-A57 model

Author: Usman Nadeem Date: 2021-01-04T10:58:43Z New Revision: 685c8b537af3138cff24ec6060a86140b8963a1e URL: https://github.com/llvm/llvm-project/commit/685c8b537af3138cff24ec6060a86140b8963a1e DIFF: https://github.com/llvm/llvm-project/commit/685c8b537af3138cff24ec6060a86140b8963a1e.diff LOG:

[llvm-branch-commits] [llvm] a9f14cd - [ARM] Add bank conflict hazarding

Author: David Penry Date: 2020-12-23T14:00:59Z New Revision: a9f14cdc6203c05425f8b17228ff368f7fd9ae29 URL: https://github.com/llvm/llvm-project/commit/a9f14cdc6203c05425f8b17228ff368f7fd9ae29 DIFF: https://github.com/llvm/llvm-project/commit/a9f14cdc6203c05425f8b17228ff368f7fd9ae29.diff LOG: [

[llvm-branch-commits] [llvm] f47bac5 - [ARM] Extra vecreduce tests with smaller than legal types. NFC

Author: David Green Date: 2020-12-20T21:20:39Z New Revision: f47bac5dd207c672e803e08685e084e5d66f8bce URL: https://github.com/llvm/llvm-project/commit/f47bac5dd207c672e803e08685e084e5d66f8bce DIFF: https://github.com/llvm/llvm-project/commit/f47bac5dd207c672e803e08685e084e5d66f8bce.diff LOG: [

[llvm-branch-commits] [llvm] 1de3e7f - [ARM] Improve handling of empty VPT blocks in tail predicated loops

Author: David Green Date: 2020-12-14T11:17:01Z New Revision: 1de3e7fd620bc9db2df96a12401bde4bde722785 URL: https://github.com/llvm/llvm-project/commit/1de3e7fd620bc9db2df96a12401bde4bde722785 DIFF: https://github.com/llvm/llvm-project/commit/1de3e7fd620bc9db2df96a12401bde4bde722785.diff LOG: [

[llvm-branch-commits] [llvm] ab97c9b - [LV] Fix scalar cost for tail predicated loops

Author: David Green Date: 2020-12-12T14:21:40Z New Revision: ab97c9bdb747c873cd35a18229e2694156a7607d URL: https://github.com/llvm/llvm-project/commit/ab97c9bdb747c873cd35a18229e2694156a7607d DIFF: https://github.com/llvm/llvm-project/commit/ab97c9bdb747c873cd35a18229e2694156a7607d.diff LOG: [

[llvm-branch-commits] [llvm] f6e885a - [ARM] Test for showing scalar vector costs. NFC

Author: David Green Date: 2020-12-12T11:43:14Z New Revision: f6e885ad2a94357f6f4d18ddf26a8111b3df7ed3 URL: https://github.com/llvm/llvm-project/commit/f6e885ad2a94357f6f4d18ddf26a8111b3df7ed3 DIFF: https://github.com/llvm/llvm-project/commit/f6e885ad2a94357f6f4d18ddf26a8111b3df7ed3.diff LOG: [

[llvm-branch-commits] [llvm] 3f571be - [ARM] Make t2DoLoopStartTP a terminator

Author: David Green Date: 2020-12-11T09:23:57Z New Revision: 3f571be1c07b48846f9c1ff31c088b00c3ef1f13 URL: https://github.com/llvm/llvm-project/commit/3f571be1c07b48846f9c1ff31c088b00c3ef1f13 DIFF: https://github.com/llvm/llvm-project/commit/3f571be1c07b48846f9c1ff31c088b00c3ef1f13.diff LOG: [

[llvm-branch-commits] [llvm] 0447f35 - [ARM][RegAlloc] Add t2LoopEndDec

Author: David Green Date: 2020-12-10T12:14:23Z New Revision: 0447f3508f0217e06b4acaaec0937091d071100a URL: https://github.com/llvm/llvm-project/commit/0447f3508f0217e06b4acaaec0937091d071100a DIFF: https://github.com/llvm/llvm-project/commit/0447f3508f0217e06b4acaaec0937091d071100a.diff LOG: [

[llvm-branch-commits] [llvm] 5abbf20 - [ARM] Additional test for Min loop. NFC

Author: David Green Date: 2020-12-10T10:49:00Z New Revision: 5abbf20f0fe5a1fed0d455bc682ca20d0eb651f7 URL: https://github.com/llvm/llvm-project/commit/5abbf20f0fe5a1fed0d455bc682ca20d0eb651f7 DIFF: https://github.com/llvm/llvm-project/commit/5abbf20f0fe5a1fed0d455bc682ca20d0eb651f7.diff LOG: [

[llvm-branch-commits] [llvm] b0ce615 - [ARM] Remove copies from low overhead phi inductions.

Author: David Green Date: 2020-12-10T10:30:31Z New Revision: b0ce615b2d29524b0b3541d07dd561665b710e79 URL: https://github.com/llvm/llvm-project/commit/b0ce615b2d29524b0b3541d07dd561665b710e79 DIFF: https://github.com/llvm/llvm-project/commit/b0ce615b2d29524b0b3541d07dd561665b710e79.diff LOG: [

[llvm-branch-commits] [llvm] eec5b99 - [ARM] MVE vcreate tests, for dual lane moves. NFC

Author: David Green Date: 2020-12-10T09:17:34Z New Revision: eec5b99901826852f13e11e7f807e175d434f1cd URL: https://github.com/llvm/llvm-project/commit/eec5b99901826852f13e11e7f807e175d434f1cd DIFF: https://github.com/llvm/llvm-project/commit/eec5b99901826852f13e11e7f807e175d434f1cd.diff LOG: [

[llvm-branch-commits] [llvm] 384383e - [ARM] Common inverse constant predicates to VPNOT

Author: David Green Date: 2020-12-09T07:56:44Z New Revision: 384383e15c177cd0dddae6b0999e527663fb3e22 URL: https://github.com/llvm/llvm-project/commit/384383e15c177cd0dddae6b0999e527663fb3e22 DIFF: https://github.com/llvm/llvm-project/commit/384383e15c177cd0dddae6b0999e527663fb3e22.diff LOG: [

[llvm-branch-commits] [llvm] 8254d70 - [ARM] Constant Mask VPT block tests. NFC

Author: David Green Date: 2020-12-09T07:44:49Z New Revision: 8254d70a38838af9a4bba7d1062f758fa2fc7214 URL: https://github.com/llvm/llvm-project/commit/8254d70a38838af9a4bba7d1062f758fa2fc7214 DIFF: https://github.com/llvm/llvm-project/commit/8254d70a38838af9a4bba7d1062f758fa2fc7214.diff LOG: [

[llvm-branch-commits] [llvm] 03e675f - [ARM] Turn pred_cast(xor(x, -1)) into xor(pred_cast(x), -1)

Author: David Green Date: 2020-12-08T15:22:46Z New Revision: 03e675fd128bed754454fc176357ad0ec6660c47 URL: https://github.com/llvm/llvm-project/commit/03e675fd128bed754454fc176357ad0ec6660c47 DIFF: https://github.com/llvm/llvm-project/commit/03e675fd128bed754454fc176357ad0ec6660c47.diff LOG: [

[llvm-branch-commits] [llvm] 91fb9ea - [ARM] Remove dead instructions before creating VPT block bundles

Author: David Green Date: 2020-12-08T14:05:07Z New Revision: 91fb9eac0b562cdfdc6b677f8ab2ee67f1ae1a77 URL: https://github.com/llvm/llvm-project/commit/91fb9eac0b562cdfdc6b677f8ab2ee67f1ae1a77 DIFF: https://github.com/llvm/llvm-project/commit/91fb9eac0b562cdfdc6b677f8ab2ee67f1ae1a77.diff LOG: [

[llvm-branch-commits] [llvm] c100d7b - [NFC] Chec[^k] -> Check

Author: David Green Date: 2020-12-08T11:54:39Z New Revision: c100d7ba36a5501bba6f7107a531323a51498bf6 URL: https://github.com/llvm/llvm-project/commit/c100d7ba36a5501bba6f7107a531323a51498bf6 DIFF: https://github.com/llvm/llvm-project/commit/c100d7ba36a5501bba6f7107a531323a51498bf6.diff LOG: [

[llvm-branch-commits] [llvm] d9bf624 - [ARM] Revert low overhead loops with calls before registry allocation.

Author: David Green Date: 2020-12-07T15:44:40Z New Revision: d9bf6245bfef41ad7606f0e64e0c4f12d65a2b46 URL: https://github.com/llvm/llvm-project/commit/d9bf6245bfef41ad7606f0e64e0c4f12d65a2b46 DIFF: https://github.com/llvm/llvm-project/commit/d9bf6245bfef41ad7606f0e64e0c4f12d65a2b46.diff LOG: [

[llvm-branch-commits] [llvm] 99eb0f1 - [Intrinsics] Re-remove experimental_vector_reduce intrinsics

Author: David Green Date: 2020-12-02T09:22:41Z New Revision: 99eb0f16c35cdaa04dea4c5bbad4f86408e9dcfd URL: https://github.com/llvm/llvm-project/commit/99eb0f16c35cdaa04dea4c5bbad4f86408e9dcfd DIFF: https://github.com/llvm/llvm-project/commit/99eb0f16c35cdaa04dea4c5bbad4f86408e9dcfd.diff LOG: [

[llvm-branch-commits] [llvm] eedf0ed - [ARM] Mark select and selectcc of MVE vector operations as expand.

Author: David Green Date: 2020-12-01T15:05:55Z New Revision: eedf0ed63e82ba2f8d2cbc12d6dae61035ed4f9a URL: https://github.com/llvm/llvm-project/commit/eedf0ed63e82ba2f8d2cbc12d6dae61035ed4f9a DIFF: https://github.com/llvm/llvm-project/commit/eedf0ed63e82ba2f8d2cbc12d6dae61035ed4f9a.diff LOG: [

[llvm-branch-commits] [llvm] 09d82fa - [AArch64] Update pass pipeline test. NFC

Author: David Green Date: 2020-12-01T10:40:04Z New Revision: 09d82fa95f4561a6a2ce80bce00209018ba70c24 URL: https://github.com/llvm/llvm-project/commit/09d82fa95f4561a6a2ce80bce00209018ba70c24 DIFF: https://github.com/llvm/llvm-project/commit/09d82fa95f4561a6a2ce80bce00209018ba70c24.diff LOG: [

[llvm-branch-commits] [llvm] 7923d71 - [ARM] PREDICATE_CAST demanded bits

Author: David Green Date: 2020-12-01T10:32:24Z New Revision: 7923d71b4a7a88f97c8a3efe1eb1473a4b2f5bf3 URL: https://github.com/llvm/llvm-project/commit/7923d71b4a7a88f97c8a3efe1eb1473a4b2f5bf3 DIFF: https://github.com/llvm/llvm-project/commit/7923d71b4a7a88f97c8a3efe1eb1473a4b2f5bf3.diff LOG: [

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