@@ -2432,12 +2437,40 @@ static void
tryToCreateAbstractReductionRecipe(VPReductionRecipe *Red,
Red->replaceAllUsesWith(AbstractR);
}
+/// This function tries to create an abstract recipe from a partial reduction
to
+/// hide its mul and extends from cost estimation.
+stati
@@ -986,11 +986,23 @@ InstructionCost TargetTransformInfo::getShuffleCost(
TargetTransformInfo::PartialReductionExtendKind
TargetTransformInfo::getPartialReductionExtendKind(Instruction *I) {
- if (isa(I))
-return PR_SignExtend;
- if (isa(I))
+ auto *Cast = dyn_cast(I);
@@ -2056,55 +2056,6 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe,
}
};
-/// A recipe for forming partial reductions. In the loop, an accumulator and
sdesmalen-arm wrote:
(We discussed this offline) swapping the operands in the debug-print functi
@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
sdesmale
@@ -2432,12 +2437,40 @@ static void
tryToCreateAbstractReductionRecipe(VPReductionRecipe *Red,
Red->replaceAllUsesWith(AbstractR);
}
+/// This function tries to create an abstract recipe from a partial reduction
to
+/// hide its mul and extends from cost estimation.
+stati
@@ -986,11 +986,23 @@ InstructionCost TargetTransformInfo::getShuffleCost(
TargetTransformInfo::PartialReductionExtendKind
TargetTransformInfo::getPartialReductionExtendKind(Instruction *I) {
- if (isa(I))
-return PR_SignExtend;
- if (isa(I))
+ auto *Cast = dyn_cast(I);
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/137683
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@@ -2496,6 +2501,9 @@ class VPMulAccumulateReductionRecipe : public
VPReductionRecipe {
Type *ResultTy;
+ /// If the reduction this is based on is a partial reduction.
sdesmalen-arm wrote:
This comment makes no sense.
https://github.com/llvm/llvm-projec
@@ -2438,14 +2438,14 @@
VPMulAccumulateReductionRecipe::computeCost(ElementCount VF,
return Ctx.TTI.getPartialReductionCost(
Instruction::Add, Ctx.Types.inferScalarType(getVecOp0()),
Ctx.Types.inferScalarType(getVecOp1()), getResultType(), VF,
-TTI:
https://github.com/sdesmalen-arm deleted
https://github.com/llvm/llvm-project/pull/136173
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@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
sdesmale
@@ -2056,55 +2056,6 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe,
}
};
-/// A recipe for forming partial reductions. In the loop, an accumulator and
sdesmalen-arm wrote:
Would it be possible to make the change of `VPPartialReductionRecipe : publ
@@ -219,6 +219,8 @@ class TargetTransformInfo {
/// Get the kind of extension that an instruction represents.
static PartialReductionExtendKind
getPartialReductionExtendKind(Instruction *I);
+ static PartialReductionExtendKind
+ getPartialReductionExtendKind(Instruction
sdesmalen-arm wrote:
@arsenm are you happy for me to reland this?
I've done better testing this time around; doing a two-stage build with
sanitisers enabled and running LNT on both X86 and AArch64 platforms.
https://github.com/llvm/llvm-project/pull/134408
_
@@ -5039,10 +5039,26 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+ElementCount VF = VFs[J];
+// The output from scaled phis and scaled reductions act
@@ -5039,10 +5039,25 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+// The output from scaled phis and scaled reductions actually have
+// fewer lanes
https://github.com/sdesmalen-arm commented:
You'll probably want to rebase on top of #126437 again, as some of the code has
changed and will cause a merge conflict.
https://github.com/llvm/llvm-project/pull/133090
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@@ -5039,10 +5039,25 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+// The output from scaled phis and scaled reductions actually have
+// fewer lanes
@@ -2,6 +2,7 @@
; RUN: opt -passes=loop-vectorize -enable-epilogue-vectorization=false
-mattr=+neon,+dotprod -force-vector-interleave=1 -S < %s | FileCheck %s
--check-prefixes=CHECK-INTERLEAVE1
; RUN: opt -passes=loop-vectorize -enable-epilogue-vectorization=false
-mattr=+neo
@@ -329,11 +329,10 @@ define <2 x half> @chain_hi_to_lo_global() {
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:v_mov_b32_e32 v0, 2
-; GFX11-TRUE16-NEXT:v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:
https://github.com/sdesmalen-arm approved this pull request.
There is no risk in adding this to the release branch, because all
functionality is hidden behind a flag. The TableGen/SubtargetEmitter.cpp change
should not affect anything, because it merely emits an extra `enum class` to
the `*Gen
https://github.com/sdesmalen-arm created
https://github.com/llvm/llvm-project/pull/121780
The code added in #116191 that updated the lanemasks for rematerialized
values checked if `DefMI`'s destination register had a subreg index.
This seems to have missed the following case:
```
%0:gpr32 = M
sdesmalen-arm wrote:
> Hi! How important are these backports for the release branch? Are they
> bugfixes? What's the risk of them?
Hi @tru, these are all bugfixes for things that would somehow lead to a
compilation failure when targeting AArch64 SME instructions. I don't see any
risks in cher
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/117695
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https://github.com/llvm/llvm-project/pull/117695
>From de526e5893e901c350fc9bd6d8013d7d1dbd42c6 Mon Sep 17 00:00:00 2001
From: Amara Emerson
Date: Tue, 13 Aug 2024 00:39:14 -0700
Subject: [PATCH 1/3] [AArch64][Darwin][SME] Don't try to save VG to the sta
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/117695
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https://github.com/sdesmalen-arm created
https://github.com/llvm/llvm-project/pull/117695
f314e12 uses `requiresSaveVG` which was introduced in 334a366ba792, which is
also missing from the release/19.x branch.
I figured it made sense to cherry-pick that one as well.
>From de526e5893e901c350fc9
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sdesmalen-arm wrote:
I think I need to create a new PR for this as Github doesn't allow me to reopen
and choose a different branch to merge into.
https://github.com/llvm/llvm-project/pull/114263
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sdesmalen-arm wrote:
Trying to reopen..
https://github.com/llvm/llvm-project/pull/114263
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sdesmalen-arm wrote:
It wasn't, but I also didn't realise that I closed it. Could Github have done
this automatically after the branch it was based of was deleted? (I was about
to push the rebased branch of this PR after merging #114391 and #114392)
https://github.com/llvm/llvm-project/pull/11
https://github.com/sdesmalen-arm closed
https://github.com/llvm/llvm-project/pull/114263
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https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/114392
>From 303e1c87e0ea835d5892afaa04c9e72d2d1778f4 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Thu, 31 Oct 2024 09:54:52 +
Subject: [PATCH] [TableGen] Fix calculation of Lanemask for RCs with
ar
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector ReservedHi = {
sdesmalen-arm wrote:
I don't think there is a bug; the code for moving an instruction goes through
the list of operands
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector ReservedHi = {
sdesmalen-arm wrote:
Without marking the registers as reserved, then for the example below:
```
---
name:sv2
https://github.com/sdesmalen-arm edited
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sdesmalen-arm wrote:
> Hi, since we are wrapping up LLVM 19.1.0 we are very strict with the fixes we
> pick at this point. Can you please respond to the following questions to help
> me understand if this has to be included in the final release or not.
Sure, I appreciate your diligence!
> Is
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/107406
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https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/106135
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sdesmalen-arm wrote:
Rationale; this helps people who use LLVM 19 to write code for the SME2.1
intrinsics, which the compiler already supports, but without the macros set a
user couldn't write compliant code, e.g. `#if defined __ARM_FEATURE_SME_B16B16,
, #endif`, because the macro would not be
https://github.com/sdesmalen-arm approved this pull request.
Thanks for making this change! The Clang/driver behaviour looks correct to me
now. The patch is a lot smaller than the patches that went into main, so
hopefully this can still make it into LLVM 19!
https://github.com/llvm/llvm-projec
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/101959
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sdesmalen-arm wrote:
> Is this safe enough to reland? Have it lived without a problem in main for a
> bit?
Thanks for checking. The only failures I would have expected are from lit
tests, but the PR was merged on Monday and I've not seen any buildbot failures,
so I believe it is safe.
There
https://github.com/sdesmalen-arm approved this pull request.
It would be good if this could make it into the LLVM 19 release.
https://github.com/llvm/llvm-project/pull/101007
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https://github.com/sdesmalen-arm requested changes to this pull request.
For some odd reason, `clang/test/CodeGen/aarch64-sme-inline-streaming-attrs.c`
seems to be failing on some buildbots with an error that says:
> `unable to create target: No available targets are compatible with triple
> "a
sdesmalen-arm wrote:
It would be great if we could merge this fix into the release branch!
https://github.com/llvm/llvm-project/pull/100546
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@@ -568,6 +568,48 @@ AArch64TTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
}
return Cost;
}
+ case Intrinsic::vector_extract: {
+// If both the vector argument and the return type are legal types and the
+// index is 0, then this should b
@@ -568,6 +568,48 @@ AArch64TTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
}
return Cost;
}
+ case Intrinsic::vector_extract: {
+// If both the vector argument and the return type are legal types and the
+// index is 0, then this should b
@@ -568,6 +568,32 @@ AArch64TTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
}
return Cost;
}
+ case Intrinsic::vector_extract: {
+// If both the vector argument and the return type are legal types, then
+// this should be a no-op or simple
https://github.com/sdesmalen-arm approved this pull request.
Looks pretty low-risk to me and would be nice to get into the release if we can.
(how is this PR different from #81593?)
https://github.com/llvm/llvm-project/pull/81616
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https://github.com/sdesmalen-arm approved this pull request.
Looks pretty low-risk to me and would be nice to get into the release if we can.
https://github.com/llvm/llvm-project/pull/81593
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Author: Sander de Smalen
Date: 2022-03-14T09:44:55Z
New Revision: 329fda39c507e8740978d10458451dcdb21563be
URL:
https://github.com/llvm/llvm-project/commit/329fda39c507e8740978d10458451dcdb21563be
DIFF:
https://github.com/llvm/llvm-project/commit/329fda39c507e8740978d10458451dcdb21563be.diff
L
Author: Sander de Smalen
Date: 2021-01-25T12:27:01Z
New Revision: 171d12489f20818e292362342b5665c689073ad2
URL:
https://github.com/llvm/llvm-project/commit/171d12489f20818e292362342b5665c689073ad2
DIFF:
https://github.com/llvm/llvm-project/commit/171d12489f20818e292362342b5665c689073ad2.diff
L
Author: Sander de Smalen
Date: 2021-01-25T11:26:56Z
New Revision: d196f9e2fca3ff767aa7d2dcaf4654724a79e18c
URL:
https://github.com/llvm/llvm-project/commit/d196f9e2fca3ff767aa7d2dcaf4654724a79e18c
DIFF:
https://github.com/llvm/llvm-project/commit/d196f9e2fca3ff767aa7d2dcaf4654724a79e18c.diff
L
Author: Sander de Smalen
Date: 2021-01-12T08:44:58Z
New Revision: c8a914db5c60dbeb5b638f30a9915855a67805f7
URL:
https://github.com/llvm/llvm-project/commit/c8a914db5c60dbeb5b638f30a9915855a67805f7
DIFF:
https://github.com/llvm/llvm-project/commit/c8a914db5c60dbeb5b638f30a9915855a67805f7.diff
L
Author: Sander de Smalen
Date: 2021-01-06T11:45:05Z
New Revision: aa280c99f708dca9dea96bc9070d6194d2622529
URL:
https://github.com/llvm/llvm-project/commit/aa280c99f708dca9dea96bc9070d6194d2622529
DIFF:
https://github.com/llvm/llvm-project/commit/aa280c99f708dca9dea96bc9070d6194d2622529.diff
L
Author: Sander de Smalen
Date: 2021-01-06T11:30:13Z
New Revision: 84a1120943a651184bae507fed5d648fee381ae4
URL:
https://github.com/llvm/llvm-project/commit/84a1120943a651184bae507fed5d648fee381ae4
DIFF:
https://github.com/llvm/llvm-project/commit/84a1120943a651184bae507fed5d648fee381ae4.diff
L
Author: Sander de Smalen
Date: 2021-01-06T10:43:48Z
New Revision: e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5
URL:
https://github.com/llvm/llvm-project/commit/e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5
DIFF:
https://github.com/llvm/llvm-project/commit/e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5.diff
L
Author: Sander de Smalen
Date: 2021-01-06T09:40:53Z
New Revision: a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf
URL:
https://github.com/llvm/llvm-project/commit/a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf
DIFF:
https://github.com/llvm/llvm-project/commit/a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf.diff
L
Author: Sander de Smalen
Date: 2021-01-06T09:36:51Z
New Revision: a9f5e4375b36e5316b8d6f9731be6bfa5a70e276
URL:
https://github.com/llvm/llvm-project/commit/a9f5e4375b36e5316b8d6f9731be6bfa5a70e276
DIFF:
https://github.com/llvm/llvm-project/commit/a9f5e4375b36e5316b8d6f9731be6bfa5a70e276.diff
L
Author: Sander de Smalen
Date: 2020-12-09T11:25:21Z
New Revision: d568cff696e8fb89ce1b040561c037412767af60
URL:
https://github.com/llvm/llvm-project/commit/d568cff696e8fb89ce1b040561c037412767af60
DIFF:
https://github.com/llvm/llvm-project/commit/d568cff696e8fb89ce1b040561c037412767af60.diff
L
Author: Sander de Smalen
Date: 2020-12-09T11:25:21Z
New Revision: adc37145dec9cadf76af05326150ed22a3cc2fdd
URL:
https://github.com/llvm/llvm-project/commit/adc37145dec9cadf76af05326150ed22a3cc2fdd
DIFF:
https://github.com/llvm/llvm-project/commit/adc37145dec9cadf76af05326150ed22a3cc2fdd.diff
L
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