[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split via Concat vector types for atomic load (PR #120640)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120640 >From 1dd74be335e6f087396091f2546b6a74ef128f03 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 16:25:55 -0500 Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for atomic load Vecto

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Widen <2 x T> vector types for atomic load (PR #120598)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120598 >From fc42ee7d2100a51bdf47db8b7919f4393afaa9ce Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 11:19:39 -0500 Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic load Vector ty

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split via Concat vector types for atomic load (PR #120640)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120640 >From 1dd74be335e6f087396091f2546b6a74ef128f03 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 16:25:55 -0500 Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for atomic load Vecto

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120716 >From a4b1e36c80ff37096ccfb41b84cf39a8a6405262 Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 20 Dec 2024 06:14:28 -0500 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Remove unused elements from atomic vector. (PR #125432)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/125432 >From b0d976b4858248fdf7dc3f638984f6394b12b3fd Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 31 Jan 2025 13:12:56 -0500 Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic vector. After spl

[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120385 >From d6cac89c8b9a864b029535420f87a141a5e140e7 Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:37:17 -0500 Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load `load atomic

[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for unaligned >1 sizes. (PR #120387)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120387 >From 3fd1c8a3fce161f17aef0cf58f234307e20df80b Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:40:32 -0500 Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes. Unaligned atomic ve

[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120386 >From 5a5f241f740896d6c8b86a0b912a757fcf518597 Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:38:23 -0500 Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG When lowering atom

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split via Concat vector types for atomic load (PR #120640)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120640 >From 7565845a3dd33fc1df7a771b165fbf095145f9d6 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 16:25:55 -0500 Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for atomic load Vecto

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Widen <2 x T> vector types for atomic load (PR #120598)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120598 >From e262387ca4870f7bae5de152b954461fa0311eb2 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 11:19:39 -0500 Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic load Vector ty

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135894 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135894 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135717 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135717 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)

koachan wrote: Hmm, changing my approach here. To make the patch much simpler, instead of trying to handle every combination of operations, this one will only handle the basic cases of literal `-(a+b)` and `-(a*b)`. Handling other equivalent patterns will be done in separate patches in the fut

[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

@@ -3588,8 +3588,13 @@ bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const { bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { - return Subtarget->isVIS() && (VT == MVT::f32

[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)

@@ -316,4 +316,17 @@ def : Pat<(i64 (sext (i32 (bitconvert f32:$src, (MOVSTOSW $src)>; def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>; def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>; def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>; + +// OP-then-neg

[llvm-branch-commits] [llvm] [AArch64][llvm] Pre-commit tests for #xxxxx (NFC) (PR #137702)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Jonathan Thackray (jthackray) Changes Add pre-commit tests for lowering atomicrmw `fminimum`/`fmaximum` to AArch64 assembler, in a subsequent change. --- Patch is 153.26 KiB, truncated to 20.00 KiB below, full version: https:/

[llvm-branch-commits] [llvm] [AArch64][llvm] Codegen for 16/32/64-bit floating-point atomicrmw fminimum/faximum (PR #137703)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Jonathan Thackray (jthackray) Changes Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and LD{B}FMIN atomic instructions. --- Patch is 71.76

[llvm-branch-commits] [compiler-rt] release/20.x: [sanitizer_common] Remove interceptors for deprecated struct termio (#137403) (PR #137707)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/137707 Backport 59978b21ad9c65276ee8e14f26759691b8a65763 Requested by: @tstellar >From 29b693e7af536fcd200e0b68db01ab29a46b11a3 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 28 Apr 2025 13:45:11 -0700 Subjec

[llvm-branch-commits] [compiler-rt] release/20.x: [sanitizer_common] Remove interceptors for deprecated struct termio (#137403) (PR #137707)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/137707 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] release/20.x: [sanitizer_common] Remove interceptors for deprecated struct termio (#137403) (PR #137707)

llvmbot wrote: @llvm/pr-subscribers-compiler-rt-sanitizer Author: None (llvmbot) Changes Backport 59978b21ad9c65276ee8e14f26759691b8a65763 Requested by: @tstellar --- Full diff: https://github.com/llvm/llvm-project/pull/137707.diff 3 Files Affected: - (modified) compiler-rt/lib/sanit

[llvm-branch-commits] [compiler-rt] release/20.x: [sanitizer_common] Remove interceptors for deprecated struct termio (#137403) (PR #137707)

llvmbot wrote: @enh-google What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/137707 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/li

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split via Concat vector types for atomic load (PR #120640)

@@ -1421,6 +1424,35 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { SetSplitVector(SDValue(N, ResNo), Lo, Hi); } +void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) { jofrn wrote: I had tried doing it by splitting L

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split via Concat vector types for atomic load (PR #120640)

@@ -1421,6 +1424,35 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { SetSplitVector(SDValue(N, ResNo), Lo, Hi); } +void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) { + SDLoc dl(LD); + + EVT MemoryVT = LD->getMemoryVT(); + unsigne

[llvm-branch-commits] [llvm] [MachinePipeliner] Introduce a new class for loop-carried deps (PR #137663)

llvmbot wrote: @llvm/pr-subscribers-backend-hexagon Author: Ryotaro Kasuga (kasuga-fj) Changes In MachinePipeliner, loop-carried memory dependencies are represented by DAG, which makes things complicated and causes some necessary dependencies to be missing. This patch introduces a new cl

[llvm-branch-commits] [llvm] [NFC] Refactoring MCDXBC to support out of order storage of root parameters (PR #137284)

https://github.com/joaosaffran reopened https://github.com/llvm/llvm-project/pull/137284 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] [RTSan] Cherry pick rtsan osspinlock fix to release/20.x (PR #137353)

https://github.com/thetruestblue reopened https://github.com/llvm/llvm-project/pull/137353 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] [RTSan] Cherry pick rtsan osspinlock fix to release/20.x (PR #137353)

https://github.com/thetruestblue closed https://github.com/llvm/llvm-project/pull/137353 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NFC] Refactoring MCDXBC to support out of order storage of root parameters (PR #137284)

https://github.com/joaosaffran closed https://github.com/llvm/llvm-project/pull/137284 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [flang][OpenMP] Overhaul implementation of ATOMIC construct (PR #137852)

llvmbot wrote: @llvm/pr-subscribers-flang-semantics @llvm/pr-subscribers-flang-openmp Author: Krzysztof Parzyszek (kparzysz) Changes The parser will accept a wide variety of illegal attempts at forming an ATOMIC construct, leaving it to the semantic analysis to diagnose any issues. This

[llvm-branch-commits] [llvm] [MachinePipeliner] Introduce a new class for loop-carried deps (PR #137663)

aankit-ca wrote: @kasuga-fj Should this PR be against the main branch? https://github.com/llvm/llvm-project/pull/137663 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-

[llvm-branch-commits] [compiler-rt] [RTSan] Cherry pick rtsan osspinlock fix to release/20.x (PR #137353)

https://github.com/thetruestblue updated https://github.com/llvm/llvm-project/pull/137353 >From 2453cd24fd5fb9778b55155f77bf9d05a49539f9 Mon Sep 17 00:00:00 2001 From: davidtrevelyan Date: Thu, 13 Mar 2025 10:18:25 + Subject: [PATCH 1/2] [rtsan][Apple] Add interceptor for _os_nospin_lock_lo

[llvm-branch-commits] [compiler-rt] [RTSan] Cherry pick rtsan osspinlock fix to release/20.x (PR #137353)

https://github.com/thetruestblue milestoned https://github.com/llvm/llvm-project/pull/137353 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [mlir] [mlir][OpenMP] cancel(lation point) taskgroup LLVMIR (PR #137841)

llvmbot wrote: @llvm/pr-subscribers-mlir-openmp @llvm/pr-subscribers-mlir Author: Tom Eccles (tblah) Changes A cancel or cancellation point for taskgroup is always nested inside of a task inside of the taskgroup. For the task which is cancelled, it is that task which needs to be cleaned

[llvm-branch-commits] [lld] release/20.x: [wasm-ld] Refactor WasmSym from static globals to per-link context (#134970) (PR #137620)

mcbarton wrote: > > Do you not build llvm from source in your project? Can't you therefore > > build from tip-of-tree? > > Hi, yes I think the latest changes on the release/latest_version.x branch is > being used for https://github.com/compiler-research/CppInterOp (@vgvassilev > or @mcbarton

[llvm-branch-commits] [llvm] [NFC] Refactoring DXContainerYaml Root Parameter representation (PR #138318)

https://github.com/joaosaffran updated https://github.com/llvm/llvm-project/pull/138318 >From b2bfb0257cfd424dafbc9a46542528ade42a17ad Mon Sep 17 00:00:00 2001 From: joaosaffran Date: Fri, 2 May 2025 00:42:56 + Subject: [PATCH 1/3] refactoring root signature dxcontainer yaml representation

[llvm-branch-commits] [llvm] [NFC] Refactoring DXContainerYaml Root Parameter representation (PR #138318)

@@ -37,17 +37,6 @@ Parts: ShaderRegister: 31 RegisterSpace: 32 DATA_STATIC_WHILE_SET_AT_EXECUTE: true - - ParameterType: 0 # SRV joaosaffran wrote: Need to rebase, that is why. It should go away on the next commit or two. ht

[llvm-branch-commits] [llvm] [NFC] Refactoring DXContainerYaml Root Parameter representation (PR #138318)

https://github.com/joaosaffran updated https://github.com/llvm/llvm-project/pull/138318 >From b2bfb0257cfd424dafbc9a46542528ade42a17ad Mon Sep 17 00:00:00 2001 From: joaosaffran Date: Fri, 2 May 2025 00:42:56 + Subject: [PATCH 1/4] refactoring root signature dxcontainer yaml representation

[llvm-branch-commits] [llvm] [NFC] Refactoring DXContainerYaml Root Parameter representation (PR #138318)

@@ -278,33 +280,35 @@ void DXContainerWriter::writeParts(raw_ostream &OS) { auto Header = dxbc::RootParameterHeader{Param.Type, Param.Visibility, Param.Offset}; -switch (Param.Type) { -case llvm::to_underl

[llvm-branch-commits] [llvm] e9b8c1e - Revert "[ms] [llvm-ml] Implement support for PROC NEAR/FAR (#131707)"

Author: Eric Astor Date: 2025-05-02T18:16:27-04:00 New Revision: e9b8c1ea6a7a7ead31f7e003408c794df2c8965a URL: https://github.com/llvm/llvm-project/commit/e9b8c1ea6a7a7ead31f7e003408c794df2c8965a DIFF: https://github.com/llvm/llvm-project/commit/e9b8c1ea6a7a7ead31f7e003408c794df2c8965a.diff LO

[llvm-branch-commits] [llvm] [NFC] Refactoring MCDXBC to support out of order storage of root parameters (PR #137284)

llvmbot wrote: @llvm/pr-subscribers-backend-directx Author: None (joaosaffran) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/137284.diff 4 Files Affected: - (modified) llvm/include/llvm/MC/DXContainerRootSignature.h (+73-7) - (modified) llvm/lib/MC/DXContainerRootS

[llvm-branch-commits] [llvm] [NFC] Refactoring MCDXBC to support out of order storage of root parameters (PR #137284)

https://github.com/joaosaffran ready_for_review https://github.com/llvm/llvm-project/pull/137284 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NFC] Refactoring MCDXBC to support out of order storage of root parameters (PR #137284)

https://github.com/joaosaffran edited https://github.com/llvm/llvm-project/pull/137284 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)

https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138399 >From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions c

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138400 None ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81) ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82) ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83) ELF_RELOC(R_SPARC_GOTDATA_OP, 84) +ELF_RELOC(R_SPARC_WDISP10, 88) koachan wrote: This is redundant with the one in PR

[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)

koachan wrote: Ping? https://github.com/llvm/llvm-project/pull/135717 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

koachan wrote: Ping? https://github.com/llvm/llvm-project/pull/135718 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)

llvmbot wrote: @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/138401.diff 6 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+5-2) - (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+17)

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Koakuma (koachan) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/138401.diff 6 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+5-2) - (modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (+17) - (modifie

[llvm-branch-commits] [SPARC][IAS][NFC] Rename CBCOND -> CPBCOND (PR #138402)

llvmbot wrote: @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) Changes This is in prep for OSA2011 instruction definitions, which has a CBCond instruction family. --- Full diff: https://github.com/llvm/llvm-project/pull/138402.diff 3 Files Affected: - (modified) llvm/lib/

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Koakuma (koachan) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/138400.diff 5 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+9-4) - (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+5) - (added) llvm

[llvm-branch-commits] [SPARC][IAS][NFC] Rename CBCOND -> CPBCOND (PR #138402)

https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138402 This is in prep for OSA2011 instruction definitions, which has a CBCond instruction family. ___ llvm-branch-commits mailing list [email protected] h

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138403 None ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)

llvmbot wrote: @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) Changes >From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instruct

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)

https://github.com/koachan created https://github.com/llvm/llvm-project/pull/138401 None ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

llvmbot wrote: @llvm/pr-subscribers-llvm-binary-utilities Author: Koakuma (koachan) Changes --- Patch is 56.90 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/138403.diff 15 Files Affected: - (modified) llvm/include/llvm/BinaryFormat/ELFRel

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Koakuma (koachan) Changes --- Patch is 56.90 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/138403.diff 15 Files Affected: - (modified) llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def (+1)

[llvm-branch-commits] [clang] release/20.x: [Clang] Fix the trailing comma regression (#136273) (PR #136283)

https://github.com/cor3ntin approved this pull request. Sorry, I was not near a computer last week. LGTM https://github.com/llvm/llvm-project/pull/136283 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi

[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/138400 >From b2e8de55ea9e54239a017eb932f7107f29f465a4 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 08:57:07 +0700 Subject: [PATCH] Add other instructions & fix typo Created using spr 1.3.5 --- llvm/li

[llvm-branch-commits] [llvm] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 >From 50422a4d24403ef55bf76ccd710511e8dec6b77d Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 09:33:39 +0700 Subject: [PATCH] Rework isFPImmLegal Created using spr 1.3.5 --- llvm/lib/Target/Sparc

[llvm-branch-commits] [llvm] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/138399 >From 8618666abc7028770617cd77adfc83c61550dbd0 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sat, 3 May 2025 20:50:21 +0700 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?= =?UTF-8?q?

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

@@ -0,0 +1,21 @@ +//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[llvm-branch-commits] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

@@ -3613,13 +3613,15 @@ bool SparcTargetLowering::isFNegFree(EVT VT) const { bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { + bool CanLower = false; if (VT != MVT::f32 && VT != MVT::f64)

[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

koachan wrote: > What about other instructions? (OTHERW, NORMALW, INVALWP) Added, thanks! https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/l

[llvm-branch-commits] [lld] [LLD][COFF] Don't dllimport from static libraries (#134443) (PR #138354)

llvmbot wrote: @llvm/pr-subscribers-lld-coff Author: Alexandre Ganea (aganea) Changes Backport https://github.com/llvm/llvm-project/pull/134443 on release/20.x: > This reverts commit 6a1bdd9 and re-instate behavior that matches what MSVC link.exe does, that is, error out when trying to d

[llvm-branch-commits] [clang] release/20.x: [clang-format] RemoveParentheses shouldn't remove empty… (PR #138380)

llvmbot wrote: @llvm/pr-subscribers-clang-format Author: Owen Pan (owenca) Changes … parentheses (#138229) Backport d3506ee573a2aa1403817642ef45f8c0305bb572 --- Full diff: https://github.com/llvm/llvm-project/pull/138380.diff 2 Files Affected: - (modified) clang/lib/Format/UnwrappedLi

[llvm-branch-commits] [llvm] "Recommit "[ConstraintElim] Simplify cmp after uadd.sat/usub.sat (#135603)" (PR #136467)

el-ev wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/136467?utm_source=stack-comment-downstack-mergeability-warning"; >

[llvm-branch-commits] [llvm] ARM: Avoid using getNumUses (PR #136355)

llvmbot wrote: @llvm/pr-subscribers-backend-arm Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/136355.diff 1 Files Affected: - (modified) llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp (+3-3) ``diff diff --git a/llvm/lib/T

[llvm-branch-commits] [llvm] AArch64: Use use_empty instead of getNumUses == 0 (PR #136356)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/136356.diff 1 Files Affected: - (modified) llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp (+4-4) ``diff diff --git a/llvm/lib/T

[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: clarify MCPlusBuilder callbacks interface (PR #136147)

llvmbot wrote: @llvm/pr-subscribers-bolt Author: Anatoly Trosinenko (atrosinenko) Changes Clarify the semantics of `getAuthenticatedReg` and remove a redundant `isAuthenticationOfReg` method, as combined auth+something instructions (such as `retaa` on AArch64) should be handled carefully

[llvm-branch-commits] [clang] Backport to 20.x "[clang][analyzer] Fix error path of builtin overflow (#136345)" (PR #136589)

llvmbot wrote: @llvm/pr-subscribers-clang-static-analyzer-1 Author: Pavel Skripkin (pskrgag) Changes According to https://clang.llvm.org/docs/LanguageExtensions.html#checked-arithmetic-builtins, result of builtin_*_overflow functions will be initialized even in case of overflow. Align an

[llvm-branch-commits] [libcxx] release/20.x: [libc++] Fix check for _LIBCPP_HAS_NO_WIDE_CHARACTERS in features.py (#131675) (PR #136449)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/136449 Backport f909b2229ac16ae3898d8b158bee85c384173dfa 297f6d9f6b215bd7f58cf500b979b94dedbba7bb Requested by: @mstorsjo >From 79e10b190029b749e042d1aaec3ee697a2f5d41a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin

[llvm-branch-commits] [libcxx] release/20.x: [libc++] Fix check for _LIBCPP_HAS_NO_WIDE_CHARACTERS in features.py (#131675) (PR #136449)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/136449 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libcxx] release/20.x: [libc++] Fix check for _LIBCPP_HAS_NO_WIDE_CHARACTERS in features.py (#131675) (PR #136449)

llvmbot wrote: @ldionne @mstorsjo What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/136449 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/ma

[llvm-branch-commits] [libcxx] release/20.x: [libc++] Fix check for _LIBCPP_HAS_NO_WIDE_CHARACTERS in features.py (#131675) (PR #136449)

llvmbot wrote: @llvm/pr-subscribers-libcxx Author: None (llvmbot) Changes Backport f909b2229ac16ae3898d8b158bee85c384173dfa 297f6d9f6b215bd7f58cf500b979b94dedbba7bb Requested by: @mstorsjo --- Full diff: https://github.com/llvm/llvm-project/pull/136449.diff 9 Files Affected: - (modif

[llvm-branch-commits] [clang] [CIR] Make UndefAttr use AttrBuilderWithInferredContext (PR #136605)

llvmbot wrote: @llvm/pr-subscribers-clangir Author: Henrich Lauko (xlauko) Changes This mirrors incubator changes from https://github.com/llvm/clangir/pull/1577 --- Full diff: https://github.com/llvm/llvm-project/pull/136605.diff 2 Files Affected: - (modified) clang/include/clang/CIR/D

[llvm-branch-commits] [clang] [CIR] Make UndefAttr use AttrBuilderWithInferredContext (PR #136605)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Henrich Lauko (xlauko) Changes This mirrors incubator changes from https://github.com/llvm/clangir/pull/1577 --- Full diff: https://github.com/llvm/llvm-project/pull/136605.diff 2 Files Affected: - (modified) clang/include/clang/CIR/Dia

[llvm-branch-commits] [clang] [CIR] Let ConstantOp builder infer its type automatically (PR #136606)

llvmbot wrote: @llvm/pr-subscribers-clangir Author: Henrich Lauko (xlauko) Changes This mirrors incubator changes from https://github.com/llvm/clangir/pull/1578 --- Full diff: https://github.com/llvm/llvm-project/pull/136606.diff 5 Files Affected: - (modified) clang/include/clang/CIR/D

[llvm-branch-commits] [clang] 61475ff - Revert "[Fuchsia] Disable PIC (#136376)"

Author: gulfemsavrun Date: 2025-04-21T14:33:31-07:00 New Revision: 61475ffa75fd202f8cd3d3ffdf547919b9f13f0d URL: https://github.com/llvm/llvm-project/commit/61475ffa75fd202f8cd3d3ffdf547919b9f13f0d DIFF: https://github.com/llvm/llvm-project/commit/61475ffa75fd202f8cd3d3ffdf547919b9f13f0d.diff

[llvm-branch-commits] [clang] e35cf35 - Revert "[HLSL] Make it possible to assign an array from a cbuffer (#134174)"

Author: Sarah Spall Date: 2025-04-21T09:27:45-07:00 New Revision: e35cf35feff443c6dd9fbc0b5ab00efa8e282fa0 URL: https://github.com/llvm/llvm-project/commit/e35cf35feff443c6dd9fbc0b5ab00efa8e282fa0 DIFF: https://github.com/llvm/llvm-project/commit/e35cf35feff443c6dd9fbc0b5ab00efa8e282fa0.diff L

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #138828)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Akshat Oke (optimisan) Changes This allows -passes option to target function passes in the codegen pipeline by their CL name. --- Full diff: https://github.com/llvm/llvm-project/pull/138828.diff 3 Files Affected: - (modified)

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120716 >From 72fd8a6b0d8d304992a804e7e05367389feedc2c Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 20 Dec 2024 06:14:28 -0500 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Remove unused elements from atomic vector. (PR #125432)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/125432 >From c5cfc13dc2b4c70860fddf9060805c57a932ba22 Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 31 Jan 2025 13:12:56 -0500 Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic vector. After spl

[llvm-branch-commits] [llvm] [SelectionDAG][X86] Remove unused elements from atomic vector. (PR #125432)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/125432 >From c5cfc13dc2b4c70860fddf9060805c57a932ba22 Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 31 Jan 2025 13:12:56 -0500 Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic vector. After spl

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #120640)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120640 >From 4783f04e8ce1786d3cb40e8573cd602b9f0979b5 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 16:25:55 -0500 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120385 >From c476a2452e64f7f6127ad0265c4c6aba7a08531a Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:37:17 -0500 Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load `load atomic

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #138635)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/138635 >From 939a68f81bd2add47607063c83123c252cc156c8 Mon Sep 17 00:00:00 2001 From: jofernau_amdeng Date: Tue, 6 May 2025 01:48:11 -0400 Subject: [PATCH] [X86] Remove extra MOV after widening atomic load This change ad

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120716 >From 8e1beaef4c295d500183bd82e1ddb0010128d4b2 Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 20 Dec 2024 06:14:28 -0500 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #120640)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120640 >From 4783f04e8ce1786d3cb40e8573cd602b9f0979b5 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 16:25:55 -0500 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #120640)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120640 >From 4783f04e8ce1786d3cb40e8573cd602b9f0979b5 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 19 Dec 2024 16:25:55 -0500 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for unaligned >1 sizes. (PR #120387)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120387 >From 01f388d501562796484ac3d1be8e29c27a33b702 Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:40:32 -0500 Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes. Unaligned atomic ve

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #138635)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/138635 >From 939a68f81bd2add47607063c83123c252cc156c8 Mon Sep 17 00:00:00 2001 From: jofernau_amdeng Date: Tue, 6 May 2025 01:48:11 -0400 Subject: [PATCH] [X86] Remove extra MOV after widening atomic load This change ad

[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120385 >From c476a2452e64f7f6127ad0265c4c6aba7a08531a Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:37:17 -0500 Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load `load atomic

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #138635)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/138635 >From 939a68f81bd2add47607063c83123c252cc156c8 Mon Sep 17 00:00:00 2001 From: jofernau_amdeng Date: Tue, 6 May 2025 01:48:11 -0400 Subject: [PATCH] [X86] Remove extra MOV after widening atomic load This change ad

[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120385 >From c476a2452e64f7f6127ad0265c4c6aba7a08531a Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 18 Dec 2024 03:37:17 -0500 Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load `load atomic

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/120716 >From 8e1beaef4c295d500183bd82e1ddb0010128d4b2 Mon Sep 17 00:00:00 2001 From: jofrn Date: Fri, 20 Dec 2024 06:14:28 -0500 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

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