[llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.32 - 1.33
---
Log message:
It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers if
it isn't inlined (at -O3). Force it to be inlined.
---
Diffs of the changes: (+3 -3)
X86Subtarget.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.32
llvm/lib/Target/X86/X86Subtarget.cpp:1.33
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.32 Wed Oct 4 13:33:00 2006
+++ llvm/lib/Target/X86/X86Subtarget.cppFri Oct 6 02:50:56 2006
@@ -28,7 +28,7 @@
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
the
/// specified arguments. If we can't run cpuid on the host, return true.
-static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
+static inline bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned
*rEBX,
unsigned *rECX, unsigned *rEDX) {
#if defined(__x86_64__)
asm (pushq\t%%rbx\n\t
@@ -76,8 +76,8 @@
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
if (GetCpuIDAndInfo(0x1, EAX, EBX, ECX, EDX))
return generic;
- unsigned Family = (EAX (0x (32 - 4)) 8) 8; // Bits 8 - 11
- unsigned Model = (EAX (0x (32 - 4)) 4) 4; // Bits 4 - 7
+ unsigned Family = (EAX 8) 0xf; // Bits 8 - 11
+ unsigned Model = (EAX 4) 0xf; // Bits 4 - 7
GetCpuIDAndInfo(0x8001, EAX, EBX, ECX, EDX);
bool Em64T = EDX (1 29);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/Makefile X86.td X86Subtarget.cpp X86Subtarget.h
Changes in directory llvm/lib/Target/X86: Makefile updated: 1.28 - 1.29 X86.td updated: 1.27 - 1.28 X86Subtarget.cpp updated: 1.34 - 1.35 X86Subtarget.h updated: 1.18 - 1.19 --- Log message: Still need to support -mcpu= or cross compilation will fail. Doh. --- Diffs of the changes: (+195 -7) Makefile |3 + X86.td | 73 + X86Subtarget.cpp | 107 +-- X86Subtarget.h | 19 - 4 files changed, 195 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/Makefile diff -u llvm/lib/Target/X86/Makefile:1.28 llvm/lib/Target/X86/Makefile:1.29 --- llvm/lib/Target/X86/Makefile:1.28 Fri Oct 6 03:21:07 2006 +++ llvm/lib/Target/X86/MakefileFri Oct 6 04:17:41 2006 @@ -14,6 +14,7 @@ BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ X86GenRegisterInfo.inc X86GenInstrNames.inc \ X86GenInstrInfo.inc X86GenAsmWriter.inc \ -X86GenAsmWriter1.inc X86GenDAGISel.inc +X86GenAsmWriter1.inc X86GenDAGISel.inc \ +X86GenSubtarget.inc include $(LEVEL)/Makefile.common Index: llvm/lib/Target/X86/X86.td diff -u llvm/lib/Target/X86/X86.td:1.27 llvm/lib/Target/X86/X86.td:1.28 --- llvm/lib/Target/X86/X86.td:1.27 Fri Oct 6 03:21:07 2006 +++ llvm/lib/Target/X86/X86.td Fri Oct 6 04:17:41 2006 @@ -17,6 +17,79 @@ include ../Target.td //===--===// +// X86 Subtarget features. +// + +def Feature64Bit : SubtargetFeature64bit, HasX86_64, true, +Support 64-bit instructions; +def FeatureMMX : SubtargetFeaturemmx,X86SSELevel, MMX, +Enable MMX instructions; +def FeatureSSE1 : SubtargetFeaturesse, X86SSELevel, SSE1, +Enable SSE instructions; +def FeatureSSE2 : SubtargetFeaturesse2, X86SSELevel, SSE2, +Enable SSE2 instructions; +def FeatureSSE3 : SubtargetFeaturesse3, X86SSELevel, SSE3, +Enable SSE3 instructions; +def Feature3DNow : SubtargetFeature3dnow, X863DNowLevel, ThreeDNow, +Enable 3DNow! instructions; +def Feature3DNowA: SubtargetFeature3dnowa, X863DNowLevel, ThreeDNowA, +Enable 3DNow! Athlon instructions; + +//===--===// +// X86 processors supported. +//===--===// + +class Procstring Name, listSubtargetFeature Features + : ProcessorName, NoItineraries, Features; + +def : Procgeneric, []; +def : Proci386,[]; +def : Proci486,[]; +def : Procpentium, []; +def : Procpentium-mmx, [FeatureMMX]; +def : Proci686,[]; +def : Procpentiumpro, []; +def : Procpentium2,[FeatureMMX]; +def : Procpentium3,[FeatureMMX, FeatureSSE1]; +def : Procpentium-m, [FeatureMMX, FeatureSSE1, FeatureSSE2]; +def : Procpentium4,[FeatureMMX, FeatureSSE1, FeatureSSE2]; +def : Procx86-64, [FeatureMMX, FeatureSSE1, FeatureSSE2, + Feature64Bit]; +def : Procyonah, [FeatureMMX, FeatureSSE1, FeatureSSE2, + FeatureSSE3]; +def : Procprescott,[FeatureMMX, FeatureSSE1, FeatureSSE2, + FeatureSSE3]; +def : Procnocona, [FeatureMMX, FeatureSSE1, FeatureSSE2, + FeatureSSE3, Feature64Bit]; +def : Proccore2, [FeatureMMX, FeatureSSE1, FeatureSSE2, + FeatureSSE3, Feature64Bit]; + +def : Prock6, [FeatureMMX]; +def : Prock6-2,[FeatureMMX, Feature3DNow]; +def : Prock6-3,[FeatureMMX, Feature3DNow]; +def : Procathlon, [FeatureMMX, Feature3DNow, Feature3DNowA]; +def : Procathlon-tbird,[FeatureMMX, Feature3DNow, Feature3DNowA]; +def : Procathlon-4,[FeatureMMX, FeatureSSE1, Feature3DNow, + Feature3DNowA]; +def : Procathlon-xp, [FeatureMMX, FeatureSSE1, Feature3DNow, + Feature3DNowA]; +def : Procathlon-mp, [FeatureMMX, FeatureSSE1, Feature3DNow, + Feature3DNowA]; +def : Prock8, [FeatureMMX, FeatureSSE1, FeatureSSE2, + Feature3DNow, Feature3DNowA, Feature64Bit]; +def : Procopteron, [FeatureMMX, FeatureSSE1, FeatureSSE2, + Feature3DNow, Feature3DNowA, Feature64Bit]; +def : Procathlon64,[FeatureMMX, FeatureSSE1, FeatureSSE2, + Feature3DNow, Feature3DNowA, Feature64Bit]; +def : Procathlon-fx,
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.54 - 1.55
---
Log message:
fix some bugs affecting functions with no arguments
---
Diffs of the changes: (+4 -2)
ARMISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.54
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.55
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.54Fri Oct 6 07:50:22 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Oct 6 12:26:30 2006
@@ -181,6 +181,8 @@
}
unsigned getStackSize(void) {
int last = is_reg.size() - 1;
+if (last 0)
+ return 0;
if (isRegister(last))
return 0;
return getOffset(last) + MVT::getSizeInBits(getType(last))/8;
@@ -193,7 +195,7 @@
last--;
return last;
}
- unsigned lastRegNum(void) {
+ int lastRegNum(void) {
intl = lastRegArg();
if (l 0)
return -1;
@@ -264,7 +266,7 @@
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDOperand InFlag;
- for (unsigned i = 0, e = Layout.lastRegArg(); i = e; ++i) {
+ for (int i = 0, e = Layout.lastRegArg(); i = e; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
unsigned RegNum = Layout.getRegisterNum(i);
unsigned Reg1 = regs[RegNum];
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.403 - 1.404
---
Log message:
Fix a miscompilation of:
long long foo(long long X) {
return (long long)(signed char)(int)X;
}
Instead of:
_foo:
extsb r2, r4
srawi r3, r4, 31
mr r4, r2
blr
we now produce:
_foo:
extsb r4, r4
srawi r3, r4, 31
blr
This fixes a miscompilation in ConstantFolding.cpp.
---
Diffs of the changes: (+5 -3)
LegalizeDAG.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.403
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.403 Thu Oct 5 17:57:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 6 12:34:12 2006
@@ -4349,12 +4349,14 @@
case ISD::SIGN_EXTEND_INREG:
ExpandOp(Node-getOperand(0), Lo, Hi);
-// Sign extend the lo-part.
+// sext_inreg the low part if needed.
+Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node-getOperand(1));
+
+// The high part gets the sign extension from the lo-part. This handles
+// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
DAG.getConstant(MVT::getSizeInBits(NVT)-1,
TLI.getShiftAmountTy()));
-// sext_inreg the low part if needed.
-Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node-getOperand(1));
break;
case ISD::BSWAP: {
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[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.140 - 1.141
---
Log message:
ugly codegen
---
Diffs of the changes: (+22 -0)
README.txt | 22 ++
1 files changed, 22 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.140
llvm/lib/Target/X86/README.txt:1.141
--- llvm/lib/Target/X86/README.txt:1.140Fri Oct 6 03:21:07 2006
+++ llvm/lib/Target/X86/README.txt Fri Oct 6 12:39:34 2006
@@ -711,4 +711,26 @@
into x.h == 0
+//===-===//
+We currently compile sign_extend_inreg into two shifts:
+
+long foo(long X) {
+ return (long)(signed char)X;
+}
+
+becomes:
+
+_foo:
+movl 4(%esp), %eax
+shll $24, %eax
+sarl $24, %eax
+ret
+
+This could be:
+
+_foo:
+movsbl 4(%esp),%eax
+ret
+
+//===-===//
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[llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.35 - 1.36
---
Log message:
80 col violation.
---
Diffs of the changes: (+4 -3)
X86Subtarget.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.35
llvm/lib/Target/X86/X86Subtarget.cpp:1.36
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.35 Fri Oct 6 04:17:41 2006
+++ llvm/lib/Target/X86/X86Subtarget.cppFri Oct 6 13:57:51 2006
@@ -28,8 +28,9 @@
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
the
/// specified arguments. If we can't run cpuid on the host, return true.
-static inline bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned
*rEBX,
-unsigned *rECX, unsigned *rEDX) {
+static inline bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
+ unsigned *rEBX, unsigned *rECX,
+ unsigned *rEDX) {
#if defined(__x86_64__)
asm (pushq\t%%rbx\n\t
cpuid\n\t
@@ -103,7 +104,7 @@
unsigned Family = (EAX 8) 0xf; // Bits 8 - 11
unsigned Model = (EAX 4) 0xf; // Bits 4 - 7
GetCpuIDAndInfo(0x8001, EAX, EBX, ECX, EDX);
- bool Em64T = EDX (1 29);
+ bool Em64T = (EDX 29) 0x1;
union {
unsigned u[3];
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[llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/454.calculix/Makefile
Changes in directory llvm-test/External/SPEC/CFP2006/454.calculix: Makefile updated: 1.4 - 1.5 --- Log message: Another fix for the caluculix test. It was getting header files from the wrong place. Blast! --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/External/SPEC/CFP2006/454.calculix/Makefile diff -u llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.4 llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.5 --- llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.4 Wed Sep 27 16:57:16 2006 +++ llvm-test/External/SPEC/CFP2006/454.calculix/Makefile Fri Oct 6 15:07:58 2006 @@ -234,10 +234,10 @@ -I$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxManager/src \ -I$(SPEC_BENCH_DIR)/src/SPOOLES/SymbFac/src \ -I$(SPEC_BENCH_DIR)/src/SPOOLES/Tree/src \ - -I$(SPEC_BENCH_DIR)/src/SPOOLES/Utilities/src \ -I$(SPEC_BENCH_DIR)/src/SPOOLES/ZV/src\ -I$(SPEC_BENCH_DIR)/src/SPOOLES/misc/src \ -I$(SPEC_BENCH_DIR)/src/SPOOLES \ + -I$(SPEC_BENCH_DIR)/src/SPOOLES/Utilities/src \ -I$(SPEC_BENCH_DIR)/src \ -I$(SPEC_BENCH_DIR)/src/include ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile
Changes in directory llvm-test/External/SPEC/CFP2006/459.GemsFDTD: Makefile updated: 1.2 - 1.3 --- Log message: Added dependencies so that things build properly --- Diffs of the changes: (+15 -0) Makefile | 15 +++ 1 files changed, 15 insertions(+) Index: llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile diff -u llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile:1.2 llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile:1.3 --- llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile:1.2 Wed Sep 6 15:41:12 2006 +++ llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile Fri Oct 6 15:29:30 2006 @@ -17,3 +17,18 @@ else STDOUT_FILENAME := train.log endif + +GemsFDTD.c: parameter.c readdata.c leapfrog.c +NFT.c: parameter.c globalvar.c posvector.c fourier_transf.c errorcheck.c huygens.c excite.c +PEC.c: parameter.c errorcheck.c readline.c globalvar.c +UPML.c: parameter.c globalvar.c errorcheck.c PEC.c +calcflops.c: globalvar.c parameter.c huygens.c UPML.c NFT.c +excite.c: parameter.c globalvar.c +fourier_transf.c: parameter.c +globalvar.c: parameter.c +huygens.c: parameter.c globalvar.c excite.c errorcheck.c +leapfrog.c: errorcheck.c parameter.c huygens.c update.c UPML.c PEC.c NFT.c calcflops.c globalvar.c progress.c +posvector.c: parameter.c +progress.c: parameter.c globalvar.c +readdata.c: parameter.c globalvar.c errorcheck.c huygens.c UPML.c excite.c NFT.c PEC.c progress.c +update.c: parameter.c globalvar.c ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.56 - 1.57
ARMInstrInfo.td updated: 1.32 - 1.33
---
Log message:
add optional input flag to FMRRD
---
Diffs of the changes: (+4 -3)
ARMISelDAGToDAG.cpp |4 ++--
ARMInstrInfo.td |3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.56
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.57
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.56Fri Oct 6 14:10:05 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Oct 6 15:33:26 2006
@@ -284,8 +284,8 @@
Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
SDVTListVTs = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg}; //missing flag
- Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+ SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag};
+ Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4);
} else {
if (VT == MVT::f32)
Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.32
llvm/lib/Target/ARM/ARMInstrInfo.td:1.33
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.32Thu Oct 5 11:48:49 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Fri Oct 6 15:33:26 2006
@@ -78,7 +78,8 @@
def armfsitod : SDNodeARMISD::FSITOD, SDTUnaryOp;
def SDTarmfmrrd: SDTypeProfile0, 3, [SDTCisInt0, SDTCisInt1,
SDTCisFP2];
-def armfmrrd : SDNodeARMISD::FMRRD, SDTarmfmrrd, [SDNPHasChain,
SDNPOutFlag];
+def armfmrrd : SDNodeARMISD::FMRRD, SDTarmfmrrd,
+[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag];
def SDTarmfmdrr: SDTypeProfile1, 2, [SDTCisFP0, SDTCisInt1,
SDTCisInt2];
def armfmdrr : SDNodeARMISD::FMDRR, SDTarmfmdrr, [];
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[llvm-commits] CVS: llvm/lib/CodeGen/MachineBasicBlock.cpp
Changes in directory llvm/lib/CodeGen:
MachineBasicBlock.cpp updated: 1.31 - 1.32
---
Log message:
print labels even if a MBB doesn't have a corresponding LLVM BB, just don't
print the LLVM BB label.
---
Diffs of the changes: (+4 -3)
MachineBasicBlock.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.31
llvm/lib/CodeGen/MachineBasicBlock.cpp:1.32
--- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.31 Thu Oct 5 20:12:44 2006
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp Fri Oct 6 16:28:17 2006
@@ -94,9 +94,10 @@
}
const BasicBlock *LBB = getBasicBlock();
- if (LBB)
-OS \n LBB-getName() ( (const void*)this
-, LLVM BB @ (const void*) LBB , ID# getNumber()
):\n;
+ OS \n;
+ if (LBB) OS LBB-getName();
+ OS ( (const void*)this
+ , LLVM BB @ (const void*) LBB , ID# getNumber() ):\n;
// Print the preds of this block according to the CFG.
if (!pred_empty()) {
OS Predecessors according to CFG:;
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[llvm-commits] llvm-gcc commit (dwarf2)
This fixes the build on mingw. Anton K wrote this patch: dwarf.diff Description: Binary data -Chris___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.283 - 1.284
---
Log message:
jump tables handle pic
---
Diffs of the changes: (+0 -5)
SelectionDAGISel.cpp |5 -
1 files changed, 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.283
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.284
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.283Thu Oct 5
17:57:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Oct 6 17:32:29 2006
@@ -846,11 +846,6 @@
}
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable JT) {
- // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
- // we need to add the address of the jump table to the value loaded, since
- // the entries in the jump table will be differences rather than absolute
- // addresses.
-
// Emit the code for the jump table
MVT::ValueType PTy = TLI.getPointerTy();
assert((PTy == MVT::i32 || PTy == MVT::i64)
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.79 - 1.80
---
Log message:
Add support for targets to declare that they use a GOT
---
Diffs of the changes: (+11 -0)
TargetLowering.h | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.79
llvm/include/llvm/Target/TargetLowering.h:1.80
--- llvm/include/llvm/Target/TargetLowering.h:1.79 Tue Oct 3 19:50:21 2006
+++ llvm/include/llvm/Target/TargetLowering.h Fri Oct 6 17:46:34 2006
@@ -85,6 +85,10 @@
MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling;
}
+ /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
+ /// codegen.
+ bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
+
/// isSetCCExpensive - Return true if the setcc operation is expensive for
/// this target.
bool isSetCCExpensive() const { return SetCCIsExpensive; }
@@ -469,6 +473,9 @@
//
protected:
+ /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
+ /// GOT for PC-relative code.
+ void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
/// setShiftAmountType - Describe the type that should be used for shift
/// amounts. This type defaults to the pointer type.
@@ -731,6 +738,10 @@
///
MVT::ValueType PointerTy;
+ /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
+ ///
+ bool UsesGlobalOffsetTable;
+
/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
/// PointerTy is.
MVT::ValueType ShiftAmountTy;
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.64 - 1.65 --- Log message: Alpha uses a got --- Diffs of the changes: (+2 -0) AlphaISelLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.64 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.65 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.64Thu Oct 5 17:59:48 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Fri Oct 6 17:46:51 2006 @@ -44,6 +44,8 @@ setSetCCResultType(MVT::i64); setSetCCResultContents(ZeroOrOneSetCCResult); + setUsesGlobalOffsetTable(true); + addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.107 - 1.108
---
Log message:
If a target uses a GOT, put it in the jt data section, not the text
section. This will fix alpha when Andrew implements
AlphaTargetMachine::getTargetLowering().
---
Diffs of the changes: (+12 -4)
AsmPrinter.cpp | 16
1 files changed, 12 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.107
llvm/lib/CodeGen/AsmPrinter.cpp:1.108
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.107 Thu Oct 5 16:40:14 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Fri Oct 6 17:50:56 2006
@@ -22,6 +22,7 @@
#include llvm/Support/MathExtras.h
#include llvm/Target/TargetAsmInfo.h
#include llvm/Target/TargetData.h
+#include llvm/Target/TargetLowering.h
#include llvm/Target/TargetMachine.h
#include iostream
#include cerrno
@@ -200,10 +201,17 @@
// Pick the directive to use to print the jump table entries, and switch to
// the appropriate section.
if (TM.getRelocationModel() == Reloc::PIC_) {
-// In PIC mode, we need to emit the jump table to the same section as the
-// function body itself, otherwise the label differences won't make sense.
-const Function *F = MF.getFunction();
-SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
+TargetLowering *LoweringInfo = TM.getTargetLowering();
+if (LoweringInfo LoweringInfo-usesGlobalOffsetTable()) {
+ SwitchToDataSection(TAI-getJumpTableDataSection(), 0);
+ if (TD-getPointerSize() == 8)
+JTEntryDirective = TAI-getData64bitsDirective();
+} else {
+ // In PIC mode, we need to emit the jump table to the same section as the
+ // function body itself, otherwise the label differences won't make
sense.
+ const Function *F = MF.getFunction();
+ SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
+}
} else {
SwitchToDataSection(TAI-getJumpTableDataSection(), 0);
if (TD-getPointerSize() == 8)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: TargetLowering.cpp updated: 1.73 - 1.74 --- Log message: initialize ivar --- Diffs of the changes: (+1 -0) TargetLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.73 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.74 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.73 Tue Oct 3 19:52:21 2006 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppFri Oct 6 17:52:08 2006 @@ -30,6 +30,7 @@ memset(LoadXActions, 0, sizeof(LoadXActions)); IsLittleEndian = TD-isLittleEndian(); + UsesGlobalOffsetTable = false; ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD-getIntPtrType()); ShiftAmtHandling = Undefined; memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaTargetAsmInfo.cpp updated: 1.3 - 1.4 --- Log message: Set the jt section --- Diffs of the changes: (+1 -0) AlphaTargetAsmInfo.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp:1.3 llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp:1.4 --- llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp:1.3Wed Oct 4 22:13:59 2006 +++ llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cppFri Oct 6 17:52:33 2006 @@ -19,4 +19,5 @@ AlignmentIsInBytes = false; PrivateGlobalPrefix = $; JumpTableDirective = .gprel32; + JumpTableDataSection = \t.section .rodata\n; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.404 - 1.405 --- Log message: Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom part was always forced to be sextload, even when we needed an zextload. --- Diffs of the changes: (+2 -3) LegalizeDAG.cpp |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.405 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404 Fri Oct 6 12:34:12 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 6 19:58:36 2006 @@ -4474,13 +4474,12 @@ SDOperand Chain = Node-getOperand(0); SDOperand Ptr = Node-getOperand(1); MVT::ValueType EVT = castVTSDNode(Node-getOperand(3))-getVT(); -unsigned LType = Node-getConstantOperandVal(4); +ISD::LoadExtType LType = (ISD::LoadExtType)Node-getConstantOperandVal(4); if (EVT == NVT) Lo = DAG.getLoad(NVT, Chain, Ptr, Node-getOperand(2)); else - Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node-getOperand(2), - EVT); + Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node-getOperand(2), EVT); // Remember that we legalized the chain. AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.133 - 1.134
---
Log message:
eliminate redundancy
---
Diffs of the changes: (+32 -60)
X86InstrSSE.td | 92 +++--
1 files changed, 32 insertions(+), 60 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.133
llvm/lib/Target/X86/X86InstrSSE.td:1.134
--- llvm/lib/Target/X86/X86InstrSSE.td:1.133Tue Oct 3 01:55:11 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Oct 6 23:52:09 2006
@@ -2289,66 +2289,38 @@
Requires[HasSSE2];
// bit_convert
-def : Pat(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
+let Predicates = [HasSSE2] in {
+ def : Pat(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.134 - 1.135
---
Log message:
Remove RSQRTSS[rm] RCPSS[rm], which are dead.
Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].
---
Diffs of the changes: (+16 -21)
X86InstrSSE.td | 37 -
1 files changed, 16 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.134
llvm/lib/Target/X86/X86InstrSSE.td:1.135
--- llvm/lib/Target/X86/X86InstrSSE.td:1.134Fri Oct 6 23:52:09 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:09:48 2006
@@ -194,6 +194,15 @@
class SS_Intmbits8 o, string asm, Intrinsic IntId
: SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
+
+
+multiclass SS_IntUnarybits8 o, string asm, Intrinsic IntId {
+ def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
+ def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+ [(set VR128:$dst, (v4f32 (IntId (load addr:$src];
+}
+
class SD_Intrbits8 o, string asm, Intrinsic IntId
: SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
[(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
@@ -380,15 +389,6 @@
sqrtsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))];
-def RSQRTSSr : SSI0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- rsqrtss {$src, $dst|$dst, $src}, [];
-def RSQRTSSm : SSI0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- rsqrtss {$src, $dst|$dst, $src}, [];
-def RCPSSr : SSI0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- rcpss {$src, $dst|$dst, $src}, [];
-def RCPSSm : SSI0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- rcpss {$src, $dst|$dst, $src}, [];
-
let isTwoAddress = 1 in {
let isCommutable = 1 in {
def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
@@ -451,23 +451,18 @@
int_x86_sse2_sub_sd;
}
-def Int_SQRTSSr : SS_Intr0x51, sqrtss {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ss;
-def Int_SQRTSSm : SS_Intm0x51, sqrtss {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ss;
+defm Int_SQRTSS : SS_IntUnary0x51, sqrtss {$src, $dst|$dst, $src},
+ int_x86_sse_sqrt_ss;
+
def Int_SQRTSDr : SD_Intr0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
def Int_SQRTSDm : SD_Intm0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
-def Int_RSQRTSSr : SS_Intr0x52, rsqrtss {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ss;
-def Int_RSQRTSSm : SS_Intm0x52, rsqrtss {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ss;
-def Int_RCPSSr : SS_Intr0x53, rcpss {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ss;
-def Int_RCPSSm : SS_Intm0x53, rcpss {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ss;
+defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss {$src, $dst|$dst, $src},
+ int_x86_sse_rsqrt_ss;
+defm Int_RCPSS : SS_IntUnary0x53, rcpss {$src, $dst|$dst, $src},
+ int_x86_sse_rcp_ss;
let isTwoAddress = 1 in {
let isCommutable = 1 in {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.135 - 1.136
---
Log message:
pull operand string into the multiclass
---
Diffs of the changes: (+9 -10)
X86InstrSSE.td | 19 +--
1 files changed, 9 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.135
llvm/lib/Target/X86/X86InstrSSE.td:1.136
--- llvm/lib/Target/X86/X86InstrSSE.td:1.135Sat Oct 7 00:09:48 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:13:26 2006
@@ -196,10 +196,12 @@
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
-multiclass SS_IntUnarybits8 o, string asm, Intrinsic IntId {
- def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+multiclass SS_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
+ def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
- def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+ def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
}
@@ -451,19 +453,16 @@
int_x86_sse2_sub_sd;
}
-defm Int_SQRTSS : SS_IntUnary0x51, sqrtss {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ss;
+defm Int_SQRTSS : SS_IntUnary0x51, sqrtss , int_x86_sse_sqrt_ss;
+defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss, int_x86_sse_rsqrt_ss;
+defm Int_RCPSS : SS_IntUnary0x53, rcpss , int_x86_sse_rcp_ss;
+
def Int_SQRTSDr : SD_Intr0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
def Int_SQRTSDm : SD_Intm0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
-defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ss;
-defm Int_RCPSS : SS_IntUnary0x53, rcpss {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ss;
-
let isTwoAddress = 1 in {
let isCommutable = 1 in {
def Int_MAXSSrr : SS_Intrr0x5F, maxss {$src2, $dst|$dst, $src2},
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.136 - 1.137
---
Log message:
convert the sole sd unary intrinsic to a multiclass for consistency
---
Diffs of the changes: (+9 -19)
X86InstrSSE.td | 28 +---
1 files changed, 9 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.136
llvm/lib/Target/X86/X86InstrSSE.td:1.137
--- llvm/lib/Target/X86/X86InstrSSE.td:1.136Sat Oct 7 00:13:26 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:19:31 2006
@@ -188,13 +188,6 @@
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
-class SS_Intrbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
-[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
-class SS_Intmbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
-[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
-
multiclass SS_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@@ -205,12 +198,14 @@
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
}
-class SD_Intrbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
-[(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
-class SD_Intmbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
-[(set VR128:$dst, (v2f64 (IntId (load addr:$src];
+multiclass SD_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
+ def r : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
+ def m : SDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ [(set VR128:$dst, (v2f64 (IntId (load addr:$src];
+}
class SS_Intrrbits8 o, string asm, Intrinsic IntId
: SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
@@ -454,15 +449,10 @@
}
defm Int_SQRTSS : SS_IntUnary0x51, sqrtss , int_x86_sse_sqrt_ss;
+defm Int_SQRTSD : SD_IntUnary0x51, sqrtsd , int_x86_sse2_sqrt_sd;
defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss, int_x86_sse_rsqrt_ss;
defm Int_RCPSS : SS_IntUnary0x53, rcpss , int_x86_sse_rcp_ss;
-
-def Int_SQRTSDr : SD_Intr0x51, sqrtsd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_sd;
-def Int_SQRTSDm : SD_Intm0x51, sqrtsd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_sd;
-
let isTwoAddress = 1 in {
let isCommutable = 1 in {
def Int_MAXSSrr : SS_Intrr0x5F, maxss {$src2, $dst|$dst, $src2},
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.137 - 1.138
---
Log message:
Pull operand info up into parent class for scalar sse intrinsics.
---
Diffs of the changes: (+41 -61)
X86InstrSSE.td | 102 ++---
1 files changed, 41 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.137
llvm/lib/Target/X86/X86InstrSSE.td:1.138
--- llvm/lib/Target/X86/X86InstrSSE.td:1.137Sat Oct 7 00:19:31 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:26:13 2006
@@ -207,17 +207,21 @@
[(set VR128:$dst, (v2f64 (IntId (load addr:$src];
}
-class SS_Intrrbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class SS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
-class SS_Intrmbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
+class SS_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
-class SD_Intrrbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class SD_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
-class SD_Intrmbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
+class SD_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
class PS_Intrbits8 o, string asm, Intrinsic IntId
@@ -410,42 +414,26 @@
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def Int_ADDSSrr : SS_Intrr0x58, addss {$src2, $dst|$dst, $src2},
- int_x86_sse_add_ss;
-def Int_ADDSDrr : SD_Intrr0x58, addsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_add_sd;
-def Int_MULSSrr : SS_Intrr0x59, mulss {$src2, $dst|$dst, $src2},
- int_x86_sse_mul_ss;
-def Int_MULSDrr : SD_Intrr0x59, mulsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_mul_sd;
-}
-
-def Int_ADDSSrm : SS_Intrm0x58, addss {$src2, $dst|$dst, $src2},
- int_x86_sse_add_ss;
-def Int_ADDSDrm : SD_Intrm0x58, addsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_add_sd;
-def Int_MULSSrm : SS_Intrm0x59, mulss {$src2, $dst|$dst, $src2},
- int_x86_sse_mul_ss;
-def Int_MULSDrm : SD_Intrm0x59, mulsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_mul_sd;
-
-def Int_DIVSSrr : SS_Intrr0x5E, divss {$src2, $dst|$dst, $src2},
- int_x86_sse_div_ss;
-def Int_DIVSSrm : SS_Intrm0x5E, divss {$src2, $dst|$dst, $src2},
- int_x86_sse_div_ss;
-def Int_DIVSDrr : SD_Intrr0x5E, divsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_div_sd;
-def Int_DIVSDrm : SD_Intrm0x5E, divsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_div_sd;
-
-def Int_SUBSSrr : SS_Intrr0x5C, subss {$src2, $dst|$dst, $src2},
- int_x86_sse_sub_ss;
-def Int_SUBSSrm : SS_Intrm0x5C, subss {$src2, $dst|$dst, $src2},
- int_x86_sse_sub_ss;
-def Int_SUBSDrr : SD_Intrr0x5C, subsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_sub_sd;
-def Int_SUBSDrm : SD_Intrm0x5C, subsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_sub_sd;
+def Int_ADDSSrr : SS_Intrr0x58, addss, int_x86_sse_add_ss;
+def Int_ADDSDrr : SD_Intrr0x58, addsd, int_x86_sse2_add_sd;
+def Int_MULSSrr : SS_Intrr0x59, mulss, int_x86_sse_mul_ss;
+def Int_MULSDrr : SD_Intrr0x59, mulsd, int_x86_sse2_mul_sd;
+}
+
+def Int_ADDSSrm : SS_Intrm0x58, addss, int_x86_sse_add_ss;
+def Int_ADDSDrm : SD_Intrm0x58, addsd, int_x86_sse2_add_sd;
+def Int_MULSSrm : SS_Intrm0x59, mulss, int_x86_sse_mul_ss;
+def Int_MULSDrm : SD_Intrm0x59, mulsd, int_x86_sse2_mul_sd;
+
+def Int_DIVSSrr : SS_Intrr0x5E, divss, int_x86_sse_div_ss;
+def Int_DIVSSrm : SS_Intrm0x5E, divss, int_x86_sse_div_ss;
+def Int_DIVSDrr : SD_Intrr0x5E, divsd, int_x86_sse2_div_sd;
+def Int_DIVSDrm : SD_Intrm0x5E, divsd,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.138 - 1.139
---
Log message:
remove dead/duplicate instructions
---
Diffs of the changes: (+0 -21)
X86InstrSSE.td | 21 -
1 files changed, 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.138
llvm/lib/Target/X86/X86InstrSSE.td:1.139
--- llvm/lib/Target/X86/X86InstrSSE.td:1.138Sat Oct 7 00:26:13 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:41:52 2006
@@ -390,27 +390,6 @@
sqrtsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))];
-let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- maxss {$src2, $dst|$dst, $src2}, [];
-def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
- maxsd {$src2, $dst|$dst, $src2}, [];
-def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- minss {$src2, $dst|$dst, $src2}, [];
-def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
- minsd {$src2, $dst|$dst, $src2}, [];
-}
-def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- maxss {$src2, $dst|$dst, $src2}, [];
-def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
- maxsd {$src2, $dst|$dst, $src2}, [];
-def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- minss {$src2, $dst|$dst, $src2}, [];
-def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
- minsd {$src2, $dst|$dst, $src2}, [];
-}
-
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
let isCommutable = 1 in {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.139 - 1.140
---
Log message:
Factor operands into packed unary classes
---
Diffs of the changes: (+21 -25)
X86InstrSSE.td | 46 +-
1 files changed, 21 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.139
llvm/lib/Target/X86/X86InstrSSE.td:1.140
--- llvm/lib/Target/X86/X86InstrSSE.td:1.139Sat Oct 7 00:41:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:47:20 2006
@@ -237,17 +237,21 @@
: PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))];
-class PS_Intrrbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class PS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
-class PS_Intrmbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
+class PS_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))];
-class PD_Intrrbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class PD_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
-class PD_Intrmbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
+class PD_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))];
class S3D_Intrrbits8 o, string asm, Intrinsic IntId
@@ -1045,23 +1049,15 @@
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def MAXPSrr : PS_Intrr0x5F, maxps {$src2, $dst|$dst, $src2},
- int_x86_sse_max_ps;
-def MAXPDrr : PD_Intrr0x5F, maxpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_max_pd;
-def MINPSrr : PS_Intrr0x5D, minps {$src2, $dst|$dst, $src2},
- int_x86_sse_min_ps;
-def MINPDrr : PD_Intrr0x5D, minpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_min_pd;
-}
-def MAXPSrm : PS_Intrm0x5F, maxps {$src2, $dst|$dst, $src2},
- int_x86_sse_max_ps;
-def MAXPDrm : PD_Intrm0x5F, maxpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_max_pd;
-def MINPSrm : PS_Intrm0x5D, minps {$src2, $dst|$dst, $src2},
- int_x86_sse_min_ps;
-def MINPDrm : PD_Intrm0x5D, minpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_min_pd;
+def MAXPSrr : PS_Intrr0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrr : PD_Intrr0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrr : PS_Intrr0x5D, minps, int_x86_sse_min_ps;
+def MINPDrr : PD_Intrr0x5D, minpd, int_x86_sse2_min_pd;
+}
+def MAXPSrm : PS_Intrm0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrm : PD_Intrm0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrm : PS_Intrm0x5D, minps, int_x86_sse_min_ps;
+def MINPDrm : PD_Intrm0x5D, minpd, int_x86_sse2_min_pd;
}
// Logical
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.140 - 1.141
---
Log message:
simplify patterns by merging in operand info
---
Diffs of the changes: (+30 -34)
X86InstrSSE.td | 64 ++---
1 files changed, 30 insertions(+), 34 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.140
llvm/lib/Target/X86/X86InstrSSE.td:1.141
--- llvm/lib/Target/X86/X86InstrSSE.td:1.140Sat Oct 7 00:47:20 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:50:25 2006
@@ -224,17 +224,21 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
-class PS_Intrbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+class PS_Intrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId VR128:$src))];
-class PS_Intmbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+class PS_Intmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId (loadv4f32 addr:$src)))];
-class PD_Intrbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+class PD_Intrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId VR128:$src))];
-class PD_Intmbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
+class PD_Intmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))];
class PS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
@@ -1029,35 +1033,27 @@
(loadv2f64 addr:$src2)))];
}
-def SQRTPSr : PS_Intr0x51, sqrtps {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ps;
-def SQRTPSm : PS_Intm0x51, sqrtps {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ps;
-def SQRTPDr : PD_Intr0x51, sqrtpd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_pd;
-def SQRTPDm : PD_Intm0x51, sqrtpd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_pd;
-
-def RSQRTPSr : PS_Intr0x52, rsqrtps {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ps;
-def RSQRTPSm : PS_Intm0x52, rsqrtps {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ps;
-def RCPPSr : PS_Intr0x53, rcpps {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ps;
-def RCPPSm : PS_Intm0x53, rcpps {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ps;
+def SQRTPSr : PS_Intr0x51, sqrtps, int_x86_sse_sqrt_ps;
+def SQRTPSm : PS_Intm0x51, sqrtps, int_x86_sse_sqrt_ps;
+def SQRTPDr : PD_Intr0x51, sqrtpd, int_x86_sse2_sqrt_pd;
+def SQRTPDm : PD_Intm0x51, sqrtpd, int_x86_sse2_sqrt_pd;
+
+def RSQRTPSr : PS_Intr0x52, rsqrtps, int_x86_sse_rsqrt_ps;
+def RSQRTPSm : PS_Intm0x52, rsqrtps, int_x86_sse_rsqrt_ps;
+def RCPPSr : PS_Intr0x53, rcpps, int_x86_sse_rcp_ps;
+def RCPPSm : PS_Intm0x53, rcpps, int_x86_sse_rcp_ps;
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def MAXPSrr : PS_Intrr0x5F, maxps, int_x86_sse_max_ps;
-def MAXPDrr : PD_Intrr0x5F, maxpd, int_x86_sse2_max_pd;
-def MINPSrr : PS_Intrr0x5D, minps, int_x86_sse_min_ps;
-def MINPDrr : PD_Intrr0x5D, minpd, int_x86_sse2_min_pd;
-}
-def MAXPSrm : PS_Intrm0x5F, maxps, int_x86_sse_max_ps;
-def MAXPDrm : PD_Intrm0x5F, maxpd, int_x86_sse2_max_pd;
-def MINPSrm : PS_Intrm0x5D, minps, int_x86_sse_min_ps;
-def MINPDrm : PD_Intrm0x5D, minpd, int_x86_sse2_min_pd;
+def MAXPSrr : PS_Intrr0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrr : PD_Intrr0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrr : PS_Intrr0x5D, minps, int_x86_sse_min_ps;
+def MINPDrr : PD_Intrr0x5D, minpd, int_x86_sse2_min_pd;
+}
+def MAXPSrm : PS_Intrm0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrm : PD_Intrm0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrm : PS_Intrm0x5D, minps, int_x86_sse_min_ps;
+def MINPDrm : PD_Intrm0x5D, minpd, int_x86_sse2_min_pd;
}
// Logical
___
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