Just like every other place in gallium.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/drivers/freedreno/Makefile.am | 2 +-
src/gallium/drivers/nouveau/Makefile.am | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Ben Widawsky b...@bwidawsk.net writes:
+ void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
+ struct brw_reg dst);
super bikesheddy, but this function name sounds pretty bad, though I
understand it's a side-effect of the name of the opcode
Hi,
I have been trying to get OpenGL sw rastering to work on Linux based ARM
CortexA15 device but for some reason gallium llvmpipe gives me a
segmentation fault. Has anybody managed to run sw rastering using gallium
llvmpipe on ARM? Softpipe seems to be working ok.
I am using the following
On Tue, Apr 14, 2015 at 1:04 PM, Eric Anholt e...@anholt.net wrote:
Rob Clark robdcl...@gmail.com writes:
From: Rob Clark robcl...@freedesktop.org
Signed-off-by: Rob Clark robcl...@freedesktop.org
1-3 (with the fix to 1 that you posted in irc) are:
Reviewed-by: Eric Anholt e...@anholt.net
Cc: Rob Clark robcl...@freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/drivers/freedreno/Makefile.am | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/Makefile.am
b/src/gallium/drivers/freedreno/Makefile.am
Otherwise we'll error out due to unresolved nir symbols. Note that we
still fail to link due to unresolved _mesa_error_no_memory().
Based on commit 101142c4010(xa: support for drivers which use NIR)
Cc: Rob Clark robcl...@freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
We no longer need to (although we can) provide this symbol ourselves.
Cc: Rob Clark robcl...@freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 8
1 file changed, 8 deletions(-)
diff --git
Accidentally added since the introduction of the file.
Cc: 10.4 10.5 mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/drivers/r300/Automake.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Rather than forcing everyone to provide their own definition of the symbol
provide a common weak one, which anyone can override if needed.
This resolved the build of the standalone pipe-drivers, as it provides a
default symbol which was missing previously.
Cc: Rob Clark robcl...@freedesktop.org
Similar to commit 127f8767e0a and 101142c4010.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/targets/d3dadapter9/Makefile.am | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/targets/d3dadapter9/Makefile.am
b/src/gallium/targets/d3dadapter9/Makefile.am
Thus we can remove the workaround that we previously had.
Cc: Rob Clark robcl...@freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/state_trackers/xa/xa_tracker.c | 12
1 file changed, 12 deletions(-)
diff --git
On 14 April 2015 at 17:22, Ian Romanick i...@freedesktop.org wrote:
On 04/14/2015 08:36 AM, Emil Velikov wrote:
On 14 April 2015 at 13:52, Jose Fonseca jfons...@vmware.com wrote:
On 13/04/15 22:59, Ian Romanick wrote:
On 04/10/2015 03:36 PM, Jose Fonseca wrote:
From: José Fonseca
Hi,
I can run arm llvmpipe glxgears on IFC6410 (Snapdragon 600 APQ8064,
Krait 300) without problems.
llvm 3.5
mesa 10.4.3
both are fedora 21 standard packages without modifications.
I haven't tried anything more complex than glxgears
jan
On Wed, 2015-04-15 at 16:30 +0200, Roland Scheidegger
There were reports with varying success of running llvmpipe with arm in
the past but I haven't heard anything for a while. In theory it should
work (and crashing in the pixel shader is an indication the vertex
shader worked or at least didn't crash).
But it's not really tested and hence might
On 14 April 2015 at 17:35, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Previously GLX_EXT_create_context_es2_profile was marked as direct
only so that it would not depend on server support. Since the
extension required functions that are part of
On Wed, Apr 15, 2015 at 10:32 AM, Connor Abbott cwabbo...@gmail.com wrote:
But more immediately, I hit a sort of snag: I cannot seem to narrow
from 32b to 16b at the same time I move to address register. Which
ends up meaning I need a mov from 32b to 16b followed by a 2nd mov to
get it into
On Tue, Apr 14, 2015 at 7:08 PM, Rob Clark robdcl...@gmail.com wrote:
On Tue, Apr 14, 2015 at 6:24 PM, Connor Abbott cwabbo...@gmail.com wrote:
On Tue, Apr 14, 2015 at 5:16 PM, Rob Clark robdcl...@gmail.com wrote:
On Tue, Apr 14, 2015 at 4:59 PM, Jason Ekstrand ja...@jlekstrand.net
wrote:
+
From: Ian Romanick ian.d.roman...@intel.com
Shader-db results:
GM45 NIR:
total instructions in shared programs: 4082044 - 4081919 (-0.00%)
instructions in affected programs: 27609 - 27484 (-0.45%)
helped:44
Iron Lake NIR:
total instructions in shared
Thanks for the replies.
I tried to upgrade LLVM from 3.3 to 3.4 after I sent the e-mail but ended
up having an internal compiler error from gcc linaro toolchain compiler.
Nice. I could try a more up-to-date version of Mesa to see if it helps.
Although I have learned that I can not take the most
On Wed, Apr 15, 2015 at 12:37 PM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Shader-db results:
GM45 NIR:
total instructions in shared programs: 4082044 - 4081919 (-0.00%)
instructions in affected programs: 27609 - 27484 (-0.45%)
helped:
On Wed, Apr 1, 2015 at 6:19 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 75
1 file changed, 38 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
Commit 5a06ee738 added a step to the generator to set up the message
header when generating the VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
instruction. That pseudo opcode is implemented in terms of multiple
actual opcodes, one of which writes to one of the source registers in
order to set up the message
There were three places in the visitor that had a similar chunk of
code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register
for the offset. This patch combines the chunks into a helper function
to reduce the code duplication. It will also be useful in the next
patch to expand what
On Wed, Apr 15, 2015 at 06:58:02PM +0100, Neil Roberts wrote:
Commit 5a06ee738 added a step to the generator to set up the message
header when generating the VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
instruction. That pseudo opcode is implemented in terms of multiple
actual opcodes, one of which
On Wed, Apr 15, 2015 at 9:50 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Wed, Apr 15, 2015 at 12:37 PM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Shader-db results:
GM45 NIR:
total instructions in shared programs: 4082044 - 4081919 (-0.00%)
From: Ian Romanick ian.d.roman...@intel.com
In response to another patch, Emil asked for some clarification how this
stuff works. Rather than just reply to the e-mail, I decided to update
the exlanation in the code.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Cc: Emil Velikov
This enables using _mesa_meta_pbo_TexSubImage() to upload data
to R16G16B16X16 texture. Earlier it fell back to slower paths.
Jenkins run shows no piglit regressions.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 6 ++
1 file changed,
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 644cb41..7fd812e 100644
---
Reduces the number of conditions tested in if to one in case of
non-integer formats. Makes no functional changes.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
On 15 April 2015 at 18:33, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 15, 2015 at 7:08 AM, Emil Velikov emil.l.veli...@gmail.com
wrote:
Rather than forcing everyone to provide their own definition of the symbol
provide a common weak one, which anyone can override if needed.
This
On Wed, Apr 15, 2015 at 06:58:01PM +0100, Neil Roberts wrote:
There were three places in the visitor that had a similar chunk of
code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register
for the offset. This patch combines the chunks into a helper function
to reduce the code
On Wed, Apr 15, 2015 at 7:08 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
Rather than forcing everyone to provide their own definition of the symbol
provide a common weak one, which anyone can override if needed.
This resolved the build of the standalone pipe-drivers, as it provides a
On 15 April 2015 at 10:24, Michel Dänzer mic...@daenzer.net wrote:
On 09.04.2015 03:27, Emil Velikov wrote:
As mentioned by Michel Dänzer for LLVM = 3.6 we create the
LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi
context. For older LLVM or hardware (r600) the triple is
On Wed, Apr 1, 2015 at 6:19 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
Instead of the complicated and broken-by-design pile of heuristics we had
before, we now have a straightforward lowering:
1) All header sources are copied directly using force_writemask_all and,
since they are
On Wed 15 Apr 2015, Emil Velikov wrote:
On 14 April 2015 at 17:22, Ian Romanick i...@freedesktop.org wrote:
On 04/14/2015 08:36 AM, Emil Velikov wrote:
On 14 April 2015 at 13:52, Jose Fonseca jfons...@vmware.com wrote:
On 13/04/15 22:59, Ian Romanick wrote:
On 04/10/2015 03:36 PM, Jose
On Tue 14 Apr 2015, Ian Romanick wrote:
From: Ian Romanick ian.d.roman...@intel.com
Previously GLX_EXT_create_context_es2_profile was marked as direct
only so that it would not depend on server support. Since the
extension required functions that are part of
GLX_ARB_create_context_profile,
On Wed 15 Apr 2015, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
On Wed, Apr 15, 2015 at 2:24 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Jason noticed that shader_time was bumping the reference count on the
gl_shader_program and gl_program structures, in code called during
compilation.
Not only were these never unreferenced, but it meant fragment
On 14/04/15 17:22, Ian Romanick wrote:
On 04/14/2015 08:36 AM, Emil Velikov wrote:
On 14 April 2015 at 13:52, Jose Fonseca jfons...@vmware.com wrote:
On 13/04/15 22:59, Ian Romanick wrote:
On 04/10/2015 03:36 PM, Jose Fonseca wrote:
From: José Fonseca jfons...@vmware.com
The latest
On Fri, Apr 3, 2015 at 7:28 AM, Francisco Jerez curroje...@riseup.net wrote:
Jason Ekstrand ja...@jlekstrand.net writes:
On Thu, Apr 2, 2015 at 3:01 AM, Francisco Jerez curroje...@riseup.net
wrote:
Jason Ekstrand ja...@jlekstrand.net writes:
Instead of the complicated and broken-by-design
On 04/15/2015 11:56 AM, Emil Velikov wrote:
On 15 April 2015 at 18:33, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 15, 2015 at 7:08 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
Rather than forcing everyone to provide their own definition of the symbol
provide a common weak one, which
The ir_tex opcode turns into a sample or sample_c message, which will try to
compute derivatives to determine the lod. This produces garbage for
non-fragment shaders where the sample coordinates don't correspond to
subspans.
We fix this by rewriting the opcode from ir_tex to ir_txl and setting
On 15/04/15 20:38, Brian Paul wrote:
On 04/15/2015 11:56 AM, Emil Velikov wrote:
On 15 April 2015 at 18:33, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 15, 2015 at 7:08 AM, Emil Velikov
emil.l.veli...@gmail.com wrote:
Rather than forcing everyone to provide their own definition of the
Rob Clark robdcl...@gmail.com writes:
On Tue, Apr 14, 2015 at 1:04 PM, Eric Anholt e...@anholt.net wrote:
Rob Clark robdcl...@gmail.com writes:
From: Rob Clark robcl...@freedesktop.org
Signed-off-by: Rob Clark robcl...@freedesktop.org
1-3 (with the fix to 1 that you posted in irc) are:
On 14/04/15 17:35, Ian Romanick wrote:
From: Ian Romanick ian.d.roman...@intel.com
Previously GLX_EXT_create_context_es2_profile was marked as direct
only so that it would not depend on server support. Since the
extension required functions that are part of
GLX_ARB_create_context_profile,
On Wednesday, April 15, 2015 11:38:51 AM Anuj Phogat wrote:
This enables using _mesa_meta_pbo_TexSubImage() to upload data
to R16G16B16X16 texture. Earlier it fell back to slower paths.
Jenkins run shows no piglit regressions.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
On 04/14/2015 02:20 PM, Jose Fonseca wrote:
On 14/04/15 17:56, Brian Paul wrote:
Subroutines need labels so they can be identied by CAL instructions.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git
From: Rob Clark robcl...@freedesktop.org
v2: move ishl into ttn (instead of driver backend) to keep the units
consistent between immediate and indirect offsets
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 69
On 04/15/2015 12:41 PM, Kristian Høgsberg wrote:
The ir_tex opcode turns into a sample or sample_c message, which will try to
compute derivatives to determine the lod. This produces garbage for
non-fragment shaders where the sample coordinates don't correspond to
subspans.
We fix this by
https://bugs.freedesktop.org/show_bug.cgi?id=90032
--- Comment #11 from Felix von Leitner felix-freedesk...@fefe.de ---
Good news! It works now that I recompiled llvm with RTTI support!
I thought I had RTTI in my LLVM but I was doing it wrong.
For the record: the right way to build LLVM with
On Wed, Apr 15, 2015 at 6:15 PM, Ian Romanick i...@freedesktop.org wrote:
On 04/15/2015 10:56 AM, Emil Velikov wrote:
On 15 April 2015 at 18:33, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 15, 2015 at 7:08 AM, Emil Velikov emil.l.veli...@gmail.com
wrote:
Rather than forcing everyone to
On 04/15/2015 10:56 AM, Emil Velikov wrote:
On 15 April 2015 at 18:33, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 15, 2015 at 7:08 AM, Emil Velikov emil.l.veli...@gmail.com
wrote:
Rather than forcing everyone to provide their own definition of the symbol
provide a common weak one,
On Wed, Apr 15, 2015 at 2:14 PM, Thomas Helland
thomashellan...@gmail.com wrote:
This follows the same pattern as in the hash_table.
Reviewed-by: Jason Ekstrand jason.ekstrand at intel.com
Fix the email address before committing, whoever commits.
Signed-off-by: Thomas Helland
On Wednesday, April 15, 2015 02:47:01 PM Ian Romanick wrote:
On 04/15/2015 12:41 PM, Kristian Høgsberg wrote:
The ir_tex opcode turns into a sample or sample_c message, which will try to
compute derivatives to determine the lod. This produces garbage for
non-fragment shaders where the
Reviewed-by: Marek Olšák marek.ol...@amd.com
Marek
On Wed, Apr 15, 2015 at 4:08 PM, Emil Velikov emil.l.veli...@gmail.com wrote:
Accidentally added since the introduction of the file.
Cc: 10.4 10.5 mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
From: Rob Clark robcl...@freedesktop.org
For lowering if/else, I need a way to insert at the end of the previous
block.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/glsl/nir/nir_builder.h | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git
On Wed, Apr 15, 2015 at 4:28 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On Wednesday, April 15, 2015 02:47:01 PM Ian Romanick wrote:
On 04/15/2015 12:41 PM, Kristian Høgsberg wrote:
The ir_tex opcode turns into a sample or sample_c message, which will try
to
compute derivatives to
On Wed, Apr 15, 2015 at 1:31 PM, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 1, 2015 at 6:19 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
Instead of the complicated and broken-by-design pile of heuristics we had
before, we now have a straightforward lowering:
1) All header sources
Reviewed-by: Connor Abbott cwabo...@gmail.com
On Wed, Apr 15, 2015 at 9:18 PM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Suggested by Jason on a different patch after some comments /
questions by Ilia.
Signed-off-by: Ian Romanick
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Wed, Apr 15, 2015 at 6:18 PM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Suggested by Jason on a different patch after some comments /
questions by Ilia.
Signed-off-by: Ian Romanick
Rob Clark robdcl...@gmail.com writes:
From: Rob Clark robcl...@freedesktop.org
v2: move ishl into ttn (instead of driver backend) to keep the units
consistent between immediate and indirect offsets
This looks good to me.
Reviewed-by: Eric Anholt e...@anholt.net
signature.asc
From: Ian Romanick ian.d.roman...@intel.com
Suggested by Jason on a different patch after some comments /
questions by Ilia.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Cc: Jason Ekstrand jason.ekstr...@intel.com
---
src/glsl/nir/nir_search.c | 4 ++--
1 file changed, 2 insertions(+),
On Wed, Apr 15, 2015 at 5:13 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
On Wed, Apr 15, 2015 at 1:31 PM, Matt Turner matts...@gmail.com wrote:
On Wed, Apr 1, 2015 at 6:19 PM, Jason Ekstrand ja...@jlekstrand.net wrote:
Instead of the complicated and broken-by-design pile of heuristics we had
On 04/15/2015 04:28 PM, Kenneth Graunke wrote:
On Wednesday, April 15, 2015 02:47:01 PM Ian Romanick wrote:
On 04/15/2015 12:41 PM, Kristian Høgsberg wrote:
The ir_tex opcode turns into a sample or sample_c message, which will try to
compute derivatives to determine the lod. This produces
Jason Ekstrand ja...@jlekstrand.net writes:
On Sat, Apr 11, 2015 at 4:25 PM, Thomas Helland
thomashellan...@gmail.com wrote:
The performance numbers (shader-db runtime) are:
Difference at 95.0% confidence
-14.7608 +/- 3.36786
-9.05064% +/- 2.06501%
(Original runtime was 160
The same rationale applies here as for the hash table.
Power of two size should give better performance,
and using the algorithm hash = sh + i/2 + i*i/2
should result in only distinct hash values when hitting collisions.
Difference at 95.0% confidence
-7.9505 +/- 2.44011
-5.04357% +/-
This follows the same pattern as in the hash_table.
Reviewed-by: Jason Ekstrand jason.ekstrand at intel.com
Signed-off-by: Thomas Helland thomashellan...@gmail.com
---
src/util/set.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/src/util/set.c b/src/util/set.c
index
That's good to know. I've always thought it's a bit of a pity that it
isn't optimized at all for arm (doesn't use any arm intrinsics, though
with newer llvm versions it is probably not all that important any more,
and I'm not even sure which neon intrinsics would be useful) but someone
would need
On 12.04.2015 04:11, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
On 09.04.2015 20:27, eveli...@kemper.freedesktop.org (Emil Velikov) wrote:
@@ -2740,7 +2741,45 @@ static int si_generate_gs_copy_shader(struct si_screen
*sscreen,
return r;
}
-int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
+static void
It is true that a gl_shader_program with ID 0 will be a fixed-function
fragment program; a gl_program with ID 0 but NULL gl_shader_program
means that it's a fixed-function vertex shader.
But that's not terribly interesting or relevant to what we're doing.
We just need to know that ID 0 means
0 is not a valid GLSL shader or ARB program ID. For some reason,
shader_time used -1 instead...so we had code to detect 0, then override
it to -1.
We can just delete that.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_program.c | 14 ++
1
On 09.04.2015 03:27, Emil Velikov wrote:
As mentioned by Michel Dänzer for LLVM = 3.6 we create the
LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi
context. For older LLVM or hardware (r600) the triple is always r600--
and is created at a later stage - radeon_llvm_compile()
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