On 06/26/2017 09:31 PM, Marek Olšák wrote:
Reviewed-by: Marek Olšák
Marek
Thanks for reviewing, Marek.
/Thomas
On Thu, Jun 22, 2017 at 1:00 PM, Thomas Hellstrom wrote:
The mesa state tracker was needlessly flushing the front buffer even if
Ok, so I just looked into it a little further, and I guess that since
nir_to_llvm needs to know about the ABI to know where all the
"special" inputs/outputs like tess factors, position etc. are,
switching radv to using the normal input/output intrinsics would be
better done as part of your series,
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index b236bed..a674a60 100644
---
From: Marek Olšák
Shader key size: 107 -> 47
Divisors of 0 and 1 are encoded in the shader key. Greater instance divisors
are loaded from a constant buffer.
The shader code doing the division is huge. Is it something we need to
worry about? Does any app use instance
Reviewed-by: Marek Olšák
Marek
On Mon, Jun 26, 2017 at 10:48 PM, Brian Paul wrote:
> Add the new 'flags' parameter to pipe_loader_sw_create_screen().
> ---
> src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ++-
> 1 file changed, 2 insertions(+),
On 16/06/17 18:12, Juan A. Suarez Romero wrote:
Commit 00620782c9 (i965: use nir_shader_gather_info() over
do_set_program_inouts()) changed how we compute the outputs written.
In the previous version it was using the IR declared outputs, while in
the new one it uses NIR to parse the
From: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 ++
src/mesa/drivers/dri/i965/intel_fbo.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 92d1d2a..9c9b859
From: Ian Romanick
brw_blorp.c: In function ‘brw_blorp_clear_depth_stencil’:
brw_blorp.c:913:53: warning: unused parameter ‘partial_clear’
[-Wunused-parameter]
GLbitfield mask, bool partial_clear)
From: Ian Romanick
textdata bss dec hex filename
7155246 256860 37332 7449438 71ab5e 32-bit i965_dri.so before
7155058 256860 37332 7449250 71aaa2 32-bit i965_dri.so after
6788683 328056 50704 7167443 6d5dd3 64-bit i965_dri.so before
From: Ian Romanick
In file included from brw_context.h:40:0,
from brw_blorp.c:32:
../../../../../src/intel/compiler/brw_compiler.h: In function
‘brw_stage_has_packed_dispatch’:
../../../../../src/intel/compiler/brw_compiler.h:1150:61: warning: unused
From: Ian Romanick
textdata bss dec hex filename
7155954 256860 37332 7450146 71ae22 32-bit i965_dri.so before
7155858 256860 37332 7450050 71adc2 32-bit i965_dri.so after
6789395 328056 50704 7168155 6d609b 64-bit i965_dri.so before
From: Ian Romanick
brw_blorp.c:1007:4: warning: ‘num_layers’ may be used uninitialized in this
function [-Wmaybe-uninitialized]
blorp_clear_depth_stencil(, _surf, _surf,
^
From: Ian Romanick
Since i965 no longer uses this function for clearing color buffers,
there is no driver left that will ever support integer textures and use
_mesa_meta_glsl_Clear.
As a side note, the has_integer_textures check was rubbish anyway
because meta always
From: Jason Ekstrand
It's a bit rare, but blorp can trigger a urb reconfiguration. When that
happens, we need to re-upload the URB config. Fortunately, this isn't as
bad as it looks because gen7_upload_urb will not re-emit the packet if it
would end up being a no-op
From: Ian Romanick
v2: Use textwrap.dedent to make the source line a lot shorter.
Shortening (?) the line was requested by Jason.
Signed-off-by: Ian Romanick
---
src/intel/genxml/gen_pack_header.py | 9 +++--
1 file changed, 7
From: Ian Romanick
textdata bss dec hex filename
7154994 256860 37332 7449186 71aa62 32-bit i965_dri.so before
7154994 256860 37332 7449186 71aa62 32-bit i965_dri.so after
6788475 328056 50704 7167235 6d5d03 64-bit i965_dri.so before
From: Ian Romanick
These are basically DSA versions of glLoadIdentity() and glLoadMatrix().
textdata bss dec hex filename
7155026 256860 37332 7449218 71aa82 32-bit i965_dri.so before
7155246 256860 37332 7449438 71ab5e 32-bit i965_dri.so
From: Ian Romanick
textdata bss dec hex filename
7155058 256860 37332 7449250 71aaa2 32-bit i965_dri.so before
7154994 256860 37332 7449186 71aa62 32-bit i965_dri.so after
6788611 328056 50704 7167371 6d5d8b 64-bit i965_dri.so before
Add the new 'flags' parameter to pipe_loader_sw_create_screen().
---
src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
Rob Herring writes:
> vc4 now depends on renderonly functions, but these weren't added to the
> Android build resulting in the following errors:
>
> src/gallium/drivers/vc4/vc4_resource.c:380: error: undefined reference to
> 'renderonly_scanout_destroy'
>
On Thu, Jun 22, 2017 at 9:19 AM, Nicolai Hähnle wrote:
> On 20.06.2017 20:00, Marek Olšák wrote:
>>
>> From: Marek Olšák
>>
>> sizeof(struct si_shader_key):
>>Before reverting the 2 commits: 120 bytes
>>After reverting the 2 commits: 128 bytes
>>
On Mon, Jun 26, 2017 at 09:07:12PM +0300, Topi Pohjolainen wrote:
> CID: 1413018
> Signed-off-by: Topi Pohjolainen
> ---
> src/intel/vulkan/anv_device.c | 1 +
> 1 file changed, 1 insertion(+)
>
This patch is
Reviewed-by: Nanley Chery
>
Looks good to me.
For the series:
Reviewed-by: Samuel Pitoiset
On 06/23/2017 08:30 PM, Karol Herbst wrote:
Running Tomb Raider on Nouveau I found some flicker caused by ignoring precise
modifiers on variables inside Nouveau.
This series add precise/invariant
vc4 now depends on renderonly functions, but these weren't added to the
Android build resulting in the following errors:
src/gallium/drivers/vc4/vc4_resource.c:380: error: undefined reference to
'renderonly_scanout_destroy'
src/gallium/drivers/vc4/vc4_resource.c:681: error: undefined reference
On Wednesday, June 21, 2017 6:25:28 PM PDT Lionel Landwerlin wrote:
> Counter related to timings will be sensitive to any delay introduced
> by the software. In particular if our begin & end of performance
> queries end up in different batches, time related counters will
> exhibit biffer values
I can verify that the fix works.
Thank you!
George
> On Jun 26, 2017, at 3:24 PM, Marek Olšák wrote:
>
> I just pushed the fix.
>
> Marek
>
> On Mon, Jun 26, 2017 at 10:01 PM, Kyriazis, George
> wrote:
>> Marek
>>
>> Our windows mesa build
On Monday, June 26, 2017 11:07:11 AM PDT Topi Pohjolainen wrote:
> Makes coverity happier.
>
> Fix indentation in gen >= 8 block while at it.
>
> CID: 1413020
> CC: Rafael Antognolli
> Signed-off-by: Topi Pohjolainen
> ---
>
For the series:
Reviewed-by: Marek Olšák
Marek
On Thu, Jun 22, 2017 at 4:35 PM, Samuel Pitoiset
wrote:
> This prevents glViewport() and friends to always flush and
> trigger _NEW_VIEWPORT.
>
> Signed-off-by: Samuel Pitoiset
On 06/26/2017 09:01 AM, Jason Ekstrand wrote:
> This fixes the Piglit ARB_texture_views rendering-formats test.
>
> Cc: "17.1"
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git
On Mon, 2017-06-26 at 14:23 +0100, Emil Velikov wrote:
> On 23 June 2017 at 00:07, Andres Gomez wrote:
> > On Mon, 2017-06-19 at 12:36 +0100, Emil Velikov wrote:
> > > Hi Nicolai,
> > >
> > > On 12 June 2017 at 20:33, Nicolai Hähnle wrote:
> > > > From:
Build mesa 4751 completed
Commit 25ea7aa5cd by Marek Olšák on 6/26/2017 8:23 PM:
mesa/glthread: don't include pthread.h\n\nNot needed. This fixes the Windows build.
Configure your notification preferences
I just pushed the fix.
Marek
On Mon, Jun 26, 2017 at 10:01 PM, Kyriazis, George
wrote:
> Marek
>
> Our windows mesa build broke with your checkin: "mesa/glthread: remove
> HAVE_PTHREAD guards”.
>
> Namely:
>
> Compiling src\mesa\main\context.c ...
> context.c
>
These two are good finds!
Patch 2&3 are:
Reviewed-by: Samuel Pitoiset
On 06/25/2017 12:39 AM, Ilia Mirkin wrote:
Previously the logic would decide that the record is kept, which
translates into keep = false in the caller, which meant that these
passes did not run.
Yes, but I've since rebased it out on my 'cts' branch.
On Mon, Jun 26, 2017 at 4:02 PM, Samuel Pitoiset
wrote:
> Looks like the patch is based on your bindless branch. :)
>
> Reviewed-by: Samuel Pitoiset
>
>
> On 06/24/2017 07:24 PM, Ilia
Jason, you CCed this whole series for stable. However:
* Patch 1/16 already landed, but without the -stable tag. Should it be
cherry-picked? It looks like yes.
* Patch 2/16 did not land. Is it in need of review or it has been
superseded?
* Patches 3-15/16 were already cherry-picked in the
On Monday, 2017-06-26 21:07:12 +0300, Topi Pohjolainen wrote:
> CID: 1413018
> Signed-off-by: Topi Pohjolainen
Both patches are
Reviewed-by: Eric Engestrom
> ---
> src/intel/vulkan/anv_device.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
Would be better to introduce a helper into MemoryOpt for that (same for
stores).
Either way, looks good.
Reviewed-by: Samuel Pitoiset
On 06/25/2017 12:39 AM, Ilia Mirkin wrote:
This has no effect since in practice this will only play for
memory-backed files, for
Looks like the patch is based on your bindless branch. :)
Reviewed-by: Samuel Pitoiset
On 06/24/2017 07:24 PM, Ilia Mirkin wrote:
The idxbuf could linger, and when a clear happened, which also uses the
3d bufctx, we could get an error trying to access it.
This
Marek
Our windows mesa build broke with your checkin: "mesa/glthread: remove
HAVE_PTHREAD guards”.
Namely:
Compiling src\mesa\main\context.c ...
context.c
c:\users\gkyriazi\src\mesa\src\mesa\main\glthread.h(34): fatal error C1083:
Cannot open include file: 'pthread.h': No such file or
Reviewed-by: Samuel Pitoiset
On 06/24/2017 06:50 PM, Ilia Mirkin wrote:
All the BuildUtil helpers just insert the operation into the current BB.
So we have to take care that any fetchSrc() operations happen before the
operation whose setIndirect() it goes into.
On Fri, Jun 16, 2017 at 03:41:50PM -0700, Jason Ekstrand wrote:
> From: Ben Widawsky
>
> v2: move is_aux into if block. (Jason)
> Use else block instead of goto (Jason)
>
> v3: Fix up logic for is_aux (Ben)
> Fix up size calculations and add FIXME (Ben)
>
> v4 (Jason
On Fri, Jun 16, 2017 at 03:41:49PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/intel_screen.c | 55
> +---
> 1 file changed, 50 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
>
If there are no objections to other patches, patches 3-4 are:
Reviewed-by: Marek Olšák
Marek
On Thu, Jun 22, 2017 at 12:42 PM, Thomas Hellstrom
wrote:
> Add a state tracker interface method to flush outstanding swapbuffers, and
> add a call to it
Jason, it doesn't seem like this patch has landed in master. Are you in
need of review or is it that this has been superseded?
Thanks!
On Wed, 2017-05-10 at 16:08 -0700, Jason Ekstrand wrote:
> One of the key invariants of the relocation system is the
> presumed_offset field. The assumption is
On Mon, Jun 26, 2017 at 10:30:40PM +0300, Pohjolainen, Topi wrote:
> On Fri, Jun 16, 2017 at 03:41:47PM -0700, Jason Ekstrand wrote:
> > From: Ben Widawsky
> >
> > This code will disable actually creating these buffers for the scanout,
> > but it puts the allocation in place.
Reviewed-by: Marek Olšák
Marek
On Thu, Jun 22, 2017 at 1:00 PM, Thomas Hellstrom wrote:
> The mesa state tracker was needlessly flushing the front buffer even if it
> hadn't been drawn to since the last flush. This was happening during
>
On Fri, Jun 16, 2017 at 03:41:47PM -0700, Jason Ekstrand wrote:
> From: Ben Widawsky
>
> This code will disable actually creating these buffers for the scanout,
> but it puts the allocation in place.
>
> Primarily this patch is split out for review, it can be squashed in
>
Forgot to mention... I think I'll take a pass at doing this today.
It'll distract me from some weird bug I've been trying to fight with
the AMD_shader_ballot stuff :)
On Mon, Jun 26, 2017 at 12:24 PM, Connor Abbott wrote:
> So, I think that rather than doing this, we should
So, I think that rather than doing this, we should make radv call
nir_lower_io instead. There's currently a bunch of code in the
NIR-to-LLVM translation to calculate dereference offsets and split up
loads, which is just silly - use the lowering pass instead!
On Mon, Jun 26, 2017 at 7:09 AM,
On Mon, Jun 26, 2017 at 09:27:53PM +0300, Pohjolainen, Topi wrote:
> On Fri, Jun 16, 2017 at 03:41:36PM -0700, Jason Ekstrand wrote:
> > We want to start using create_for_dri_image for all miptrees created
> > from __DRIimage, including those which come from a window system. In
> > order to allow
In my opinion, dumping resources isn't very useful. I think it would
be better to remove that completely.
Marek
On Mon, Jun 26, 2017 at 6:28 PM, Cherniak, Bruce
wrote:
> Back in February, I submitted a patch for review to address an a crash in
> GALLIUM_TRACE.
>
> It
So the solution to this so far has been to call this both from driver
and from mesa/st. (The mesa/st call to nir_lower_tex is only in the
rare case of gles + yuv EGLImageExternal (ie. basically a hack because
android expects YUV texture support. So I guess not worth optimizing
for.)
BR,
-R
On
I think this would probably be a lot simpler if it ran after
nir_lower_io, since you wouldn't need to do all the dereference
munging to compute the offset. That is, instead of translating
load_var intrinsics, it would translate load_uniform intrinsics into
load_ubo intrinsics. Also, it would mean
Multisample surfaces only have a single miplevel so there's no reason to
be passing the extra parameters around. It only leads to confusion.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git
---
src/intel/blorp/blorp.h | 6 +++
src/intel/blorp/blorp_clear.c | 105 +++-
src/intel/blorp/blorp_nir_builder.h | 102 +++
src/intel/blorp/blorp_priv.h| 1 +
4 files changed, 213 insertions(+), 1
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c94fb4f..829a4c5 100644
---
---
src/mesa/drivers/dri/i965/brw_blorp.c | 24
src/mesa/drivers/dri/i965/brw_blorp.h | 5
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +--
3 files changed, 67 insertions(+), 2 deletions(-)
diff --git
On Saturday, June 24, 2017 3:54:59 PM PDT Jason Ekstrand wrote:
> This is effectively a revert of 388f02729bbf88ba104f4f8ee1fdf005a240969c
> though much code has been added since. Kristian initially moved it to
> try and avoid locking problems with meta-based resolves. Now that meta
> is gone
On Fri, Jun 16, 2017 at 03:41:34PM -0700, Jason Ekstrand wrote:
> From: Ben Widawsky
>
> Allows us to continue utilizing common miptree creation using __DRIimage
> without creating a new DRIimage (for the intel_process_dri2_buffer()
> case).
Just looking this patch locally I
On Fri, Jun 16, 2017 at 03:41:36PM -0700, Jason Ekstrand wrote:
> We want to start using create_for_dri_image for all miptrees created
> from __DRIimage, including those which come from a window system. In
> order to allow for fast clears to still work on window system buffers,
> we need to allow
On Mon, Jun 26, 2017 at 10:09 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
this is nicer than my old approach of just hacking in
nir_print_shader() calls at various points and recompiling ;-)
I suppose one thing that would be clever is if you
CID: 1413018
Signed-off-by: Topi Pohjolainen
---
src/intel/vulkan/anv_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 5505befcfa..b09caa38a4 100644
--- a/src/intel/vulkan/anv_device.c
+++
Makes coverity happier.
Fix indentation in gen >= 8 block while at it.
CID: 1413020
CC: Rafael Antognolli
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 6 +++---
1 file changed, 3 insertions(+), 3
Hi Lucas,
Thanks, I'll be trying these out shortly.
On Mon, Jun 26, 2017 at 12:24 PM, Lucas Stach wrote:
> Fixes miscompilation of shaders in glmark2 ideas, leading to GPU hangs.
One of the quirks about the glmark2-es2[ideas] gpu hangcheck is that
after a fresh boot it
Samuel Iglesias Gonsálvez writes:
> On Fri, 2017-06-23 at 11:06 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > On Thu, 2017-06-22 at 16:25 -0700, Francisco Jerez wrote:
>> > > Samuel Iglesias Gonsálvez
On Mon, Jun 26, 2017 at 4:56 PM, Cherniak, Bruce
wrote:
>
>> On Jun 23, 2017, at 7:50 PM, Marek Olšák wrote:
>>
>> Thanks. It can only be reproduced with process isolation enabled in
>> piglit, which is not something I test.
>
> I don't do anything
Hi Andres,
You should cherry-pick below commits to mesa stable:
1. Commit eb23be1 - i965: Add and initialize l3_banks field for gen7+
2. Commit 8521559 - i965: Fix broxton 2x6 l3 config
Please let me know if you have any problems cherry picking them.
Thanks
Anuj
On Mon, Jun 26, 2017 at 8:21
On Monday, June 26, 2017 5:59:40 AM PDT Eric Engestrom wrote:
> Signed-off-by: Eric Engestrom
> ---
> src/intel/vulkan/anv_private.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_private.h
On Thu, Jun 22, 2017 at 12:25 PM, Timothy Arceri wrote:
> On 22/06/17 18:46, Samuel Pitoiset wrote:
>>
>> Here's a shader-db report:
>>
>> https://pastebin.com/raw/QBMnF2pv
>>
>> This doesn't sound like a total win actually...
>
>
> I'm surprised to see this. I thought we
Back in February, I submitted a patch for review to address an a crash in
GALLIUM_TRACE.
It never got a review, and I forgot to follow up on it. Is this a correct fix
and useful to anyone
else?
Thanks,
Bruce
From patchwork Wed Feb 1 20:20:38 2017
Content-Type: text/plain;
> On Jun 26, 2017, at 8:11 AM, Emil Velikov wrote:
>
> Hi Tim,
>
> On 22 June 2017 at 22:13, Tim Rowley wrote:
>> Switch from a macro-based simd intrinsics layer to a more C++
>> implementation, which also adds AVX512 optimizations to
If we blit from a rendertarget or a depthstencil buffer there might still
be dirty data in the TS buffer which needs to be flushed out.
Fixes missing shadow tiles in glmark2 shadow.
Signed-off-by: Lucas Stach
---
This is on top of "etnaviv: flush color cache and depth
The labels array may change its virtual address on a reallocation, so
it is invalid to cache pointers into the array. Rather than using the
pointer directly, remember the array index.
Fixes miscompilation of shaders in glmark2 ideas, leading to GPU hangs.
Fixes: c9e8b49b (etnaviv: gallium driver
On Jun 26, 2017, at 8:02 AM, Emil Velikov
> wrote:
On 22 June 2017 at 22:13, Tim Rowley
> wrote:
Hardcode split to four files currently. Decreases swr build
time on KNL by
Reviewed-by: Marek Olšák
Marek
On Fri, Jun 23, 2017 at 12:56 AM, Timothy Arceri wrote:
> ---
> src/mesa/main/uniform_query.cpp | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/uniform_query.cpp
The buffer intrinsics should be used instead of the image ones.
Signed-off-by: Alex Smith
Cc:
---
This applies on top of James Legg's recent series [1], since they both
touch the same function.
[1]
On Jun 26, 2017, at 7:57 AM, Emil Velikov
> wrote:
Hi Tim,
On 22 June 2017 at 22:13, Tim Rowley
> wrote:
Hardcode split to four files currently. Decreases swr build
time on
Ping...
On Wed, Jun 21, 2017 at 4:40 PM, Gurchetan Singh <
gurchetansi...@chromium.org> wrote:
> Emil,
>
> If I understand you correctly, you're proposing to add the ability to use
> the kms_swrast driver in platform_x11.c (the host is a standard Ubuntu box
> for the emulator use case, not CrOS)
> On Jun 26, 2017, at 7:41 AM, Emil Velikov wrote:
> On 22 June 2017 at 22:12, Tim Rowley wrote:
>> Highlights include splitting the heavily templated files into multiple
>> chunks to speed compile (2x for a large machine), and switching the
This fixes the Piglit ARB_texture_views rendering-formats test.
Cc: "17.1"
---
src/mesa/drivers/dri/i965/brw_blorp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
Reviewed-by: Bruce Cherniak
> On Jun 26, 2017, at 9:34 AM, Eric Engestrom wrote:
>
> On Monday, 2017-06-26 09:03:13 -0500, Tim Rowley wrote:
>> Some combinations of c++ compilers and standard libraries had problems
>> with the
Hi,
On 22.06.2017 23:14, Chad Versace wrote:
On Thu 22 Jun 2017, Chad Versace wrote:
On Thu 22 Jun 2017, Kenneth Graunke wrote:
The author eventually emailed me and said that he considers it a
"finished experiment" and said the rendering method (geometry shader
based approach) is inefficient,
Reviewed-by: Tim Rowley
>
On Jun 26, 2017, at 10:26 AM, Bruce Cherniak
> wrote:
Fix regression of "no rendering" on simple apps like glxgears by
setting an explicit full
On 26 June 2017 at 11:15, Juan A. Suarez Romero wrote:
> On Tue, 2017-06-13 at 11:14 +0200, Juan A. Suarez Romero wrote:
>> v2: NIR fmax/fmin already handles NaN (Connor).
>> ---
>
> Implemented the functions using fmax/fmin.
>
> Could you review it? Thank you!
Sorry, I
Am 26.06.2017 um 15:29 schrieb Leo Liu:
It's enabled through message buffer for UVD
Signed-off-by: Leo Liu
Acked-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 1 +
src/gallium/drivers/radeon/radeon_vcn_dec.h | 2 ++
2
Fix regression of "no rendering" on simple apps like glxgears by
setting an explicit full surface clear_rect when scissor is not
enabled.
This regressed with commit 00173d91 "st/mesa: don't set 16
scissors and 16 viewports if they're unused" due to an assumption
that a default scissor rect is
Anuj, this depends on:
https://cgit.freedesktop.org/mesa/mesa/commit/src/mesa?id=eb23be1d97da290073d76c2510b8999b250f0139
Which didn't make it for -stable. Should we cherry-pick that too?
On Mon, 2017-06-12 at 10:01 -0700, Anuj Phogat wrote:
> The new table added in this patch matches with the
Can someone please confirm if we can claim explicit sync support on android
with mesa today?
If yes, which tests can be used to verify this other than flatland?
Sorry for typo in last email below (corrected).
Regards,
Yogesh.
From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
On 26.06.2017 16:58, Emil Velikov wrote:
> Hi Constantine,
>
> Thanks for giving r600 some much needed love.
>
> While the patch has landed, just going to share some generic comments.
> Most of which are documented here
> https://www.mesa3d.org/submittingpatches.html.
Thanks for the feedback!
> On Jun 23, 2017, at 7:50 PM, Marek Olšák wrote:
>
> Thanks. It can only be reproduced with process isolation enabled in
> piglit, which is not something I test.
I don't do anything special with process isolation. For me this is enough to
reproduce:
bin/shader_runner
On Fri, 2017-06-23 at 11:06 -0700, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
> > On Thu, 2017-06-22 at 16:25 -0700, Francisco Jerez wrote:
> > > Samuel Iglesias Gonsálvez writes:
> > >
> > > > Signed-off-by: Samuel Iglesias
On Monday, 2017-06-26 09:03:13 -0500, Tim Rowley wrote:
> Some combinations of c++ compilers and standard libraries had problems
> with the string::replace code we were using previously.
>
> This should fix the travis-ci system.
Yup, confirmed: https://travis-ci.org/1ace/mesa/builds/247116248
Hi Roland,
Am Montag, 26. Juni 2017, 15:51:12 CEST schrieb Marc Dietrich:
> Am Montag, 26. Juni 2017, 15:35:15 CEST schrieb Grigori Goronzy:
> > On 2017-06-26 15:11, Marc Dietrich wrote:
> > > unfortunately, this change broke vmware/vmplayer here (bisected).
> > > Windows
> > > guest on linux
On Sat, Jun 24, 2017 at 10:41:58AM +0200, Christian Gmeiner wrote:
> Hi
>
> 2017-06-22 14:39 GMT+02:00 Wladimir J. van der Laan :
> > On Wed, Jun 21, 2017 at 10:36:46PM +0200, Christian Gmeiner wrote:
> >> Passes all ext_texture_swizzle piglits.
> >
> > You seem to have dropped
On 26 June 2017 at 10:40, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> Undefined data will eventually trigger a valgrind error while computing
> its CRC32 while writing it into the disk cache, but at that point, it is
> basically impossible to
From: Nicolai Hähnle
This simplifies a bunch of places that no longer need special treatment
of value_count == 1. We rely on LLVM to optimize away the 1-element vector
types.
This fixes a bunch of bugs where 1-element arrays are indexed indirectly.
---
From: Nicolai Hähnle
---
src/amd/common/ac_nir_to_llvm.c | 30 +++---
src/amd/common/ac_shader_abi.h | 1 +
src/gallium/drivers/radeonsi/si_shader.c | 1 +
3 files changed, 21 insertions(+), 11 deletions(-)
diff --git
Reviewed-by: Marek Olšák
Marek
On Fri, Jun 23, 2017 at 12:44 AM, Timothy Arceri wrote:
> v2: rebase on new _mesa_flush_vertices_for_uniforms() helper
> ---
> src/mesa/main/uniform_query.cpp | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff
From: Nicolai Hähnle
---
src/amd/common/ac_nir_to_llvm.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0457d43..156b685 100644
---
From: Nicolai Hähnle
VS with streamout is always a HW VS.
---
src/gallium/drivers/radeonsi/si_state_shaders.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
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