Re: [Mesa-dev] [PATCH] egl/dri: fix error value with unknown drm format

matches the spec Reviewed-by: Tapani Pälli On 11/13/18 4:10 PM, Lionel Landwerlin wrote: According to the EGL_EXT_image_dma_buf_import spec, creating an EGL image with a DRM format not supported should yield the BAD_MATCH error : " * If is EGL_LINUX_DMA_BUF_EXT, and the

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

On Tuesday, November 13, 2018 2:33:58 PM PST Anuj Phogat wrote: > Use L3 configuration table specified in h/w specification. > > Signed-off-by: Anuj Phogat > Cc: Kenneth Graunke > Cc: Francisco Jerez > Cc: Lionel Landwerlin > --- > src/intel/common/gen_l3_config.c | 16 ++-- > 1

[Mesa-dev] [PATCH 2/2] radv: make use of nir_remove_dead_barriers()

--- src/amd/vulkan/radv_pipeline.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 33076cc2bd..577d17e614 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1843,6 +1843,12 @@

[Mesa-dev] [PATCH 1/2] nir: add new nir_remove_dead_barriers() pass

Link time opts can remove unused outputs leaving behind useless barriers. This pass is intended to be called after linking so I've added it to nir_linking_helpers.c This pass removes some barriers from Witcher 3 (DXVK) Vulkan shaders. --- src/compiler/nir/nir.h | 1 +

Re: [Mesa-dev] [RFC] mesa/st: better colormask check for clear fallback

Reviewed-by: Marek Olšák On Tue, Nov 13, 2018, 2:34 PM Rob Clark For RGB surfaces (for example) we don't really care that the colormask > is 0x7 instead of 0xf. This should not trigger clear_with_quad() > slowpath. > > Signed-off-by: Rob Clark > --- > This avoids some mem->gmem for webgl and

Re: [Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

On Tue, Nov 13, 2018, 6:00 PM Rob Clark On Tue, Nov 13, 2018 at 5:25 PM Eric Anholt wrote: > > > > Rob Clark writes: > > > > > If we can't clear all the buffers with pctx->clear() (say, for example, > > > because of ColorMask), push the buffers we *can* clear with > pctx->clear() > > > first.

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Am 14.11.18 um 03:21 schrieb Matt Turner: > On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger wrote: >> >> Am 13.11.18 um 23:49 schrieb Dylan Baker: >>> Quoting Roland Scheidegger (2018-11-13 14:13:00) Am 13.11.18 um 18:00 schrieb Dylan Baker: > Quoting Erik Faye-Lund (2018-11-13

[Mesa-dev] [Bug 102597] [Regression] mpv, high rendering times (two to three times higher)

https://bugs.freedesktop.org/show_bug.cgi?id=102597 --- Comment #10 from Dieter Nützel --- Code fix under way: https://lists.freedesktop.org/archives/mesa-dev/2018-November/209473.html With this patch mpv drops notably, apart that '--vo=opengl-hq' isn't available any longer. Was replaced by

Re: [Mesa-dev] [PATCH 1/2] radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TS

For the series Tested-by: Dieter Nützel mpv drops notably, apart that '--vo=opengl-hq' isn't available any longer. Was replaced by '--vo=gpu'. Dieter Am 13.11.2018 22:23, schrieb Marek Olšák: From: Marek Olšák There are no writes. --- src/gallium/drivers/radeonsi/si_fence.c | 3

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Am 14.11.18 um 03:02 schrieb Roland Scheidegger: > Am 13.11.18 um 23:49 schrieb Dylan Baker: >> Quoting Roland Scheidegger (2018-11-13 14:13:00) >>> Am 13.11.18 um 18:00 schrieb Dylan Baker: Quoting Erik Faye-Lund (2018-11-13 01:34:53) > On Mon, 2018-11-12 at 09:22 -0800, Dylan Baker

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger wrote: > > Am 13.11.18 um 23:49 schrieb Dylan Baker: > > Quoting Roland Scheidegger (2018-11-13 14:13:00) > >> Am 13.11.18 um 18:00 schrieb Dylan Baker: > >>> Quoting Erik Faye-Lund (2018-11-13 01:34:53) > On Mon, 2018-11-12 at 09:22 -0800,

Re: [Mesa-dev] [radeonsi] Blender/vsraytrace/fsraytrace/gsraytrace - GPUShader: compile error

I can confirm, that adding -fno-store-merging looks like a workaround, but with 20-33% (!!!) speed decrease (most (synthetic) benchmarks) and bigger files. Cheers, Dieter Am 13.11.2018 04:59, schrieb Dieter Nützel: GREAT hint Tim! Yes, of course. /home/dieter> gcc --version gcc (SUSE

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Am 13.11.18 um 23:49 schrieb Dylan Baker: > Quoting Roland Scheidegger (2018-11-13 14:13:00) >> Am 13.11.18 um 18:00 schrieb Dylan Baker: >>> Quoting Erik Faye-Lund (2018-11-13 01:34:53) On Mon, 2018-11-12 at 09:22 -0800, Dylan Baker wrote: > Quoting Erik Faye-Lund (2018-11-12 04:51:47)

Re: [Mesa-dev] [ANNOUNCE] Mesa 18.2.5 release candidate

On Mon, Nov 12, 2018 at 8:35 AM Juan A. Suarez Romero wrote: > > Hello list, > > The candidate for the Mesa 18.2.5 is now available. Currently we have: > - 25 queued > - 0 nominated (outstanding) > - and 2 rejected patch If it's not a big deal if would be convenient for me (for Gentoo) to

Re: [Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

On Tue, Nov 13, 2018 at 6:50 PM Rob Clark wrote: > > On Tue, Nov 13, 2018 at 6:19 PM Eric Anholt wrote: > > > > Rob Clark writes: > > > > > On Tue, Nov 13, 2018 at 5:25 PM Eric Anholt wrote: > > >> > > >> Rob Clark writes: > > >> > > >> > If we can't clear all the buffers with pctx->clear()

[Mesa-dev] [PATCH] radeonsi: fix video APIs on Raven2

From: Marek Olšák This was missed when I added the new enum. Cc: 18.3 --- src/gallium/drivers/radeonsi/si_get.c | 9 ++--- src/gallium/drivers/radeonsi/si_uvd.c | 3 ++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_get.c

Re: [Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

On Tue, Nov 13, 2018 at 6:19 PM Eric Anholt wrote: > > Rob Clark writes: > > > On Tue, Nov 13, 2018 at 5:25 PM Eric Anholt wrote: > >> > >> Rob Clark writes: > >> > >> > If we can't clear all the buffers with pctx->clear() (say, for example, > >> > because of ColorMask), push the buffers we

[Mesa-dev] [PATCH 8/8] intel/compiler: Lower SSBO and shared loads/stores in NIR

We have a bunch of code to do this in the back-end compiler but it's fairly specific to typed surface messages and the way we emit them. This breaks it out into NIR were it's easier to do things a bit more generally. It also means we can easily share the code between the bec4 and FS back-ends if

[Mesa-dev] [PATCH 7/8] nir: Add alignment parameters to SSBO, UBO, and shared access

This also changes spirv_to_nir and glsl_to_nir to set them. The one place that doesn't set them is shared memory access lowering in nir_lower_io. That will have to be updated before any consumers of it can effectively use these new alignments. --- src/compiler/glsl/glsl_to_nir.cpp|

[Mesa-dev] [PATCH 2/8] nir/builder: Assert that intN_t immediates fit

This assert won't catch all mistakes with this helper but it will at least ensure that the top bits are all zero or all one which should help catch bugs. --- src/compiler/nir/nir_builder.h | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_builder.h

[Mesa-dev] [PATCH 1/8] nir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16

It messes up when trying to lower. Cc: mesa-sta...@lists.freedesktop.org --- src/compiler/nir/nir_lower_alu_to_scalar.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index 0be3aba9456..7ef032cd164

[Mesa-dev] [PATCH 0/8] intel: Move shared/SSBO access lowering to NIR

In order to properly do all the different kinds of SSBO and SLM writes that we have in GL and Vulkan, we have to do some lowering. The hardware doesn't have instructions for writing a N-bit vecM with an arbitrary write-mask. Instead, we have byte scattered messages which work on a scalar byte,

[Mesa-dev] [PATCH 6/8] nir/glsl: Force 32-bit for UBO and SSBO Booleans

--- src/compiler/glsl/glsl_to_nir.cpp | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 0479f8fcfe4..9bb0f5d4044 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++

[Mesa-dev] [PATCH 3/8] nir/builder: Add iadd_imm and imul_imm helpers

The pattern of adding or multiplying an integer by an immediate is fairly common especially in deref chain handling. This adds a helper for it and uses it a few places. The advantage to the helper is that it automatically handles bit sizes for you. --- src/compiler/nir/nir_builder.h | 12

[Mesa-dev] [PATCH 5/8] nir/spirv: Force 32-bit for UBO and SSBO Booleans

--- src/compiler/spirv/vtn_variables.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 586dcc5b99c..e1e2c8c26ba 100644 --- a/src/compiler/spirv/vtn_variables.c +++

[Mesa-dev] [PATCH 4/8] nir/builder: Add a nir_pack/unpack/bitcast helpers

The new helpers can generate any pack/unpack operation including those for which we do not have specific opcodes and they express a bitcast in terms of these pack/unpack operations. In particular, the new helpers properly handle 8-bit types. --- src/compiler/nir/nir_builder.h | 126

Re: [Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

Rob Clark writes: > On Tue, Nov 13, 2018 at 5:25 PM Eric Anholt wrote: >> >> Rob Clark writes: >> >> > If we can't clear all the buffers with pctx->clear() (say, for example, >> > because of ColorMask), push the buffers we *can* clear with pctx->clear() >> > first. Tilers want to see clears

Re: [Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

On Tue, Nov 13, 2018 at 5:25 PM Eric Anholt wrote: > > Rob Clark writes: > > > If we can't clear all the buffers with pctx->clear() (say, for example, > > because of ColorMask), push the buffers we *can* clear with pctx->clear() > > first. Tilers want to see clears coming before draws to enable

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Quoting Roland Scheidegger (2018-11-13 14:13:00) > Am 13.11.18 um 18:00 schrieb Dylan Baker: > > Quoting Erik Faye-Lund (2018-11-13 01:34:53) > >> On Mon, 2018-11-12 at 09:22 -0800, Dylan Baker wrote: > >>> Quoting Erik Faye-Lund (2018-11-12 04:51:47) > On Fri, 2018-11-09 at 10:40 -0800,

[Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

Use L3 configuration table specified in h/w specification. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/common/gen_l3_config.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 2/5] i965/icl: Set use full ways in L3CNTLREG

L3 allocation table in h/w specification recommends using 4 KB granularity for programming allocation fields in L3CNTLREG. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_defines.h | 1 +

[Mesa-dev] [PATCH 3/5] intel/icl: Set way_size_per_bank to 4

Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/common/gen_l3_config.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c index

[Mesa-dev] [PATCH 5/5] anv/icl: Set use full ways in L3CNTLREG

L3 allocation table in h/w specification recommends using 4 KB granularity for programming allocation fields in L3CNTLREG. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/genxml/gen11.xml | 1 + src/intel/vulkan/genX_cmd_buffer.c

[Mesa-dev] [PATCH 4/5] i965/icl: Set config#9 as default config

Config#6 recommended by h/w specification causes multiple piglit regressions. Use config#9 instead which works well. Setting a weight here so that we get the desired config. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin ---

Re: [Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

Rob Clark writes: > If we can't clear all the buffers with pctx->clear() (say, for example, > because of ColorMask), push the buffers we *can* clear with pctx->clear() > first. Tilers want to see clears coming before draws to enable fast- > paths, and clearing one of the attachments with a

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Am 13.11.18 um 18:00 schrieb Dylan Baker: > Quoting Erik Faye-Lund (2018-11-13 01:34:53) >> On Mon, 2018-11-12 at 09:22 -0800, Dylan Baker wrote: >>> Quoting Erik Faye-Lund (2018-11-12 04:51:47) On Fri, 2018-11-09 at 10:40 -0800, Dylan Baker wrote: > Which has the same behavior.

Re: [Mesa-dev] [PATCH v3] i965: Fix calculation of layers array length for isl_view

On Tue, Nov 13, 2018 at 4:53 PM Jason Ekstrand wrote: > > On Mon, Sep 10, 2018 at 10:21 AM Danylo Piliaiev > wrote: >> >> Handle all cases in calculation of layers count for isl_view >> taking into account texture view and image unit. >> st_convert_image was taken as a reference. >> >> When

Re: [Mesa-dev] [PATCH v2] nir: Allow to skip integer ops in nir_lower_to_source_mods

Looks correct. Reviewed-by: Jason Ekstrand On Mon, Nov 12, 2018 at 2:17 AM Gert Wollny wrote: > From: Gert Wollny > > Some hardware supports source mods only for float operations. Make it > possible to skip lowering to source mods in these cases. > > v2: use option flags instead of a boolean

Re: [Mesa-dev] [PATCH v3] i965: Fix calculation of layers array length for isl_view

On Mon, Sep 10, 2018 at 10:21 AM Danylo Piliaiev wrote: > Handle all cases in calculation of layers count for isl_view > taking into account texture view and image unit. > st_convert_image was taken as a reference. > > When u->Layered is true the whole level is taken with respect to > image

Re: [Mesa-dev] [PATCH] st/mesa: don't do L3 thread pinning for Blender

Hi Marek Sure. Thanks for writing these patches. The looks good. I've done some small testing: drawoverhead numbers looks great in my eyes: 29: DrawElements ( 1 VBO, 8 UBO, 8 Tex) w/ sample mask enable change: 6.63 million (94.7%) Hitman benchmark runs nicely, even slightly bit faster

Re: [Mesa-dev] [PATCH 1/2] nir: add lowering for ffloor

On Tue, Nov 13, 2018 at 3:21 PM Roland Scheidegger wrote: > Am 12.11.18 um 20:40 schrieb Jason Ekstrand: > > On Mon, Nov 12, 2018 at 1:29 PM Christian Gmeiner > > mailto:christian.gmei...@gmail.com>> > wrote: > > > > Hi Jason > > > > Am Sa., 1. Sep. 2018 um 21:23 Uhr schrieb Jason

Re: [Mesa-dev] [PATCH 05/22] nir/spirv: cast shift operand to u32

yeah... I planned to push the first two patches some time ago. Simply forgot about those. On Tue, Nov 13, 2018 at 10:13 PM Jason Ekstrand wrote: > > Also, I don't see why this one and the first two can't land today. They're > obvious clean-ups. > > On Tue, Nov 13, 2018 at 3:11 PM Jason Ekstrand

[Mesa-dev] [PATCH 2/2] radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSED

From: Marek Olšák Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102597 Cc: 18.3 --- src/gallium/drivers/radeonsi/si_query.c | 15 --- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_query.c

[Mesa-dev] [PATCH 1/2] radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TS

From: Marek Olšák There are no writes. --- src/gallium/drivers/radeonsi/si_fence.c | 3 +-- src/gallium/drivers/radeonsi/si_perfcounter.c | 3 +-- src/gallium/drivers/radeonsi/si_query.c | 8 +++- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 1/2] nir: add lowering for ffloor

Am 12.11.18 um 20:40 schrieb Jason Ekstrand: > On Mon, Nov 12, 2018 at 1:29 PM Christian Gmeiner > mailto:christian.gmei...@gmail.com>> wrote: > > Hi Jason > > Am Sa., 1. Sep. 2018 um 21:23 Uhr schrieb Jason Ekstrand > mailto:ja...@jlekstrand.net>>: > > > > I don't think

Re: [Mesa-dev] [PATCH 05/22] nir/spirv: cast shift operand to u32

Also, I don't see why this one and the first two can't land today. They're obvious clean-ups. On Tue, Nov 13, 2018 at 3:11 PM Jason Ekstrand wrote: > Reviewed-by: Jason Ekstrand > Cc: mesa-sta...@lists.freedesktop.org > > On Tue, Nov 13, 2018 at 9:48 AM Karol Herbst wrote: > >> v2: fix for

Re: [Mesa-dev] [PATCH 05/22] nir/spirv: cast shift operand to u32

Reviewed-by: Jason Ekstrand Cc: mesa-sta...@lists.freedesktop.org On Tue, Nov 13, 2018 at 9:48 AM Karol Herbst wrote: > v2: fix for specialization constants as well > > Signed-off-by: Karol Herbst > --- > src/compiler/spirv/spirv_to_nir.c | 20 >

[Mesa-dev] [PATCH 4/9] freedreno: a2xx: set VIZ_QUERY_ID on a20x

Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c index 20bfd06b13..50e2fe13eb 100644 ---

[Mesa-dev] [PATCH 7/9] freedreno: use GENERIC instead of TEXCOORD for blit program

blip_fp uses GENERIC as input, so blit_vp should match for linking Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/freedreno_program.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/freedreno/freedreno_program.c

[Mesa-dev] [PATCH 8/9] freedreno: implement a20x hw binning

Not in this patch: emitting the hw binning variant and filling the "draw_patches". That is part of the ir2 patch. Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_draw.c | 47 +-- src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 8 +-

[Mesa-dev] [PATCH 6/9] freedreno: a2xx texture update

Adds all missing texture related logic. For everything to work it also needs changes to ir2/fd2_program, which are part of the ir2 update patch. Note: it needs rnndb update Signed-off-by: Jonathan Marek --- .../drivers/freedreno/Makefile.sources| 2 +

[Mesa-dev] [PATCH 2/9] freedreno: a2xx: fix POINT_MINMAX_MAX overflow

As it stands, it overflows to zero. Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_rasterizer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_rasterizer.c

[Mesa-dev] [PATCH 5/9] a2xx: Compute depth base in gmem correctly

Note: it needs rnndb update Signed-off-by: Marek Vasut Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_gmem.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c

[Mesa-dev] [PATCH 1/9] freedreno: a2xx: fd2_draw update for a20x

Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/a2xx/fd2_draw.c | 97 --- .../drivers/freedreno/freedreno_batch.c | 1 + .../drivers/freedreno/freedreno_batch.h | 1 + .../drivers/freedreno/freedreno_draw.c| 2 +

[Mesa-dev] [PATCH 3/9] freedreno: add missing a20x ids

200: 256KiB GMEM A200 (imx53) 201: 128KiB GMEM A200 (imx51) Signed-off-by: Jonathan Marek --- src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c

[Mesa-dev] [RFC] mesa/st: better colormask check for clear fallback

For RGB surfaces (for example) we don't really care that the colormask is 0x7 instead of 0xf. This should not trigger clear_with_quad() slowpath. Signed-off-by: Rob Clark --- This avoids some mem->gmem for webgl and probably other things using a RGB surface. This should be ok for 24b packed

Re: [Mesa-dev] [PATCH 06/13] anv: move helper function internally

Thanks, pushed 1-6 for now. On 08/11/2018 22:42, Jason Ekstrand wrote: I left a nit on 3.  Otherwise, 1-6 are Reviewed-by: Jason Ekstrand > On Mon, Nov 5, 2018 at 9:36 AM Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>> wrote: It's only used in

[Mesa-dev] [PATCH] mesa/st: swap order of clear() and clear_with_quad()

If we can't clear all the buffers with pctx->clear() (say, for example, because of ColorMask), push the buffers we *can* clear with pctx->clear() first. Tilers want to see clears coming before draws to enable fast- paths, and clearing one of the attachments with a quad-draw first confuses that

[Mesa-dev] [PATCH 3/3] st/xa: Support Component Alpha with trivial blending

Support Component Alpha for those composite operations that do not require per-channel alpha blending. Signed-off-by: Thomas Hellstrom Reviewed-by: Brian Paul --- src/gallium/state_trackers/xa/xa_composite.c | 33 src/gallium/state_trackers/xa/xa_priv.h | 1 +

Re: [Mesa-dev] [RFC PATCH 7/8] mesa/main: Remove now superfluos tests for both EXT_sRGB and EXT_framebuffer_sRGB

Why not order the series such that this commit is not needed? On Tue, Nov 13, 2018 at 12:28 PM Gert Wollny wrote: > > From: Gert Wollny > > Signed-off-by: Gert Wollny > --- > src/mesa/main/fbobject.c | 2 +- > src/mesa/main/teximage.c | 3 +-- > src/mesa/main/version.c | 5 ++--- > 3 files

[Mesa-dev] [PATCH 1/3] st/xa: Fix transformations when we have both source and mask samplers

In the case when we had both source and mask samplers, transformations were typically not applied correctly. Signed-off-by: Thomas Hellstrom Reviewed-by: Brian Paul --- src/gallium/state_trackers/xa/xa_renderer.c | 117 1 file changed, 49 insertions(+), 68 deletions(-)

[Mesa-dev] [PATCH 2/3] st/xa: Minor renderer cleanups

constify function arguments to clean up the code a bit. Reported-by: Brian Paul Signed-off-by: Thomas Hellstrom Reviewed-by: Brian Paul --- src/gallium/state_trackers/xa/xa_renderer.c | 24 ++--- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git

Re: [Mesa-dev] [RFC PATCH 4/8] mesa/main/version: Lower the requirements for GLES 3.0

Is ARB_framebuffer_object really needed? IIRC one of the sticking points is that it allows differently-sized render targets. Does ES3 allow that? If so, this is fine. On Tue, Nov 13, 2018 at 12:28 PM Gert Wollny wrote: > > From: Gert Wollny > > GLES 3.0 does not actually require support for

Re: [Mesa-dev] [PATCH 2/2] util/ralloc: Make sizeof(linear_header) a multiple of 8

On Tue, Nov 13, 2018 at 9:43 AM Emil Velikov wrote: > > Hi Matt, > > On Mon, 12 Nov 2018 at 21:26, Matt Turner wrote: > > > > Prior to this patch sizeof(linear_header) was 20 bytes in a > > non-debug build on 32-bit platforms. We do some pointer arithmetic to > > calculate the next available

Re: [Mesa-dev] [PATCH 2/2] util/ralloc: Make sizeof(linear_header) a multiple of 8

Hi Matt, On Mon, 12 Nov 2018 at 21:26, Matt Turner wrote: > > Prior to this patch sizeof(linear_header) was 20 bytes in a > non-debug build on 32-bit platforms. We do some pointer arithmetic to > calculate the next available location with > >ptr = (linear_size_chunk *)((char *)[1] +

Re: [Mesa-dev] [RFC PATCH 1/8] Gallium: Add new CAPS to indicate whether a driver can switch SRGB write

On Tue, Nov 13, 2018 at 12:28 PM Gert Wollny wrote: > > From: Gert Wollny > > Add a new cap that indicates whether the drivers supports > enabling/disabling the conversion from linear space to sRGB > for a framebuffer attachment. > > Signed-off-by: Gert Wollny > --- >

[Mesa-dev] [RFC PATCH 7/8] mesa/main: Remove now superfluos tests for both EXT_sRGB and EXT_framebuffer_sRGB

From: Gert Wollny Signed-off-by: Gert Wollny --- src/mesa/main/fbobject.c | 2 +- src/mesa/main/teximage.c | 3 +-- src/mesa/main/version.c | 5 ++--- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c index

[Mesa-dev] [RFC PATCH 8/8] mesa/main: Expose EXT_sRGB_write_control

From: Gert Wollny Use EXT_framebuffer_sRGB to expose EXT_sRGB_write_control on GLES. Remove the checks for desktion GL in the enable calls, since EXT_framebuffer_sRGB now also indicates support for switching the linear-sRGB color space conversion on GLES. Thanks to Ilia Mirkin for all the

[Mesa-dev] [RFC PATCH 6/8] i965: Set flag for EXT_sRGB

From: Gert Wollny Signed-off-by: Gert Wollny --- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index d7e02efb54..ca369e39f2 100644 ---

[Mesa-dev] [RFC PATCH 5/8] mesa/st: rework support for sRGB framebuffer attachements

From: Gert Wollny For GLES sRGB framebuffer attachemnt support is provided in two steps: sRGB attachments like described in EXT_sRGB and GLES 3.0 that enable linear to sRGB color space transformation automatically, and sRGB write control that brings GLES on par with EXT_framebuffer_sRGB. Set the

[Mesa-dev] [RFC PATCH 3/8] mesa/main: Add flag for EXT_sRGB and use it parallel with EXT_framebuffer_sRGB

From: Gert Wollny EXT_sRGB is an (incomplete) GLES extension that provides support for sRGB framebuffer attachments, hence it can be used to check for this support as an alternative to EXT_framebuffer_sRGB that provies the same functionality but also sRGB write control support. All drivers that

[Mesa-dev] [RFC PATCH 4/8] mesa/main/version: Lower the requirements for GLES 3.0

From: Gert Wollny GLES 3.0 does not actually require support for EXT_framebuffer_sRGB, it only needs support for sRGB attachments to framebuffers. Signed-off-by: Gert Wollny --- src/mesa/main/version.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [RFC PATCH 2/8] virgl: Set sRGB write control CAP based on host capabilities

From: Gert Wollny Signed-off-by: Gert Wollny --- src/gallium/drivers/virgl/virgl_hw.h | 1 + src/gallium/drivers/virgl/virgl_screen.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/gallium/drivers/virgl/virgl_hw.h b/src/gallium/drivers/virgl/virgl_hw.h index

[Mesa-dev] [RFC PATCH 1/8] Gallium: Add new CAPS to indicate whether a driver can switch SRGB write

From: Gert Wollny Add a new cap that indicates whether the drivers supports enabling/disabling the conversion from linear space to sRGB for a framebuffer attachment. Signed-off-by: Gert Wollny --- src/gallium/auxiliary/util/u_screen.c | 3 +++ src/gallium/docs/source/screen.rst| 3 +++

[Mesa-dev] [RFC PATCH 0/8] Add and enable extension EXT_sRGB_write_control (reworked)

From: Gert Wollny Dear all, based on the feedback given by Ilia I've completely reworked the series to add internal support for EXT_sRGB as a stepstone to implement EXT_sRGB_write_control and expose GLES 3.0 properly. Since the series has been reworked thoroughly, most of the original patches

Re: [Mesa-dev] [PATCH mesa] xmlpool: update translation po files

On Tuesday, 2018-11-13 13:37:14 +, Emil Velikov wrote: > On Mon, 12 Nov 2018 at 18:14, Dylan Baker wrote: > > > > Quoting Eric Engestrom (2018-11-12 09:47:22) > > > On Monday, 2018-11-12 16:56:32 +, Emil Velikov wrote: > > > > On Mon, 12 Nov 2018 at 14:24, Eric Engestrom > > > > wrote:

Re: [Mesa-dev] [PATCH v2 5/5] intel/tools: avoid 'ignoring return value'

On Tuesday, 2018-11-13 14:19:32 +0200, asimiklit.w...@gmail.com wrote: > From: Andrii Simiklit > > 1. tools/i965_disasm.c:58:4: warning: > ignoring return value of ‘fread’, > declared with attribute warn_unused_result > fread(assembly, *end, 1, fp); > > v2: - Fixed incorrect

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Quoting Erik Faye-Lund (2018-11-13 01:34:53) > On Mon, 2018-11-12 at 09:22 -0800, Dylan Baker wrote: > > Quoting Erik Faye-Lund (2018-11-12 04:51:47) > > > On Fri, 2018-11-09 at 10:40 -0800, Dylan Baker wrote: > > > > Which has the same behavior. > > > > > > Does it? I'm not so sure... IROUND_POS

Re: [Mesa-dev] [PATCH v2 4/5] main: avoid 'may be used uninitialized' warnings

On Tuesday, 2018-11-13 14:19:31 +0200, asimiklit.w...@gmail.com wrote: > From: Andrii Simiklit > > 1. main/texcompress_etc.c:1314:12: > warning: ‘*((void *)+2)’ may be used uninitialized in this function > 2. main/texcompress_etc.c:1354:12: > warning: ‘*((void *)+2)’ may be used

[Mesa-dev] [Bug 108734] Regression: [bisected] dEQP-GLES31.functional.tessellation.invariance.* start failing on r600

https://bugs.freedesktop.org/show_bug.cgi?id=108734 Bug ID: 108734 Summary: Regression: [bisected] dEQP-GLES31.functional.tessellation.invariance.* start failing on r600 Product: Mesa Version: git

Re: [Mesa-dev] [PATCH v2 3/5] i965: avoid 'unused variable'

On Tuesday, 2018-11-13 14:19:30 +0200, asimiklit.w...@gmail.com wrote: > From: Andrii Simiklit > > 1. brw_pipe_control.c:311:34: warning: > unused variable ‘devinfo’ > 2. brw_program_binary.c:209:19: warning: > unused variable ‘gen_size’ > 3. brw_program_binary.c:216:19: warning: >

Re: [Mesa-dev] [PATCH] egl/dri: fix error value with unknown drm format

On 13/11/2018 15:43, Emil Velikov wrote: On Tue, 13 Nov 2018 at 14:11, Lionel Landwerlin wrote: According to the EGL_EXT_image_dma_buf_import spec, creating an EGL image with a DRM format not supported should yield the BAD_MATCH error : " * If is EGL_LINUX_DMA_BUF_EXT, and the

[Mesa-dev] [PATCH 22/22] nir/spirv: handle OpBitcasts for pointers

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 5 +- src/compiler/spirv/vtn_alu.c | 187 +- src/compiler/spirv/vtn_private.h | 3 + 3 files changed, 115 insertions(+), 80 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c

[Mesa-dev] [PATCH 14/22] nir: add legal bit_sizes to intrinsics

With OpenCL some system values match the address bits, but in GLSL we also have some system values being 64 bit. With this it is possible to adjust the builder functions so that depending on the bit_sizes the correct bit_size is used or an additional argument is added in case of multiple possible

[Mesa-dev] [PATCH 20/22] nir/spirv: physical pointer support

this adds support for pointers from CL kernels. The basic idea here is to be able to start a deref chain from a random ssa value and vice versa. changes summed up: 1. derefs can start from a deref_cast 2. new ptr_as_array deref type to offset a pointer 3. derefs can end with a ssa_from_deref

[Mesa-dev] [PATCH 19/22] nir/spirv: handle kernel function parameters

the idea here is to generate an entry point stub function wrapping around the actual kernel function and turn all parameters into shader inputs with byte addressing instead of vec4. This gives us several advantages: 1. calling kernel functions doesn't differ from calling any other function 2. CL

[Mesa-dev] [PATCH 03/22] nir/spirv: initial handling of OpenCL.std extension opcodes

Not complete, mostly just adding things as I encounter them in CTS. But not getting far enough yet to hit most of the OpenCL.std instructions. Anyway, this is better than nothing and covers the most common builtins. Signed-off-by: Karol Herbst --- src/compiler/nir/meson.build | 1 +

[Mesa-dev] [PATCH 12/22] nir: add type alignment support to lower_io

From: Rob Clark For cl we can have structs with 8/16/32/64 bit scalar types (as well as, ofc, arrays/structs/etc), which are padded according to 'C' rules. So for lowering struct deref's we need to not just consider a field's size, but also it's alignment. Signed-off-by: Karol Herbst ---

[Mesa-dev] [PATCH 17/22] nir: rename global to private memory

the naming is a bit confusing no matter how you look at it. Within OpenCL "global" memory is memory accessible from all threads. glsl "global" memory normally refers to shader thread private memory declared at global scope. As we already use "shared" for memory shared across all thrads of a work

[Mesa-dev] [PATCH 15/22] nir: add support for address bit sized system values

Signed-off-by: Karol Herbst --- src/amd/vulkan/radv_meta_buffer.c | 8 ++-- src/amd/vulkan/radv_meta_bufimage.c | 16 src/amd/vulkan/radv_meta_fast_clear.c | 4 +- src/amd/vulkan/radv_meta_resolve_cs.c | 4 +- src/amd/vulkan/radv_query.c

[Mesa-dev] [PATCH 09/22] glsl: add cl_size and cl_alignment

Signed-off-by: Karol Herbst --- src/compiler/glsl_types.cpp | 48 + src/compiler/glsl_types.h | 10 src/compiler/nir_types.cpp | 12 ++ src/compiler/nir_types.h| 4 4 files changed, 74 insertions(+) diff --git

[Mesa-dev] [PATCH 13/22] nir/spirv: parse memory model

Signed-off-by: Karol Herbst --- src/compiler/nir/nir.h| 8 src/compiler/nir/nir_clone.c | 1 + src/compiler/nir/nir_serialize.c | 2 ++ src/compiler/spirv/spirv_to_nir.c | 15 +-- 4 files changed, 24 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 04/22] nir/spirv: add OpIsFinite and OpIsNormal

From: Rob Clark changes by Karol: v2: make compatible with 64 bit floats fix isfinite v3: use snake_case. Signed-off-by: Karol Herbst --- src/compiler/spirv/vtn_alu.c | 32 1 file changed, 32 insertions(+) diff --git a/src/compiler/spirv/vtn_alu.c

[Mesa-dev] [PATCH 10/22] nir/vtn: add caps for some cl related capabilities

From: Rob Clark vtn supports these, so don't squalk if user is happy with enabling these. Signed-off-by: Karol Herbst --- src/compiler/shader_info.h | 3 +++ src/compiler/spirv/spirv_to_nir.c | 16 +--- src/compiler/spirv/vtn_variables.c | 6 -- 3 files changed, 20

[Mesa-dev] [PATCH 05/22] nir/spirv: cast shift operand to u32

v2: fix for specialization constants as well Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 20 src/compiler/spirv/vtn_alu.c | 11 +++ 2 files changed, 31 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c

[Mesa-dev] [PATCH 21/22] spirv/cl: support vload/vstore

Signed-off-by: Karol Herbst --- src/compiler/spirv/vtn_opencl.c | 59 + 1 file changed, 59 insertions(+) diff --git a/src/compiler/spirv/vtn_opencl.c b/src/compiler/spirv/vtn_opencl.c index 089e6168fd8..ecaca4c17bc 100644 --- a/src/compiler/spirv/vtn_opencl.c +++

[Mesa-dev] [PATCH 07/22] glsl: add packed for struct types

We need this for OpenCL kernels because we have to apply C rules for alignment and padding inside structs and for this we also have to know if a struct is packed or not. Signed-off-by: Karol Herbst --- src/compiler/glsl_types.cpp | 17 +++-- src/compiler/glsl_types.h |

[Mesa-dev] [PATCH 16/22] nir+vtn: vec8+vec16 support

This introduces new vec8 and vec16 instructions (which are the only instructions taking more than 4 sources), in order to construct 8 and 16 component vectors. In order to avoid fixing up the non-autogenerated nir_build_alu() sites and making them pass 16 src args for the benefit of the two

[Mesa-dev] [PATCH 08/22] glsl: add glsl_base_get_byte_size

Signed-off-by: Karol Herbst --- src/compiler/glsl_types.h | 34 ++ src/compiler/nir_types.h | 30 +- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h index

[Mesa-dev] [PATCH 06/22] vtn: handle SpvExecutionModelKernel

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 3 +++ src/compiler/spirv/vtn_private.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 2c214324774..650eb6a977c 100644 ---

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