Re: [Mesa-dev] [PATCH] nir: shuffle fmuls to allow const evaluation

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] Fwd: New Defects reported by Coverity Scan for Mesa

Coverity thinks there are some bad shifts introduced by commit c2acf97. I think it thinks that first can be 64 because 64 is the greatest value that can be returned by ffsll(), but that's not actually possible? If that's correct, maybe an assert is in order. ** CID 1398563:(BAD_SHIFT)

Re: [Mesa-dev] [PATCH 04/11] i965/vec4/nir: vec4 also need to remap vs attributes

On 01/09, Juan A. Suarez Romero wrote: From: Alejandro Piñeiro Doubles need extra space, so we would need to do a remapping for vec4 too in order to take that into account. We reuse the already existing remap_vs_attrs, but passing is_scalar, so they could remap

Re: [Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

On Sun, Jan 8, 2017 at 10:53 PM, Matt Turner <matts...@gmail.com> wrote: > On 01/05, Samuel Iglesias Gonsálvez wrote: >> >> From: "Juan A. Suarez Romero" <jasua...@igalia.com> >> >> When dealing with DF uniforms with just 1 component, we set

Re: [Mesa-dev] [PATCH v2] Rename the DEBUG macro to MESA_DEBUG

I don't like adding workarounds to our codebase for someone else's problem, generally, but specifically I think this is a bad idea because the name MESA_DEBUG is already used (it's an environment variable), and this is a completely separate meaning. ___

Re: [Mesa-dev] [PATCH] glsl: Do not allow scalar types in vector relational functions

On Mon, Jan 9, 2017 at 6:34 AM, Boyan Ding <boyan.j.d...@gmail.com> wrote: > 2016-11-23 21:20 GMT+08:00 Boyan Ding <boyan.j.d...@gmail.com>: >> 2016-11-07 20:27 GMT+08:00 Boyan Ding <boyan.j.d...@gmail.com>: >>> 2016-11-05 3:23 GMT+08:00 Matt Turner <matts..

Re: [Mesa-dev] [PATCH 00/22] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

I have just started reviewing the series, and I have two trivial comments that seem to apply to a number of patches. The first is that we prefer to use the name BayTrail (abbreviation BYT) instead of Valleyview (and its abbreviation VLV) in comments. I'm not really sure why, to be honest. The

Re: [Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

On 01/05, Samuel Iglesias Gonsálvez wrote: From: "Juan A. Suarez Romero" When dealing with DF uniforms with just 1 component, we set stride 0 to use the value along the operation. However, when duplicating the regioning parameters in IVB/VLV, we are violating the regioning

Re: [Mesa-dev] [PATCH 03/22] i965/fs: duplicate regioning parameters and execsize for DF in IVB/VLV

prisingly good job of always using the name BayTrail (BYT) instead of Valleyview (VLV) in i965. Let's s/Valleyview/BayTrail/ This also applies to BayTrail. Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature __

Re: [Mesa-dev] [PATCH 01/22] i965/disasm: also print nibctrl in IVB for execsize=8

... } this is just the disassembler, so we don't need to implement logic that decides when NibCtrl is valid and when it's not -- just disassemble what's there :) (I renamed nib_ctl -> nib_ctrl in the above block intentionally to match the field name). You can pre

Re: [Mesa-dev] [PATCH] mapi: update the asm code to support x32

On Sun, Jan 8, 2017 at 9:38 AM, Grazvydas Ignotas wrote: > Fixes crashes when both glx-tls and asm are enabled on x32. > > Cc: mesa-sta...@lists.freedesktop.org > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94512 > Signed-off-by: Grazvydas Ignotas

Re: [Mesa-dev] [PATCH 1/2] mesa: Bump the version to 17.0

Both look good to me. Thanks for doing that. Acked-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 07/10] nir: add imprecise flrp optimisation

On Sat, Jan 7, 2017 at 3:58 AM, Timothy Arceri wrote: > On BDW: > > total instructions in shared programs: 13061890 -> 13061877 (-0.00%) > instructions in affected programs: 2441 -> 2428 (-0.53%) > helped: 13 > HURT: 0 > > total cycles in shared programs: 256612254

Re: [Mesa-dev] [PATCH 10/10] nir: add late opt to turn inot/b2f combos back to bcsel

On Sat, Jan 7, 2017 at 3:58 AM, Timothy Arceri wrote: > We turn these from bcsel into inot/b2f combos in order for other > optimisation passes to get further, once we have finished turn > the ones that remain and are used in more than a single expression > back into

Re: [Mesa-dev] [PATCH 01/10] nir: Convert ineg(b2i(a)) to a if it's a boolean.

, was Ken noticed it was subtly wrong. Maybe you can spot another way of doing the same thing. Regardless, Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Fix texturing in the vec4 TCS and GS backends.

On Fri, Jan 6, 2017 at 10:27 AM, Jason Ekstrand wrote: > Sorry I didn't fix vec4 when I fixed fs. :-( > > Reciewed-by: Jason Ekstrand Ken, make sure to fix the "Reciewed" typo when applying the patch. ___

Re: [Mesa-dev] [PATCH] i965: Allow a per gen timebase scale factor

application couldn't use > - * GL_QUERY_COUNTER_BITS to handle rollover correctly. Instead, we > - * report 36 bits and truncate at that (rolling over 5 times as often > - * as the HW counter), and when the 32-bit counter rolls over, it > - * happens to also be at a rollover in the reported value from near > - * (1<<36) to 0. > - * > - * The low 32 bits rolls over in ~343 seconds. Our 36-bit result > - * rolls over every ~69 seconds. > - * > - * The query BO contains a single timestamp value in results[0]. > + /* The query BO contains a single timestamp value in results[0]. */ > + query->Base.Result = brw_timebase_scale(brw, results[0]); > + > + /* Ensure the scaled timestamp overflows according to > + * GL_QUERY_COUNTER_BITS > */ > - query->Base.Result = 80 * (results[0] & 0x); > - query->Base.Result &= (1ull << 36) - 1; > + query->Base.Result &= (1ull << ctx->Const.QueryCounterBits.Timestamp) > - 1; >break; > > case GL_SAMPLES_PASSED_ARB: > -- > 2.11.0 Looks good to me. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] configure: Fix another bashism.

Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] vec4: use DIM instruction when loading DF immediates in HSW

On Wed, Jan 4, 2017 at 6:36 AM, Samuel Iglesias Gonsálvez <sigles...@igalia.com> wrote: > On Tue, 2017-01-03 at 12:14 -0500, Matt Turner wrote: >> On Tue, Jan 3, 2017 at 7:27 AM, Samuel Iglesias Gonsálvez >> <sigles...@igalia.com> wrote: >> > Signed-off-b

Re: [Mesa-dev] [PATCH 2/2] i965/disasm: remove printing hstride and width in align16 DF source regions

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] vec4: use DIM instruction when loading DF immediates in HSW

dst = retype(dst_reg(VGRF, alloc.allocate(2)), > BRW_REGISTER_TYPE_DF); Does this need to be alloc.allocate(2)? Since we're just loading 64-bits worth of data, shouldn't one register be fine? If that is indeed okay, then with that change: Reviewed-by: Matt Turner <matts...@gmail

Re: [Mesa-dev] [PATCH] i965/fs: fix exec_size when emitting DIM instruction

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] swr: Fix BugID 9919 compile error (icc-only).

On Thu, Dec 22, 2016 at 7:06 PM, Bruce Cherniak wrote: > ICC doesn't like the use of nullptr (std::nullptr_t) argument in > p_atomic_set. GCC and clang don't complain. Is BugID 9919 publicly accessible? If so, I'd provide a link to it. If it's not, I'd include the

Re: [Mesa-dev] [PATCH 13/13] i965: disable loop unrolling in GLSL IR

On Wed, Dec 21, 2016 at 8:26 PM, Timothy Arceri wrote: > There is a single regression in loop unrolling which is: > > loops HURT: shaders/orbital_explorer.shader_test GS SIMD8:0 -> 1 > > However the loop is huge so it seems reasonable not to unroll it. It's >

Re: [Mesa-dev] [PATCH 13/13] i965: disable loop unrolling in GLSL IR

On Thu, Dec 22, 2016 at 2:07 PM, Jason Ekstrand wrote: > I have no real opinion on this patch. Matt? Ken? I'm generally in favor. I suggested Tim split this off from his other patch which enabled NIR loop unrolling so that we could see what contributions each logical

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Tue, Dec 13, 2016 at 2:01 AM, Samuel Iglesias Gonsálvez <sigles...@igalia.com> wrote: > On Mon, 2016-12-05 at 15:21 -0800, Matt Turner wrote: >> i965/vec4: add a helper function to create double immediates >> >> Can leave for later: Shouldn't we use the DIM i

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Wed, Dec 21, 2016 at 10:01 AM, Matt Turner <matts...@gmail.com> wrote: > On Tue, Oct 11, 2016 at 4:01 AM, Iago Toral Quiroga <ito...@igalia.com> wrote: >> i965/disasm: fix subreg for dst in Align16 mode > > I just noticed that this commit has a rebase mistake. Tim

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Tue, Oct 11, 2016 at 4:01 AM, Iago Toral Quiroga wrote: > i965/disasm: fix subreg for dst in Align16 mode I just noticed that this commit has a rebase mistake. Tim changed the code in July to use PRIu64, but this patch reverts back to %u.

Re: [Mesa-dev] [PATCH] glsl: Fix program interface queries relating to interface blocks.

On Mon, Dec 19, 2016 at 4:13 PM, Kenneth Graunke wrote: > For what it's worth, the OpenGL wiki's Program Introspection page(*), > under "Interface block member naming" gives an example matching my above > reply. It says: > > uniform BlockName3 > { > int mem;

Re: [Mesa-dev] [PATCH v3] compiler/glsl: fix precision problem of tanh

On Mon, Dec 19, 2016 at 5:12 PM, Giuseppe Bilotta wrote: > Just one question though —not knowing much of the shader language, can > I expect expm1 to be available? No, expm1 doesn't exist in GLSL. ___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

also pinged Curro to ask if he'll review it. > * i965/vec4: add a SIMD lowering pass > > Replied here [1]. Silly messy hardware. :) > * i965/vec4: Prevent copy propagation from violating pre-gen8 > restrictions > > Replied here [1]. > > * i965/vec4: run scalarize_

Re: [Mesa-dev] [PATCH] Mesa: Return GL error INVALID_OPERATION in case invalid format/type

On Thu, Dec 15, 2016 at 5:19 PM, Matt Turner <matts...@gmail.com> wrote: > On Wed, Dec 14, 2016 at 5:10 PM, Randy Xu <randy...@intel.com> wrote: >> From: "Xu,Randy" <randy...@intel.com> > > Reminder to fix your configured name. And also please stop C

Re: [Mesa-dev] [PATCH] Mesa: Return GL error INVALID_OPERATION in case invalid format/type

On Wed, Dec 14, 2016 at 5:10 PM, Randy Xu wrote: > From: "Xu,Randy" Reminder to fix your configured name. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH] Mesa: Return GL error INVALID_OPERATION in case invalid format/type

On Tue, Dec 13, 2016 at 4:28 AM, Randy Xu wrote: > From: "Xu,Randy" Please configure your name properly: git config --global user.name "Randy Xu" > > Refer to GLES3.2 spec in 8.5 > Textures with a base internal format of DEPTH_COMPONENT, DEPTH_- >

Re: [Mesa-dev] Proposal of date-based Mesa versioning for 2017

On Mon, Dec 12, 2016 at 7:28 AM, Emil Velikov wrote: > * Should we drop the $VERSION directory in the URL, since it causes a > fair bit of nuisance during RC stage. > Namely from: > https://mesa.freedesktop.org/archive/$VERSION/mesa-$VERSION.tar.{xz,gz} > to: >

Re: [Mesa-dev] [PATCH] i965: Print out cycle estimates at the start of block annotations.

Good plan. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

i965/vec4: handle 32 and 64 bit channels in liveness analysis Please indent the returned multiline expressions in var_from_reg() like we do elsewhere, so that the second line begins on the same column as the first line. */ goes on its own line. I'm

Re: [Mesa-dev] [PATCH] glsl: Make copy propagation not panic when it sees an intrinsic.

On Fri, Dec 9, 2016 at 8:28 PM, Kenneth Graunke wrote: > A number of games have large arrays of constants, which we promote to > uniforms. This introduces copies from the uniform array to the original > temporary array. Normally, copy propagation eliminates those copies,

Re: [Mesa-dev] [PATCH] automake: make the build less chatty

On Thu, Dec 8, 2016 at 6:55 AM, Emil Velikov wrote: > On 8 December 2016 at 14:07, Nicolai Hähnle wrote: >> On 08.12.2016 12:30, Emil Velikov wrote: >>> >>> On 7 December 2016 at 20:20, Eric Anholt wrote: Emil Velikov

Re: [Mesa-dev] [PATCH] i965: Drop redundant key->outputs_written initialization.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Initialize "separate" flag in VUE maps.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 15/18] i965: Validate "General Restrictions on Regioning Parameters"

Ken reviewed all the easy patches, up to this point in the series. Does anyone else want to review the rest? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/4] i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.

Ping. This series fixes a real bug that affects multiple games. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

struction to backend_instruction i965/vec4: fix size_written for doubles i965/vec4: fix regs_read() for doubles i965/vec4: use the IR's execution size i965/vec4: dump the instruction execution size I made it to here today. Anything with no or trivial feedback is Reviewed-by: Matt Turne

Re: [Mesa-dev] [PATCH 00/50] GL_ARB_gpu_shader_int64... this time for sure!

On Mon, Dec 5, 2016 at 2:20 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > On Mon, Dec 5, 2016 at 5:09 PM, Connor Abbott <cwabbo...@gmail.com> wrote: >> On Mon, Dec 5, 2016 at 3:22 PM, Matt Turner <matts...@gmail.com> wrote: >>> On 12/05, Matt Turner wrote: &g

[Mesa-dev] [PATCH] i965: Emit proper NOPs.

The PRMs for HSW and newer say that other than the opcode and DebugCtrl bits of the instruction word, the rest must be zero. By zeroing the instruction word manually, we avoid using any of the state inherited through brw_codegen. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=96959 ---

Re: [Mesa-dev] [PATCH 00/50] GL_ARB_gpu_shader_int64... this time for sure!

On 12/05, Matt Turner wrote: On 11/28, Ian Romanick wrote: From: Ian Romanick <ian.d.roman...@intel.com> Patches 42 through 50 enable the extension on BDW+. 42-48 are Reviewed-by: Matt Turner <matts...@gmail.com> I don't understand the 64-bit CMP issue, so I'm booting a SK

Re: [Mesa-dev] [PATCH 00/50] GL_ARB_gpu_shader_int64... this time for sure!

On 11/28, Ian Romanick wrote: From: Ian Romanick <ian.d.roman...@intel.com> Patches 42 through 50 enable the extension on BDW+. 42-48 are Reviewed-by: Matt Turner <matts...@gmail.com> I don't understand the 64-bit CMP issue, so I'm booting a SKL to see how fp64 works. s

Re: [Mesa-dev] [PATCH 00/50] GL_ARB_gpu_shader_int64... this time for sure!

On Wed, Nov 30, 2016 at 1:11 PM, Matt Turner <matts...@gmail.com> wrote: > On 11/28, Ian Romanick wrote: >> >> From: Ian Romanick <ian.d.roman...@intel.com> >> >> I believe that I have addressed all of the review feedback from the >> previous itera

Re: [Mesa-dev] [PATCH] glsl: fix ldexp lowering if bitfield insert lowering is also requested

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i915: Stop claiming GL 2.1 support.

On Fri, Dec 2, 2016 at 12:22 PM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 2 December 2016 at 19:49, Matt Turner <matts...@gmail.com> wrote: >> A user reporting an unrelated bug (98964) said that he has to set >> MESA_GL_VERSION_OVERRIDE=1.4 when running

[Mesa-dev] [PATCH] i915: Stop claiming GL 2.1 support.

A user reporting an unrelated bug (98964) said that he has to set MESA_GL_VERSION_OVERRIDE=1.4 when running Chromium otherwise it's too slow. I presume that it's attempting to use GL 2.0/2.1 features that aren't hardware-supported on i915. --- src/mesa/drivers/dri/i915/intel_screen.c | 2 +- 1

Re: [Mesa-dev] [PATCH 14/18] i965: Replace reg_type_size[] with a function.

On Sun, Nov 27, 2016 at 1:26 AM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Tuesday, November 22, 2016 11:59:48 AM PST Matt Turner wrote: >> A function is necessary to handle immediate types. >> --- >> src/mesa/drivers/dri/i965/brw_disasm.c | 35 --

Re: [Mesa-dev] [PATCH 00/50] GL_ARB_gpu_shader_int64... this time for sure!

ect have changed in a non-trivial way since last being sent to he list. Several patches that have not changed need review: Patches 23 through 33 add lowering passes for 64-bit operations. I sent a few comments, and I cannot claim to have verified the division routine, but the rest are Reviewed

Re: [Mesa-dev] [PATCH 27/50] glsl: Add "built-in" function for 64-bit integer sign()

On 11/28, Ian Romanick wrote: From: Ian Romanick These functions are directly available in shaders. A #define is added to detect the presence. This allows these functions to be tested using piglit regardless of whether the driver uses them for lowering. The GLSL

Re: [Mesa-dev] [PATCH 26/50] glsl: Add a lowering pass for 64-bit integer multiplication

On 11/28, Ian Romanick wrote: From: Ian Romanick Signed-off-by: Ian Romanick --- src/compiler/Makefile.glsl.am| 1 + src/compiler/Makefile.sources| 1 + src/compiler/glsl/ir_optimization.h | 6 +

Re: [Mesa-dev] [PATCH 25/50] glsl: Add "built-in" functions to do 64x64 => 64 multiplication

On 11/28, Ian Romanick wrote: From: Ian Romanick These functions are directly available in shaders. A #define is added to detect the presence. This allows these functions to be tested using piglit regardless of whether the driver uses them for lowering. The GLSL

Re: [Mesa-dev] [PATCH 23/50] glsl/standalone: Enable ARB_gpu_shader_int64

print_without_indent("r%04X_data.i64[%u] = %" PRId64 ";\n", +my_index, +i, + ir->value.i64[i]); Missing break. With that fixed, Re

[Mesa-dev] [PATCH 2/4] i965/fs: Add unit tests for copy propagation pass.

Pretty basic, but it's a start. --- src/mesa/drivers/dri/i965/Makefile.am | 7 + .../drivers/dri/i965/test_fs_copy_propagation.cpp | 204 + 2 files changed, 211 insertions(+) create mode 100644 src/mesa/drivers/dri/i965/test_fs_copy_propagation.cpp diff --git

[Mesa-dev] [PATCH 3/4] i965/fs: Reject copy propagation into SEL if not min/max.

We shouldn't ever see a SEL with conditional mod other than GE (for max) or L (for min), but we might see one with predication and no conditional mod. total instructions in shared programs: 8241806 -> 8241902 (0.00%) instructions in affected programs: 13284 -> 13380 (0.72%) HURT: 62 total cycles

[Mesa-dev] [PATCH 1/4] i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.

Matches the vec4 backend, cmod propagation, and saturate propagation. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +- src/mesa/drivers/dri/i965/brw_fs.h| 6 +++--- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 15 --- 3 files

[Mesa-dev] [PATCH 4/4] nir: Move fsat outside of fmin/fmax if second arg is 0 to 1.

instructions in affected programs: 550 -> 544 (-1.09%) helped: 6 cycles in affected programs: 6952 -> 6850 (-1.47%) helped: 6 --- src/compiler/nir/nir_opt_algebraic.py | 2 ++ src/compiler/nir/nir_search_helpers.h | 23 +++ 2 files changed, 25 insertions(+) diff --git

[Mesa-dev] [PATCH 2/4] i965/cfg: Initialize bblock_t::cycle_count.

schedule_instructions(bblock_t *) isn't called on blocks with a single instruction, and since it is the only thing that set cycle_count, cycle_count would be uninitialized. A non-empty block with bblock_t::cycle_count == 0 is arguably a bug. That'll be fixed in the next commit. ---

[Mesa-dev] [PATCH 3/4] i965/sched: Make 'time' a local variable.

--- src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 28d1e90..9d7ba3b 100644 ---

[Mesa-dev] [PATCH 4/4] i965/sched: Schedule trivial blocks.

In commit 45cd76e342d1e8e schedule_instructions(bblock_t *) began setting bblock_t::cycle_count, but that function was not called on trivial blocks. Remove the code to skip trivial blocks so that cycle_count is set. --- src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 3 --- 1 file

[Mesa-dev] [PATCH 1/4] i965/cfg: Initialize cfg_t::cycle_count.

This reverts commit b4001af1744a02f472bd1204458662088307981b. --- src/mesa/drivers/dri/i965/brw_cfg.cpp | 1 + src/mesa/drivers/dri/i965/brw_cfg.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp b/src/mesa/drivers/dri/i965/brw_cfg.cpp

Re: [Mesa-dev] [PATCH] i965: Fix a mistake from porting the URB allocation code to arrays.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill

On 11/11, Juan A. Suarez Romero wrote: Do not evaluate spill costs for registers that were already marked as no_spill. --- Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list me

Re: [Mesa-dev] [PATCH] i965: Use 3DSTATE_CLIP's User Clip Distance Enable bitmask on Gen8+.

Cherryview. Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> --- Neat! Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https:/

Re: [Mesa-dev] [PATCH 3/3] glsl/cache/tests: Cast cache_get result to avoid compiler warning

On 11/22, Aaron Watry wrote: disk_cache_get returns void*, but we were storing/comparing a char*. Signed-off-by: Aaron Watry --- Note that this did, and still, segfaults for me when I actually run it... Strange. It passes for me. But at least the compiler is no longer

Re: [Mesa-dev] [PATCH 1/3] compiler/glsl/tests: Fix print format when building 32-bit on 64-bit host

Patches 1 and 2 are Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 17/18] i965: Validate "Region Alignment Rules"

--- src/mesa/drivers/dri/i965/brw_eu_validate.c| 410 - src/mesa/drivers/dri/i965/test_eu_validate.cpp | 288 + 2 files changed, 697 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c

[Mesa-dev] [PATCH 16/18] i965: Validate "General Restrictions Based on Operand Types"

--- src/mesa/drivers/dri/i965/brw_eu_validate.c| 215 + src/mesa/drivers/dri/i965/test_eu_validate.cpp | 58 +++ 2 files changed, 273 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index

[Mesa-dev] [PATCH 13/18] i965: Validate math instruction sources.

--- src/mesa/drivers/dri/i965/brw_eu_emit.c| 9 - src/mesa/drivers/dri/i965/test_eu_validate.cpp | 23 +++ 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index

[Mesa-dev] [PATCH 07/18] i965: Add a test for the EU assembly validator.

--- src/mesa/drivers/dri/i965/Makefile.am | 7 + src/mesa/drivers/dri/i965/test_eu_validate.cpp | 169 + 2 files changed, 176 insertions(+) create mode 100644 src/mesa/drivers/dri/i965/test_eu_validate.cpp diff --git a/src/mesa/drivers/dri/i965/Makefile.am

[Mesa-dev] [PATCH 11/18] i965: Factor out send_restrictions() function.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 34 +++-- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index d03ed71..8c2eb99 100644 ---

[Mesa-dev] [PATCH 15/18] i965: Validate "General Restrictions on Regioning Parameters"

--- src/mesa/drivers/dri/i965/brw_eu_validate.c| 139 src/mesa/drivers/dri/i965/test_eu_validate.cpp | 220 + 2 files changed, 359 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c

[Mesa-dev] [PATCH 14/18] i965: Replace reg_type_size[] with a function.

A function is necessary to handle immediate types. --- src/mesa/drivers/dri/i965/brw_disasm.c | 35 src/mesa/drivers/dri/i965/brw_eu_emit.c | 58 +++-- src/mesa/drivers/dri/i965/brw_reg.h | 8 + 3 files changed, 77 insertions(+), 24

[Mesa-dev] [PATCH 18/18] i965: Validate "Special Cases for Byte Operations"

Do this in general_restrictions_based_on_operand_types() because the two rules that "Special Cases for Byte Operations" relax are checked there. --- src/mesa/drivers/dri/i965/brw_eu_validate.c| 70 +--- src/mesa/drivers/dri/i965/test_eu_validate.cpp | 89

[Mesa-dev] [PATCH 12/18] i965: Claim that SEND/math has two sources.

src1 must be a descriptor (including the information to determine that the SEND is doing an extended math operation), but src0 can actually be null since it serves as the source of the implicit GRF -> MRF move. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 9 - 1 file changed, 8

[Mesa-dev] [PATCH 05/18] i965: Make ERROR_IF usable from other functions.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index fa1d67c..e23f1ec 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c +++

[Mesa-dev] [PATCH 03/18] i965/vec4: Use UW-typed operands when dest is UW.

Using a UD-typed operand makes the execution size D, and if the size of the execution type is greater than the size of the destination type, the destination must be appropriately strided. We actually just want UW-types all around. --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 10

[Mesa-dev] [PATCH 09/18] i965: Simplify num_sources_from_inst().

desc will always be non-NULL, because brw_validate_instructions() does not attempt to validate any instructions that fail the is_unsupported_inst() check. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 10/18] i965: Factor out sources_not_null() validation function.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 40 + 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index efb1f1c..d03ed71 100644 ---

[Mesa-dev] [PATCH 08/18] i965: Structure code so unsupported inst will not generate more errors.

We want to rely on brw_opcode_desc() always returning non-NULL in other validation functions. Other validation functions will be in the else case of the block added in this patch. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff

[Mesa-dev] [PATCH 04/18] i965: Mark error annotation on correct SIMD16 inst.

inst, whose assignment can be seen in the last line of context pointed to the correct instruction in the SIMD16 program, but src_offset was the offset from the beginning of the SIMD16 program. So if an instruction at offset 0x100 in the SIMD16 program was illegal, we would mark an error on the

[Mesa-dev] [PATCH 00/18] i965: More shader validation

This series adds the core "Register Region Restrictions" to the shader validator. I've added a make check test to verify that the validation checks are correct. There is still quite a bit more to do, but the next section in the PRM is "Special Requirements for Handling Double Precision Data

[Mesa-dev] [PATCH 06/18] i965: Add a CHECK macro to call more complicated validation funcs.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index e23f1ec..3225386 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c +++

[Mesa-dev] [PATCH 02/18] i965: Use W-typed immediate in brw_F32TO16().

--- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index cfb3fa0..3146271 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++

Re: [Mesa-dev] [PATCH 4/3] i965/hiz: Add debug dump for depth/hiz buffers around hiz ops

Acked-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] intel/common: Add an is_kabylake field to gen_device_info

On Tue, Nov 8, 2016 at 1:21 PM, Jason Ekstrand wrote: > Most of the 3-D engine Kaby Lake is identical to Sky Lake. However, there > are a few small differences that we need to be able to detect. > > Signed-off-by: Jason Ekstrand I noticed this patch

Re: [Mesa-dev] [PATCH 07/12] docs/submittingpatches: flesh out "how to nominate" methods

On 11/16, Emil Velikov wrote: From: Emil Velikov Currently things are a bit buried within the text, making it harder to find out. Move at the top and be clear what is _not_ a good idea. We had some people consistently using the "bad" way and then being unhappy that

Re: [Mesa-dev] [PATCH mesa] egl: fix helper function name

On Tue, Nov 15, 2016 at 3:43 PM, Eric Engestrom wrote: > Signed-off-by: Eric Engestrom > --- > src/egl/main/eglapi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c > index

Re: [Mesa-dev] Fwd: New Defects reported by Coverity Scan for Mesa

On Tue, Nov 15, 2016 at 5:35 PM, Jordan Justen <jordan.l.jus...@intel.com> wrote: > On 2016-11-15 16:21:27, Matt Turner wrote: >> Jordan, >> >> In >> >> commit 0041169cacb300a882b4dc38cd341f98bf2a7c38 >> Author: Jordan Justen <jordan.l.jus...@inte

[Mesa-dev] Fwd: New Defects reported by Coverity Scan for Mesa

Jordan, In commit 0041169cacb300a882b4dc38cd341f98bf2a7c38 Author: Jordan Justen Date: Fri Oct 21 12:56:49 2016 +0100 i965: Wrap MCS miptree in intel_miptree_aux_buffer you changed intel_miptree_alloc_mcs() to return mt->mcs_buf != NULL. mt->mcs_buf is

[Mesa-dev] Stable release process

A long time ago, patch authors were tasked with cherry-picking their patches to stable branches. Today we Cc mesa-sta...@lists.freedesktop.org and Emil rebases those patches onto stable. Cc'ing the list happens even on patches sent for their first review that are ultimately rejected, creating a

Re: [Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 0/2][RFC] Rework how glsl runs optimization passes

On Sat, Nov 12, 2016 at 5:29 PM, Thomas Helland wrote: > After looking into how optimization passes are run, it became apparent > that most glsl optimization passes only show benefit of one run. > My idea was that some optimization passes will snowball on each other, >

Re: [Mesa-dev] [Mesa-announce] Mesa 12.0.4 release candidate

On Tue, Nov 8, 2016 at 1:59 PM, Emil Velikov wrote: > Jordan Justen (1) > 49c24d8 i965: fix noop_scissor range issue on width/height > Note: temporary on hold since it causes GPU lockups on 32bit builds. Let's just drop this one. I found it in an old branch and

Re: [Mesa-dev] [PATCH 1/2] intel/common: Add an is_kabylake field to gen_device_info

sn't seem particularly necessary for a single field. I'd prefer to just put .is_kabylake in the KBL structs, unless you've got further plans. With that fixed, both patches are Reviewed-by: Matt Turner <matts...@gmail.com> Neat find. :) ___ mesa

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