[Mesa-dev] [Bug 91711] mesa-9.1.3: undefined reference to `wglGetProcAddress@4'

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=91711

Timothy Arceri  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |NOTABUG

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[Mesa-dev] [Bug 58716] Crash in _mesa_unpack_rgba_row() during glDrawArrays() call

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=58716

Timothy Arceri  changed:

   What|Removed |Added

 Resolution|--- |INVALID
 Status|NEW |RESOLVED

--- Comment #5 from Timothy Arceri  ---
The Windows GDI has been removed from Mesa. Closing.

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[Mesa-dev] [Bug 26820] Sharing contexts crashes on Windows

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=26820

Timothy Arceri  changed:

   What|Removed |Added

 Resolution|--- |INVALID
 Status|NEW |RESOLVED

--- Comment #5 from Timothy Arceri  ---
The Windows GDI has been removed from Mesa. Closing.

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[Mesa-dev] [Bug 94088] [llvmpipe] SIGFPE pthread_barrier_destroy.c:40

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=94088

Steve Langasek  changed:

   What|Removed |Added

 CC||steve.langa...@canonical.co
   ||m

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[Mesa-dev] [Bug 94088] [llvmpipe] SIGFPE pthread_barrier_destroy.c:40

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=94088

Steve Langasek  changed:

   What|Removed |Added

 Resolution|FIXED   |---
 Status|RESOLVED|REOPENED

--- Comment #2 from Steve Langasek  ---
Hello,

The patch for this bug is incomplete.  In between the calls to
pipe_barrier_init() and pipe_barrier_destroy() are calls to
pipe_barrier_wait(), which is implemented on top of pthread_barrier_wait().

Since pipe_barrier_init() has not been called, the calls to
pthread_barrier_wait() have undefined behavior, as per
,
.

The applied commit is sufficient to fix the immediate SIGFPE problem with
glibc, but the API is still being used incorrectly and could result in future
crashes on other implementations.

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[Mesa-dev] [Bug 94512] X segfaults with glx-tls enabled in a x32 environment

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=94512

Michel Dänzer  changed:

   What|Removed |Added

 QA Contact|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
   |.org|org
   Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
   |.org|org
  Component|Drivers/Gallium/radeonsi|GLX

--- Comment #4 from Michel Dänzer  ---
Sounds like it's not a driver specific issue then but a general one with
GLX-TLS on x32.

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Re: [Mesa-dev] [PATCH 00/11] radeonsi: shader buffer support (atomic counters, ssbo)

2016-03-21 Thread eocallaghan 

Hi Nicolai,

Thanks for taking over this work and going the whole nine yards with it!

This series is, Reviewed-by: Edward O'Callaghan 



Thanks again,
Edward.

On 2016-03-22 10:21, Nicolai Hähnle wrote:

Hi,

since shader images have laid most of the foundation, here are shader 
buffers
now. This is the last extension missing for OpenGL 4.2 (we still need 
to turn

on GLSL 4.2, but I think that only involves flipping a bit).

As with shader images, this extension needs bleeding edge LLVM - this 
time,
important patches have not landed upstream yet, and if you want to try 
this

code you'll need my LLVM branch at
https://cgit.freedesktop.org/~nh/llvm/log/?h=images

(For those following along at home, the necessary LLVM patches for 
shader

images have already landed upstream.)

In principle, there are two alternative implementations for shader 
buffers:
using LLVM IR  pointers with LLVM-native load/store instructions 
directly, or
using intrinsics that operate on GCN buffer descriptors. This 
implementation
uses the second approach. A brief comparison between the two 
approaches:


1. The pointer approach would use FLAT memory instructions on CI+, 
which
   operate on 64 bit pointers rather than 128 bit buffer descriptors. 
This

   would reduce SGPR memory pressure slightly.

2. LLVM understands pointers for alias analysis, so it's possible that 
it
   would generate somewhat better code if we were to use pointers in 
the

   IR.

3. The buffer load/store intructions have built-in bounds checks. 
Bounds
   checks are required for an honest implementation of the 
ARB_robustness

   extension, which we claim to support.

The last point makes it obvious that the implementation really needs to 
use
buffer intrinsics, but it'd be interesting to know how big the 
difference
in code quality is versus something that uses pointers. To get the best 
of

both worlds, we should really find a way to teach LLVM's alias analysis
about what those buffer descriptors mean. For now, this current 
approach is

the right way to do it.

Please review!

Thanks,
Nicolai

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Bug 79706 depends on bug 72326, which changed state.

Bug 72326 Summary: [swrast] piglit glean pbo regression
https://bugs.freedesktop.org/show_bug.cgi?id=72326

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |INVALID

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[Mesa-dev] [Bug 72326] [swrast] piglit glean pbo regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=72326

Vinson Lee  changed:

   What|Removed |Added

 Resolution|--- |INVALID
 Status|NEW |RESOLVED

--- Comment #3 from Vinson Lee  ---
glean pbo is now longer a valid piglit test.

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[Mesa-dev] [Bug 79039] [TRACKER] Mesa 10.2 release tracker

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=79039
Bug 79039 depends on bug 72326, which changed state.

Bug 72326 Summary: [swrast] piglit glean pbo regression
https://bugs.freedesktop.org/show_bug.cgi?id=72326

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |INVALID

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[Mesa-dev] [Bug 78318] [swrast] piglit glsl-kwin-blur-1 regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=78318

--- Comment #6 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

piglit glsl-kwin-blur-1 regression is still present.

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Re: [Mesa-dev] [PATCH] mesa: replace gl_context->Multisample._Enabled with _mesa_is_multisample_enabled.

2016-03-21 Thread eocallaghan 

Too quick, very nice cleanup, thanks.

Reviewed-by: Edward O'Callaghan 

On 2016-03-22 12:58, Bas Nieuwenhuizen wrote:

This removes any dependency on driver validation of the number of
framebuffer samples.

Signed-off-by: Bas Nieuwenhuizen 
---
 src/mesa/drivers/dri/i965/brw_util.h   |  5 +++--
 src/mesa/drivers/dri/i965/gen6_cc.c|  6 +++---
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |  2 +-
 src/mesa/drivers/dri/i965/gen8_blend_state.c   |  6 +++---
 src/mesa/drivers/dri/i965/gen8_depth_state.c   |  3 ++-
 src/mesa/drivers/dri/i965/gen8_sf_state.c  |  4 ++--
 src/mesa/main/framebuffer.c| 19 
+++

 src/mesa/main/framebuffer.h|  3 +++
 src/mesa/main/mtypes.h |  1 -
 src/mesa/main/state.c  | 17 
-

 src/mesa/program/prog_statevars.c  |  2 +-
 src/mesa/state_tracker/st_atom_rasterizer.c|  4 ++--
 src/mesa/state_tracker/st_atom_shader.c|  2 +-
 src/mesa/swrast/s_points.c |  4 ++--
 14 files changed, 42 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_util.h
b/src/mesa/drivers/dri/i965/brw_util.h
index 1f27e98..3e9a6ee 100644
--- a/src/mesa/drivers/dri/i965/brw_util.h
+++ b/src/mesa/drivers/dri/i965/brw_util.h
@@ -34,6 +34,7 @@
 #define BRW_UTIL_H

 #include "brw_context.h"
+#include "main/framebuffer.h"

 extern GLuint brw_translate_blend_factor( GLenum factor );
 extern GLuint brw_translate_blend_equation( GLenum mode );
@@ -49,13 +50,13 @@ brw_get_line_width(struct brw_context *brw)
 * implementation-dependent maximum non-antialiased line width."
 */
float line_width =
-  CLAMP(!brw->ctx.Multisample._Enabled && 
!brw->ctx.Line.SmoothFlag

+  CLAMP(!_mesa_is_multisample_enabled(>ctx) &&
!brw->ctx.Line.SmoothFlag
 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
 0.0f, brw->ctx.Const.MaxLineWidth);
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);

/* Line width of 0 is not allowed when MSAA enabled */
-   if (brw->ctx.Multisample._Enabled) {
+   if (_mesa_is_multisample_enabled(>ctx)) {
   if (line_width_u3_7 == 0)
  line_width_u3_7 = 1;
} else if (brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c
b/src/mesa/drivers/dri/i965/gen6_cc.c
index cee139b..f5a7d4d 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -198,14 +198,14 @@ gen6_upload_blend_state(struct brw_context *brw)
   if(!is_buffer_zero_integer_format) {
  /* _NEW_MULTISAMPLE */
  blend[b].blend1.alpha_to_coverage =
-ctx->Multisample._Enabled &&
ctx->Multisample.SampleAlphaToCoverage;
+_mesa_is_multisample_enabled(ctx) &&
ctx->Multisample.SampleAlphaToCoverage;

/* From SandyBridge PRM, volume 2 Part 1, section 8.2.3, BLEND_STATE:
 * DWord 1, Bit 30 (AlphaToOne Enable):
 * "If Dual Source Blending is enabled, this bit must be disabled"
 */
  WARN_ONCE(ctx->Color.Blend[b]._UsesDualSrc &&
-   ctx->Multisample._Enabled &&
+   _mesa_is_multisample_enabled(ctx) &&
ctx->Multisample.SampleAlphaToOne,
"HW workaround: disabling alpha to one with dual 
src "

"blending\n");
@@ -213,7 +213,7 @@ gen6_upload_blend_state(struct brw_context *brw)
 blend[b].blend1.alpha_to_one = false;
 else
blend[b].blend1.alpha_to_one =
-	   ctx->Multisample._Enabled && 
ctx->Multisample.SampleAlphaToOne;
+	   _mesa_is_multisample_enabled(ctx) && 
ctx->Multisample.SampleAlphaToOne;


  blend[b].blend1.alpha_to_coverage_dither = (brw->gen >= 7);
   }
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index 8eb620d..fcd313a 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -171,7 +171,7 @@ gen6_determine_sample_mask(struct brw_context *brw)
/* BRW_NEW_NUM_SAMPLES */
unsigned num_samples = brw->num_samples;

-   if (ctx->Multisample._Enabled) {
+   if (_mesa_is_multisample_enabled(ctx)) {
   if (ctx->Multisample.SampleCoverage) {
  coverage = ctx->Multisample.SampleCoverageValue;
  coverage_invert = ctx->Multisample.SampleCoverageInvert;
diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c
b/src/mesa/drivers/dri/i965/gen8_blend_state.c
index 786c79a..63186bd 100644
--- a/src/mesa/drivers/dri/i965/gen8_blend_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_blend_state.c
@@ -65,7 +65,7 @@ gen8_upload_blend_state(struct brw_context *brw)

if (rb_zero_type != GL_INT && rb_zero_type != GL_UNSIGNED_INT) {

Re: [Mesa-dev] [PATCH] tgsi: drop unused set_exec/kill_mask interfaces.

2016-03-21 Thread Brian Paul 

On 03/21/2016 06:29 PM, Dave Airlie wrote:

From: Dave Airlie 

These don't get used and haven't been in git history from what I can
see, so drop them.


Well, tgsi_set_exec_mask() was used, but had no effect.




Signed-off-by: Dave Airlie 
---
  src/gallium/auxiliary/draw/draw_gs.c  |  6 --
  src/gallium/auxiliary/draw/draw_vs_exec.c |  6 --
  src/gallium/auxiliary/tgsi/tgsi_exec.h| 25 -
  3 files changed, 37 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_gs.c 
b/src/gallium/auxiliary/draw/draw_gs.c
index 6b33341..fcef31b 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -206,12 +206,6 @@ static unsigned tgsi_gs_run(struct draw_geometry_shader 
*shader,
  {
 struct tgsi_exec_machine *machine = shader->machine;

-   tgsi_set_exec_mask(machine,
-  1,
-  input_primitives > 1,
-  input_primitives > 2,
-  input_primitives > 3);
-
 /* run interpreter */
 tgsi_exec_machine_run(machine);

diff --git a/src/gallium/auxiliary/draw/draw_vs_exec.c 
b/src/gallium/auxiliary/draw/draw_vs_exec.c
index abd64f5..3fd8ef3 100644
--- a/src/gallium/auxiliary/draw/draw_vs_exec.c
+++ b/src/gallium/auxiliary/draw/draw_vs_exec.c
@@ -159,12 +159,6 @@ vs_exec_run_linear( struct draw_vertex_shader *shader,
   input = (const float (*)[4])((const char *)input + input_stride);
}

-  tgsi_set_exec_mask(machine,
- 1,
- max_vertices > 1,
- max_vertices > 2,
- max_vertices > 3);
-
/* run interpreter */
tgsi_exec_machine_run( machine );

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 12a6875..991c3bf 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -196,10 +196,6 @@ struct tgsi_sampler
  #define TGSI_EXEC_TEMP_HALF_I   (TGSI_EXEC_NUM_TEMPS + 3)
  #define TGSI_EXEC_TEMP_HALF_C   0

-/* execution mask, each value is either 0 or ~0 */
-#define TGSI_EXEC_MASK_I(TGSI_EXEC_NUM_TEMPS + 3)
-#define TGSI_EXEC_MASK_C1
-
  /* 4 register buffer for various purposes */
  #define TGSI_EXEC_TEMP_R0   (TGSI_EXEC_NUM_TEMPS + 4)
  #define TGSI_EXEC_NUM_TEMP_R4
@@ -397,27 +393,6 @@ boolean
  tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst);


-static inline void
-tgsi_set_kill_mask(struct tgsi_exec_machine *mach, unsigned mask)
-{
-   mach->Temps[TGSI_EXEC_TEMP_KILMASK_I].xyzw[TGSI_EXEC_TEMP_KILMASK_C].u[0] =
-  mask;
-}
-
-
-/** Set execution mask values prior to executing the shader */
-static inline void
-tgsi_set_exec_mask(struct tgsi_exec_machine *mach,
-   boolean ch0, boolean ch1, boolean ch2, boolean ch3)
-{
-   int *mask = mach->Temps[TGSI_EXEC_MASK_I].xyzw[TGSI_EXEC_MASK_C].i;
-   mask[0] = ch0 ? ~0 : 0;
-   mask[1] = ch1 ? ~0 : 0;
-   mask[2] = ch2 ? ~0 : 0;
-   mask[3] = ch3 ? ~0 : 0;
-}
-
-
  extern void
  tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
 unsigned num_bufs,



Reviewed-by: Brian Paul 

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[Mesa-dev] [Bug 77288] [swrast] piglit glean glsl1 regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=77288

--- Comment #7 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

piglit glean glsl1 regression on swrast is still present.

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[Mesa-dev] [Bug 59777] [softpipe] piglit interpolation-noperspective-gl_BackColor-flat-distance regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=59777

Vinson Lee  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #3 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This test is now passing on softpipe.

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Bug 79706 depends on bug 59777, which changed state.

Bug 59777 Summary: [softpipe] piglit 
interpolation-noperspective-gl_BackColor-flat-distance regression
https://bugs.freedesktop.org/show_bug.cgi?id=59777

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Bug 79706 depends on bug 61153, which changed state.

Bug 61153 Summary: [softpipe] piglit 
interpolation-noperspective-gl_BackColor-flat-vertex regression
https://bugs.freedesktop.org/show_bug.cgi?id=61153

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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[Mesa-dev] [Bug 61153] [softpipe] piglit interpolation-noperspective-gl_BackColor-flat-vertex regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=61153

Vinson Lee  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This test is now passing on softpipe.

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Bug 79706 depends on bug 61326, which changed state.

Bug 61326 Summary: [softpipe] piglit 
interpolation-noperspective-gl_BackSecondaryColor-flat-vertex regression
https://bugs.freedesktop.org/show_bug.cgi?id=61326

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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[Mesa-dev] [Bug 61326] [softpipe] piglit interpolation-noperspective-gl_BackSecondaryColor-flat-vertex regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=61326

Vinson Lee  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This tests now passes on softpipe.

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[Mesa-dev] [Bug 91100] [softpipe] piglit egl-create-pbuffer-surface regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=91100

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This regression is still present.

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=79706
Bug 79706 depends on bug 90539, which changed state.

Bug 90539 Summary: [softpipe] piglit varying-packing-simple dmat3 array 
regression
https://bugs.freedesktop.org/show_bug.cgi?id=90539

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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[Mesa-dev] [Bug 90539] [softpipe] piglit varying-packing-simple dmat3 array regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=90539

Vinson Lee  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

varying-packing-simple dmat3 array is passes on softpipe now.

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[Mesa-dev] [Bug 92552] [softpipe] piglit egl-create-context-valid-flag-forward-compatible-gl regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=92552

--- Comment #11 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This regression is still present.

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[Mesa-dev] [Bug 92946] [softpipe] piglit fcc-front-buffer-distraction regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=92946

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This regression is still present.

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[Mesa-dev] [Bug 92954] [softpipe] piglit drawbuffer-modes regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=92954

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

This regression is still present.

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[Mesa-dev] [Bug 93203] [softpipe] piglit gl30basic regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=93203

--- Comment #1 from Vinson Lee  ---
mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (11.3.0-devel)

This regression is still present.

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[Mesa-dev] [Bug 94657] [llvmpipe] [softpipe] piglit arb_texture_view-getteximage-srgb regression

2016-03-21 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=94657

Bug ID: 94657
   Summary: [llvmpipe] [softpipe] piglit
arb_texture_view-getteximage-srgb regression
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: bisected, regression
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org
CC: mar...@gmail.com, nhaeh...@gmail.com

mesa: 1e8435ce0cce671024ebf9c5465ea8bdcb563b69 (master 11.3.0-devel)

$ ./bin/arb_texture_view-getteximage-srgb -auto
Wrong color for GL_SRGB8_ALPHA8 texture view.
Expected 0xffff but found 0x 
PIGLIT: {"result": "fail" }

a8eea696b8966d119e213d532158f63c5b280740 is the first bad commit
commit a8eea696b8966d119e213d532158f63c5b280740
Author: Nicolai Hähnle 
Date:   Mon Mar 14 15:33:34 2016 -0500

st/mesa: honour sized internal formats in st_choose_format (v2)

The bitcasting which is possible with shader images (and texture views?)
requires that when the user specifies a sized internal format for a
texture, we really allocate that format. To this end:

(1) find_exact_format should ignore sized internal formats and

(2) some of the entries in the mapping table corresponding to sized
internal formats are reordered to use an RGBA format instead of
a BGRA one.

This fixes arb_shader_image_load_store-bitcast in the (work in progress)
ARB_shader_image_load_store implementation for radeonsi.

v2: don't change the mapping of GL_RGB10: the change caused a regression
because it preferred a format with an alpha channel, and GL_RGB10
is not among the supported formats for shader images

Reviewed-by: Marek Olšák 

:04 04 572b09e6a4cec5c7267d43ecfe6e497775faf753
77f5d9b5f75285074cc89652de547f5129ea1b99 Msrc
bisect run success

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[Mesa-dev] [PATCH] mesa: replace gl_context->Multisample._Enabled with _mesa_is_multisample_enabled.

2016-03-21 Thread Bas Nieuwenhuizen 
This removes any dependency on driver validation of the number of
framebuffer samples.

Signed-off-by: Bas Nieuwenhuizen 
---
 src/mesa/drivers/dri/i965/brw_util.h   |  5 +++--
 src/mesa/drivers/dri/i965/gen6_cc.c|  6 +++---
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |  2 +-
 src/mesa/drivers/dri/i965/gen8_blend_state.c   |  6 +++---
 src/mesa/drivers/dri/i965/gen8_depth_state.c   |  3 ++-
 src/mesa/drivers/dri/i965/gen8_sf_state.c  |  4 ++--
 src/mesa/main/framebuffer.c| 19 +++
 src/mesa/main/framebuffer.h|  3 +++
 src/mesa/main/mtypes.h |  1 -
 src/mesa/main/state.c  | 17 -
 src/mesa/program/prog_statevars.c  |  2 +-
 src/mesa/state_tracker/st_atom_rasterizer.c|  4 ++--
 src/mesa/state_tracker/st_atom_shader.c|  2 +-
 src/mesa/swrast/s_points.c |  4 ++--
 14 files changed, 42 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_util.h 
b/src/mesa/drivers/dri/i965/brw_util.h
index 1f27e98..3e9a6ee 100644
--- a/src/mesa/drivers/dri/i965/brw_util.h
+++ b/src/mesa/drivers/dri/i965/brw_util.h
@@ -34,6 +34,7 @@
 #define BRW_UTIL_H
 
 #include "brw_context.h"
+#include "main/framebuffer.h"
 
 extern GLuint brw_translate_blend_factor( GLenum factor );
 extern GLuint brw_translate_blend_equation( GLenum mode );
@@ -49,13 +50,13 @@ brw_get_line_width(struct brw_context *brw)
 * implementation-dependent maximum non-antialiased line width."
 */
float line_width =
-  CLAMP(!brw->ctx.Multisample._Enabled && !brw->ctx.Line.SmoothFlag
+  CLAMP(!_mesa_is_multisample_enabled(>ctx) && 
!brw->ctx.Line.SmoothFlag
 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
 0.0f, brw->ctx.Const.MaxLineWidth);
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
 
/* Line width of 0 is not allowed when MSAA enabled */
-   if (brw->ctx.Multisample._Enabled) {
+   if (_mesa_is_multisample_enabled(>ctx)) {
   if (line_width_u3_7 == 0)
  line_width_u3_7 = 1;
} else if (brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
index cee139b..f5a7d4d 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -198,14 +198,14 @@ gen6_upload_blend_state(struct brw_context *brw)
   if(!is_buffer_zero_integer_format) {
  /* _NEW_MULTISAMPLE */
  blend[b].blend1.alpha_to_coverage =
-ctx->Multisample._Enabled && 
ctx->Multisample.SampleAlphaToCoverage;
+_mesa_is_multisample_enabled(ctx) && 
ctx->Multisample.SampleAlphaToCoverage;
 
/* From SandyBridge PRM, volume 2 Part 1, section 8.2.3, BLEND_STATE:
 * DWord 1, Bit 30 (AlphaToOne Enable):
 * "If Dual Source Blending is enabled, this bit must be disabled"
 */
  WARN_ONCE(ctx->Color.Blend[b]._UsesDualSrc &&
-   ctx->Multisample._Enabled &&
+   _mesa_is_multisample_enabled(ctx) &&
ctx->Multisample.SampleAlphaToOne,
"HW workaround: disabling alpha to one with dual src "
"blending\n");
@@ -213,7 +213,7 @@ gen6_upload_blend_state(struct brw_context *brw)
 blend[b].blend1.alpha_to_one = false;
 else
blend[b].blend1.alpha_to_one =
-  ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne;
+  _mesa_is_multisample_enabled(ctx) && 
ctx->Multisample.SampleAlphaToOne;
 
  blend[b].blend1.alpha_to_coverage_dither = (brw->gen >= 7);
   }
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index 8eb620d..fcd313a 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -171,7 +171,7 @@ gen6_determine_sample_mask(struct brw_context *brw)
/* BRW_NEW_NUM_SAMPLES */
unsigned num_samples = brw->num_samples;
 
-   if (ctx->Multisample._Enabled) {
+   if (_mesa_is_multisample_enabled(ctx)) {
   if (ctx->Multisample.SampleCoverage) {
  coverage = ctx->Multisample.SampleCoverageValue;
  coverage_invert = ctx->Multisample.SampleCoverageInvert;
diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c 
b/src/mesa/drivers/dri/i965/gen8_blend_state.c
index 786c79a..63186bd 100644
--- a/src/mesa/drivers/dri/i965/gen8_blend_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_blend_state.c
@@ -65,7 +65,7 @@ gen8_upload_blend_state(struct brw_context *brw)
 
if (rb_zero_type != GL_INT && rb_zero_type != GL_UNSIGNED_INT) {
   /* _NEW_MULTISAMPLE */
-  if (ctx->Multisample._Enabled) {
+  if (_mesa_is_multisample_enabled(ctx)) {
  if

Re: [Mesa-dev] [PATCH 09/21] nir: Add a phi node placement helper

2016-03-21 Thread Connor Abbott 
On Mon, Mar 21, 2016 at 7:37 PM, Jason Ekstrand  wrote:
>
>
> On Mon, Mar 21, 2016 at 4:21 PM, Connor Abbott  wrote:
>>
>> On Mon, Mar 21, 2016 at 6:51 PM, Connor Abbott 
>> wrote:
>> > So overall, I think that there needs to be some explanation of the
>> > design choices in the implementation. The API documentation is great,
>> > but digging into the implementation might be a little daunting without
>> > knowing e.g. why NEEDS_PHI is a thing. From what I gather, there are
>> > three potential states a phi node can be in, once it's determined by
>> > the usual dominance-frontier algorithm that it needs to be there:
>> >
>> > 1. There's just a NEEDS_PHI entry. IMHO this is a little bit of a
>> > misnomer. This means something like "we might need to insert a phi, if
>> > something uses it."
>> > 2. The phi has been constructed and added to the list of phis
>> > associated with this value, but it hasn't been inserted into the block
>> > yet. This means something like "we know that this phi is actually
>> > needed, but we haven't materialized its sources yet."
>> > 3. The phi has actually been inserted into the block.
>
>
> Right.  How about something like this:
>
> Phi building happens in three stages:
>
> 1) Create a phi_builder_value:  When the value is created, the user provides
> a bitset that tells the phi builder what blocks have definitions for that
> value.  The builder then uses dominance information to determine which
> blocks need to have phi nodes.
>
> 2) Add and retrieve definitions:  This stage provides the builder with all
> of the information that it needs for figuring out which definitions go where
> and phi builder tells the user what definitions it should use.  This must be
> done in an order that respects dominance.  When the user requests a def that
> needs a phi, a phi node is created and its definition is returned.  The phi
> nodes returned have no sources at this point because the builder does not
> yet have enough information to set the sources correctly.

How about something like "They also haven't been inserted into the
program yet. Instead, we insert them into a list which keeps track of
phis whose sources haven't been added."

>
> 3) Finalize the builder:  This is where we do most of the real work.  In
> parcitular, this is where we actually add sources to the phi nodes.  At this
> point, we finally have all of the definition information so we can setup the
> phis.

How about mentioning the fact that we might have to create more phi
nodes? Something like "In the process of setting up the phi sources,
we may realize that more phi nodes have to be created. In that case,
we add them to the list and continue until the list is empty."

>
> I can put that in comments somewhere if you'd like.

Sure. I'll leave it up to you where to put it, though.

>
>>
>> > There isn't enough explanation as to why #2 needs to be separate from
>> > #3. I think it made more sense to me once I realized that the "phis"
>> > list is actually a worklist, and nir_phi_builder_finish() is really a
>> > worklist-based algorithm for recursively filling in phi node
>> > dependencies, and when we go from #1 to #2 we're really just inserting
>> > the phi into the worklist.
>> >
>> > On Sat, Feb 13, 2016 at 9:14 PM, Jason Ekstrand 
>> > wrote:
>> >> Right now, we have phi placement code in two places and there are other
>> >> places where it would be nice to be able to do this analysis.  Instead
>> >> of
>> >> repeating it all over the place, this commit adds a helper for placing
>> >> all
>> >> of the needed phi nodes for a value.
>> >> ---
>> >>  src/compiler/Makefile.sources  |   2 +
>> >>  src/compiler/nir/Makefile.sources  |   2 +
>> >>  src/compiler/nir/nir_phi_builder.c | 254
>> >> +
>> >>  src/compiler/nir/nir_phi_builder.h |  84 
>> >>  4 files changed, 342 insertions(+)
>> >>  create mode 100644 src/compiler/nir/nir_phi_builder.c
>> >>  create mode 100644 src/compiler/nir/nir_phi_builder.h
>> >>
>> >> diff --git a/src/compiler/Makefile.sources
>> >> b/src/compiler/Makefile.sources
>> >> index c9780d6..4a1b120 100644
>> >> --- a/src/compiler/Makefile.sources
>> >> +++ b/src/compiler/Makefile.sources
>> >> @@ -213,6 +213,8 @@ NIR_FILES = \
>> >> nir/nir_opt_peephole_select.c \
>> >> nir/nir_opt_remove_phis.c \
>> >> nir/nir_opt_undef.c \
>> >> +   nir/nir_phi_builder.c \
>> >> +   nir/nir_phi_builder.h \
>> >> nir/nir_print.c \
>> >> nir/nir_remove_dead_variables.c \
>> >> nir/nir_search.c \
>> >> diff --git a/src/compiler/nir/Makefile.sources
>> >> b/src/compiler/nir/Makefile.sources
>> >> index 0755a10..7269f9f 100644
>> >> --- a/src/compiler/nir/Makefile.sources
>> >> +++ b/src/compiler/nir/Makefile.sources
>> >> @@ -57,6 +57,8 @@ NIR_FILES = \
>> >> nir_opt_peephole_select.c \
>> >>

Re: [Mesa-dev] [PATCH] tgsi: drop unused set_exec/kill_mask interfaces.

2016-03-21 Thread eocallaghan 

Reviewed-by: Edward O'Callaghan 

On 2016-03-22 11:29, Dave Airlie wrote:

From: Dave Airlie 

These don't get used and haven't been in git history from what I can
see, so drop them.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/draw/draw_gs.c  |  6 --
 src/gallium/auxiliary/draw/draw_vs_exec.c |  6 --
 src/gallium/auxiliary/tgsi/tgsi_exec.h| 25 
-

 3 files changed, 37 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_gs.c
b/src/gallium/auxiliary/draw/draw_gs.c
index 6b33341..fcef31b 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -206,12 +206,6 @@ static unsigned tgsi_gs_run(struct
draw_geometry_shader *shader,
 {
struct tgsi_exec_machine *machine = shader->machine;

-   tgsi_set_exec_mask(machine,
-  1,
-  input_primitives > 1,
-  input_primitives > 2,
-  input_primitives > 3);
-
/* run interpreter */
tgsi_exec_machine_run(machine);

diff --git a/src/gallium/auxiliary/draw/draw_vs_exec.c
b/src/gallium/auxiliary/draw/draw_vs_exec.c
index abd64f5..3fd8ef3 100644
--- a/src/gallium/auxiliary/draw/draw_vs_exec.c
+++ b/src/gallium/auxiliary/draw/draw_vs_exec.c
@@ -159,12 +159,6 @@ vs_exec_run_linear( struct draw_vertex_shader 
*shader,
  input = (const float (*)[4])((const char *)input + 
input_stride);

   }

-  tgsi_set_exec_mask(machine,
- 1,
- max_vertices > 1,
- max_vertices > 2,
- max_vertices > 3);
-
   /* run interpreter */
   tgsi_exec_machine_run( machine );

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 12a6875..991c3bf 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -196,10 +196,6 @@ struct tgsi_sampler
 #define TGSI_EXEC_TEMP_HALF_I   (TGSI_EXEC_NUM_TEMPS + 3)
 #define TGSI_EXEC_TEMP_HALF_C   0

-/* execution mask, each value is either 0 or ~0 */
-#define TGSI_EXEC_MASK_I(TGSI_EXEC_NUM_TEMPS + 3)
-#define TGSI_EXEC_MASK_C1
-
 /* 4 register buffer for various purposes */
 #define TGSI_EXEC_TEMP_R0   (TGSI_EXEC_NUM_TEMPS + 4)
 #define TGSI_EXEC_NUM_TEMP_R4
@@ -397,27 +393,6 @@ boolean
 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst);


-static inline void
-tgsi_set_kill_mask(struct tgsi_exec_machine *mach, unsigned mask)
-{
-   
mach->Temps[TGSI_EXEC_TEMP_KILMASK_I].xyzw[TGSI_EXEC_TEMP_KILMASK_C].u[0] 
=

-  mask;
-}
-
-
-/** Set execution mask values prior to executing the shader */
-static inline void
-tgsi_set_exec_mask(struct tgsi_exec_machine *mach,
-   boolean ch0, boolean ch1, boolean ch2, boolean ch3)
-{
-   int *mask = mach->Temps[TGSI_EXEC_MASK_I].xyzw[TGSI_EXEC_MASK_C].i;
-   mask[0] = ch0 ? ~0 : 0;
-   mask[1] = ch1 ? ~0 : 0;
-   mask[2] = ch2 ? ~0 : 0;
-   mask[3] = ch3 ? ~0 : 0;
-}
-
-
 extern void
 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
unsigned num_bufs,


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[Mesa-dev] [PATCH] tgsi: drop unused set_exec/kill_mask interfaces.

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

These don't get used and haven't been in git history from what I can
see, so drop them.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/draw/draw_gs.c  |  6 --
 src/gallium/auxiliary/draw/draw_vs_exec.c |  6 --
 src/gallium/auxiliary/tgsi/tgsi_exec.h| 25 -
 3 files changed, 37 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_gs.c 
b/src/gallium/auxiliary/draw/draw_gs.c
index 6b33341..fcef31b 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -206,12 +206,6 @@ static unsigned tgsi_gs_run(struct draw_geometry_shader 
*shader,
 {
struct tgsi_exec_machine *machine = shader->machine;
 
-   tgsi_set_exec_mask(machine,
-  1,
-  input_primitives > 1,
-  input_primitives > 2,
-  input_primitives > 3);
-
/* run interpreter */
tgsi_exec_machine_run(machine);
 
diff --git a/src/gallium/auxiliary/draw/draw_vs_exec.c 
b/src/gallium/auxiliary/draw/draw_vs_exec.c
index abd64f5..3fd8ef3 100644
--- a/src/gallium/auxiliary/draw/draw_vs_exec.c
+++ b/src/gallium/auxiliary/draw/draw_vs_exec.c
@@ -159,12 +159,6 @@ vs_exec_run_linear( struct draw_vertex_shader *shader,
  input = (const float (*)[4])((const char *)input + input_stride);
   } 
 
-  tgsi_set_exec_mask(machine,
- 1,
- max_vertices > 1,
- max_vertices > 2,
- max_vertices > 3);
-
   /* run interpreter */
   tgsi_exec_machine_run( machine );
 
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 12a6875..991c3bf 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -196,10 +196,6 @@ struct tgsi_sampler
 #define TGSI_EXEC_TEMP_HALF_I   (TGSI_EXEC_NUM_TEMPS + 3)
 #define TGSI_EXEC_TEMP_HALF_C   0
 
-/* execution mask, each value is either 0 or ~0 */
-#define TGSI_EXEC_MASK_I(TGSI_EXEC_NUM_TEMPS + 3)
-#define TGSI_EXEC_MASK_C1
-
 /* 4 register buffer for various purposes */
 #define TGSI_EXEC_TEMP_R0   (TGSI_EXEC_NUM_TEMPS + 4)
 #define TGSI_EXEC_NUM_TEMP_R4
@@ -397,27 +393,6 @@ boolean
 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst);
 
 
-static inline void
-tgsi_set_kill_mask(struct tgsi_exec_machine *mach, unsigned mask)
-{
-   mach->Temps[TGSI_EXEC_TEMP_KILMASK_I].xyzw[TGSI_EXEC_TEMP_KILMASK_C].u[0] =
-  mask;
-}
-
-
-/** Set execution mask values prior to executing the shader */
-static inline void
-tgsi_set_exec_mask(struct tgsi_exec_machine *mach,
-   boolean ch0, boolean ch1, boolean ch2, boolean ch3)
-{
-   int *mask = mach->Temps[TGSI_EXEC_MASK_I].xyzw[TGSI_EXEC_MASK_C].i;
-   mask[0] = ch0 ? ~0 : 0;
-   mask[1] = ch1 ? ~0 : 0;
-   mask[2] = ch2 ? ~0 : 0;
-   mask[3] = ch3 ? ~0 : 0;
-}
-
-
 extern void
 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
unsigned num_bufs,
-- 
2.5.0

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Re: [Mesa-dev] [PATCH] egl: adds EGL_KHR_reusable_sync to egl_dri

2016-03-21 Thread dw kim 
On Mon, Mar 21, 2016 at 08:35:20PM +0100, Marek Olšák wrote:
> On Wed, Mar 9, 2016 at 2:28 AM, Dongwon Kim  wrote:
> > This patch enables an EGL extension, EGL_KHR_reusable_sync.
> > This new extension basically provides a way for multiple APIs or
> > threads to be excuted synchronously via a "reusable sync"
> > primitive shared by those threads/API calls.
> >
> > This was implemented based on the specification at
> >
> > https://www.khronos.org/registry/egl/extensions/KHR/EGL_KHR_reusable_sync.txt
> >
> > Signed-off-by: Dongwon Kim 
> > ---
> >  src/egl/drivers/dri2/egl_dri2.c | 197 
> > ++--
> >  src/egl/drivers/dri2/egl_dri2.h |   2 +
> >  src/egl/main/eglapi.c   |   8 ++
> >  src/egl/main/eglsync.c  |   3 +-
> >  4 files changed, 200 insertions(+), 10 deletions(-)
> >
> > diff --git a/src/egl/drivers/dri2/egl_dri2.c 
> > b/src/egl/drivers/dri2/egl_dri2.c
> > index 8f50f0c..78164e4 100644
> > --- a/src/egl/drivers/dri2/egl_dri2.c
> > +++ b/src/egl/drivers/dri2/egl_dri2.c
> > @@ -38,6 +38,8 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  #ifdef HAVE_LIBDRM
> >  #include 
> >  #include 
> > @@ -623,6 +625,8 @@ dri2_setup_screen(_EGLDisplay *disp)
> >   disp->Extensions.KHR_cl_event2 = EGL_TRUE;
> > }
> >
> > +   disp->Extensions.KHR_reusable_sync = EGL_TRUE;
> > +
> > if (dri2_dpy->image) {
> >if (dri2_dpy->image->base.version >= 10 &&
> >dri2_dpy->image->getCapabilities != NULL) {
> > @@ -2389,14 +2393,33 @@ dri2_egl_ref_sync(struct dri2_egl_sync *sync)
> > p_atomic_inc(>refcount);
> >  }
> >
> > -static void
> > +static EGLint
> >  dri2_egl_unref_sync(struct dri2_egl_display *dri2_dpy,
> >  struct dri2_egl_sync *dri2_sync)
> >  {
> > +   EGLint ret;
> > +
> > if (p_atomic_dec_zero(_sync->refcount)) {
> > -  dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, 
> > dri2_sync->fence);
> > +  /* mutex and cond should be freed if not freed yet. */
> > +  if (dri2_sync->mutex)
> > + free(dri2_sync->mutex);
> > +
> > +  if (dri2_sync->cond) {
> > + ret = pthread_cond_destroy(dri2_sync->cond);
> > +
> > + if (ret)
> > +return EGL_FALSE;
> > +
> > + free(dri2_sync->cond);
> > +  }
> > +
> > +  if (dri2_sync->fence)
> > + dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, 
> > dri2_sync->fence);
> > +
> >free(dri2_sync);
> > }
> > +
> > +   return EGL_TRUE;
> >  }
> >
> >  static _EGLSync *
> > @@ -2408,6 +2431,7 @@ dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy,
> > struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> > struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx);
> > struct dri2_egl_sync *dri2_sync;
> > +   EGLint ret;
> >
> > dri2_sync = calloc(1, sizeof(struct dri2_egl_sync));
> > if (!dri2_sync) {
> > @@ -2450,6 +2474,23 @@ dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy,
> >  dri2_sync->fence, 0, 0))
> >   dri2_sync->base.SyncStatus = EGL_SIGNALED_KHR;
> >break;
> > +
> > +   case EGL_SYNC_REUSABLE_KHR:
> > +  dri2_sync->cond = calloc(1, sizeof(pthread_cond_t));
> > +  dri2_sync->mutex = calloc(1, sizeof(pthread_mutex_t));
> > +  ret = pthread_cond_init(dri2_sync->cond, NULL);
> > +
> > +  if (ret) {
> > + _eglError(EGL_BAD_PARAMETER, "eglCreateSyncKHR");
> > + free(dri2_sync->cond);
> > + free(dri2_sync->mutex);
> > + free(dri2_sync);
> > + return NULL;
> > +  }
> > +
> > +  /* initial status of reusable sync must be "unsignaled" */
> > +  dri2_sync->base.SyncStatus = EGL_UNSIGNALED_KHR;
> > +  break;
> > }
> >
> > p_atomic_set(_sync->refcount, 1);
> > @@ -2461,9 +2502,33 @@ dri2_destroy_sync(_EGLDriver *drv, _EGLDisplay *dpy, 
> > _EGLSync *sync)
> >  {
> > struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> > struct dri2_egl_sync *dri2_sync = dri2_egl_sync(sync);
> > +   EGLint ret = EGL_TRUE;
> > +   EGLint err;
> >
> > -   dri2_egl_unref_sync(dri2_dpy, dri2_sync);
> > -   return EGL_TRUE;
> > +   /* if type of sync is EGL_SYNC_REUSABLE_KHR and it is not signaled yet,
> > +* then unlock all threads possibly blocked by the reusable sync before
> > +* destroying it.
> > +*/
> > +   if (dri2_sync->base.Type == EGL_SYNC_REUSABLE_KHR &&
> > +   dri2_sync->base.SyncStatus == EGL_UNSIGNALED_KHR) {
> > +  dri2_sync->base.SyncStatus = EGL_SIGNALED_KHR;
> > +  /* unblock all threads currently blocked by sync */
> > +  ret = pthread_cond_broadcast(dri2_sync->cond);
> > +
> > +  if (ret) {
> > + _eglError(EGL_BAD_PARAMETER, "eglDestroySyncKHR");
> > + ret = EGL_FALSE;
> 
> BAD_PARAMETER is not the correct error for a pthread_cond_broadcast
> failure. I'm not sure, but I think we

[Mesa-dev] [PATCH] swrast: silence texture_slices warning

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

In file included from ../../src/compiler/glsl/list.h:74:0,
 from ./main/mtypes.h:47,
 from ./main/errors.h:43,
 from ./main/imports.h:44,
 from ./main/context.h:52,
 from swrast/s_texture.c:30:
swrast/s_texture.c: In function ‘check_map_teximage’:
swrast/s_texture.c:191:34: warning: passing argument 1 of ‘texture_slices’ 
discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
assert(slice < texture_slices(texImage));
  ^
swrast/s_texture.c:63:1: note: expected ‘struct gl_texture_image *’ but 
argument is of type ‘const struct gl_texture_image *’
 texture_slices(struct gl_texture_image *texImage)
 ^

Signed-off-by: Dave Airlie 
---
 src/mesa/swrast/s_texture.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index 25918e3..d35bea9 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -60,7 +60,7 @@ _swrast_delete_texture_image(struct gl_context *ctx,
 }
 
 static unsigned int
-texture_slices(struct gl_texture_image *texImage)
+texture_slices(const struct gl_texture_image *texImage)
 {
if (texImage->TexObject->Target == GL_TEXTURE_1D_ARRAY)
   return texImage->Height;
-- 
2.5.0

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Re: [Mesa-dev] [PATCH] radeonsi: fix out-of-bounds indexing of shader images

2016-03-21 Thread eocallaghan 

Reviewed-by: Edward O'Callaghan 

On 2016-03-22 07:41, Nicolai Hähnle wrote:

From: Nicolai Hähnle 

Results are undefined but may not crash. Without this change, 
out-of-bounds

indexing can lead to VM faults and GPU hangs.

Constant buffers, samplers, and possibly others will eventually need 
similar

treatment to support GL_ARB_robust_buffer_access_behavior.
---
 src/gallium/drivers/radeonsi/si_shader.c | 44 
+++-

 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 9ad2290..1e4bf82 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -532,6 +532,37 @@ static LLVMValueRef get_indirect_index(struct
si_shader_context *ctx,
 }

 /**
+ * Like get_indirect_index, but restricts the return value to a 
(possibly

+ * undefined) value inside [0..num).
+ */
+static LLVMValueRef get_bounded_indirect_index(struct 
si_shader_context *ctx,

+  const struct tgsi_ind_register 
*ind,
+  int rel_index, unsigned num)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
+   LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
+   LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
+   LLVMValueRef cc;
+
+   if (util_is_power_of_two(num)) {
+   result = LLVMBuildAnd(builder, result, c_max, "");
+   } else {
+   /* In theory, this MAX pattern should result in code that is
+* as good as the bit-wise AND above.
+*
+* In practice, LLVM generates worse code (at the time of
+* writing), because its value tracking is not strong enough.
+*/
+   cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
+   result = LLVMBuildSelect(builder, cc, result, c_max, "");
+   }
+
+   return result;
+}
+
+
+/**
  * Calculate a dword address given an input or output register and a 
stride.

  */
 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
@@ -2814,7 +2845,18 @@ image_fetch_rsrc(
LLVMValueRef rsrc_ptr;
LLVMValueRef tmp;

-		ind_index = get_indirect_index(ctx, >Indirect, 
image->Register.Index);

+   /* From the GL_ARB_shader_image_load_store extension spec:
+*
+*If a shader performs an image load, store, or atomic
+*operation using an image variable declared as an array,
+*and if the index used to select an individual element is
+*negative or greater than or equal to the size of the
+*array, the results of the operation are undefined but may
+*not lead to termination.
+*/
+   ind_index = get_bounded_indirect_index(ctx, >Indirect,
+  image->Register.Index,
+  SI_NUM_IMAGES);

rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_IMAGES);
tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);


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Re: [Mesa-dev] [PATCH 09/21] nir: Add a phi node placement helper

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 4:21 PM, Connor Abbott  wrote:

> On Mon, Mar 21, 2016 at 6:51 PM, Connor Abbott 
> wrote:
> > So overall, I think that there needs to be some explanation of the
> > design choices in the implementation. The API documentation is great,
> > but digging into the implementation might be a little daunting without
> > knowing e.g. why NEEDS_PHI is a thing. From what I gather, there are
> > three potential states a phi node can be in, once it's determined by
> > the usual dominance-frontier algorithm that it needs to be there:
> >
> > 1. There's just a NEEDS_PHI entry. IMHO this is a little bit of a
> > misnomer. This means something like "we might need to insert a phi, if
> > something uses it."
> > 2. The phi has been constructed and added to the list of phis
> > associated with this value, but it hasn't been inserted into the block
> > yet. This means something like "we know that this phi is actually
> > needed, but we haven't materialized its sources yet."
> > 3. The phi has actually been inserted into the block.
>

Right.  How about something like this:

Phi building happens in three stages:

1) Create a phi_builder_value:  When the value is created, the user
provides a bitset that tells the phi builder what blocks have definitions
for that value.  The builder then uses dominance information to determine
which blocks need to have phi nodes.

2) Add and retrieve definitions:  This stage provides the builder with all
of the information that it needs for figuring out which definitions go
where and phi builder tells the user what definitions it should use.  This
must be done in an order that respects dominance.  When the user requests a
def that needs a phi, a phi node is created and its definition is
returned.  The phi nodes returned have no sources at this point because the
builder does not yet have enough information to set the sources correctly.

3) Finalize the builder:  This is where we do most of the real work.  In
parcitular, this is where we actually add sources to the phi nodes.  At
this point, we finally have all of the definition information so we can
setup the phis.

I can put that in comments somewhere if you'd like.


> > There isn't enough explanation as to why #2 needs to be separate from
> > #3. I think it made more sense to me once I realized that the "phis"
> > list is actually a worklist, and nir_phi_builder_finish() is really a
> > worklist-based algorithm for recursively filling in phi node
> > dependencies, and when we go from #1 to #2 we're really just inserting
> > the phi into the worklist.
> >
> > On Sat, Feb 13, 2016 at 9:14 PM, Jason Ekstrand 
> wrote:
> >> Right now, we have phi placement code in two places and there are other
> >> places where it would be nice to be able to do this analysis.  Instead
> of
> >> repeating it all over the place, this commit adds a helper for placing
> all
> >> of the needed phi nodes for a value.
> >> ---
> >>  src/compiler/Makefile.sources  |   2 +
> >>  src/compiler/nir/Makefile.sources  |   2 +
> >>  src/compiler/nir/nir_phi_builder.c | 254
> +
> >>  src/compiler/nir/nir_phi_builder.h |  84 
> >>  4 files changed, 342 insertions(+)
> >>  create mode 100644 src/compiler/nir/nir_phi_builder.c
> >>  create mode 100644 src/compiler/nir/nir_phi_builder.h
> >>
> >> diff --git a/src/compiler/Makefile.sources
> b/src/compiler/Makefile.sources
> >> index c9780d6..4a1b120 100644
> >> --- a/src/compiler/Makefile.sources
> >> +++ b/src/compiler/Makefile.sources
> >> @@ -213,6 +213,8 @@ NIR_FILES = \
> >> nir/nir_opt_peephole_select.c \
> >> nir/nir_opt_remove_phis.c \
> >> nir/nir_opt_undef.c \
> >> +   nir/nir_phi_builder.c \
> >> +   nir/nir_phi_builder.h \
> >> nir/nir_print.c \
> >> nir/nir_remove_dead_variables.c \
> >> nir/nir_search.c \
> >> diff --git a/src/compiler/nir/Makefile.sources
> b/src/compiler/nir/Makefile.sources
> >> index 0755a10..7269f9f 100644
> >> --- a/src/compiler/nir/Makefile.sources
> >> +++ b/src/compiler/nir/Makefile.sources
> >> @@ -57,6 +57,8 @@ NIR_FILES = \
> >> nir_opt_peephole_select.c \
> >> nir_opt_remove_phis.c \
> >> nir_opt_undef.c \
> >> +   nir_phi_builder.c \
> >> +   nir_phi_builder.h \
> >> nir_print.c \
> >> nir_remove_dead_variables.c \
> >> nir_search.c \
> >> diff --git a/src/compiler/nir/nir_phi_builder.c
> b/src/compiler/nir/nir_phi_builder.c
> >> new file mode 100644
> >> index 000..5429083
> >> --- /dev/null
> >> +++ b/src/compiler/nir/nir_phi_builder.c
> >> @@ -0,0 +1,254 @@
> >> +/*
> >> + * Copyright © 2016 Intel Corporation
> >> + *
> >> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> >> + * copy of this software and associated documentation files (the
> "Software"),
> >> + * to deal in the Software without

Re: [Mesa-dev] [PATCH] radeonsi: fix out-of-bounds indexing of shader images

2016-03-21 Thread Nicolai Hähnle 

On 21.03.2016 15:41, Nicolai Hähnle wrote:

From: Nicolai Hähnle 

Results are undefined but may not crash. Without this change, out-of-bounds
indexing can lead to VM faults and GPU hangs.

Constant buffers, samplers, and possibly others will eventually need similar
treatment to support GL_ARB_robust_buffer_access_behavior.


FWIW, I read the relevant specs again, and we do already need to apply 
the same change to the other buffers as well for ARB_robustness. I'll 
follow up with a patch soon.


Amusingly enough, this ends up producing cleaner code. The reason is 
simple: previously, LLVM produced code that works with a full 32 bit 
index, hence manipulating 64 bit pointer values all the way. By masking 
down to the low bits, LLVM understands that some of the intermediate 
computations (i.e., multiplying by the stride of the descriptor array) 
can be done using only 32 bit registers.


Cheers,
Nicolai


---
  src/gallium/drivers/radeonsi/si_shader.c | 44 +++-
  1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 9ad2290..1e4bf82 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -532,6 +532,37 @@ static LLVMValueRef get_indirect_index(struct 
si_shader_context *ctx,
  }

  /**
+ * Like get_indirect_index, but restricts the return value to a (possibly
+ * undefined) value inside [0..num).
+ */
+static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
+  const struct tgsi_ind_register 
*ind,
+  int rel_index, unsigned num)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
+   LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
+   LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
+   LLVMValueRef cc;
+
+   if (util_is_power_of_two(num)) {
+   result = LLVMBuildAnd(builder, result, c_max, "");
+   } else {
+   /* In theory, this MAX pattern should result in code that is
+* as good as the bit-wise AND above.
+*
+* In practice, LLVM generates worse code (at the time of
+* writing), because its value tracking is not strong enough.
+*/
+   cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
+   result = LLVMBuildSelect(builder, cc, result, c_max, "");
+   }
+
+   return result;
+}
+
+
+/**
   * Calculate a dword address given an input or output register and a stride.
   */
  static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
@@ -2814,7 +2845,18 @@ image_fetch_rsrc(
LLVMValueRef rsrc_ptr;
LLVMValueRef tmp;

-   ind_index = get_indirect_index(ctx, >Indirect, 
image->Register.Index);
+   /* From the GL_ARB_shader_image_load_store extension spec:
+*
+*If a shader performs an image load, store, or atomic
+*operation using an image variable declared as an array,
+*and if the index used to select an individual element is
+*negative or greater than or equal to the size of the
+*array, the results of the operation are undefined but may
+*not lead to termination.
+*/
+   ind_index = get_bounded_indirect_index(ctx, >Indirect,
+  image->Register.Index,
+  SI_NUM_IMAGES);

rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_IMAGES);
tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);


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[Mesa-dev] [PATCH 02/11] radeonsi: implement set_shader_buffers

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_descriptors.c |  61 +-
 src/gallium/drivers/radeonsi/si_pipe.h|   1 +
 src/gallium/drivers/radeonsi/si_shader.c  |   5 +-
 src/gallium/drivers/radeonsi/si_shader.h  | 114 +-
 4 files changed, 123 insertions(+), 58 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index c7c30bf..72bd50f 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -746,6 +746,55 @@ static void si_set_constant_buffer(struct pipe_context 
*ctx, uint shader, uint s
buffers->desc.list_dirty = true;
 }
 
+/* SHADER BUFFERS */
+
+static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
+ unsigned start_slot, unsigned count,
+ struct pipe_shader_buffer *sbuffers)
+{
+   struct si_context *sctx = (struct si_context *)ctx;
+   struct si_buffer_resources *buffers = >shader_buffers[shader];
+   unsigned i;
+
+   assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
+
+   for (i = 0; i < count; ++i) {
+   struct pipe_shader_buffer *sbuffer = sbuffers ? [i] : 
NULL;
+   struct r600_resource *buf;
+   unsigned slot = start_slot + i;
+   uint32_t *desc = buffers->desc.list + slot * 4;
+   uint64_t va;
+
+   if (!sbuffer || !sbuffer->buffer) {
+   pipe_resource_reference(>buffers[slot], NULL);
+   memset(desc, 0, sizeof(uint32_t) * 4);
+   buffers->desc.enabled_mask &= ~(1llu << slot);
+   continue;
+   }
+
+   buf = (struct r600_resource *)sbuffer->buffer;
+   va = buf->gpu_address + sbuffer->buffer_offset;
+
+   desc[0] = va;
+   desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ S_008F04_STRIDE(0);
+   desc[2] = sbuffer->buffer_size;
+   desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+ S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+
+   pipe_resource_reference(>buffers[slot], >b.b);
+   radeon_add_to_buffer_list(>b, >b.gfx, buf,
+ buffers->shader_usage, buffers->priority);
+   buffers->desc.enabled_mask |= 1llu << slot;
+   }
+
+   buffers->desc.list_dirty = true;
+}
+
 /* RING BUFFERS */
 
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
@@ -1072,10 +1121,12 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
}
}
 
-   /* Constant buffers. */
+   /* Constant and shader buffers. */
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
si_reset_buffer_resources(sctx, >const_buffers[shader],
  buf, old_va);
+   si_reset_buffer_resources(sctx, >shader_buffers[shader],
+ buf, old_va);
}
 
/* Texture buffers - update virtual addresses in sampler view 
descriptors. */
@@ -1255,6 +1306,7 @@ void si_emit_shader_userdata(struct si_context *sctx, 
struct r600_atom *atom)
si_emit_shader_pointer(sctx, >rw_buffers[i].desc, 
base, false);
 
si_emit_shader_pointer(sctx, >const_buffers[i].desc, 
base, false);
+   si_emit_shader_pointer(sctx, >shader_buffers[i].desc, 
base, false);
si_emit_shader_pointer(sctx, >samplers[i].views.desc, 
base, false);
si_emit_shader_pointer(sctx, >images[i].desc, base, 
false);
}
@@ -1274,6 +1326,9 @@ void si_init_all_descriptors(struct si_context *sctx)
si_init_buffer_resources(>rw_buffers[i],
 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
 RADEON_USAGE_READWRITE, 
RADEON_PRIO_RINGS_STREAMOUT);
+   si_init_buffer_resources(>shader_buffers[i],
+SI_NUM_SHADER_BUFFERS, 
SI_SGPR_SHADER_BUFFERS,
+RADEON_USAGE_READWRITE, 
RADEON_PRIO_SHADER_RW_BUFFER);
 
si_init_descriptors(>samplers[i].views.desc,
SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
@@ -1291,6 +1346,7 @@ void si_init_all_descriptors(struct si_context *sctx)
sctx->b.b.bind_sampler_states = si_bind_sampler_states;

[Mesa-dev] [PATCH 04/11] radeonsi: adjust buffer_append_args to take a 128 bit resource

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

Move the buffer resource extraction code out into its own function.
---
 src/gallium/drivers/radeonsi/si_shader.c | 30 +++---
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 0be886e..1313134 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2924,9 +2924,28 @@ static void image_append_args(
 }
 
 /**
+ * Given a 256 bit resource, extract the top half (which stores the buffer
+ * resource in the case of textures and images).
+ */
+static LLVMValueRef extract_rsrc_top_half(
+   struct si_shader_context *ctx,
+   LLVMValueRef rsrc)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
+   LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
+
+   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
+   rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, 
bld_base->uint_bld.one, "");
+   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
+
+   return rsrc;
+}
+
+/**
  * Append the resource and indexing arguments for buffer intrinsics.
  *
- * \param rsrc the 256 bit resource
+ * \param rsrc the v4i32 buffer resource
  * \param index index into the buffer
  */
 static void buffer_append_args(
@@ -2936,17 +2955,11 @@ static void buffer_append_args(
LLVMValueRef index,
bool atomic)
 {
-   struct gallivm_state *gallivm = >radeon_bld.gallivm;
struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
const struct tgsi_full_instruction *inst = emit_data->inst;
-   LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
 
-   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
-   rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, 
bld_base->uint_bld.one, "");
-   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
-
emit_data->args[emit_data->arg_count++] = rsrc;
emit_data->args[emit_data->arg_count++] = index; /* vindex */
emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* 
voffset */
@@ -2975,6 +2988,7 @@ static void load_fetch_args(
coords = image_fetch_coords(bld_base, inst, 1);
 
if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
buffer_append_args(ctx, emit_data, rsrc, coords, false);
} else {
emit_data->args[0] = coords;
@@ -3052,6 +3066,7 @@ static void store_fetch_args(
emit_data->args[0] = data;
emit_data->arg_count = 1;
 
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
buffer_append_args(ctx, emit_data, rsrc, coords, false);
} else {
emit_data->args[0] = data;
@@ -3131,6 +3146,7 @@ static void atomic_fetch_args(
emit_data->args[emit_data->arg_count++] = data1;
 
if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
buffer_append_args(ctx, emit_data, rsrc, coords, true);
} else {
emit_data->args[emit_data->arg_count++] = coords;
-- 
2.5.0

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[Mesa-dev] [PATCH 03/11] radeonsi: preload shader buffers in shaders

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_shader.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index efc00f3..0be886e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -97,6 +97,7 @@ struct si_shader_context
LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
LLVMValueRef lds;
LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
+   LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
@@ -4668,6 +4669,21 @@ static void preload_constants(struct si_shader_context 
*ctx)
}
 }
 
+static void preload_shader_buffers(struct si_shader_context *ctx)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_SHADER_BUFFERS);
+   int buf, maxbuf;
+
+   maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
+ SI_NUM_SHADER_BUFFERS - 1);
+   for (buf = 0; buf <= maxbuf; ++buf) {
+   ctx->shader_buffers[buf] =
+   build_indexed_load_const(
+   ctx, ptr, lp_build_const_int32(gallivm, buf));
+   }
+}
+
 static void preload_samplers(struct si_shader_context *ctx)
 {
struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
@@ -5529,6 +5545,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
create_meta_data();
create_function();
preload_constants();
+   preload_shader_buffers();
preload_samplers();
preload_images();
preload_streamout_buffers();
-- 
2.5.0

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[Mesa-dev] [PATCH 08/11] radeonsi: add shader buffer support to TGSI_OPCODE_STORE

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_shader.c | 129 ++-
 1 file changed, 111 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index d651df9..1a0f75b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3114,41 +3114,129 @@ static void store_fetch_args(
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   struct tgsi_full_src_register image;
-   unsigned target = inst->Memory.Texture;
+   struct tgsi_full_src_register memory;
LLVMValueRef chans[4];
LLVMValueRef data;
-   LLVMValueRef coords;
LLVMValueRef rsrc;
unsigned chan;
 
emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
 
-   image = tgsi_full_src_register_from_dst(>Dst[0]);
-   coords = image_fetch_coords(bld_base, inst, 0);
-
for (chan = 0; chan < 4; ++chan) {
chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
}
data = lp_build_gather_values(gallivm, chans, 4);
 
-   if (target == TGSI_TEXTURE_BUFFER) {
-   image_fetch_rsrc(bld_base, , false, );
-   emit_data->args[0] = data;
-   emit_data->arg_count = 1;
+   emit_data->args[emit_data->arg_count++] = data;
+
+   memory = tgsi_full_src_register_from_dst(>Dst[0]);
 
-   rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords,
-  bld_base->uint_bld.zero, false);
+   if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
+   LLVMValueRef offset;
+   LLVMValueRef tmp;
+
+   rsrc = shader_buffer_fetch_rsrc(ctx, );
+
+   tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
+   offset = LLVMBuildBitCast(builder, tmp, 
bld_base->uint_bld.elem_type, "");
+
+   buffer_append_args(ctx, emit_data, rsrc, 
bld_base->uint_bld.zero,
+  offset, false);
} else {
+   unsigned target = inst->Memory.Texture;
+   LLVMValueRef coords;
+
+   coords = image_fetch_coords(bld_base, inst, 0);
+
+   if (target == TGSI_TEXTURE_BUFFER) {
+   image_fetch_rsrc(bld_base, , false, );
+
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+   bld_base->uint_bld.zero, false);
+   } else {
+   emit_data->args[1] = coords;
+   image_fetch_rsrc(bld_base, , true, 
_data->args[2]);
+   emit_data->args[3] = lp_build_const_int32(gallivm, 15); 
/* dmask */
+   emit_data->arg_count = 4;
+
+   image_append_args(ctx, emit_data, target, false);
+   }
+   }
+}
+
+static void store_emit_buffer(
+   struct si_shader_context *ctx,
+   struct lp_build_emit_data *emit_data)
+{
+   const struct tgsi_full_instruction *inst = emit_data->inst;
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
+   struct lp_build_context *uint_bld = 
>radeon_bld.soa.bld_base.uint_bld;
+   LLVMValueRef base_data = emit_data->args[0];
+   LLVMValueRef base_offset = emit_data->args[3];
+   unsigned writemask = inst->Dst[0].Register.WriteMask;
+
+   while (writemask) {
+   int start, count;
+   const char *intrinsic_name;
+   LLVMValueRef data;
+   LLVMValueRef offset;
+   LLVMValueRef tmp;
+
+   u_bit_scan_consecutive_range(, , );
+
+   /* Due to an LLVM limitation, split 3-element writes
+* into a 2-element and a 1-element write. */
+   if (count == 3) {
+   writemask |= 1 << (start + 2);
+   count = 2;
+   }
+
+   if (count == 4) {
+   data = base_data;
+   intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
+   } else if (count == 2) {
+   LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
+
+   tmp = LLVMBuildExtractElement(
+   builder, base_data,
+   lp_build_const_int32(gallivm, start), "");
+   data = LLVMBuildInsertElement(
+   builder, LLVMGetUndef(v2f32), tmp,
+   uint_bld->zero,

[Mesa-dev] [PATCH 11/11] docs: mark atomic counters and SSBOs as done for radeonsi

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

While I'm at it, add the image extensions in the GL ES section of GL3.txt.
---
 docs/GL3.txt  | 12 ++--
 docs/relnotes/11.3.0.html |  4 +++-
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 89cc662..4bb7970 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -150,7 +150,7 @@ GL 4.2, GLSL 4.20:
 
   GL_ARB_texture_compression_bptc   DONE (i965, nvc0, 
r600, radeonsi)
   GL_ARB_compressed_texture_pixel_storage   DONE (all drivers)
-  GL_ARB_shader_atomic_counters DONE (i965, nvc0)
+  GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
radeonsi)
   GL_ARB_texture_storageDONE (all drivers)
   GL_ARB_transform_feedback_instanced   DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_base_instance  DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, softpipe)
@@ -179,7 +179,7 @@ GL 4.3, GLSL 4.30:
   GL_ARB_program_interface_queryDONE (all drivers)
   GL_ARB_robust_buffer_access_behavior  not started
   GL_ARB_shader_image_size  DONE (i965, radeonsi)
-  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0)
+  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
radeonsi)
   GL_ARB_stencil_texturing  DONE (i965/gen8+, 
nv50, nvc0, r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_texture_buffer_range   DONE (nv50, nvc0, 
i965, r600, radeonsi, llvmpipe)
   GL_ARB_texture_query_levels   DONE (all drivers that 
support GLSL 1.30)
@@ -230,10 +230,10 @@ GLES3.1, GLSL ES 3.1
   GL_ARB_explicit_uniform_location  DONE (all drivers that 
support GLSL)
   GL_ARB_framebuffer_no_attachments DONE (i965)
   GL_ARB_program_interface_queryDONE (all drivers)
-  GL_ARB_shader_atomic_counters DONE (i965, nvc0)
-  GL_ARB_shader_image_load_storeDONE (i965)
-  GL_ARB_shader_image_size  DONE (i965)
-  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0)
+  GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
radeonsi)
+  GL_ARB_shader_image_load_storeDONE (i965, radeonsi)
+  GL_ARB_shader_image_size  DONE (i965, radeonsi)
+  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
radeonsi)
   GL_ARB_shading_language_packing   DONE (all drivers)
   GL_ARB_separate_shader_objectsDONE (all drivers)
   GL_ARB_stencil_texturing  DONE (i965/gen8+, 
nv50, nvc0, r600, radeonsi, llvmpipe, softpipe)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 04564a8..7fa2857 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -45,9 +45,11 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 GL_ARB_internalformat_query2 on i965
-GL_ARB_shader_atomic_counter_ops on nvc0
+GL_ARB_shader_atomic_counters on radeonsi
+GL_ARB_shader_atomic_counter_ops on nvc0, radeonsi
 GL_ARB_shader_image_load_store on radeonsi
 GL_ARB_shader_image_size on radeonsi
+GL_ARB_shader_storage_buffer_object on radeonsi
 GL_OES_texture_border_clamp and GL_EXT_texture_border_clamp on all drivers 
that support GL_ARB_texture_border_clamp
 GL_OES_shader_image_atomic on all drivers that support 
GL_ARB_shader_image_load_store
 
-- 
2.5.0

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[Mesa-dev] [PATCH 09/11] radeonsi: add shader buffer support to TGSI_OPCODE_RESQ

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_shader.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 1a0f75b..87dc229 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3373,14 +3373,17 @@ static void resq_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
 {
+   struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction *inst = emit_data->inst;
const struct tgsi_full_src_register *reg = >Src[0];
-   unsigned tex_target = inst->Memory.Texture;
 
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 
-   if (tex_target == TGSI_TEXTURE_BUFFER) {
+   if (reg->Register.File == TGSI_FILE_BUFFER) {
+   emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
+   emit_data->arg_count = 1;
+   } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
image_fetch_rsrc(bld_base, reg, false, _data->args[0]);
emit_data->arg_count = 1;
} else {
@@ -3389,7 +3392,7 @@ static void resq_fetch_args(
emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* 
dmask */
emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
-   emit_data->args[5] = tgsi_is_array_image(tex_target) ?
+   emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da 
*/
emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
@@ -3407,10 +3410,12 @@ static void resq_emit(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction *inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
LLVMValueRef out;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
+   out = LLVMBuildExtractElement(builder, emit_data->args[0],
+ lp_build_const_int32(gallivm, 2), 
"");
+   } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
out = get_buffer_size(bld_base, emit_data->args[0]);
} else {
out = lp_build_intrinsic(
@@ -3419,7 +3424,7 @@ static void resq_emit(
LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
 
/* Divide the number of layers by 6 to get the number of cubes. 
*/
-   if (target == TGSI_TEXTURE_CUBE_ARRAY) {
+   if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
 
-- 
2.5.0

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[Mesa-dev] [PATCH 05/11] radeonsi: add offset parameter to buffer_append_args

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_shader.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 1313134..b5e962f 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2946,13 +2946,15 @@ static LLVMValueRef extract_rsrc_top_half(
  * Append the resource and indexing arguments for buffer intrinsics.
  *
  * \param rsrc the v4i32 buffer resource
- * \param index index into the buffer
+ * \param index index into the buffer (stride-based)
+ * \param offset byte offset into the buffer
  */
 static void buffer_append_args(
struct si_shader_context *ctx,
struct lp_build_emit_data *emit_data,
LLVMValueRef rsrc,
LLVMValueRef index,
+   LLVMValueRef offset,
bool atomic)
 {
struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
@@ -2962,7 +2964,7 @@ static void buffer_append_args(
 
emit_data->args[emit_data->arg_count++] = rsrc;
emit_data->args[emit_data->arg_count++] = index; /* vindex */
-   emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* 
voffset */
+   emit_data->args[emit_data->arg_count++] = offset; /* voffset */
if (!atomic) {
emit_data->args[emit_data->arg_count++] =
inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | 
TGSI_MEMORY_VOLATILE) ?
@@ -2989,7 +2991,8 @@ static void load_fetch_args(
 
if (target == TGSI_TEXTURE_BUFFER) {
rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords, false);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, false);
} else {
emit_data->args[0] = coords;
emit_data->args[1] = rsrc;
@@ -3067,7 +3070,8 @@ static void store_fetch_args(
emit_data->arg_count = 1;
 
rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords, false);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, false);
} else {
emit_data->args[0] = data;
emit_data->args[1] = coords;
@@ -3147,7 +3151,8 @@ static void atomic_fetch_args(
 
if (target == TGSI_TEXTURE_BUFFER) {
rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords, true);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, true);
} else {
emit_data->args[emit_data->arg_count++] = coords;
emit_data->args[emit_data->arg_count++] = rsrc;
-- 
2.5.0

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[Mesa-dev] [PATCH 07/11] radeonsi: add shader buffer support to TGSI_OPCODE_LOAD

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_shader.c | 89 +---
 1 file changed, 70 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 795140b..d651df9 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2975,7 +2975,6 @@ static void buffer_append_args(
LLVMValueRef offset,
bool atomic)
 {
-   struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
const struct tgsi_full_instruction *inst = emit_data->inst;
LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
@@ -2999,28 +2998,75 @@ static void load_fetch_args(
struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction * inst = emit_data->inst;
unsigned target = inst->Memory.Texture;
-   LLVMValueRef coords;
LLVMValueRef rsrc;
 
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 
-   image_fetch_rsrc(bld_base, >Src[0], false, );
-   coords = image_fetch_coords(bld_base, inst, 1);
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
+   LLVMBuilderRef builder = gallivm->builder;
+   LLVMValueRef offset;
+   LLVMValueRef tmp;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
-   rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords,
-  bld_base->uint_bld.zero, false);
+   rsrc = shader_buffer_fetch_rsrc(ctx, >Src[0]);
+
+   tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
+   offset = LLVMBuildBitCast(builder, tmp, 
bld_base->uint_bld.elem_type, "");
+
+   buffer_append_args(ctx, emit_data, rsrc, 
bld_base->uint_bld.zero,
+  offset, false);
} else {
-   emit_data->args[0] = coords;
-   emit_data->args[1] = rsrc;
-   emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* 
dmask */
-   emit_data->arg_count = 3;
+   LLVMValueRef coords;
 
-   image_append_args(ctx, emit_data, target, false);
+   image_fetch_rsrc(bld_base, >Src[0], false, );
+   coords = image_fetch_coords(bld_base, inst, 1);
+
+   if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+   bld_base->uint_bld.zero, false);
+   } else {
+   emit_data->args[0] = coords;
+   emit_data->args[1] = rsrc;
+   emit_data->args[2] = lp_build_const_int32(gallivm, 15); 
/* dmask */
+   emit_data->arg_count = 3;
+
+   image_append_args(ctx, emit_data, target, false);
+   }
}
 }
 
+static void load_emit_buffer(struct si_shader_context *ctx,
+struct lp_build_emit_data *emit_data)
+{
+   const struct tgsi_full_instruction *inst = emit_data->inst;
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
+   uint writemask = inst->Dst[0].Register.WriteMask;
+   uint count = util_last_bit(writemask);
+   const char *intrinsic_name;
+   LLVMTypeRef dst_type;
+
+   switch (count) {
+   case 1:
+   intrinsic_name = "llvm.amdgcn.buffer.load.f32";
+   dst_type = ctx->f32;
+   break;
+   case 2:
+   intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
+   dst_type = LLVMVectorType(ctx->f32, 2);
+   break;
+   default: // 3 & 4
+   intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
+   dst_type = ctx->v4f32;
+   count = 4;
+   }
+
+   emit_data->output[emit_data->chan] = lp_build_intrinsic(
+   builder, intrinsic_name, dst_type,
+   emit_data->args, emit_data->arg_count,
+   LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+}
+
 static void load_emit(
const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
@@ -3030,18 +3076,23 @@ static void load_emit(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
char intrinsic_name[32];
char coords_type[8];
 
if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)

[Mesa-dev] [PATCH 06/11] radeonsi: add shader buffer support to TGSI_OPCODE_ATOM*

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_shader.c | 61 
 1 file changed, 46 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index b5e962f..795140b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2774,6 +2774,24 @@ static void membar_emit(
emit_optimization_barrier(ctx);
 }
 
+static LLVMValueRef
+shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
+const struct tgsi_full_src_register *reg)
+{
+   LLVMValueRef ind_index;
+   LLVMValueRef rsrc_ptr;
+
+   if (!reg->Register.Indirect)
+   return ctx->shader_buffers[reg->Register.Index];
+
+   ind_index = get_bounded_indirect_index(ctx, >Indirect,
+  reg->Register.Index,
+  SI_NUM_SHADER_BUFFERS);
+
+   rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_SHADER_BUFFERS);
+   return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
+}
+
 static bool tgsi_is_array_sampler(unsigned target)
 {
return target == TGSI_TEXTURE_1D_ARRAY ||
@@ -3122,18 +3140,12 @@ static void atomic_fetch_args(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
LLVMValueRef data1, data2;
-   LLVMValueRef coords;
LLVMValueRef rsrc;
LLVMValueRef tmp;
 
emit_data->dst_type = bld_base->base.elem_type;
 
-   image_fetch_rsrc(bld_base, >Src[0], target != TGSI_TEXTURE_BUFFER,
-);
-   coords = image_fetch_coords(bld_base, inst, 1);
-
tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, 
"");
 
@@ -3149,15 +3161,34 @@ static void atomic_fetch_args(
emit_data->args[emit_data->arg_count++] = data2;
emit_data->args[emit_data->arg_count++] = data1;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
-   rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords,
-  bld_base->uint_bld.zero, true);
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
+   LLVMValueRef offset;
+
+   rsrc = shader_buffer_fetch_rsrc(ctx, >Src[0]);
+
+   tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
+   offset = LLVMBuildBitCast(builder, tmp, 
bld_base->uint_bld.elem_type, "");
+
+   buffer_append_args(ctx, emit_data, rsrc, 
bld_base->uint_bld.zero,
+  offset, true);
} else {
-   emit_data->args[emit_data->arg_count++] = coords;
-   emit_data->args[emit_data->arg_count++] = rsrc;
+   unsigned target = inst->Memory.Texture;
+   LLVMValueRef coords;
+
+   image_fetch_rsrc(bld_base, >Src[0],
+target != TGSI_TEXTURE_BUFFER, );
+   coords = image_fetch_coords(bld_base, inst, 1);
 
-   image_append_args(ctx, emit_data, target, true);
+   if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, true);
+   } else {
+   emit_data->args[emit_data->arg_count++] = coords;
+   emit_data->args[emit_data->arg_count++] = rsrc;
+
+   image_append_args(ctx, emit_data, target, true);
+   }
}
 }
 
@@ -3169,11 +3200,11 @@ static void atomic_emit(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
char intrinsic_name[40];
LLVMValueRef tmp;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
+   inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
snprintf(intrinsic_name, sizeof(intrinsic_name),
 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
} else {
-- 
2.5.0

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[Mesa-dev] [PATCH 10/11] radeonsi: enable shader buffer pipe caps

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_pipe.c  | 4 ++--
 src/gallium/drivers/radeonsi/si_state.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index dd1103e..685026c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -329,6 +329,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
 
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return 4;
 
@@ -352,7 +353,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
-   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
@@ -538,7 +538,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, 
unsigned shader, enu
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
-   return 0;
+   return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
}
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index c4d6b9d..95a69e8 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -160,6 +160,8 @@ struct si_shader_data {
 
 #define SI_NUM_IMAGES  16
 
+#define SI_NUM_SHADER_BUFFERS  16
+
 /* Read-write buffer slots.
  *
  * Ring buffers:0..1
-- 
2.5.0

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[Mesa-dev] [PATCH 00/11] radeonsi: shader buffer support (atomic counters, ssbo)

2016-03-21 Thread Nicolai Hähnle 
Hi,

since shader images have laid most of the foundation, here are shader buffers
now. This is the last extension missing for OpenGL 4.2 (we still need to turn
on GLSL 4.2, but I think that only involves flipping a bit).

As with shader images, this extension needs bleeding edge LLVM - this time,
important patches have not landed upstream yet, and if you want to try this
code you'll need my LLVM branch at 
https://cgit.freedesktop.org/~nh/llvm/log/?h=images

(For those following along at home, the necessary LLVM patches for shader
images have already landed upstream.)

In principle, there are two alternative implementations for shader buffers:
using LLVM IR  pointers with LLVM-native load/store instructions directly, or
using intrinsics that operate on GCN buffer descriptors. This implementation
uses the second approach. A brief comparison between the two approaches:

1. The pointer approach would use FLAT memory instructions on CI+, which
   operate on 64 bit pointers rather than 128 bit buffer descriptors. This
   would reduce SGPR memory pressure slightly.

2. LLVM understands pointers for alias analysis, so it's possible that it
   would generate somewhat better code if we were to use pointers in the
   IR.

3. The buffer load/store intructions have built-in bounds checks. Bounds
   checks are required for an honest implementation of the ARB_robustness
   extension, which we claim to support.

The last point makes it obvious that the implementation really needs to use
buffer intrinsics, but it'd be interesting to know how big the difference
in code quality is versus something that uses pointers. To get the best of
both worlds, we should really find a way to teach LLVM's alias analysis
about what those buffer descriptors mean. For now, this current approach is
the right way to do it.

Please review!

Thanks,
Nicolai

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[Mesa-dev] [PATCH 01/11] radeonsi: move resetting of constant buffers into a separate function

2016-03-21 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

This will be re-used for shader buffers.
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 41 +--
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 815b87b..c7c30bf 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -977,6 +977,30 @@ void si_update_compressed_colortex_masks(struct si_context 
*sctx)
 
 /* BUFFER DISCARD/INVALIDATION */
 
+/** Reset descriptors of buffer resources after \p buf has been invalidated. */
+static void si_reset_buffer_resources(struct si_context *sctx,
+ struct si_buffer_resources *buffers,
+ struct pipe_resource *buf,
+ uint64_t old_va)
+{
+   uint64_t mask = buffers->desc.enabled_mask;
+
+   while (mask) {
+   unsigned i = u_bit_scan64();
+   if (buffers->buffers[i] == buf) {
+   si_desc_reset_buffer_offset(>b.b,
+   buffers->desc.list + i*4,
+   old_va, buf);
+   buffers->desc.list_dirty = true;
+
+   radeon_add_to_buffer_list(>b, >b.gfx,
+   (struct r600_resource *)buf,
+   buffers->shader_usage,
+   buffers->priority);
+   }
+   }
+}
+
 /* Reallocate a buffer a update all resource bindings where the buffer is
  * bound.
  *
@@ -1050,21 +1074,8 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
 
/* Constant buffers. */
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
-   struct si_buffer_resources *buffers = 
>const_buffers[shader];
-   uint64_t mask = buffers->desc.enabled_mask;
-
-   while (mask) {
-   unsigned i = u_bit_scan64();
-   if (buffers->buffers[i] == buf) {
-   si_desc_reset_buffer_offset(ctx, 
buffers->desc.list + i*4,
-   old_va, buf);
-   buffers->desc.list_dirty = true;
-
-   radeon_add_to_buffer_list(>b, 
>b.gfx,
- rbuffer, 
buffers->shader_usage,
- buffers->priority);
-   }
-   }
+   si_reset_buffer_resources(sctx, >const_buffers[shader],
+ buf, old_va);
}
 
/* Texture buffers - update virtual addresses in sampler view 
descriptors. */
-- 
2.5.0

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Re: [Mesa-dev] [PATCH 09/21] nir: Add a phi node placement helper

2016-03-21 Thread Connor Abbott 
On Mon, Mar 21, 2016 at 6:51 PM, Connor Abbott  wrote:
> So overall, I think that there needs to be some explanation of the
> design choices in the implementation. The API documentation is great,
> but digging into the implementation might be a little daunting without
> knowing e.g. why NEEDS_PHI is a thing. From what I gather, there are
> three potential states a phi node can be in, once it's determined by
> the usual dominance-frontier algorithm that it needs to be there:
>
> 1. There's just a NEEDS_PHI entry. IMHO this is a little bit of a
> misnomer. This means something like "we might need to insert a phi, if
> something uses it."
> 2. The phi has been constructed and added to the list of phis
> associated with this value, but it hasn't been inserted into the block
> yet. This means something like "we know that this phi is actually
> needed, but we haven't materialized its sources yet."
> 3. The phi has actually been inserted into the block.
>
> There isn't enough explanation as to why #2 needs to be separate from
> #3. I think it made more sense to me once I realized that the "phis"
> list is actually a worklist, and nir_phi_builder_finish() is really a
> worklist-based algorithm for recursively filling in phi node
> dependencies, and when we go from #1 to #2 we're really just inserting
> the phi into the worklist.
>
> On Sat, Feb 13, 2016 at 9:14 PM, Jason Ekstrand  wrote:
>> Right now, we have phi placement code in two places and there are other
>> places where it would be nice to be able to do this analysis.  Instead of
>> repeating it all over the place, this commit adds a helper for placing all
>> of the needed phi nodes for a value.
>> ---
>>  src/compiler/Makefile.sources  |   2 +
>>  src/compiler/nir/Makefile.sources  |   2 +
>>  src/compiler/nir/nir_phi_builder.c | 254 
>> +
>>  src/compiler/nir/nir_phi_builder.h |  84 
>>  4 files changed, 342 insertions(+)
>>  create mode 100644 src/compiler/nir/nir_phi_builder.c
>>  create mode 100644 src/compiler/nir/nir_phi_builder.h
>>
>> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
>> index c9780d6..4a1b120 100644
>> --- a/src/compiler/Makefile.sources
>> +++ b/src/compiler/Makefile.sources
>> @@ -213,6 +213,8 @@ NIR_FILES = \
>> nir/nir_opt_peephole_select.c \
>> nir/nir_opt_remove_phis.c \
>> nir/nir_opt_undef.c \
>> +   nir/nir_phi_builder.c \
>> +   nir/nir_phi_builder.h \
>> nir/nir_print.c \
>> nir/nir_remove_dead_variables.c \
>> nir/nir_search.c \
>> diff --git a/src/compiler/nir/Makefile.sources 
>> b/src/compiler/nir/Makefile.sources
>> index 0755a10..7269f9f 100644
>> --- a/src/compiler/nir/Makefile.sources
>> +++ b/src/compiler/nir/Makefile.sources
>> @@ -57,6 +57,8 @@ NIR_FILES = \
>> nir_opt_peephole_select.c \
>> nir_opt_remove_phis.c \
>> nir_opt_undef.c \
>> +   nir_phi_builder.c \
>> +   nir_phi_builder.h \
>> nir_print.c \
>> nir_remove_dead_variables.c \
>> nir_search.c \
>> diff --git a/src/compiler/nir/nir_phi_builder.c 
>> b/src/compiler/nir/nir_phi_builder.c
>> new file mode 100644
>> index 000..5429083
>> --- /dev/null
>> +++ b/src/compiler/nir/nir_phi_builder.c
>> @@ -0,0 +1,254 @@
>> +/*
>> + * Copyright © 2016 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the 
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "nir_phi_builder.h"
>> +#include "nir/nir_vla.h"
>> +
>> +struct nir_phi_builder {
>> +   nir_shader *shader;
>> +   nir_function_impl *impl;
>> +
>> +   /* Copied from the impl for easy access */
>> +   unsigned num_blocks;
>> +
>> +   /* Array of all blocks indexed by block->index. */
>> +   nir_block **blocks;
>> +
>> +   /* Hold on to the values so we can

Re: [Mesa-dev] [PATCH 23/29] nir: add i2d and u2d opcodes

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:06 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> ---
>  src/compiler/nir/glsl_to_nir.cpp | 6 ++
>  src/compiler/nir/nir_opcodes.py  | 2 ++
>  2 files changed, 8 insertions(+)
>
> diff --git a/src/compiler/nir/glsl_to_nir.cpp
> b/src/compiler/nir/glsl_to_nir.cpp
> index 952d787..d087a77 100644
> --- a/src/compiler/nir/glsl_to_nir.cpp
> +++ b/src/compiler/nir/glsl_to_nir.cpp
> @@ -1357,6 +1357,12 @@ nir_visitor::visit(ir_expression *ir)
> case ir_unop_d2i:  result = nir_d2i(, srcs[0]);   break;
> case ir_unop_d2u:  result = nir_d2u(, srcs[0]);   break;
> case ir_unop_d2b:  result = nir_d2b(, srcs[0]);   break;
> +   case ir_unop_i2d:
> +  result = supports_ints ? nir_i2d(, srcs[0]) : nir_fmov(,
> srcs[0]);
> +  break;
> +   case ir_unop_u2d:
> +  result = supports_ints ? nir_u2d(, srcs[0]) : nir_fmov(,
> srcs[0]);
>

If you're going to be using the u2d opcode, you'd better support integers.


> +  break;
> case ir_unop_i2u:
> case ir_unop_u2i:
> case ir_unop_bitcast_i2f:
> diff --git a/src/compiler/nir/nir_opcodes.py
> b/src/compiler/nir/nir_opcodes.py
> index a161ac1..cf6ce83 100644
> --- a/src/compiler/nir/nir_opcodes.py
> +++ b/src/compiler/nir/nir_opcodes.py
> @@ -164,6 +164,7 @@ unop_convert("f2u", tuint32, tfloat32, "src0") #
> Float-to-unsigned conversion
>  unop_convert("d2i", tint32, tfloat64, "src0") # Double-to-integer
> conversion.
>  unop_convert("d2u", tuint32, tfloat64, "src0") # Double-to-unsigned
> conversion.
>  unop_convert("i2f", tfloat32, tint32, "src0") # Integer-to-float
> conversion.
> +unop_convert("i2d", tfloat64, tint32, "src0") # Integer-to-double
> conversion.
>  # Float-to-boolean conversion
>  unop_convert("f2b", tbool, tfloat32, "src0 != 0.0f")
>  unop_convert("d2b", tbool, tfloat64, "src0 != 0.0")
> @@ -173,6 +174,7 @@ unop_convert("b2f", tfloat32, tbool, "src0 ? 1.0f :
> 0.0f")
>  unop_convert("i2b", tbool, tint32, "src0 != 0")
>  unop_convert("b2i", tint32, tbool, "src0 ? 1 : 0") # Boolean-to-int
> conversion
>  unop_convert("u2f", tfloat32, tuint32, "src0") # Unsigned-to-float
> conversion.
> +unop_convert("u2d", tfloat64, tuint32, "src0") # Unsigned-to-double
> conversion.
>  # double-to-float conversion
>  unop_convert("d2f", tfloat32, tfloat64, "src0") # Single to double
> precision
>  unop_convert("f2d", tfloat64, tfloat32, "src0") # Double to single
> precision
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 19/29] nir: fix up bit sizes for undefined alu sources

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> Undefined sources in alu operations don't have a valid bit size because
> they are uninitialized. Simply ignoring undefined sources for bit size
> validation is not enough since drivers can check and operate with the
> bit-size and that can lead to issues later on. Instead, fix undefined
> sources to always have a compatible bit size.
>

I'm not sure what I think about this.  I think I'd rather have undefs
simply have the right bitsize.


> v2 (Sam):
> - Use helper to get type size from nir_alu_type.
> ---
>  src/compiler/nir/nir_validate.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/src/compiler/nir/nir_validate.c
> b/src/compiler/nir/nir_validate.c
> index 9f18d1c..645c15a 100644
> --- a/src/compiler/nir/nir_validate.c
> +++ b/src/compiler/nir/nir_validate.c
> @@ -180,9 +180,11 @@ validate_alu_src(nir_alu_instr *instr, unsigned
> index, validate_state *state)
>
> unsigned num_components;
> unsigned src_bit_size;
> +   bool is_undef = false;
> if (src->src.is_ssa) {
>src_bit_size = src->src.ssa->bit_size;
>num_components = src->src.ssa->num_components;
> +  is_undef = src->src.ssa->parent_instr->type ==
> nir_instr_type_ssa_undef;
> } else {
>src_bit_size = src->src.reg.reg->bit_size;
>if (src->src.reg.reg->is_packed)
> @@ -205,12 +207,20 @@ validate_alu_src(nir_alu_instr *instr, unsigned
> index, validate_state *state)
>
> if (nir_alu_type_get_type_size(src_type)) {
>/* This source has an explicit bit size */
> +  if (is_undef) {
> + src_bit_size = nir_alu_type_get_type_size(src_type);
> + src->src.ssa->bit_size = src_bit_size;
> +  }
>assert(nir_alu_type_get_type_size(src_type) == src_bit_size);
> } else {
>if
> (!nir_alu_type_get_type_size(nir_op_infos[instr->op].output_type)) {
>   unsigned dest_bit_size =
>  instr->dest.dest.is_ssa ? instr->dest.dest.ssa.bit_size
>  : instr->dest.dest.reg.reg->bit_size;
> + if (is_undef) {
> +src_bit_size = dest_bit_size;
> +src->src.ssa->bit_size = dest_bit_size;
> + }
>   assert(dest_bit_size == src_bit_size);
>}
> }
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH] radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)

2016-03-21 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Mon, Mar 21, 2016 at 5:38 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> This fixes arb_shader_image_load_store-host-mem-barrier.
>
> v2: flush TC L2 for index buffers on <= CIK (Marek)
> ---
>  src/gallium/drivers/radeonsi/si_state.c | 14 --
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index b9bdd47..3a490aa 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3536,18 +3536,28 @@ static void si_memory_barrier(struct pipe_context 
> *ctx, unsigned flags)
> if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
>  PIPE_BARRIER_SHADER_BUFFER |
>  PIPE_BARRIER_TEXTURE |
> -PIPE_BARRIER_IMAGE)) {
> +PIPE_BARRIER_IMAGE |
> +PIPE_BARRIER_STREAMOUT_BUFFER)) {
> /* As far as I can tell, L1 contents are written back to L2
>  * automatically at end of shader, but the contents of other
>  * L1 caches might still be stale. */
> sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
> }
>
> +   if (flags & PIPE_BARRIER_INDEX_BUFFER) {
> +   sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
> +
> +   /* Indices are read through TC L2 since VI. */
> +   if (sctx->screen->b.chip_class <= CIK)
> +   sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
> +   }
> +
> if (flags & PIPE_BARRIER_FRAMEBUFFER)
> sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
>
> if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
> -PIPE_BARRIER_FRAMEBUFFER)) {
> +PIPE_BARRIER_FRAMEBUFFER |
> +PIPE_BARRIER_INDIRECT_BUFFER)) {
> /* Not sure if INV_GLOBAL_L2 is the best thing here.
>  *
>  * We need to make sure that TC L1 & L2 are written back to
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 09/21] nir: Add a phi node placement helper

2016-03-21 Thread Connor Abbott 
So overall, I think that there needs to be some explanation of the
design choices in the implementation. The API documentation is great,
but digging into the implementation might be a little daunting without
knowing e.g. why NEEDS_PHI is a thing. From what I gather, there are
three potential states a phi node can be in, once it's determined by
the usual dominance-frontier algorithm that it needs to be there:

1. There's just a NEEDS_PHI entry. IMHO this is a little bit of a
misnomer. This means something like "we might need to insert a phi, if
something uses it."
2. The phi has been constructed and added to the list of phis
associated with this value, but it hasn't been inserted into the block
yet. This means something like "we know that this phi is actually
needed, but we haven't materialized its sources yet."
3. The phi has actually been inserted into the block.

There isn't enough explanation as to why #2 needs to be separate from
#3. I think it made more sense to me once I realized that the "phis"
list is actually a worklist, and nir_phi_builder_finish() is really a
worklist-based algorithm for recursively filling in phi node
dependencies, and when we go from #1 to #2 we're really just inserting
the phi into the worklist.

On Sat, Feb 13, 2016 at 9:14 PM, Jason Ekstrand  wrote:
> Right now, we have phi placement code in two places and there are other
> places where it would be nice to be able to do this analysis.  Instead of
> repeating it all over the place, this commit adds a helper for placing all
> of the needed phi nodes for a value.
> ---
>  src/compiler/Makefile.sources  |   2 +
>  src/compiler/nir/Makefile.sources  |   2 +
>  src/compiler/nir/nir_phi_builder.c | 254 
> +
>  src/compiler/nir/nir_phi_builder.h |  84 
>  4 files changed, 342 insertions(+)
>  create mode 100644 src/compiler/nir/nir_phi_builder.c
>  create mode 100644 src/compiler/nir/nir_phi_builder.h
>
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index c9780d6..4a1b120 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -213,6 +213,8 @@ NIR_FILES = \
> nir/nir_opt_peephole_select.c \
> nir/nir_opt_remove_phis.c \
> nir/nir_opt_undef.c \
> +   nir/nir_phi_builder.c \
> +   nir/nir_phi_builder.h \
> nir/nir_print.c \
> nir/nir_remove_dead_variables.c \
> nir/nir_search.c \
> diff --git a/src/compiler/nir/Makefile.sources 
> b/src/compiler/nir/Makefile.sources
> index 0755a10..7269f9f 100644
> --- a/src/compiler/nir/Makefile.sources
> +++ b/src/compiler/nir/Makefile.sources
> @@ -57,6 +57,8 @@ NIR_FILES = \
> nir_opt_peephole_select.c \
> nir_opt_remove_phis.c \
> nir_opt_undef.c \
> +   nir_phi_builder.c \
> +   nir_phi_builder.h \
> nir_print.c \
> nir_remove_dead_variables.c \
> nir_search.c \
> diff --git a/src/compiler/nir/nir_phi_builder.c 
> b/src/compiler/nir/nir_phi_builder.c
> new file mode 100644
> index 000..5429083
> --- /dev/null
> +++ b/src/compiler/nir/nir_phi_builder.c
> @@ -0,0 +1,254 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir_phi_builder.h"
> +#include "nir/nir_vla.h"
> +
> +struct nir_phi_builder {
> +   nir_shader *shader;
> +   nir_function_impl *impl;
> +
> +   /* Copied from the impl for easy access */
> +   unsigned num_blocks;
> +
> +   /* Array of all blocks indexed by block->index. */
> +   nir_block **blocks;
> +
> +   /* Hold on to the values so we can easily iterate over them. */
> +   struct exec_list values;
> +
> +   /* Worklist for phi adding */
> +   unsigned iter_count;
> +   unsigned *work;
> +   nir_block **W;
> +};
> +
> +#define NEEDS_PHI ((nir_ssa_def

Re: [Mesa-dev] [PATCH 14/29] nir: add support for printing double immediates

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Connor Abbott 
>
> ---
>  src/compiler/nir/nir_print.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
> index 30a8233..0b3f954 100644
> --- a/src/compiler/nir/nir_print.c
> +++ b/src/compiler/nir/nir_print.c
> @@ -719,7 +719,10 @@ print_load_const_instr(nir_load_const_instr *instr,
> print_state *state)
> * and then print the float in a comment for readability.
> */
>
> -  fprintf(fp, "0x%08x /* %f */", instr->value.u32[i],
> instr->value.f32[i]);
> +  if (instr->def.bit_size == 64)
> + fprintf(fp, "%f", instr->value.f64[i]);
>

Let's print out the 64-bit integer here as well.  64-bit integer support
may happen.


> +  else
> + fprintf(fp, "0x%08x /* %f */", instr->value.u32[i],
> instr->value.f32[i]);
> }
>
> fprintf(fp, ")");
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 07/29] nir/lower_tex: fix get_zero_or_one() to use sized types

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 3:39 PM, Jason Ekstrand 
wrote:

>
>
> On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
> sigles...@igalia.com> wrote:
>
>> From: Iago Toral Quiroga 
>>
>> v2 (Sam):
>> - Use helper to get type size from nir_alu_type enum.
>> ---
>>  src/compiler/nir/nir_lower_tex.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/compiler/nir/nir_lower_tex.c
>> b/src/compiler/nir/nir_lower_tex.c
>> index 4999603..a58385a 100644
>> --- a/src/compiler/nir/nir_lower_tex.c
>> +++ b/src/compiler/nir/nir_lower_tex.c
>> @@ -226,7 +226,8 @@ get_zero_or_one(nir_builder *b, nir_alu_type type,
>> uint8_t swizzle_val)
>>v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 0;
>> } else {
>>assert(swizzle_val == 5);
>> -  if (type == nir_type_float)
>> +  assert(nir_alu_type_get_type_size(type) < 64);
>> +  if (type == nir_type_float32)
>>
>
> This seems dangerious.  It switches a check from checking for float to
> checking for float32.  At the particular point in the git history where
> this patch lands, one of these checks is broken.  I'm guessing this
> actually breaks things that get fixed later when we switch glsl_to_nir to
> giving us sized types.
>
> If we're going to change tex instructions to use sized types, we need to
> do it all in one big patch and it will have to touch all three drivers
> again.
>

One more thought:  Tex instructions already have a bit size provided by the
destination so I don't see a need for having it be sized at all.  At the
end of the day it doesn't matter since we either don't have a size or we do
have a size and it's required to match.


>   v.f32[0] = v.f32[1] = v.f32[2] = v.f32[3] = 1.0;
>>else
>>   v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 1;
>> --
>> 2.5.0
>>
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Re: [Mesa-dev] [PATCH 09/29] program/nir: include bit-size information

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> ---
>  src/mesa/program/prog_to_nir.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/program/prog_to_nir.c
> b/src/mesa/program/prog_to_nir.c
> index 16b79c9..0eac73c 100644
> --- a/src/mesa/program/prog_to_nir.c
> +++ b/src/mesa/program/prog_to_nir.c
> @@ -596,7 +596,7 @@ ptn_tex(nir_builder *b, nir_alu_dest dest, nir_ssa_def
> **src,
>
> instr = nir_tex_instr_create(b->shader, num_srcs);
> instr->op = op;
> -   instr->dest_type = nir_type_float;
> +   instr->dest_type = nir_type_float32;
>

This needs to go in with 7 and 8.


> instr->is_shadow = prog_inst->TexShadow;
> instr->texture_index = prog_inst->TexSrcUnit;
> instr->sampler_index = prog_inst->TexSrcUnit;
> --
> 2.5.0
>
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Re: [Mesa-dev] tgsi_set_exec_mask?

2016-03-21 Thread Brian Paul 

On 03/21/2016 11:40 AM, Brian Paul wrote:

On 03/20/2016 08:08 PM, Dave Airlie wrote:

This appears to set some values into some temp register that we never
read from or look at again,

should it be setting something that ExecMask gets set to at machine
run time?

just noticed it while trying to work out the various mask for shader
images.


My recollection is that it's supposed to disable execution channels for
non-existant vertices.  For example, if we only have 3 vertices to
process, the 4th execution channel should be disabled.

But like you say, it doesn't seem to get used.  I could do a piglit run
with tgsi_set_exec_mask() nop'd and see what happens...


No regressions found with piglit.  Feel free to post a patch which 
removes it.


-Brian


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Re: [Mesa-dev] [PATCH 07/29] nir/lower_tex: fix get_zero_or_one() to use sized types

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> v2 (Sam):
> - Use helper to get type size from nir_alu_type enum.
> ---
>  src/compiler/nir/nir_lower_tex.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/compiler/nir/nir_lower_tex.c
> b/src/compiler/nir/nir_lower_tex.c
> index 4999603..a58385a 100644
> --- a/src/compiler/nir/nir_lower_tex.c
> +++ b/src/compiler/nir/nir_lower_tex.c
> @@ -226,7 +226,8 @@ get_zero_or_one(nir_builder *b, nir_alu_type type,
> uint8_t swizzle_val)
>v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 0;
> } else {
>assert(swizzle_val == 5);
> -  if (type == nir_type_float)
> +  assert(nir_alu_type_get_type_size(type) < 64);
> +  if (type == nir_type_float32)
>

This seems dangerious.  It switches a check from checking for float to
checking for float32.  At the particular point in the git history where
this patch lands, one of these checks is broken.  I'm guessing this
actually breaks things that get fixed later when we switch glsl_to_nir to
giving us sized types.

If we're going to change tex instructions to use sized types, we need to do
it all in one big patch and it will have to touch all three drivers again.


>   v.f32[0] = v.f32[1] = v.f32[2] = v.f32[3] = 1.0;
>else
>   v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 1;
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 05/29] nir/clone: clone bit_size in clone_load_const

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> ---
>  src/compiler/nir/nir_clone.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c
> index 7444dfe..b1da332 100644
> --- a/src/compiler/nir/nir_clone.c
> +++ b/src/compiler/nir/nir_clone.c
> @@ -354,6 +354,7 @@ clone_load_const(clone_state *state, const
> nir_load_const_instr *lc)
>
> memcpy(>value, >value, sizeof(nlc->value));
>
> +   nlc->def.bit_size = lc->def.bit_size;
>

Why not make nir_load_const_instr_create take a bit size?  That seems like
the better thing to do.  It would also guarantee that we got everything.


> add_remap(state, >def, >def);
>
> return nlc;
> --
> 2.5.0
>
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[Mesa-dev] [PATCH 3/8] tgsi: introduce NonHelperMask

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

This is a mask of which of the current 2x2 grid are non-helper
invocations. This allows us to mask off the helper invocations
later for the image operations.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 ++
 src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c 
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index a44a05c..fa1c916 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -5199,6 +5199,8 @@ tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
   default_mask = 0x1;
}
 
+   if (mach->NonHelperMask == 0)
+  mach->NonHelperMask = default_mask;
mach->CondMask = default_mask;
mach->LoopMask = default_mask;
mach->ContMask = default_mask;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 011c9c3..05ae388 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -317,6 +317,8 @@ struct tgsi_exec_machine
struct tgsi_exec_vector   QuadPos;
float Face;/**< +1 if front facing, -1 if back 
facing */
bool  flatshade_color;
+
+   uint NonHelperMask;  /**< non-helpers */
/* Conditional execution masks */
uint CondMask;  /**< For IF/ELSE/ENDIF */
uint LoopMask;  /**< For BGNLOOP/ENDLOOP */
-- 
2.5.0

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[Mesa-dev] [PATCH 4/8] softpipe: add support for explicit early depth testing

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

ARB_shader_image_load_store adds support for explicit early
depth testing. However we need to make sure we don't overwrite
values using the shader written values in this case.

This fixes early depth testing in softpipe to conform with
those requirements.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/softpipe/sp_context.h |  2 ++
 src/gallium/drivers/softpipe/sp_fs_exec.c | 16 ++--
 src/gallium/drivers/softpipe/sp_quad_depth_test.c |  4 ++--
 src/gallium/drivers/softpipe/sp_quad_fs.c |  2 +-
 src/gallium/drivers/softpipe/sp_quad_pipe.c   |  6 --
 src/gallium/drivers/softpipe/sp_state.h   |  3 ++-
 6 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/softpipe/sp_context.h 
b/src/gallium/drivers/softpipe/sp_context.h
index d5c4aaa..d18bbe6 100644
--- a/src/gallium/drivers/softpipe/sp_context.h
+++ b/src/gallium/drivers/softpipe/sp_context.h
@@ -175,6 +175,8 @@ struct softpipe_context {
} tgsi;
 
struct tgsi_exec_machine *fs_machine;
+   /** whether early depth testing is enabled */
+   bool early_depth;
 
/** The primitive drawing context */
struct draw_context *draw;
diff --git a/src/gallium/drivers/softpipe/sp_fs_exec.c 
b/src/gallium/drivers/softpipe/sp_fs_exec.c
index 8941177..e2d527d 100644
--- a/src/gallium/drivers/softpipe/sp_fs_exec.c
+++ b/src/gallium/drivers/softpipe/sp_fs_exec.c
@@ -116,7 +116,8 @@ setup_pos_vector(const struct tgsi_interp_coef *coef,
 static unsigned 
 exec_run( const struct sp_fragment_shader_variant *var,
  struct tgsi_exec_machine *machine,
- struct quad_header *quad )
+ struct quad_header *quad,
+ bool early_depth_test )
 {
/* Compute X, Y, Z, W vals for this quad */
setup_pos_vector(quad->posCoef, 
@@ -155,16 +156,19 @@ exec_run( const struct sp_fragment_shader_variant *var,
 {
uint j;
 
-   for (j = 0; j < 4; j++)
-  quad->output.depth[j] = machine->Outputs[i].xyzw[2].f[j];
+   if (!early_depth_test) {
+  for (j = 0; j < 4; j++)
+ quad->output.depth[j] = machine->Outputs[i].xyzw[2].f[j];
+   }
 }
 break;
  case TGSI_SEMANTIC_STENCIL:
 {
uint j;
-
-   for (j = 0; j < 4; j++)
-  quad->output.stencil[j] = 
(unsigned)machine->Outputs[i].xyzw[1].u[j];
+   if (!early_depth_test) {
+  for (j = 0; j < 4; j++)
+ quad->output.stencil[j] = 
(unsigned)machine->Outputs[i].xyzw[1].u[j];
+   }
 }
 break;
  }
diff --git a/src/gallium/drivers/softpipe/sp_quad_depth_test.c 
b/src/gallium/drivers/softpipe/sp_quad_depth_test.c
index 4cce9e9..847a616 100644
--- a/src/gallium/drivers/softpipe/sp_quad_depth_test.c
+++ b/src/gallium/drivers/softpipe/sp_quad_depth_test.c
@@ -782,7 +782,7 @@ depth_test_quads_fallback(struct quad_stage *qs,
 {
unsigned i, pass = 0;
const struct tgsi_shader_info *fsInfo = >softpipe->fs_variant->info;
-   boolean interp_depth = !fsInfo->writes_z;
+   boolean interp_depth = !fsInfo->writes_z || qs->softpipe->early_depth;
boolean shader_stencil_ref = fsInfo->writes_stencil;
struct depth_data data;
unsigned vp_idx = quads[0]->input.viewport_index;
@@ -902,7 +902,7 @@ choose_depth_test(struct quad_stage *qs,
 {
const struct tgsi_shader_info *fsInfo = >softpipe->fs_variant->info;
 
-   boolean interp_depth = !fsInfo->writes_z;
+   boolean interp_depth = !fsInfo->writes_z || qs->softpipe->early_depth;
 
boolean alpha = qs->softpipe->depth_stencil->alpha.enabled;
 
diff --git a/src/gallium/drivers/softpipe/sp_quad_fs.c 
b/src/gallium/drivers/softpipe/sp_quad_fs.c
index 395bc70..8fb632d 100644
--- a/src/gallium/drivers/softpipe/sp_quad_fs.c
+++ b/src/gallium/drivers/softpipe/sp_quad_fs.c
@@ -80,7 +80,7 @@ shade_quad(struct quad_stage *qs, struct quad_header *quad)
 
/* run shader */
machine->flatshade_color = softpipe->rasterizer->flatshade ? TRUE : FALSE;
-   return softpipe->fs_variant->run( softpipe->fs_variant, machine, quad );
+   return softpipe->fs_variant->run( softpipe->fs_variant, machine, quad, 
softpipe->early_depth );
 }
 
 
diff --git a/src/gallium/drivers/softpipe/sp_quad_pipe.c 
b/src/gallium/drivers/softpipe/sp_quad_pipe.c
index 7131512..dbe4c0e 100644
--- a/src/gallium/drivers/softpipe/sp_quad_pipe.c
+++ b/src/gallium/drivers/softpipe/sp_quad_pipe.c
@@ -43,15 +43,17 @@ void
 sp_build_quad_pipeline(struct softpipe_context *sp)
 {
boolean early_depth_test =
-  sp->depth_stencil->depth.enabled &&
+  (sp->depth_stencil->depth.enabled &&
   sp->framebuffer.zsbuf &&
   !sp->depth_stencil->alpha.enabled &&
   !sp->fs_variant->info.uses_kill &&
   !sp->fs_variant->info.writes_z &&
-

[Mesa-dev] [PATCH 7/8] softpipe: add image support to softpipe

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

This adds support for ARB_shader_image_load_store to softpipe.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/tgsi/tgsi_exec.h  |   4 +-
 src/gallium/drivers/softpipe/Makefile.sources   |   2 +
 src/gallium/drivers/softpipe/sp_context.c   |  20 +-
 src/gallium/drivers/softpipe/sp_context.h   |   2 +
 src/gallium/drivers/softpipe/sp_flush.c |  26 +
 src/gallium/drivers/softpipe/sp_flush.h |   2 +
 src/gallium/drivers/softpipe/sp_fs_exec.c   |   6 +-
 src/gallium/drivers/softpipe/sp_image.c | 643 
 src/gallium/drivers/softpipe/sp_image.h |  37 ++
 src/gallium/drivers/softpipe/sp_state.h |   7 +-
 src/gallium/drivers/softpipe/sp_state_derived.c |   3 +-
 src/gallium/drivers/softpipe/sp_state_image.c   |  57 +++
 src/gallium/drivers/softpipe/sp_texture.c   |   8 +-
 src/gallium/drivers/softpipe/sp_texture.h   |   4 +-
 14 files changed, 809 insertions(+), 12 deletions(-)
 create mode 100644 src/gallium/drivers/softpipe/sp_image.c
 create mode 100644 src/gallium/drivers/softpipe/sp_image.h
 create mode 100644 src/gallium/drivers/softpipe/sp_state_image.c

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 9ff8a72..99051ed 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -518,8 +518,10 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
-   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
   return 0;
+   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+  return PIPE_MAX_SHADER_IMAGES;
+
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
   return 32;
}
diff --git a/src/gallium/drivers/softpipe/Makefile.sources 
b/src/gallium/drivers/softpipe/Makefile.sources
index 2af3d6a..efe8846 100644
--- a/src/gallium/drivers/softpipe/Makefile.sources
+++ b/src/gallium/drivers/softpipe/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
sp_flush.h \
sp_fs_exec.c \
sp_fs.h \
+   sp_image.c \
sp_limits.h \
sp_prim_vbuf.c \
sp_prim_vbuf.h \
@@ -31,6 +32,7 @@ C_SOURCES := \
sp_state_blend.c \
sp_state_clip.c \
sp_state_derived.c \
+   sp_state_image.c \
sp_state.h \
sp_state_rasterizer.c \
sp_state_sampler.c \
diff --git a/src/gallium/drivers/softpipe/sp_context.c 
b/src/gallium/drivers/softpipe/sp_context.c
index d2a3220..30b0276 100644
--- a/src/gallium/drivers/softpipe/sp_context.c
+++ b/src/gallium/drivers/softpipe/sp_context.c
@@ -50,7 +50,7 @@
 #include "sp_query.h"
 #include "sp_screen.h"
 #include "sp_tex_sample.h"
-
+#include "sp_image.h"
 
 static void
 softpipe_destroy( struct pipe_context *pipe )
@@ -199,6 +199,10 @@ softpipe_create_context(struct pipe_screen *screen,
   softpipe->tgsi.sampler[i] = sp_create_tgsi_sampler();
}
 
+   for (i = 0; i < PIPE_SHADER_TYPES; i++) {
+  softpipe->tgsi.image[i] = sp_create_tgsi_image();
+   }
+
softpipe->dump_fs = debug_get_bool_option( "SOFTPIPE_DUMP_FS", FALSE );
softpipe->dump_gs = debug_get_bool_option( "SOFTPIPE_DUMP_GS", FALSE );
 
@@ -216,6 +220,7 @@ softpipe_create_context(struct pipe_screen *screen,
softpipe_init_streamout_funcs(>pipe);
softpipe_init_texture_funcs( >pipe );
softpipe_init_vertex_funcs(>pipe);
+   softpipe_init_image_funcs(>pipe);
 
softpipe->pipe.set_framebuffer_state = softpipe_set_framebuffer_state;
 
@@ -223,7 +228,8 @@ softpipe_create_context(struct pipe_screen *screen,
 
softpipe->pipe.clear = softpipe_clear;
softpipe->pipe.flush = softpipe_flush_wrapped;
-
+   softpipe->pipe.texture_barrier = softpipe_texture_barrier;
+   softpipe->pipe.memory_barrier = softpipe_memory_barrier;
softpipe->pipe.render_condition = softpipe_render_condition;

/*
@@ -272,6 +278,16 @@ softpipe_create_context(struct pipe_screen *screen,
 (struct tgsi_sampler *)
softpipe->tgsi.sampler[PIPE_SHADER_GEOMETRY]);
 
+   draw_image(softpipe->draw,
+  PIPE_SHADER_VERTEX,
+  (struct tgsi_image *)
+  softpipe->tgsi.image[PIPE_SHADER_VERTEX]);
+
+   draw_image(softpipe->draw,
+  PIPE_SHADER_GEOMETRY,
+  (struct tgsi_image *)
+  softpipe->tgsi.image[PIPE_SHADER_GEOMETRY]);
+
if (debug_get_bool_option( "SOFTPIPE_NO_RAST", FALSE ))
   softpipe->no_rast = TRUE;
 
diff --git a/src/gallium/drivers/softpipe/sp_context.h 
b/src/gallium/drivers/softpipe/sp_context.h
index d18bbe6..20a1235 100644
--- a/src/gallium/drivers/softpipe/sp_context.h
+++ b/src/gallium/drivers/softpipe/sp_context.h
@@ -83,6 +83,7 @@ struct softpipe_context {
struct pipe_scissor_state scissors[PIPE_MAX_VIEWPORTS];
struct

[Mesa-dev] [PATCH 6/8] draw: add support for passing images to vs/gs shaders.

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

This just adds support for passing through images to the
tgsi execution stage.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/draw/draw_context.c | 18 ++
 src/gallium/auxiliary/draw/draw_context.h |  6 ++
 src/gallium/auxiliary/draw/draw_gs.c  |  2 +-
 src/gallium/auxiliary/draw/draw_private.h |  3 +++
 src/gallium/auxiliary/draw/draw_vs_exec.c |  2 +-
 5 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_context.c 
b/src/gallium/auxiliary/draw/draw_context.c
index 16a261c..2ba9b09 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -731,6 +731,24 @@ draw_texture_sampler(struct draw_context *draw,
}
 }
 
+/**
+ * Provide TGSI image objects for vertex/geometry shaders that use
+ * texture fetches.  This state only needs to be set once per context.
+ * This might only be used by software drivers for the time being.
+ */
+void
+draw_image(struct draw_context *draw,
+   uint shader,
+   struct tgsi_image *image)
+{
+   if (shader == PIPE_SHADER_VERTEX) {
+  draw->vs.tgsi.image = image;
+   } else {
+  debug_assert(shader == PIPE_SHADER_GEOMETRY);
+  draw->gs.tgsi.image = image;
+   }
+}
+
 
 
 
diff --git a/src/gallium/auxiliary/draw/draw_context.h 
b/src/gallium/auxiliary/draw/draw_context.h
index a5a6df5..5d9870b 100644
--- a/src/gallium/auxiliary/draw/draw_context.h
+++ b/src/gallium/auxiliary/draw/draw_context.h
@@ -48,6 +48,7 @@ struct draw_vertex_shader;
 struct draw_geometry_shader;
 struct draw_fragment_shader;
 struct tgsi_sampler;
+struct tgsi_image;
 
 /*
  * structure to contain driver internal information 
@@ -155,6 +156,11 @@ draw_texture_sampler(struct draw_context *draw,
  struct tgsi_sampler *sampler);
 
 void
+draw_image(struct draw_context *draw,
+   uint shader_type,
+   struct tgsi_image *image);
+
+void
 draw_set_sampler_views(struct draw_context *draw,
unsigned shader_stage,
struct pipe_sampler_view **views,
diff --git a/src/gallium/auxiliary/draw/draw_gs.c 
b/src/gallium/auxiliary/draw/draw_gs.c
index c4ced9f..08d8bec 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -687,7 +687,7 @@ void draw_geometry_shader_prepare(struct 
draw_geometry_shader *shader,
if (!use_llvm && shader && shader->machine->Tokens != shader->state.tokens) 
{
   tgsi_exec_machine_bind_shader(shader->machine,
 shader->state.tokens,
-draw->gs.tgsi.sampler, NULL);
+draw->gs.tgsi.sampler, 
draw->gs.tgsi.image);
}
 }
 
diff --git a/src/gallium/auxiliary/draw/draw_private.h 
b/src/gallium/auxiliary/draw/draw_private.h
index 8774beb..211bd6f 100644
--- a/src/gallium/auxiliary/draw/draw_private.h
+++ b/src/gallium/auxiliary/draw/draw_private.h
@@ -66,6 +66,7 @@ struct draw_stage;
 struct vbuf_render;
 struct tgsi_exec_machine;
 struct tgsi_sampler;
+struct tgsi_image;
 struct draw_pt_front_end;
 struct draw_assembler;
 struct draw_llvm;
@@ -267,6 +268,7 @@ struct draw_context
  struct tgsi_exec_machine *machine;
 
  struct tgsi_sampler *sampler;
+ struct tgsi_image *image;
   } tgsi;
 
   struct translate *fetch;
@@ -286,6 +288,7 @@ struct draw_context
  struct tgsi_exec_machine *machine;
 
  struct tgsi_sampler *sampler;
+ struct tgsi_image *image;
   } tgsi;
 
} gs;
diff --git a/src/gallium/auxiliary/draw/draw_vs_exec.c 
b/src/gallium/auxiliary/draw/draw_vs_exec.c
index 8c759d4..bbf5228 100644
--- a/src/gallium/auxiliary/draw/draw_vs_exec.c
+++ b/src/gallium/auxiliary/draw/draw_vs_exec.c
@@ -70,7 +70,7 @@ vs_exec_prepare( struct draw_vertex_shader *shader,
if (evs->machine->Tokens != shader->state.tokens) {
   tgsi_exec_machine_bind_shader(evs->machine,
 shader->state.tokens,
-draw->vs.tgsi.sampler, NULL);
+draw->vs.tgsi.sampler, 
draw->vs.tgsi.image);
}
 }
 
-- 
2.5.0

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[Mesa-dev] [PATCH 8/8] docs: update softpipe status for shader_image_load_store.

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 docs/GL3.txt  | 2 +-
 docs/relnotes/11.3.0.html | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 89cc662..f573c87 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -154,7 +154,7 @@ GL 4.2, GLSL 4.20:
   GL_ARB_texture_storageDONE (all drivers)
   GL_ARB_transform_feedback_instanced   DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_base_instance  DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, softpipe)
-  GL_ARB_shader_image_load_storeDONE (i965, radeonsi)
+  GL_ARB_shader_image_load_storeDONE (i965, radeonsi, 
softpipe)
   GL_ARB_conservative_depth DONE (all drivers that 
support GLSL 1.30)
   GL_ARB_shading_language_420pack   DONE (all drivers that 
support GLSL 1.30)
   GL_ARB_shading_language_packing   DONE (all drivers)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 04564a8..d24240b 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -46,7 +46,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 GL_ARB_internalformat_query2 on i965
 GL_ARB_shader_atomic_counter_ops on nvc0
-GL_ARB_shader_image_load_store on radeonsi
+GL_ARB_shader_image_load_store on radeonsi, softpipe
 GL_ARB_shader_image_size on radeonsi
 GL_OES_texture_border_clamp and GL_EXT_texture_border_clamp on all drivers 
that support GL_ARB_texture_border_clamp
 GL_OES_shader_image_atomic on all drivers that support 
GL_ARB_shader_image_load_store
-- 
2.5.0

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[Mesa-dev] [PATCH 5/8] tgsi: add support for image operations to tgsi_exec.

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

This adds support for load/store/atomic operations on images
along with image tracking support.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/draw/draw_gs.c  |   2 +-
 src/gallium/auxiliary/draw/draw_vs_exec.c |   2 +-
 src/gallium/auxiliary/tgsi/tgsi_exec.c| 229 +-
 src/gallium/auxiliary/tgsi/tgsi_exec.h|  40 +-
 src/gallium/drivers/softpipe/sp_fs_exec.c |   4 +-
 5 files changed, 271 insertions(+), 6 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_gs.c 
b/src/gallium/auxiliary/draw/draw_gs.c
index 6b33341..c4ced9f 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -687,7 +687,7 @@ void draw_geometry_shader_prepare(struct 
draw_geometry_shader *shader,
if (!use_llvm && shader && shader->machine->Tokens != shader->state.tokens) 
{
   tgsi_exec_machine_bind_shader(shader->machine,
 shader->state.tokens,
-draw->gs.tgsi.sampler);
+draw->gs.tgsi.sampler, NULL);
}
 }
 
diff --git a/src/gallium/auxiliary/draw/draw_vs_exec.c 
b/src/gallium/auxiliary/draw/draw_vs_exec.c
index abd64f5..8c759d4 100644
--- a/src/gallium/auxiliary/draw/draw_vs_exec.c
+++ b/src/gallium/auxiliary/draw/draw_vs_exec.c
@@ -70,7 +70,7 @@ vs_exec_prepare( struct draw_vertex_shader *shader,
if (evs->machine->Tokens != shader->state.tokens) {
   tgsi_exec_machine_bind_shader(evs->machine,
 shader->state.tokens,
-draw->vs.tgsi.sampler);
+draw->vs.tgsi.sampler, NULL);
}
 }
 
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c 
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index fa1c916..fe82a95 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -853,7 +853,8 @@ void
 tgsi_exec_machine_bind_shader(
struct tgsi_exec_machine *mach,
const struct tgsi_token *tokens,
-   struct tgsi_sampler *sampler)
+   struct tgsi_sampler *sampler,
+   struct tgsi_image *image)
 {
uint k;
struct tgsi_parse_context parse;
@@ -871,6 +872,7 @@ tgsi_exec_machine_bind_shader(
 
mach->Tokens = tokens;
mach->Sampler = sampler;
+   mach->Image = image;
 
if (!tokens) {
   /* unbind and free all */
@@ -3706,6 +3708,206 @@ exec_dfracexp(struct tgsi_exec_machine *mach,
}
 }
 
+static int
+get_image_coord_dim(int tgsi_tex, int *sample)
+{
+   int dim;
+   switch (tgsi_tex) {
+   case TGSI_TEXTURE_BUFFER:
+   case TGSI_TEXTURE_1D:
+  dim = 1;
+  break;
+   case TGSI_TEXTURE_2D:
+   case TGSI_TEXTURE_RECT:
+   case TGSI_TEXTURE_1D_ARRAY:
+   case TGSI_TEXTURE_2D_MSAA:
+  dim = 2;
+  break;
+   case TGSI_TEXTURE_3D:
+   case TGSI_TEXTURE_CUBE:
+   case TGSI_TEXTURE_2D_ARRAY:
+   case TGSI_TEXTURE_2D_ARRAY_MSAA:
+   case TGSI_TEXTURE_CUBE_ARRAY:
+  dim = 3;
+  break;
+   default:
+  assert(!"unknown texture target");
+  dim = 0;
+  break;
+   }
+
+   if (sample) {
+  switch (tgsi_tex) {
+  case TGSI_TEXTURE_2D_MSAA:
+ *sample = 3;
+ break;
+  case TGSI_TEXTURE_2D_ARRAY_MSAA:
+ *sample = 4;
+ break;
+  default:
+ *sample = 0;
+ break;
+  }
+   }
+   return dim;
+}
+
+static void
+exec_load(struct tgsi_exec_machine *mach,
+  const struct tgsi_full_instruction *inst)
+{
+   union tgsi_exec_channel r[4], sample_r;
+   uint unit;
+   int sample;
+   int i, j;
+   int dim;
+   uint chan;
+   float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
+   struct tgsi_image_params params;
+   int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
+
+   unit = fetch_sampler_unit(mach, inst, 0);
+   dim = get_image_coord_dim(inst->Memory.Texture, );
+   assert(dim <= 3);
+
+   params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
+   params.unit = unit;
+   params.tgsi_tex_instr = inst->Memory.Texture;
+   params.format = inst->Memory.Format;
+
+   for (i = 0; i < dim; i++) {
+  IFETCH([i], 1, TGSI_CHAN_X + i);
+   }
+
+   if (sample)
+  IFETCH(_r, 1, TGSI_CHAN_X + sample);
+
+   mach->Image->load(mach->Image, ,
+ r[0].i, r[1].i, r[2].i, sample_r.i,
+ rgba);
+   for (j = 0; j < TGSI_QUAD_SIZE; j++) {
+  r[0].f[j] = rgba[0][j];
+  r[1].f[j] = rgba[1][j];
+  r[2].f[j] = rgba[2][j];
+  r[3].f[j] = rgba[3][j];
+   }
+   for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+  if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
+ store_dest(mach, [chan], >Dst[0], inst, chan, 
TGSI_EXEC_DATA_FLOAT);
+  }
+   }
+}
+
+static void
+exec_store(struct tgsi_exec_machine *mach,
+   const struct tgsi_full_instruction *inst)
+{
+   union tgsi_exec_channel r[3], sample_r;
+   union tgsi_exec_channel value[4];
+

[Mesa-dev] [PATCH 1/8] tgsi_exec: add support for up to 3 array registers

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/tgsi/tgsi_exec.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 12a6875..011c9c3 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -205,12 +205,14 @@ struct tgsi_sampler
 #define TGSI_EXEC_NUM_TEMP_R4
 
 #define TGSI_EXEC_TEMP_ADDR (TGSI_EXEC_NUM_TEMPS + 8)
+#define TGSI_EXEC_TEMP_ADDR1(TGSI_EXEC_NUM_TEMPS + 9)
+#define TGSI_EXEC_TEMP_ADDR2(TGSI_EXEC_NUM_TEMPS + 10)
 
 /* predicate register */
-#define TGSI_EXEC_TEMP_P0   (TGSI_EXEC_NUM_TEMPS + 9)
+#define TGSI_EXEC_TEMP_P0   (TGSI_EXEC_NUM_TEMPS + 11)
 #define TGSI_EXEC_NUM_PREDS 1
 
-#define TGSI_EXEC_NUM_TEMP_EXTRAS   10
+#define TGSI_EXEC_NUM_TEMP_EXTRAS   12
 
 
 
-- 
2.5.0

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[Mesa-dev] [PATCH 2/8] tgsi_exec: handle execmask when doing indirect lookups

2016-03-21 Thread Dave Airlie 
From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/tgsi/tgsi_exec.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c 
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 126259f..a44a05c 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -1995,11 +1995,11 @@ fetch_sampler_unit(struct tgsi_exec_machine *mach,
uint sampler)
 {
uint unit;
-
+   int i;
if (inst->Src[sampler].Register.Indirect) {
   const struct tgsi_full_src_register *reg = >Src[sampler];
   union tgsi_exec_channel indir_index, index2;
-
+  const uint execmask = mach->ExecMask;
   index2.i[0] =
   index2.i[1] =
   index2.i[2] =
@@ -2012,7 +2012,13 @@ fetch_sampler_unit(struct tgsi_exec_machine *mach,
  ,
  ,
  _index);
-  unit = inst->Src[sampler].Register.Index + indir_index.i[0];
+  for (i = 0; i < TGSI_QUAD_SIZE; i++) {
+ if (execmask & (1 << i)) {
+unit = inst->Src[sampler].Register.Index + indir_index.i[i];
+break;
+ }
+  }
+
} else {
   unit = inst->Src[sampler].Register.Index;
}
-- 
2.5.0

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[Mesa-dev] softpipe ARB_shader_image_load_store support

2016-03-21 Thread Dave Airlie 
I just felt like writing this as part learning, part Vulkan needs
images so my hacks on softpipe needs them.

It passes all the piglit tests.

Dave.

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Re: [Mesa-dev] [PATCH 07/12] i965/peephole_ffma: Don't fuse exact adds

2016-03-21 Thread Francisco Jerez 
Jason Ekstrand  writes:

> ---
>  src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c 
> b/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c
> index 5ff2cba..3c1e27f 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c
> @@ -168,7 +168,9 @@ brw_nir_opt_peephole_ffma_block(nir_block *block, void 
> *void_state)
>if (add->op != nir_op_fadd)
>   continue;
>  
> -  /* TODO: Maybe bail if this expression is considered "precise"? */
> +  assert(add->dest.dest.is_ssa);
> +  if (add->exact)
> + continue;

Reviewed-by: Francisco Jerez 

>  
>assert(add->src[0].src.is_ssa && add->src[1].src.is_ssa);
>  
> -- 
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 06/12] nir/cse: Properly handle nir_ssa_def.exact

2016-03-21 Thread Francisco Jerez 
Jason Ekstrand  writes:

> ---
>  src/compiler/nir/nir_instr_set.c | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/nir_instr_set.c 
> b/src/compiler/nir/nir_instr_set.c
> index 159ded0..00e4784 100644
> --- a/src/compiler/nir/nir_instr_set.c
> +++ b/src/compiler/nir/nir_instr_set.c
> @@ -52,6 +52,7 @@ hash_alu(uint32_t hash, const nir_alu_instr *instr)
>  {
> hash = HASH(hash, instr->op);
> hash = HASH(hash, instr->dest.dest.ssa.num_components);
> +   /* We explicitly don't hash instr->dest.dest.exact */
>  
> if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_COMMUTATIVE) 
> {
>assert(nir_op_infos[instr->op].num_inputs == 2);
> @@ -267,6 +268,8 @@ nir_instrs_equal(const nir_instr *instr1, const nir_instr 
> *instr2)
>if (alu1->dest.dest.ssa.num_components != 
> alu2->dest.dest.ssa.num_components)
>   return false;
>  
> +  /* We explicitly don't hash instr->dest.dest.exact */
> +
>if (nir_op_infos[alu1->op].algebraic_properties & 
> NIR_OP_IS_COMMUTATIVE) {
>   assert(nir_op_infos[alu1->op].num_inputs == 2);
>   return (nir_alu_srcs_equal(alu1, alu2, 0, 0) &&
> @@ -496,8 +499,17 @@ nir_instr_set_add_or_rewrite(struct set *instr_set, 
> nir_instr *instr)
> struct set_entry *entry = _mesa_set_search(instr_set, instr);
> if (entry) {
>nir_ssa_def *def = nir_instr_get_dest_ssa_def(instr);
> -  nir_ssa_def *new_def =
> - nir_instr_get_dest_ssa_def((nir_instr *) entry->key);
> +  nir_instr *match = (nir_instr *) entry->key;
> +  nir_ssa_def *new_def = nir_instr_get_dest_ssa_def(match);
> +
> +  /* It's safe to replace a exact instruction with an inexact one as
> +   * long as we make it exact.  If we got here, the two instructions are
> +   * exactly identical in every other way so, once we've set the exact
> +   * bit, they are the same.
> +   */
> +  if (instr->type == nir_instr_type_alu && 
> nir_instr_as_alu(instr)->exact)
> + nir_instr_as_alu(match)->exact = true;
> +

Reviewed-by: Francisco Jerez 

>nir_ssa_def_rewrite_uses(def, nir_src_for_ssa(new_def));
>return true;
> }
> -- 
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 10/12] glsl/opt_algebraic: Don't handle invariant or precise trees

2016-03-21 Thread Francisco Jerez 
Jason Ekstrand  writes:

> ---
>  src/compiler/glsl/opt_algebraic.cpp | 16 
>  1 file changed, 16 insertions(+)
>
> diff --git a/src/compiler/glsl/opt_algebraic.cpp 
> b/src/compiler/glsl/opt_algebraic.cpp
> index 1e58062..2fea240 100644
> --- a/src/compiler/glsl/opt_algebraic.cpp
> +++ b/src/compiler/glsl/opt_algebraic.cpp
> @@ -58,6 +58,8 @@ public:
> {
> }
>  
> +   virtual ir_visitor_status visit_enter(ir_assignment *ir);
> +
> ir_rvalue *handle_expression(ir_expression *ir);
> void handle_rvalue(ir_rvalue **rvalue);
> bool reassociate_constant(ir_expression *ir1,
> @@ -80,6 +82,20 @@ public:
>  
>  } /* unnamed namespace */
>  
> +ir_visitor_status
> +ir_algebraic_visitor::visit_enter(ir_assignment *ir)
> +{
> +   ir_variable *var = ir->lhs->variable_referenced();
> +   if (var->data.invariant || var->data.precise) {
> +  /* If we're assigning to an invariant or precise variable, just bail.
> +   * Most of the algebraic optimizations aren't precision-safe.

Could you add something like the following to this comment:

| * FINISHME -- Find out which optimizations are precision-safe
| * and enable then only for invariant or precise trees.

With that change:

Reviewed-by: Francisco Jerez 

> +   */
> +  return visit_continue_with_parent;
> +   } else {
> +  return visit_continue;
> +   }
> +}
> +
>  static inline bool
>  is_vec_zero(ir_constant *ir)
>  {
> -- 
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH] i965: Fix assert conditions for src/dst x/y offsets

2016-03-21 Thread Kenneth Graunke 
On Monday, March 21, 2016 11:33:46 AM PDT Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/intel_copy_image.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c b/src/mesa/
drivers/dri/i965/intel_copy_image.c
> index 08b7623..ccb82b6 100644
> --- a/src/mesa/drivers/dri/i965/intel_copy_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
> @@ -140,9 +140,9 @@ copy_image_with_memcpy(struct brw_context *brw,
> _mesa_get_format_block_size(src_mt->format, _bw, _bh);
>  
> assert(src_width % src_bw == 0);
> -   assert(src_height % src_bw == 0);
> +   assert(src_height % src_bh == 0);
> assert(src_x % src_bw == 0);
> -   assert(src_y % src_bw == 0);
> +   assert(src_y % src_bh == 0);
>  
> /* If we are on the same miptree, same level, and same slice, then
>  * intel_miptree_map won't let us map it twice.  We have to do things a
> @@ -153,7 +153,7 @@ copy_image_with_memcpy(struct brw_context *brw,
>  
> if (same_slice) {
>assert(dst_x % src_bw == 0);
> -  assert(dst_y % src_bw == 0);
> +  assert(dst_y % src_bh == 0);
>  
>map_x1 = MIN2(src_x, dst_x);
>map_y1 = MIN2(src_y, dst_y);
> 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] tgsi_set_exec_mask?

2016-03-21 Thread Brian Paul 

On 03/20/2016 08:08 PM, Dave Airlie wrote:

This appears to set some values into some temp register that we never
read from or look at again,

should it be setting something that ExecMask gets set to at machine run time?

just noticed it while trying to work out the various mask for shader images.


My recollection is that it's supposed to disable execution channels for 
non-existant vertices.  For example, if we only have 3 vertices to 
process, the 4th execution channel should be disabled.


But like you say, it doesn't seem to get used.  I could do a piglit run 
with tgsi_set_exec_mask() nop'd and see what happens...


-Brian

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Re: [Mesa-dev] [PATCH 03/29] nir/vars_to_ssa: adapt to different bit sizes

2016-03-21 Thread Jason Ekstrand 
On Mon, Mar 21, 2016 at 5:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Connor Abbott 
>
> v2 (Sam):
> - Keep using nir_op_imov when calling nir_alu_instr_create() at
> rename_variables_block(). nir_op_fmov is not needed anymore.
>
> Signed-off-by: Samuel Iglesias Gonsálvez 
> ---
>  src/compiler/nir/nir_lower_vars_to_ssa.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
> b/src/compiler/nir/nir_lower_vars_to_ssa.c
> index 2331791..511662e 100644
> --- a/src/compiler/nir/nir_lower_vars_to_ssa.c
> +++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
> @@ -543,6 +543,8 @@ get_ssa_def_for_block(struct deref_node *node,
> nir_block *block,
> nir_ssa_undef_instr *undef =
>nir_ssa_undef_instr_create(state->shader,
>   glsl_get_vector_elements(node->type));
> +   undef->def.bit_size =
> +  glsl_get_bit_size(glsl_get_base_type(node->type));
>

Can we instead make nir_ssa_undef_instr_create take a bit size?  That seems
better than setting it manually.  We probably want to do the same for
load_cons.


> nir_instr_insert_before_cf_list(>impl->body, >instr);
> def_stack_push(node, >def, state);
> return >def;
> @@ -627,6 +629,7 @@ rename_variables_block(nir_block *block, struct
> lower_variables_state *state)
> nir_ssa_undef_instr *undef =
>nir_ssa_undef_instr_create(state->shader,
>   intrin->num_components);
> +   undef->def.bit_size = intrin->dest.ssa.bit_size;
>
> nir_instr_insert_before(>instr, >instr);
> nir_instr_remove(>instr);
> --
> 2.5.0
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Re: [Mesa-dev] [PATCH 11/11] svga: use shader sampler view declarations

2016-03-21 Thread Charmaine Lee 

Series looks good to me.

Reviewed-by: Charmaine Lee 

From: Brian Paul 
Sent: Friday, March 18, 2016 4:49 PM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee
Subject: [PATCH 11/11] svga: use shader sampler view declarations

Previously, we looked at the bound textures (via the pipe_sampler_views)
to determine texture dimensions (1D/2D/3D/etc) and datatype (float vs.
int).  But this could fail in out of memory conditions.  If we failed to
allocate a texture and didn't create a pipe_sampler_view, we'd default
to using 0 (PIPE_BUFFER) as the texture type.  This led to device errors
because of inconsistent shader code.

This change relies on all TGSI shaders having an SVIEW declaration for
each SAMP declaration.  The previous patch series does that.
---
 src/gallium/drivers/svga/svga_shader.c | 16 +++---
 src/gallium/drivers/svga/svga_shader.h |  3 +-
 src/gallium/drivers/svga/svga_tgsi_decl_sm30.c | 20 +--
 src/gallium/drivers/svga/svga_tgsi_emit.h  |  2 +
 src/gallium/drivers/svga/svga_tgsi_insn.c  |  2 +-
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c| 78 --
 6 files changed, 74 insertions(+), 47 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_shader.c 
b/src/gallium/drivers/svga/svga_shader.c
index 5c99e16..78eb3f6 100644
--- a/src/gallium/drivers/svga/svga_shader.c
+++ b/src/gallium/drivers/svga/svga_shader.c
@@ -180,18 +180,18 @@ svga_init_shader_key_common(const struct svga_context 
*svga, unsigned shader,
  assert(view->texture);
  assert(view->texture->target < (1 << 4)); /* texture_target:4 */

- key->tex[i].texture_target = view->texture->target;
-
  /* 1D/2D array textures with one slice are treated as non-arrays
   * by the SVGA3D device.  Convert the texture type here so that
   * we emit the right TEX/SAMPLE instruction in the shader.
   */
- if (view->texture->array_size == 1) {
-if (view->texture->target == PIPE_TEXTURE_1D_ARRAY) {
-   key->tex[i].texture_target = PIPE_TEXTURE_1D;
+ if (view->texture->target == PIPE_TEXTURE_1D_ARRAY ||
+ view->texture->target == PIPE_TEXTURE_2D_ARRAY) {
+if (view->texture->array_size == 1) {
+   key->tex[i].is_array = 0;
 }
-else if (view->texture->target == PIPE_TEXTURE_2D_ARRAY) {
-   key->tex[i].texture_target = PIPE_TEXTURE_2D;
+else {
+   assert(view->texture->array_size > 1);
+   key->tex[i].is_array = 1;
 }
  }

@@ -207,8 +207,6 @@ svga_init_shader_key_common(const struct svga_context 
*svga, unsigned shader,
  key->tex[i].swizzle_g = view->swizzle_g;
  key->tex[i].swizzle_b = view->swizzle_b;
  key->tex[i].swizzle_a = view->swizzle_a;
-
- key->tex[i].return_type = svga_get_texture_datatype(view->format);
   }
}
key->num_textures = svga->curr.num_sampler_views[shader];
diff --git a/src/gallium/drivers/svga/svga_shader.h 
b/src/gallium/drivers/svga/svga_shader.h
index f49fdb4..3f91574 100644
--- a/src/gallium/drivers/svga/svga_shader.h
+++ b/src/gallium/drivers/svga/svga_shader.h
@@ -98,14 +98,13 @@ struct svga_compile_key
   unsigned compare_func:3;
   unsigned unnormalized:1;
   unsigned width_height_idx:5; /**< texture unit */
-  unsigned texture_target:4;   /**< PIPE_TEXTURE_x */
+  unsigned is_array:1;
   unsigned texture_msaa:1;/**< A multisample texture? */
   unsigned sprite_texgen:1;
   unsigned swizzle_r:3;
   unsigned swizzle_g:3;
   unsigned swizzle_b:3;
   unsigned swizzle_a:3;
-  unsigned return_type:3;  /**< TGSI_RETURN_TYPE_x */
} tex[PIPE_MAX_SAMPLERS];
/* Note: svga_compile_keys_equal() depends on the variable-size
 * tex[] array being at the end of this structure.
diff --git a/src/gallium/drivers/svga/svga_tgsi_decl_sm30.c 
b/src/gallium/drivers/svga/svga_tgsi_decl_sm30.c
index ca4009b..204b814 100644
--- a/src/gallium/drivers/svga/svga_tgsi_decl_sm30.c
+++ b/src/gallium/drivers/svga/svga_tgsi_decl_sm30.c
@@ -517,15 +517,15 @@ vs30_output(struct svga_shader_emitter *emit,
 static ubyte
 svga_tgsi_sampler_type(const struct svga_shader_emitter *emit, int idx)
 {
-   switch (emit->key.tex[idx].texture_target) {
-   case PIPE_TEXTURE_1D:
+   switch (emit->sampler_target[idx]) {
+   case TGSI_TEXTURE_1D:
   return SVGA3DSAMP_2D;
-   case PIPE_TEXTURE_2D:
-   case PIPE_TEXTURE_RECT:
+   case TGSI_TEXTURE_2D:
+   case TGSI_TEXTURE_RECT:
   return SVGA3DSAMP_2D;
-   case PIPE_TEXTURE_3D:
+   case TGSI_TEXTURE_3D:
   return SVGA3DSAMP_VOLUME;
-   case PIPE_TEXTURE_CUBE:
+   case TGSI_TEXTURE_CUBE:
   return SVGA3DSAMP_CUBE;
}

@@ -585,6 +585,14 @@ svga_translate_decl_sm30( struct svga_shader_emitter *emit,
 ok = ps30_output( emit,

[Mesa-dev] [V2 05/19] mesa: Handle 3d block sizes in teximage error checks

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/teximage.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 616a929..5bd3a9d 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1112,7 +1112,7 @@ error_check_subtexture_dimensions(struct gl_context *ctx, 
GLuint dims,
   GLsizei subDepth, const char *func)
 {
const GLenum target = destImage->TexObject->Target;
-   GLuint bw, bh;
+   GLuint bw, bh, bd;
 
/* Check size */
if (subWidth < 0) {
@@ -1185,14 +1185,14 @@ error_check_subtexture_dimensions(struct gl_context 
*ctx, GLuint dims,
 * compressed formats supported by Mesa allow sub-textures to be updated
 * along compressed block boundaries.
 */
-   _mesa_get_format_block_size(destImage->TexFormat, , );
+   _mesa_get_format_block_size_3d(destImage->TexFormat, , , );
 
-   if (bw != 1 || bh != 1) {
+   if (bw != 1 || bh != 1 || bd != 1) {
   /* offset must be multiple of block size */
-  if ((xoffset % bw != 0) || (yoffset % bh != 0)) {
+  if ((xoffset % bw != 0) || (yoffset % bh != 0) || (zoffset % bd != 0)) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(xoffset = %d, yoffset = %d)",
- func, xoffset, yoffset);
+ "%s(xoffset = %d, yoffset = %d, zoffset = %d)",
+ func, xoffset, yoffset, zoffset);
  return GL_TRUE;
   }
 
@@ -1214,6 +1214,13 @@ error_check_subtexture_dimensions(struct gl_context 
*ctx, GLuint dims,
  "%s(height = %d)", func, subHeight);
  return GL_TRUE;
   }
+
+  if ((subDepth % bd != 0) &&
+  (zoffset + subDepth != (GLint) destImage->Depth)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(depth = %d)", func, subDepth);
+ return GL_TRUE;
+  }
}
 
return GL_FALSE;
-- 
2.5.0

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[Mesa-dev] [V2 03/19] mesa: Add an assert for BlockDepth in _mesa_get_format_block_size()

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index cfaac04..999e627 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -315,6 +315,9 @@ void
 _mesa_get_format_block_size(mesa_format format, GLuint *bw, GLuint *bh)
 {
const struct gl_format_info *info = _mesa_get_format_info(format);
+   /* Use _mesa_get_format_block_size_3d() for 3D blocks. */
+   assert(info->BlockDepth == 1);
+
*bw = info->BlockWidth;
*bh = info->BlockHeight;
 }
-- 
2.5.0

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[Mesa-dev] [V2 09/19] mesa: Add mesa formats for astc 3d formats

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.h | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index c6653bc..b88466f 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -635,6 +635,27 @@ typedef enum
MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10,
MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10,
MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12,
+
+   MESA_FORMAT_RGBA_ASTC_3x3x3,
+   MESA_FORMAT_RGBA_ASTC_4x3x3,
+   MESA_FORMAT_RGBA_ASTC_4x4x3,
+   MESA_FORMAT_RGBA_ASTC_4x4x4,
+   MESA_FORMAT_RGBA_ASTC_5x4x4,
+   MESA_FORMAT_RGBA_ASTC_5x5x4,
+   MESA_FORMAT_RGBA_ASTC_5x5x5,
+   MESA_FORMAT_RGBA_ASTC_6x5x5,
+   MESA_FORMAT_RGBA_ASTC_6x6x5,
+   MESA_FORMAT_RGBA_ASTC_6x6x6,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6,
MESA_FORMAT_COUNT
 } mesa_format;
 
-- 
2.5.0

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[Mesa-dev] [V2 19/19] swrast: Add texfetch_funcs entries for astc 3d formats

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/swrast/s_texfetch.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mesa/swrast/s_texfetch.c b/src/mesa/swrast/s_texfetch.c
index 27de9b3..721d088 100644
--- a/src/mesa/swrast/s_texfetch.c
+++ b/src/mesa/swrast/s_texfetch.c
@@ -440,7 +440,28 @@ texfetch_funcs[] =
FETCH_NULL(SRGB8_ALPHA8_ASTC_10x8),
FETCH_NULL(SRGB8_ALPHA8_ASTC_10x10),
FETCH_NULL(SRGB8_ALPHA8_ASTC_12x10),
-   FETCH_NULL(SRGB8_ALPHA8_ASTC_12x12)
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_12x12),
+
+   FETCH_NULL(RGBA_ASTC_3x3x3),
+   FETCH_NULL(RGBA_ASTC_4x3x3),
+   FETCH_NULL(RGBA_ASTC_4x4x3),
+   FETCH_NULL(RGBA_ASTC_4x4x4),
+   FETCH_NULL(RGBA_ASTC_5x4x4),
+   FETCH_NULL(RGBA_ASTC_5x5x4),
+   FETCH_NULL(RGBA_ASTC_5x5x5),
+   FETCH_NULL(RGBA_ASTC_6x5x5),
+   FETCH_NULL(RGBA_ASTC_6x6x5),
+   FETCH_NULL(RGBA_ASTC_6x6x6),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_3x3x3),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_4x3x3),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_4x4x3),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_4x4x4),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_5x4x4),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_5x5x4),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_5x5x5),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_6x5x5),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_6x6x5),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_6x6x6)
 };
 
 
-- 
2.5.0

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[Mesa-dev] [V2 07/19] mesa: Account for block depth in _mesa_format_image_size()

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.c | 44 +++-
 1 file changed, 23 insertions(+), 21 deletions(-)

diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 999e627..9d9830f 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -861,20 +861,22 @@ _mesa_format_image_size(mesa_format format, GLsizei width,
 GLsizei height, GLsizei depth)
 {
const struct gl_format_info *info = _mesa_get_format_info(format);
+   GLuint sz;
/* Strictly speaking, a conditional isn't needed here */
-   if (info->BlockWidth > 1 || info->BlockHeight > 1) {
+   if (info->BlockWidth > 1 || info->BlockHeight > 1 || info->BlockDepth > 1) {
   /* compressed format (2D only for now) */
-  const GLuint bw = info->BlockWidth, bh = info->BlockHeight;
+  const GLuint bw = info->BlockWidth;
+  const GLuint bh = info->BlockHeight;
+  const GLuint bd = info->BlockDepth;
   const GLuint wblocks = (width + bw - 1) / bw;
   const GLuint hblocks = (height + bh - 1) / bh;
-  const GLuint sz = wblocks * hblocks * info->BytesPerBlock;
-  return sz * depth;
-   }
-   else {
+  const GLuint dblocks = (depth + bd - 1) / bd;
+  sz = wblocks * hblocks * dblocks * info->BytesPerBlock;
+   } else
   /* non-compressed */
-  const GLuint sz = width * height * depth * info->BytesPerBlock;
-  return sz;
-   }
+  sz = width * height * depth * info->BytesPerBlock;
+
+   return sz;
 }
 
 
@@ -887,23 +889,23 @@ _mesa_format_image_size64(mesa_format format, GLsizei 
width,
   GLsizei height, GLsizei depth)
 {
const struct gl_format_info *info = _mesa_get_format_info(format);
+   uint64_t sz;
/* Strictly speaking, a conditional isn't needed here */
-   if (info->BlockWidth > 1 || info->BlockHeight > 1) {
+   if (info->BlockWidth > 1 || info->BlockHeight > 1 || info->BlockDepth > 1) {
   /* compressed format (2D only for now) */
-  const uint64_t bw = info->BlockWidth, bh = info->BlockHeight;
+  const uint64_t bw = info->BlockWidth;
+  const uint64_t bh = info->BlockHeight;
+  const uint64_t bd = info->BlockDepth;
   const uint64_t wblocks = (width + bw - 1) / bw;
   const uint64_t hblocks = (height + bh - 1) / bh;
-  const uint64_t sz = wblocks * hblocks * info->BytesPerBlock;
-  return sz * depth;
-   }
-   else {
+  const uint64_t dblocks = (depth + bd - 1) / bd;
+  sz = wblocks * hblocks * dblocks * info->BytesPerBlock;
+   } else
   /* non-compressed */
-  const uint64_t sz = ((uint64_t) width *
-   (uint64_t) height *
-   (uint64_t) depth *
-   info->BytesPerBlock);
-  return sz;
-   }
+  sz = ((uint64_t) width * (uint64_t) height *
+(uint64_t) depth * info->BytesPerBlock);
+
+   return sz;
 }
 
 
-- 
2.5.0

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[Mesa-dev] [V2 16/19] mesa: Handle astc 3d formats in _mesa_base_tex_format()

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glformats.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 7245f66..fa064e5 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -2387,8 +2387,10 @@ _mesa_base_tex_format(const struct gl_context *ctx, 
GLint internalFormat)
 return base_compressed;
}
 
-   if (ctx->Extensions.KHR_texture_compression_astc_ldr &&
-  _mesa_is_astc_format(internalFormat))
+   if ((ctx->Extensions.KHR_texture_compression_astc_ldr &&
+is_astc_2d_format(internalFormat)) ||
+   (ctx->Extensions.OES_texture_compression_astc &&
+is_astc_3d_format(internalFormat)))
 return GL_RGBA;
 
if (ctx->Extensions.MESA_ycbcr_texture) {
-- 
2.5.0

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[Mesa-dev] [V2 08/19] glapi: Update dispatch XML files for OES_texture_compression_astc.xml

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mapi/glapi/gen/Makefile.am |  1 +
 .../glapi/gen/OES_texture_compression_astc.xml | 61 ++
 src/mapi/glapi/gen/gl_API.xml  |  2 +
 3 files changed, 64 insertions(+)
 create mode 100644 src/mapi/glapi/gen/OES_texture_compression_astc.xml

diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index 8421af4..d94fd0a 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -209,6 +209,7 @@ API_XML = \
OES_EGL_image.xml \
OES_fixed_point.xml \
OES_single_precision.xml \
+   OES_texture_compression_astc.xml \
GL3x.xml \
GL4x.xml
 
diff --git a/src/mapi/glapi/gen/OES_texture_compression_astc.xml 
b/src/mapi/glapi/gen/OES_texture_compression_astc.xml
new file mode 100644
index 000..4e8de71
--- /dev/null
+++ b/src/mapi/glapi/gen/OES_texture_compression_astc.xml
@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 8b49f91..03adf08 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8271,6 +8271,8 @@
 
 
 
+http://www.w3.org/2001/XInclude"/>
+
 http://www.w3.org/2001/XInclude"/>
 
 http://www.w3.org/2001/XInclude"/>
-- 
2.5.0

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[Mesa-dev] [V2 14/19] mesa: Add a helper function is_astc_3d_format()

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glformats.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 96ab393..edcafdc 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -863,6 +863,38 @@ _mesa_is_astc_format(GLenum internalFormat)
}
 }
 
+/**
+ * Test if the given format is an ASTC 3D format.
+ */
+static bool
+is_astc_3d_format(GLenum internalFormat)
+{
+   switch (internalFormat) {
+   case GL_COMPRESSED_RGBA_ASTC_3x3x3_OES:
+   case GL_COMPRESSED_RGBA_ASTC_4x3x3_OES:
+   case GL_COMPRESSED_RGBA_ASTC_4x4x3_OES:
+   case GL_COMPRESSED_RGBA_ASTC_4x4x4_OES:
+   case GL_COMPRESSED_RGBA_ASTC_5x4x4_OES:
+   case GL_COMPRESSED_RGBA_ASTC_5x5x4_OES:
+   case GL_COMPRESSED_RGBA_ASTC_5x5x5_OES:
+   case GL_COMPRESSED_RGBA_ASTC_6x5x5_OES:
+   case GL_COMPRESSED_RGBA_ASTC_6x6x5_OES:
+   case GL_COMPRESSED_RGBA_ASTC_6x6x6_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES:
+  return true;
+   default:
+  return false;
+   }
+}
 
 /**
  * Test if the given format is an integer (non-normalized) format.
-- 
2.5.0

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[Mesa-dev] [V2 12/19] mesa: Align the values of #define's in glheader.h

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glheader.h | 58 
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
index a2d98d4..9d299e8 100644
--- a/src/mesa/main/glheader.h
+++ b/src/mesa/main/glheader.h
@@ -69,17 +69,17 @@ typedef void *GLeglImageOES;
 
 
 #ifndef GL_OES_draw_texture
-#define GL_TEXTURE_CROP_RECT_OES  0x8B9D
+#define GL_TEXTURE_CROP_RECT_OES0x8B9D
 #endif
 
 
 #ifndef GL_PROGRAM_BINARY_LENGTH_OES
-#define GL_PROGRAM_BINARY_LENGTH_OES 0x8741
+#define GL_PROGRAM_BINARY_LENGTH_OES0x8741
 #endif
 
 /* GLES 2.0 tokens */
 #ifndef GL_RGB565
-#define GL_RGB565 0x8D62
+#define GL_RGB565   0x8D62
 #endif
 
 #ifndef GL_TEXTURE_GEN_STR_OES
@@ -100,17 +100,17 @@ typedef void *GLeglImageOES;
 #endif
 
 #ifndef GL_ES_VERSION_2_0
-#define GL_SHADER_BINARY_FORMATS0x8DF8
-#define GL_NUM_SHADER_BINARY_FORMATS0x8DF9
-#define GL_SHADER_COMPILER  0x8DFA
-#define GL_MAX_VERTEX_UNIFORM_VECTORS   0x8DFB
-#define GL_MAX_VARYING_VECTORS  0x8DFC
-#define GL_MAX_FRAGMENT_UNIFORM_VECTORS 0x8DFD
+#define GL_SHADER_BINARY_FORMATS0x8DF8
+#define GL_NUM_SHADER_BINARY_FORMATS0x8DF9
+#define GL_SHADER_COMPILER  0x8DFA
+#define GL_MAX_VERTEX_UNIFORM_VECTORS   0x8DFB
+#define GL_MAX_VARYING_VECTORS  0x8DFC
+#define GL_MAX_FRAGMENT_UNIFORM_VECTORS 0x8DFD
 #endif
 
 #ifndef GL_ATI_texture_compression_3dc
-#define GL_ATI_texture_compression_3dc 1
-#define GL_COMPRESSED_LUMINANCE_ALPHA_3DC_ATI 0x8837
+#define GL_ATI_texture_compression_3dc  1
+#define GL_COMPRESSED_LUMINANCE_ALPHA_3DC_ATI   0x8837
 #endif
 
 #ifndef GL_OES_compressed_ETC1_RGB8_texture
@@ -121,7 +121,7 @@ typedef void *GLeglImageOES;
 /* Inexplicably, GL_HALF_FLOAT_OES has a different value than GL_HALF_FLOAT.
  */
 #ifndef GL_HALF_FLOAT_OES
-#define GL_HALF_FLOAT_OES 0x8D61
+#define GL_HALF_FLOAT_OES   0x8D61
 #endif
 
 
@@ -132,29 +132,29 @@ typedef void *GLeglImageOES;
  * so we need a value that's different from any of the
  * GL_VERTEX/FRAGMENT/GEOMETRY_PROGRAM tokens.
  */
-#define GL_SHADER_PROGRAM_MESA 0x
+#define GL_SHADER_PROGRAM_MESA  0x
 
 
 /* Several fields of struct gl_config can take these as values.  Since
  * GLX header files may not be available everywhere they need to be used,
  * redefine them here.
  */
-#define GLX_NONE   0x8000
-#define GLX_SLOW_CONFIG0x8001
-#define GLX_TRUE_COLOR 0x8002
-#define GLX_DIRECT_COLOR   0x8003
-#define GLX_PSEUDO_COLOR   0x8004
-#define GLX_STATIC_COLOR   0x8005
-#define GLX_GRAY_SCALE 0x8006
-#define GLX_STATIC_GRAY0x8007
-#define GLX_TRANSPARENT_RGB0x8008
-#define GLX_TRANSPARENT_INDEX  0x8009
-#define GLX_NON_CONFORMANT_CONFIG  0x800D
-#define GLX_SWAP_EXCHANGE_OML  0x8061
-#define GLX_SWAP_COPY_OML  0x8062
-#define GLX_SWAP_UNDEFINED_OML 0x8063
-
-#define GLX_DONT_CARE  0x
+#define GLX_NONE0x8000
+#define GLX_SLOW_CONFIG 0x8001
+#define GLX_TRUE_COLOR  0x8002
+#define GLX_DIRECT_COLOR0x8003
+#define GLX_PSEUDO_COLOR0x8004
+#define GLX_STATIC_COLOR0x8005
+#define GLX_GRAY_SCALE  0x8006
+#define GLX_STATIC_GRAY 0x8007
+#define GLX_TRANSPARENT_RGB 0x8008
+#define GLX_TRANSPARENT_INDEX   0x8009
+#define GLX_NON_CONFORMANT_CONFIG   0x800D
+#define GLX_SWAP_EXCHANGE_OML   0x8061
+#define GLX_SWAP_COPY_OML   0x8062
+#define GLX_SWAP_UNDEFINED_OML  0x8063
+
+#define GLX_DONT_CARE   0x
 
 
 #ifdef __cplusplus
-- 
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[Mesa-dev] [V2 02/19] mesa: Add a helper function to query 3D block sizes

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.c | 21 +
 src/mesa/main/formats.h |  4 
 2 files changed, 25 insertions(+)

diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 3d2349b..cfaac04 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -321,6 +321,27 @@ _mesa_get_format_block_size(mesa_format format, GLuint 
*bw, GLuint *bh)
 
 
 /**
+ * Return the block size (in pixels) for the given format. Normally
+ * the block size is 1x1x1. But compressed formats will have block
+ * sizes of 4x4x4, 3x3x3 pixels, etc.
+ * \param bw  returns block width in pixels
+ * \param bh  returns block height in pixels
+ * \param bd  returns block depth in pixels
+ */
+void
+_mesa_get_format_block_size_3d(mesa_format format,
+   GLuint *bw,
+   GLuint *bh,
+   GLuint *bd)
+{
+   const struct gl_format_info *info = _mesa_get_format_info(format);
+   *bw = info->BlockWidth;
+   *bh = info->BlockHeight;
+   *bd = info->BlockDepth;
+}
+
+
+/**
  * Returns the an array of four numbers representing the transformation
  * from the RGBA or SZ colorspace to the given format.  For array formats,
  * the i'th RGBA component is given by:
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index 794d599..c6653bc 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -663,6 +663,10 @@ _mesa_get_format_base_format(uint32_t format);
 extern void
 _mesa_get_format_block_size(mesa_format format, GLuint *bw, GLuint *bh);
 
+extern void
+_mesa_get_format_block_size_3d(mesa_format format, GLuint *bw,
+   GLuint *bh, GLuint *bd);
+
 extern mesa_array_format
 _mesa_array_format_flip_channels(mesa_array_format format);
 
-- 
2.5.0

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[Mesa-dev] [V2 11/19] mesa: Add OES_texture_compression_astc to extension table and gl_extensions

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/mtypes.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 54a5bb0..cbf00bf 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -339,6 +339,7 @@ EXT(OES_stencil_wrap, dummy_true
 EXT(OES_surfaceless_context , dummy_true   
  ,  x ,  x , ES1, ES2, 2012)
 EXT(OES_texture_3D  , dummy_true   
  ,  x ,  x ,  x , ES2, 2005)
 EXT(OES_texture_border_clamp, ARB_texture_border_clamp 
  ,  x ,  x ,  x , ES2, 2014)
+EXT(OES_texture_compression_astc, OES_texture_compression_astc 
  ,  x ,  x , ES1, ES2, 2015)
 EXT(OES_texture_cube_map, ARB_texture_cube_map 
  ,  x ,  x , ES1,  x , 2007)
 EXT(OES_texture_env_crossbar, ARB_texture_env_crossbar 
  ,  x ,  x , ES1,  x , 2005)
 EXT(OES_texture_float   , OES_texture_float
  ,  x ,  x ,  x , ES2, 2005)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 5d8bfe4..2b81189 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3941,6 +3941,7 @@ struct gl_extensions
GLboolean OES_texture_half_float_linear;
GLboolean OES_compressed_ETC1_RGB8_texture;
GLboolean OES_geometry_shader;
+   GLboolean OES_texture_compression_astc;
GLboolean extension_sentinel;
/** The extension string */
const GLubyte *String;
-- 
2.5.0

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[Mesa-dev] [V2 04/19] mesa: Handle 3d block sizes in getteximage error checks

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/texgetimage.c | 21 +
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index dc21551..02e6bc2 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -1037,9 +1037,9 @@ dimensions_error_check(struct gl_context *ctx,
 
/* Extra checks for compressed textures */
{
-  GLuint bw, bh;
-  _mesa_get_format_block_size(texImage->TexFormat, , );
-  if (bw > 1 || bh > 1) {
+  GLuint bw, bh, bd;
+  _mesa_get_format_block_size_3d(texImage->TexFormat, , , );
+  if (bw > 1 || bh > 1 || bd > 1) {
  /* offset must be multiple of block size */
  if (xoffset % bw != 0) {
 _mesa_error(ctx, GL_INVALID_VALUE,
@@ -1054,7 +1054,13 @@ dimensions_error_check(struct gl_context *ctx,
 }
  }
 
- /* The size must be a multiple of bw x bh, or we must be using a
+ if (zoffset % bd != 0) {
+_mesa_error(ctx, GL_INVALID_VALUE,
+"%s(zoffset = %d)", caller, zoffset);
+return true;
+ }
+
+ /* The size must be a multiple of bw x bh x bd, or we must be using a
   * offset+size that exactly hits the edge of the image.
   */
  if ((width % bw != 0) &&
@@ -1070,6 +1076,13 @@ dimensions_error_check(struct gl_context *ctx,
 "%s(height = %d)", caller, height);
 return true;
  }
+
+ if ((depth % bd != 0) &&
+ (zoffset + depth != (GLint) texImage->Depth)) {
+_mesa_error(ctx, GL_INVALID_VALUE,
+"%s(depth = %d)", caller, depth);
+return true;
+ }
   }
}
 
-- 
2.5.0

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[Mesa-dev] [V2 15/19] mesa: Account for astc 3d formats in _mesa_is_astc_format()

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glformats.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index edcafdc..7245f66 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -823,10 +823,10 @@ _mesa_is_enum_format_signed_int(GLenum format)
 }
 
 /**
- * Test if the given format is an ASTC format.
+ * Test if the given format is an ASTC 2D format.
  */
-GLboolean
-_mesa_is_astc_format(GLenum internalFormat)
+static bool
+is_astc_2d_format(GLenum internalFormat)
 {
switch (internalFormat) {
case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
@@ -897,6 +897,16 @@ is_astc_3d_format(GLenum internalFormat)
 }
 
 /**
+ * Test if the given format is an ASTC format.
+ */
+GLboolean
+_mesa_is_astc_format(GLenum internalFormat)
+{
+   return is_astc_2d_format(internalFormat) ||
+  is_astc_3d_format(internalFormat);
+}
+
+/**
  * Test if the given format is an integer (non-normalized) format.
  */
 GLboolean
-- 
2.5.0

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[Mesa-dev] [V2 13/19] mesa: Add the missing defines for GL_OES_texture_compression_astc

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glheader.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
index 9d299e8..40fada1 100644
--- a/src/mesa/main/glheader.h
+++ b/src/mesa/main/glheader.h
@@ -99,6 +99,29 @@ typedef void *GLeglImageOES;
 #define GL_PALETTE8_RGB5_A1_OES 0x8B99
 #endif
 
+#ifndef GL_OES_texture_compression_astc
+#define GL_COMPRESSED_RGBA_ASTC_3x3x3_OES   0x93C0
+#define GL_COMPRESSED_RGBA_ASTC_4x3x3_OES   0x93C1
+#define GL_COMPRESSED_RGBA_ASTC_4x4x3_OES   0x93C2
+#define GL_COMPRESSED_RGBA_ASTC_4x4x4_OES   0x93C3
+#define GL_COMPRESSED_RGBA_ASTC_5x4x4_OES   0x93C4
+#define GL_COMPRESSED_RGBA_ASTC_5x5x4_OES   0x93C5
+#define GL_COMPRESSED_RGBA_ASTC_5x5x5_OES   0x93C6
+#define GL_COMPRESSED_RGBA_ASTC_6x5x5_OES   0x93C7
+#define GL_COMPRESSED_RGBA_ASTC_6x6x5_OES   0x93C8
+#define GL_COMPRESSED_RGBA_ASTC_6x6x6_OES   0x93C9
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES   0x93E0
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES   0x93E1
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES   0x93E2
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES   0x93E3
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES   0x93E4
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES   0x93E5
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES   0x93E6
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES   0x93E7
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES   0x93E8
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES   0x93E9
+#endif
+
 #ifndef GL_ES_VERSION_2_0
 #define GL_SHADER_BINARY_FORMATS0x8DF8
 #define GL_NUM_SHADER_BINARY_FORMATS0x8DF9
-- 
2.5.0

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[Mesa-dev] [V2 18/19] mesa: Enable translation between astc 3d gl formats and mesa formats

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/texcompress.c | 80 +
 1 file changed, 80 insertions(+)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 3f453b1..9567c5d 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -612,6 +612,46 @@ _mesa_glenum_to_compressed_format(GLenum format)
   return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10;
case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
   return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12;
+   case GL_COMPRESSED_RGBA_ASTC_3x3x3_OES:
+  return MESA_FORMAT_RGBA_ASTC_3x3x3;
+   case GL_COMPRESSED_RGBA_ASTC_4x3x3_OES:
+  return MESA_FORMAT_RGBA_ASTC_4x3x3;
+   case GL_COMPRESSED_RGBA_ASTC_4x4x3_OES:
+  return MESA_FORMAT_RGBA_ASTC_4x4x3;
+   case GL_COMPRESSED_RGBA_ASTC_4x4x4_OES:
+  return MESA_FORMAT_RGBA_ASTC_4x4x4;
+   case GL_COMPRESSED_RGBA_ASTC_5x4x4_OES:
+  return MESA_FORMAT_RGBA_ASTC_5x4x4;
+   case GL_COMPRESSED_RGBA_ASTC_5x5x4_OES:
+  return MESA_FORMAT_RGBA_ASTC_5x5x4;
+   case GL_COMPRESSED_RGBA_ASTC_5x5x5_OES:
+  return MESA_FORMAT_RGBA_ASTC_5x5x5;
+   case GL_COMPRESSED_RGBA_ASTC_6x5x5_OES:
+  return MESA_FORMAT_RGBA_ASTC_6x5x5;
+   case GL_COMPRESSED_RGBA_ASTC_6x6x5_OES:
+  return MESA_FORMAT_RGBA_ASTC_6x6x5;
+   case GL_COMPRESSED_RGBA_ASTC_6x6x6_OES:
+  return MESA_FORMAT_RGBA_ASTC_6x6x6;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6;
 
default:
   return MESA_FORMAT_NONE;
@@ -760,6 +800,46 @@ _mesa_compressed_format_to_glenum(struct gl_context *ctx, 
mesa_format mesaFormat
case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12:
   return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR;
 
+   case MESA_FORMAT_RGBA_ASTC_3x3x3:
+  return GL_COMPRESSED_RGBA_ASTC_3x3x3_OES;
+   case MESA_FORMAT_RGBA_ASTC_4x3x3:
+  return GL_COMPRESSED_RGBA_ASTC_4x3x3_OES;
+   case MESA_FORMAT_RGBA_ASTC_4x4x3:
+  return GL_COMPRESSED_RGBA_ASTC_4x4x3_OES;
+   case MESA_FORMAT_RGBA_ASTC_4x4x4:
+  return GL_COMPRESSED_RGBA_ASTC_4x4x4_OES;
+   case MESA_FORMAT_RGBA_ASTC_5x4x4:
+  return GL_COMPRESSED_RGBA_ASTC_5x4x4_OES;
+   case MESA_FORMAT_RGBA_ASTC_5x5x4:
+  return GL_COMPRESSED_RGBA_ASTC_5x5x4_OES;
+   case MESA_FORMAT_RGBA_ASTC_5x5x5:
+  return GL_COMPRESSED_RGBA_ASTC_5x5x5_OES;
+   case MESA_FORMAT_RGBA_ASTC_6x5x5:
+  return GL_COMPRESSED_RGBA_ASTC_6x5x5_OES;
+   case MESA_FORMAT_RGBA_ASTC_6x6x5:
+  return GL_COMPRESSED_RGBA_ASTC_6x6x5_OES;
+   case MESA_FORMAT_RGBA_ASTC_6x6x6:
+  return GL_COMPRESSED_RGBA_ASTC_6x6x6_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES;
default:
   _mesa_problem(ctx, "Unexpected mesa texture format in"
 " _mesa_compressed_format_to_glenum()");
-- 
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[Mesa-dev] [V2 10/19] mesa: Add entries for astc 3d formats initializing struct gl_format_info

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.csv | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index 8eb69ad..285921e 100644
--- a/src/mesa/main/formats.csv
+++ b/src/mesa/main/formats.csv
@@ -349,3 +349,24 @@ MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8, astc  ,10, 8, 
1, x128, , ,
 MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10   , astc  ,10,10, 1, x128, , , 
, xyzw, srgb
 MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10   , astc  ,12,10, 1, x128, , , 
, xyzw, srgb
 MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12   , astc  ,12,12, 1, x128, , , 
, xyzw, srgb
+
+MESA_FORMAT_RGBA_ASTC_3x3x3   , astc  , 3, 3, 3, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_4x3x3   , astc  , 4, 3, 3, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_4x4x3   , astc  , 4, 4, 3, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_4x4x4   , astc  , 4, 4, 4, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x4x4   , astc  , 5, 4, 4, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x5x4   , astc  , 5, 5, 4, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x5x5   , astc  , 5, 5, 5, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x5x5   , astc  , 6, 5, 5, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x6x5   , astc  , 6, 6, 5, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x6x6   , astc  , 6, 6, 6, x128, , , 
, xyzw, rgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3   , astc  , 3, 3, 3, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3   , astc  , 4, 3, 3, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3   , astc  , 4, 4, 3, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4   , astc  , 4, 4, 4, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4   , astc  , 5, 4, 4, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4   , astc  , 5, 5, 4, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5   , astc  , 5, 5, 5, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5   , astc  , 6, 5, 5, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5   , astc  , 6, 6, 5, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6   , astc  , 6, 6, 6, x128, , , 
, xyzw, srgb
-- 
2.5.0

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[Mesa-dev] [V2 17/19] mesa: Handle astc 3d formats in _mesa_get_compressed_formats()

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/texcompress.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 3ae6452..3f453b1 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -438,6 +438,35 @@ _mesa_get_compressed_formats(struct gl_context *ctx, GLint 
*formats)
   }
}
 
+   if (_mesa_is_gles3(ctx) &&
+   ctx->Extensions.OES_texture_compression_astc) {
+  if (formats) {
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_3x3x3_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_4x3x3_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_4x4x3_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_4x4x4_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_5x4x4_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_5x5x4_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_5x5x5_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_6x5x5_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_6x6x5_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_6x6x6_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES;
+  }
+  else {
+ n += 20;
+  }
+   }
+
return n;
 }
 
-- 
2.5.0

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[Mesa-dev] [V2 06/19] mesa: Handle 3d block sizes in _mesa_compute_compressed_pixelstore

2016-03-21 Thread Anuj Phogat 
Signed-off-by: Anuj Phogat 
---
 src/mesa/main/texstore.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
index c33b109..b8d17f8 100644
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -1267,16 +1267,16 @@ _mesa_compute_compressed_pixelstore(GLuint dims, 
mesa_format texFormat,
 const struct gl_pixelstore_attrib *packing,
 struct compressed_pixelstore *store)
 {
-   GLuint bw, bh;
+   GLuint bw, bh, bd;
 
-   _mesa_get_format_block_size(texFormat, , );
+   _mesa_get_format_block_size_3d(texFormat, , , );
 
store->SkipBytes = 0;
store->TotalBytesPerRow = store->CopyBytesPerRow =
  _mesa_format_row_stride(texFormat, width);
store->TotalRowsPerSlice = store->CopyRowsPerSlice =
  (height + bh - 1) / bh;
-   store->CopySlices = depth;
+   store->CopySlices = (depth + bd - 1) / bd;
 
if (packing->CompressedBlockWidth &&
packing->CompressedBlockSize) {
-- 
2.5.0

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[Mesa-dev] [V2 01/19] mesa: Add block depth field in struct gl_format_info

2016-03-21 Thread Anuj Phogat 
This will be later required for 3D ASTC formats.

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/format_info.py   |   5 +-
 src/mesa/main/format_parser.py |  15 +-
 src/mesa/main/formats.c|   4 +-
 src/mesa/main/formats.csv  | 529 +
 4 files changed, 279 insertions(+), 274 deletions(-)

diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index 50626a85..729edbb 100644
--- a/src/mesa/main/format_info.py
+++ b/src/mesa/main/format_info.py
@@ -185,8 +185,9 @@ for fmat in formats:
 
print '  {0:d},'.format(fmat.colorspace == 'srgb')
 
-   print '  {0}, {1}, {2},'.format(fmat.block_width, fmat.block_height,
-   int(fmat.block_size() / 8))
+   print '  {0}, {1}, {2}, {3},'.format(fmat.block_width, 
fmat.block_height,
+fmat.block_depth,
+int(fmat.block_size() / 8))
 
print '  {{ {0} }},'.format(', '.join(map(str, fmat.swizzle)))
if fmat.is_array():
diff --git a/src/mesa/main/format_parser.py b/src/mesa/main/format_parser.py
index a29f207..6cd2fbc 100755
--- a/src/mesa/main/format_parser.py
+++ b/src/mesa/main/format_parser.py
@@ -227,7 +227,7 @@ class Swizzle:
 class Format:
"""Describes a pixel format."""
 
-   def __init__(self, name, layout, block_width, block_height, channels, 
swizzle, colorspace):
+   def __init__(self, name, layout, block_width, block_height, block_depth, 
channels, swizzle, colorspace):
   """Constructs a Format from some metadata and a list of channels.
 
   The channel objects must be unique to this Format and should not be
@@ -241,6 +241,7 @@ class Format:
   layout -- One of 'array', 'packed' 'other', or a compressed layout
   block_width -- The block width if the format is compressed, 1 otherwise
   block_height -- The block height if the format is compressed, 1 otherwise
+  block_depth -- The block depth if the format is compressed, 1 otherwise
   channels -- A list of Channel objects
   swizzle -- A Swizzle from this format to rgba
   colorspace -- one of 'rgb', 'srgb', 'yuv', or 'zs'
@@ -249,6 +250,7 @@ class Format:
   self.layout = layout
   self.block_width = block_width
   self.block_height = block_height
+  self.block_depth = block_depth
   self.channels = channels
   assert isinstance(swizzle, Swizzle)
   self.swizzle = swizzle
@@ -361,7 +363,7 @@ class Format:
 
def is_compressed(self):
   """Returns true if this is a compressed format."""
-  return self.block_width != 1 or self.block_height != 1
+  return self.block_width != 1 or self.block_height != 1 or 
self.block_depth != 1
 
def is_int(self):
   """Returns true if this format is an integer format.
@@ -555,12 +557,13 @@ def parse(filename):
  layout = fields[1]
  block_width = int(fields[2])
  block_height = int(fields[3])
- colorspace = fields[9]
+ block_depth = int(fields[4])
+ colorspace = fields[10]
 
  try:
-swizzle = Swizzle(fields[8])
+swizzle = Swizzle(fields[9])
  except:
 sys.exit("error parsing swizzle for format " + name)
- channels = _parse_channels(fields[4:8], layout, colorspace, swizzle)
+ channels = _parse_channels(fields[5:9], layout, colorspace, swizzle)
 
- yield Format(name, layout, block_width, block_height, channels, 
swizzle, colorspace)
+ yield Format(name, layout, block_width, block_height, block_depth, 
channels, swizzle, colorspace)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 41d40a5..3d2349b 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -68,9 +68,9 @@ struct gl_format_info
bool IsSRGBFormat;
 
/**
-* To describe compressed formats.  If not compressed, Width=Height=1.
+* To describe compressed formats.  If not compressed, Width=Height=Depth=1.
 */
-   GLubyte BlockWidth, BlockHeight;
+   GLubyte BlockWidth, BlockHeight, BlockDepth;
GLubyte BytesPerBlock;
 
uint8_t Swizzle[4];
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index a663c1e..8eb69ad 100644
--- a/src/mesa/main/formats.csv
+++ b/src/mesa/main/formats.csv
@@ -33,6 +33,7 @@
 # - layout
 # - pixel block's width
 # - pixel block's height
+# - pixel block's depth
 # - channel encoding (only meaningful for array or packed layout), containing 
for each
 #   channel the following information:
 #   - type, one of
@@ -48,303 +49,303 @@
 
 # None
 # Described as regular uint_8 bytes, i.e. MESA_FORMAT_R8_USCALED
-MESA_FORMAT_NONE  , other , 1, 1, x8  , , ,
 , 0001, rgb
+MESA_FORMAT_NONE  , other , 1, 1, 1, x8  , , , 
, 0001, rgb
 
 # Packed unorm formats
-MESA_FORMAT_A8B8G8R8_UNORM, packed, 1, 1,

[Mesa-dev] [V2 00/19] Add infrastructure for GL_OES_texture_compression_astc

2016-03-21 Thread Anuj Phogat 
I don't have a hardware which supports this extension and I realized it
after writing these patches. This blocks the testing of these patches.
So, I'm sure there will be few things left out in this series. But I
think it'll be nice to have 90% of the infrastructure ready when we
will have a hardware to enable the extension.

V2, NEW patches are based on the feedback by Brian Paul.

Anuj Phogat (19):

V1  mesa: Add block depth field in struct gl_format_info
NEW mesa: Add a helper function to query 3D block sizes
NEW mesa: Add an assert for BlockDepth in _mesa_get_format_block_size()
NEW mesa: Handle 3d block sizes in getteximage error checks
V2  mesa: Handle 3d block sizes in teximage error checks
NEW mesa: Handle 3d block sizes in _mesa_compute_compressed_pixelstore
V2  mesa: Account for block depth in _mesa_format_image_size()
V1  glapi: Update dispatch XML files for OES_texture_compression_astc.xml
V1  mesa: Add mesa formats for astc 3d formats
V1  mesa: Add entries for astc 3d formats initializing struct
gl_format_info
V1  mesa: Add OES_texture_compression_astc to extension table and
gl_extensions
V1  mesa: Align the values of #define's in glheader.h
V1  mesa: Add the missing defines for GL_OES_texture_compression_astc
V1  mesa: Add a helper function is_astc_3d_format()
V1  mesa: Account for astc 3d formats in _mesa_is_astc_format()
V1  mesa: Handle astc 3d formats in _mesa_base_tex_format()
V1  mesa: Handle astc 3d formats in _mesa_get_compressed_formats()
V1  mesa: Enable translation between astc 3d gl formats and mesa formats
V1  swrast: Add texfetch_funcs entries for astc 3d formats

 src/mapi/glapi/gen/Makefile.am |   1 +
 .../glapi/gen/OES_texture_compression_astc.xml |  61 +++
 src/mapi/glapi/gen/gl_API.xml  |   2 +
 src/mesa/main/extensions_table.h   |   1 +
 src/mesa/main/format_info.py   |   5 +-
 src/mesa/main/format_parser.py |  15 +-
 src/mesa/main/formats.c|  72 ++-
 src/mesa/main/formats.csv  | 550 +++--
 src/mesa/main/formats.h|  25 +
 src/mesa/main/glformats.c  |  54 +-
 src/mesa/main/glheader.h   |  81 +--
 src/mesa/main/mtypes.h |   1 +
 src/mesa/main/texcompress.c| 109 
 src/mesa/main/texgetimage.c|  21 +-
 src/mesa/main/teximage.c   |  19 +-
 src/mesa/main/texstore.c   |   6 +-
 src/mesa/swrast/s_texfetch.c   |  23 +-
 17 files changed, 703 insertions(+), 343 deletions(-)
 create mode 100644 src/mapi/glapi/gen/OES_texture_compression_astc.xml

-- 
2.5.0

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Re: [Mesa-dev] [PATCH 3/3] radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits

2016-03-21 Thread Nicolai Hähnle 

On 21.03.2016 06:07, Marek Olšák wrote:

On Sat, Mar 19, 2016 at 4:37 AM, Nicolai Hähnle  wrote:

From: Nicolai Hähnle 

This fixes arb_shader_image_load_store-host-mem-barrier.
---
  src/gallium/drivers/radeonsi/si_state.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 6dcd532..4093921 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3535,7 +3535,9 @@ static void si_memory_barrier(struct pipe_context *ctx, 
unsigned flags)
 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
  PIPE_BARRIER_SHADER_BUFFER |
  PIPE_BARRIER_TEXTURE |
-PIPE_BARRIER_IMAGE)) {
+PIPE_BARRIER_IMAGE |
+PIPE_BARRIER_INDEX_BUFFER |
+PIPE_BARRIER_STREAMOUT_BUFFER)) {


The hw reads the index buffer via TC L2 on VI only. The index buffer
is uncached on older chips.

I think this patch needs to flush TC L2 for PIPE_BARRIER_INDEX_BUFFER
if the chip family is not VI.


You're right. What's your take on the question of invalidating L2 vs. 
only writing L2 back to memory? I think at least VI has a TCWB bit in 
the cache actions. That would be a separate change though.



Patches 1-2:
Reviewed-by: Marek Olšák 


Thanks.

Nicolai



Marek


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Re: [Mesa-dev] [PATCH 09/17] softpipe: Set samples and layers in set_framebuffer_state() cb

2016-03-21 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Sat, Mar 19, 2016 at 7:41 AM, Edward O'Callaghan
 wrote:
> Carries across the number of samples and layers state in the
> 'softpipe_set_framebuffer_state()' callback. This state is
> part of 'ARB_framebuffer_no_attachments' support.
>
> Signed-off-by: Edward O'Callaghan 
> ---
>  src/gallium/drivers/softpipe/sp_state_surface.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/gallium/drivers/softpipe/sp_state_surface.c 
> b/src/gallium/drivers/softpipe/sp_state_surface.c
> index db4b273..1a4bf38 100644
> --- a/src/gallium/drivers/softpipe/sp_state_surface.c
> +++ b/src/gallium/drivers/softpipe/sp_state_surface.c
> @@ -94,6 +94,8 @@ softpipe_set_framebuffer_state(struct pipe_context *pipe,
>
> sp->framebuffer.width = fb->width;
> sp->framebuffer.height = fb->height;
> +   sp->framebuffer.samples = fb->samples;
> +   sp->framebuffer.layers = fb->layers;
>
> sp->dirty |= SP_NEW_FRAMEBUFFER;
>  }
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 12/17] gallium/util: Ensure util_framebuffer_get_num_samples() is valid

2016-03-21 Thread Ilia Mirkin 
On Mon, Mar 21, 2016 at 11:49 AM, Marek Olšák  wrote:
> On Sat, Mar 19, 2016 at 6:07 PM, Ilia Mirkin  wrote:
>> Normally samples == 0 is perfecly valid and means "not multisampling".
>> Why is it invalid here?
>
> Because this function never returns 0 and drivers depend on that
> behavior. The patch looks good:

Ah, indeed. This should then be squashed into the patch which adds the
behaviour in the first place, since that code does not presently exist
in git master.

  -ilia
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Re: [Mesa-dev] [PATCH] egl: adds EGL_KHR_reusable_sync to egl_dri

2016-03-21 Thread Marek Olšák 
On Wed, Mar 9, 2016 at 2:28 AM, Dongwon Kim  wrote:
> This patch enables an EGL extension, EGL_KHR_reusable_sync.
> This new extension basically provides a way for multiple APIs or
> threads to be excuted synchronously via a "reusable sync"
> primitive shared by those threads/API calls.
>
> This was implemented based on the specification at
>
> https://www.khronos.org/registry/egl/extensions/KHR/EGL_KHR_reusable_sync.txt
>
> Signed-off-by: Dongwon Kim 
> ---
>  src/egl/drivers/dri2/egl_dri2.c | 197 
> ++--
>  src/egl/drivers/dri2/egl_dri2.h |   2 +
>  src/egl/main/eglapi.c   |   8 ++
>  src/egl/main/eglsync.c  |   3 +-
>  4 files changed, 200 insertions(+), 10 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index 8f50f0c..78164e4 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -38,6 +38,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #ifdef HAVE_LIBDRM
>  #include 
>  #include 
> @@ -623,6 +625,8 @@ dri2_setup_screen(_EGLDisplay *disp)
>   disp->Extensions.KHR_cl_event2 = EGL_TRUE;
> }
>
> +   disp->Extensions.KHR_reusable_sync = EGL_TRUE;
> +
> if (dri2_dpy->image) {
>if (dri2_dpy->image->base.version >= 10 &&
>dri2_dpy->image->getCapabilities != NULL) {
> @@ -2389,14 +2393,33 @@ dri2_egl_ref_sync(struct dri2_egl_sync *sync)
> p_atomic_inc(>refcount);
>  }
>
> -static void
> +static EGLint
>  dri2_egl_unref_sync(struct dri2_egl_display *dri2_dpy,
>  struct dri2_egl_sync *dri2_sync)
>  {
> +   EGLint ret;
> +
> if (p_atomic_dec_zero(_sync->refcount)) {
> -  dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, dri2_sync->fence);
> +  /* mutex and cond should be freed if not freed yet. */
> +  if (dri2_sync->mutex)
> + free(dri2_sync->mutex);
> +
> +  if (dri2_sync->cond) {
> + ret = pthread_cond_destroy(dri2_sync->cond);
> +
> + if (ret)
> +return EGL_FALSE;
> +
> + free(dri2_sync->cond);
> +  }
> +
> +  if (dri2_sync->fence)
> + dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, 
> dri2_sync->fence);
> +
>free(dri2_sync);
> }
> +
> +   return EGL_TRUE;
>  }
>
>  static _EGLSync *
> @@ -2408,6 +2431,7 @@ dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy,
> struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx);
> struct dri2_egl_sync *dri2_sync;
> +   EGLint ret;
>
> dri2_sync = calloc(1, sizeof(struct dri2_egl_sync));
> if (!dri2_sync) {
> @@ -2450,6 +2474,23 @@ dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy,
>  dri2_sync->fence, 0, 0))
>   dri2_sync->base.SyncStatus = EGL_SIGNALED_KHR;
>break;
> +
> +   case EGL_SYNC_REUSABLE_KHR:
> +  dri2_sync->cond = calloc(1, sizeof(pthread_cond_t));
> +  dri2_sync->mutex = calloc(1, sizeof(pthread_mutex_t));
> +  ret = pthread_cond_init(dri2_sync->cond, NULL);
> +
> +  if (ret) {
> + _eglError(EGL_BAD_PARAMETER, "eglCreateSyncKHR");
> + free(dri2_sync->cond);
> + free(dri2_sync->mutex);
> + free(dri2_sync);
> + return NULL;
> +  }
> +
> +  /* initial status of reusable sync must be "unsignaled" */
> +  dri2_sync->base.SyncStatus = EGL_UNSIGNALED_KHR;
> +  break;
> }
>
> p_atomic_set(_sync->refcount, 1);
> @@ -2461,9 +2502,33 @@ dri2_destroy_sync(_EGLDriver *drv, _EGLDisplay *dpy, 
> _EGLSync *sync)
>  {
> struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> struct dri2_egl_sync *dri2_sync = dri2_egl_sync(sync);
> +   EGLint ret = EGL_TRUE;
> +   EGLint err;
>
> -   dri2_egl_unref_sync(dri2_dpy, dri2_sync);
> -   return EGL_TRUE;
> +   /* if type of sync is EGL_SYNC_REUSABLE_KHR and it is not signaled yet,
> +* then unlock all threads possibly blocked by the reusable sync before
> +* destroying it.
> +*/
> +   if (dri2_sync->base.Type == EGL_SYNC_REUSABLE_KHR &&
> +   dri2_sync->base.SyncStatus == EGL_UNSIGNALED_KHR) {
> +  dri2_sync->base.SyncStatus = EGL_SIGNALED_KHR;
> +  /* unblock all threads currently blocked by sync */
> +  ret = pthread_cond_broadcast(dri2_sync->cond);
> +
> +  if (ret) {
> + _eglError(EGL_BAD_PARAMETER, "eglDestroySyncKHR");
> + ret = EGL_FALSE;

BAD_PARAMETER is not the correct error for a pthread_cond_broadcast
failure. I'm not sure, but I think we shouldn't return an error in
this case, since the specification doesn't define an error for it.
According to pthread documentation, this error shouldn't occur if
dri2_sync->cond is valid, thus it shouldn't be an issue right?

Same for error handling of other pthread functions.

> +  }
> +   }
> +
> +   err = dri2_egl_unref_sync(dri2_dpy,

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