On 16 January 2018 at 21:57, Kenneth Graunke wrote:
> On Tuesday, January 16, 2018 11:18:13 AM PST Emil Velikov wrote:
>> Hi all,
>>
>> As you've know the Mesa 18.0.0 release plan has been available for a while
>> on the mesa3d.org website [1].
>>
>> In case you've missed
Quoting Ian Romanick (2018-01-16 09:39:07)
> On 01/12/2018 12:23 PM, Dylan Baker wrote:
> > Quoting Ian Romanick (2018-01-12 12:06:59)
> >> From: Ian Romanick
> >>
> >> This is useful for preparing data to go in a Mesa commit message.
> >>
> >> Signed-off-by: Ian
Your attached patch looks good to me. You can add my r-b to it.
Quoting Jon Turney (2018-01-15 11:50:04)
> On 12/01/2018 17:33, Dylan Baker wrote:
> > Maybe this is correct, but it makes me nervous treating with_gallium as
> > equivalent to with_dri, since gallium drivers can be built dri-less
>
Just wanted to see how things were going on this, especially for the meson bits
as I'd like to get them merged before the 18.0 merge window closes.
Quoting Greg V (2017-12-31 08:55:14)
> Hello everyone and happy new year! :)
>
> This set of patches makes the Meson build work on FreeBSD,
Currently there is not a separate option for setting the search path of
DRI drivers in meson, like there is in scons and autotools. This is an
oversight and needs to be fixed. This adds an extra option
`dri-search-path`, which will default to the value of
`dri-drivers-path`, like autotools does.
Reviewed-by: Dylan Baker
Quoting George Kyriazis (2018-01-16 13:25:45)
> cc: Dylan Baker
> ---
> src/gallium/drivers/swr/meson.build | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/gallium/drivers/swr/meson.build
>
Allow only bellagio or tizonia to be used at the same time.
Detect tizonia package config file
Generate libomx_mesa.so and install it to libtizcore.pc::pluginsdir
Only compile empty source (target.c) for now.
GSoC Project link:
https://summerofcode.withgoogle.com/projects/#4737166321123328
On Wed, Jan 17, 2018 at 8:22 PM, Leo Liu wrote:
> Hi Gurkirpal,
>
> Do we have patch 1 in the 6 patch set, or it hasn't arrived.
>
We do have a patch 1 which has been held for moderation for being too
large.
>
> Also I haven't seen the updates for Meson build in the current
I wasn't happy with the redundancy either but at the time just didn't see
how to refactor it more cleanly. I'll take a second pass to consolidate
and remove duplication.
- Chuck
On Tue, Jan 16, 2018 at 5:03 PM, Cherniak, Bruce
wrote:
>
> > On Jan 16, 2018, at 1:59
Am 16.01.2018 um 17:58 schrieb Emil Velikov:
On 5 January 2018 at 09:38, Christian König wrote:
Am 05.01.2018 um 10:36 schrieb Das, Indrajit-kumar:
From: Indrajit Das
Signed-off-by: Indrajit Das
Example Gstreamer pipeline :
MESA_ENABLE_OMX_EGLIMAGE=1 GST_GL_API=gles2 GST_GL_PLATFORM=egl gst-launch-1.0
filesrc location=movie.mp4 ! qtdemux ! h264parse ! omxh264dec ! glimagesink
Acked-by: Leo Liu
Reviewed-by: Julien Isorce
---
v2: Refactor out screen functions to st/omx
Example Gstreamer pipeline :
gst-launch-1.0 filesrc location=movie.mp4 ! qtdemux ! h264parse ! avdec_h264 !
videoconvert ! omxh264enc ! h264parse ! avdec_h264 ! videoconvert ! ximagesink
Acked-by: Leo Liu
Reviewed-by: Julien Isorce
Adds base files for adding components
Acked-by: Leo Liu
Reviewed-by: Julien Isorce
---
.../state_trackers/omx/tizonia/Makefile.sources| 4 ++-
.../state_trackers/omx/tizonia/entrypoint.c| 37 ++
On 17.01.2018 16:03, Emil Velikov wrote:
On 16 January 2018 at 21:57, Kenneth Graunke wrote:
On Tuesday, January 16, 2018 11:18:13 AM PST Emil Velikov wrote:
Hi all,
As you've know the Mesa 18.0.0 release plan has been available for a while
on the mesa3d.org website
On 01/17/2018 11:19 AM, Gurkirpal Singh wrote:
On Wed, Jan 17, 2018 at 8:22 PM, Leo Liu > wrote:
Hi Gurkirpal,
Do we have patch 1 in the 6 patch set, or it hasn't arrived.
We do have a patch 1 which has been held for moderation for being
On 01/17/2018 03:53 AM, Nicolai Hähnle wrote:
> On 12.01.2018 23:56, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> With the exception of NVIDIA hardware, these are is the values that all
>> hardware and Gallium want. The remapping is currently implemented in at
>>
On 17 January 2018 at 05:17, Brian Paul wrote:
> Both switch cases began with the same code.
Might even go a step further refactoring the common bits (say ~90%) of
the two functions into a helper.
One step at a time though - patch is a good start.
Reviewed-by: Emil Velikov
Hi Gurkirpal,
Do we have patch 1 in the 6 patch set, or it hasn't arrived.
Also I haven't seen the updates for Meson build in the current set.
@Dylan, if possible, could you give an update for the Meson build on the
current set?
Thanks,
Leo
On 01/17/2018 08:54 AM, Gurkirpal Singh
For the series:
Reviewed-by: Roland Scheidegger
Am 17.01.2018 um 06:18 schrieb Brian Paul:
> ---
> src/mesa/vbo/vbo_attrib.h | 100
> +++---
> 1 file changed, 50 insertions(+), 50 deletions(-)
>
> diff --git
The kernel is moving to a $class$instance naming scheme in preparation
for accommodating more rings in the future in a consistent manner. It is
already using the naming scheme internally, and now we are looking at
updating some soft-ABI such as the error state to use the new naming
scheme. This of
On 17.01.2018 13:34, Nicolai Hähnle wrote:
On 15.01.2018 13:31, Tapani Pälli wrote:
Hello;
Here's a refactored series of EGL_ANDROID_blob_cache. Now cache
functions are stored in disk_cache struct and the functionality
called within existing disk_cache put/get code. Problems/errors
that
On 17.01.2018 13:28, Nicolai Hähnle wrote:
On 16.01.2018 18:45, Emil Velikov wrote:
Hi Tapani,
On 15 January 2018 at 12:31, Tapani Pälli wrote:
+static void
+update_blob_cache_functions(struct dri2_egl_display *dri2_dpy,
+ struct
On Wed, Jan 17, 2018 at 6:44 AM, Mario Kleiner
wrote:
> On 01/17/2018 05:49 AM, Marek Olšák wrote:
>>
>> On Wed, Jan 17, 2018 at 3:21 AM, Mario Kleiner
>> wrote:
>>>
>>> On 01/16/2018 11:47 PM, Marek Olšák wrote:
Why?
>>>
>>>
On 17 January 2018 at 05:17, Brian Paul wrote:
> The values will never be larger than VBO_ATTRIB_MAX (currently 44).
Please add a STATIC_ASSERT (anywhere you like) so that we fail to
build if VBO_ATTRIB_MAX gets too large.
With that the whole series is:
Reviewed-by: Emil
Reviewed-by: Roland Scheidegger
Am 17.01.2018 um 06:18 schrieb Brian Paul:
> Both state->prog->info.inputs_read and state->InputsBound are GLbitfield64
> so it seems that the OR of those values should be of the same type.
> I'm not sure this fixes any actual issues though.
>
On 22 December 2017 at 23:05, Andres Gomez wrote:
> Mesa 17.2.8 is now available.
>
> In this release we have:
>
> The SPIR-V compiler has seen corrected a possible SEGFAULT.
>
> The Intel i965 driver includes a correction for Haswell involving
> doubles management.
>
> The AMD
On 17 January 2018 at 16:03, Tapani Pälli wrote:
>> - GLX/EGL
>> GLX_ARB_context_flush_control
>> EGL_KHR_context_flush_control
>> EGL_IMG_context_priority for freedreno
>> EGL_EXT_pixel_format_float, with 0 advertised float formats :-\
>
>
> I've been planning to revert
On 01/17/2018 09:39 AM, Brian Paul wrote:
> On 01/17/2018 10:08 AM, Ian Romanick wrote:
>> Should probably also change the assert(0) to unreachable(). It's
>> possible that will help the compiler generate slightly better code in
>> release builds.
>
> There's a bunch of assert(0) calls in the
On 01/17/2018 10:08 AM, Ian Romanick wrote:
Should probably also change the assert(0) to unreachable(). It's
possible that will help the compiler generate slightly better code in
release builds.
There's a bunch of assert(0) calls in the VBO code. How about I take
care of those in a separate
I sent one other tiny nit on patch 7. With or without that, the series is
Reviewed-by: Ian Romanick
On 01/17/2018 09:08 AM, Ian Romanick wrote:
> Should probably also change the assert(0) to unreachable(). It's
> possible that will help the compiler generate slightly
Reviewed-by: Ian Romanick
On 12/20/2017 11:27 AM, Francisco Jerez wrote:
> Previously the dataflow propagation algorithm would calculate the ACP
> live-in and -out sets in a two-pass fixed-point algorithm. The first
> pass would update the live-out sets of all basic
https://bugs.freedesktop.org/show_bug.cgi?id=103699
--- Comment #31 from Adam Jackson ---
To ssh://git.freedesktop.org/git/xorg/xserver
ebfb06b11..a13271f2f server-1.19-branch -> server-1.19-branch
--
You are receiving this mail because:
You are the QA Contact for the
Should probably also change the assert(0) to unreachable(). It's
possible that will help the compiler generate slightly better code in
release builds.
On 01/16/2018 09:17 PM, Brian Paul wrote:
> Both switch cases began with the same code.
> ---
> src/mesa/vbo/vbo_exec_draw.c | 15
Let's expose this only when we have formats. There are some
known issues when this is exposed without formats (on Android).
Signed-off-by: Tapani Pälli
---
src/egl/drivers/dri2/egl_dri2.c | 2 --
1 file changed, 2 deletions(-)
diff --git
On 01/16/2018 09:17 PM, Brian Paul wrote:
> ---
> src/mesa/vbo/vbo_exec_draw.c | 7 +++
> src/mesa/vbo/vbo_save_draw.c | 7 +++
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/vbo/vbo_exec_draw.c b/src/mesa/vbo/vbo_exec_draw.c
> index 5d1e588..68e9918 100644
On Wednesday, January 17, 2018 4:00:26 AM PST Nicolai Hähnle wrote:
> On 17.01.2018 01:23, Jordan Justen wrote:
> > On 2018-01-16 13:57:37, Kenneth Graunke wrote:
> >> On Tuesday, January 16, 2018 11:18:13 AM PST Emil Velikov wrote:
> >>> Hi all,
> >>>
> >>> As you've know the Mesa 18.0.0 release
On Tue, 2018-01-16 at 08:07 -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 4:57 AM, Iago Toral Quiroga > wrote:
> > From the Vulkan spec with KHX extensions:
> >
> >
> >
> > "If queries are used while executing a render pass instance that
> > has
> >
> >
Reseting to 4 would have only worked for dvec4, subtracting 4
from the original count will instead give us 6 when working with a
dvec3.
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c
Without this count will always be greater than 4 and we will always
set the writemask so the loop can never exit.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
---
src/amd/common/ac_nir_to_llvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c
On 01/16/2018 08:02 AM, Timothy Arceri wrote:
---
src/amd/common/ac_nir_to_llvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 4a80748e4e..0940dc82d8 100644
---
On 01/17/2018 02:34 AM, Bas Nieuwenhuizen wrote:
Which avoids setting or emitting them.
---
src/amd/vulkan/radv_cmd_buffer.c | 40 +++--
src/amd/vulkan/radv_pipeline.c | 64 +---
src/amd/vulkan/radv_private.h| 1 +
3 files
1-2:
Reviewed-by: Samuel Pitoiset
On 01/17/2018 02:34 AM, Bas Nieuwenhuizen wrote:
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.
---
src/amd/vulkan/radv_cmd_buffer.c | 34
https://bugs.freedesktop.org/show_bug.cgi?id=103538
--- Comment #8 from Henri Verbeet ---
(In reply to maister from comment #7)
> This might not be a bug after all. The app destroyed the X window before
> tearing down the swapchain, which is bogus, and probably where the
Can't this be moved into a new file? Or event better in AMD common code?
On 01/17/2018 02:34 AM, Bas Nieuwenhuizen wrote:
---
src/amd/vulkan/radv_pipeline.c | 66 ++
src/amd/vulkan/radv_private.h | 19
2 files changed, 85 insertions(+)
Series is,
Reviewed-by: Samuel Iglesias Gonsálvez
On 17/01/18 01:44, Ian Romanick wrote:
> This is the first series to resurrect some work that I started as long
> as 2.5 years ago. A lot of that work produced mixed bag results, but
> that was before nir_opt_algebraic.py
On 16.01.2018 19:45, Emil Velikov wrote:
Hi Tapani,
On 15 January 2018 at 12:31, Tapani Pälli wrote:
+static void
+update_blob_cache_functions(struct dri2_egl_display *dri2_dpy,
+struct dri2_egl_context *dri2_ctx)
+{
+ if (!dri2_dpy ||
On 16.01.2018 11:02, Jordan Justen wrote:
On 2018-01-15 04:31:42, Tapani Pälli wrote:
Signed-off-by: Tapani Pälli
---
src/mesa/drivers/dri/i965/brw_disk_cache.c | 2 ++
src/util/disk_cache.c | 2 ++
2 files changed, 4 insertions(+)
diff --git
If a shader only writes to an output via a constant initializer we
need to lower it before we call nir_remove_dead_variables so that
this pass sees the stores from the initializer and doesn't kill the
output.
Fixes test failures in new work-in-progress CTS tests:
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
---
src/amd/common/ac_nir_to_llvm.c | 46 +++--
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index
I put some alternative fixes together that make the test pass:
https://patchwork.freedesktop.org/series/36612/
On Wed, Jan 17, 2018 at 1:32 PM, Timothy Arceri wrote:
>
>
> On 17/01/18 22:36, Bas Nieuwenhuizen wrote:
>>
>> On Wed, Jan 17, 2018 at 10:47 AM, Timothy Arceri
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
---
src/amd/common/ac_nir_to_llvm.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 337dfdb5ec..12f7772a5c 100644
---
On 01/17/2018 08:42 AM, Ian Romanick wrote:
> On 01/17/2018 03:53 AM, Nicolai Hähnle wrote:
>> Fun fact #2: These values are simply a natural encoding of the operation
>> as a table of bit values. The result of the logic op is:
>>
>> result_bit = (logic_op >> (2 * src_bit + dst_bit)) & 1
>
> Oh
On 01/17/2018 07:20 AM, Emil Velikov wrote:
On 17 January 2018 at 05:17, Brian Paul wrote:
Both switch cases began with the same code.
Might even go a step further refactoring the common bits (say ~90%) of
the two functions into a helper.
One step at a time though - patch
On 17.01.2018 10:54, Timothy Arceri wrote:
On 17/01/18 20:47, Timothy Arceri wrote:
Reseting to 4 would have only worked for dvec4, subtracting 4
from the original count will instead give us 6 when working with a
Sorry that should be: "give us 2 when working with a dvec3"
With that, both
On 12.01.2018 23:56, Ian Romanick wrote:
From: Ian Romanick
With the exception of NVIDIA hardware, these are is the values that all
hardware and Gallium want. The remapping is currently implemented in at
least 6 places. This starts the process of consolidating to a
On 16.01.2018 22:18, Timothy Arceri wrote:
This resolves a game bug in Deal Island. The game doesn't properly
s/Deal/Dead/
Series is:
Reviewed-by: Nicolai Hähnle
handle ARB_get_program_binary with 0 supported formats, and ends up
crashing.
This will enable
On 11.01.2018 23:54, srol...@vmware.com wrote:
From: Roland Scheidegger
The command parser is very sad if we don't emit the relocs per hw query...
However, don't enable it. It mostly works, but piglit
arb_transform_feedback_overflow_query-basic shows 2 failures (it's
From the Vulkan spec with KHX extensions:
"If queries are used while executing a render pass instance that has
multiview enabled, the query uses N consecutive query indices
in the query pool (starting at query) where N is the number of bits
set in the view mask in the subpass the query
On 04.01.2018 18:37, Andres Rodriguez wrote:
On 2018-01-04 12:33 PM, Marek Olšák wrote:
Is the renaming necessary? It looks like everything would be fine if
we used the "fence" name for semaphores.
The rename was requested by nha. We could keep going with the fences
name. Or we could do
On 16.01.2018 08:02, Timothy Arceri wrote:
---
src/amd/common/ac_nir_to_llvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 4a80748e4e..0940dc82d8 100644
--- a/src/amd/common/ac_nir_to_llvm.c
For the series:
Reviewed-by: Nicolai Hähnle
On 17.01.2018 06:17, Brian Paul wrote:
The two headers already have the right extern "C" annotations.
---
src/compiler/glsl/serialize.cpp | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
On 17.01.2018 02:12, Ian Romanick wrote:
On 01/16/2018 10:11 AM, Ian Romanick wrote:
On 01/13/2018 01:47 PM, Jason Ekstrand wrote:
On January 12, 2018 14:56:26 "Ian Romanick" wrote:
From: Ian Romanick
With the exception of NVIDIA hardware,
Cool stuff :)
Except for a remark on patch #2, the series is:
Reviewed-by: Nicolai Hähnle
On 12.01.2018 04:55, Timothy Arceri wrote:
We still have more work to do but piglit results are looking
pretty good.
At GLSL 1.50 we have 30647/31118 piglit tests passing.
Al
On 17/01/18 22:36, Bas Nieuwenhuizen wrote:
On Wed, Jan 17, 2018 at 10:47 AM, Timothy Arceri wrote:
Without this count will always be greater than 4 and we will always
set the writemask so the loop can never exit.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO
On Wed, Jan 17, 2018 at 11:38 AM, Samuel Pitoiset
wrote:
> Can't this be moved into a new file? Or event better in AMD common code?
Would you think this is usable by radeonsi? They already have their
own PM4 structure integrating bo's as well (which are incompatible
On 16.01.2018 18:45, Emil Velikov wrote:
Hi Tapani,
On 15 January 2018 at 12:31, Tapani Pälli wrote:
+static void
+update_blob_cache_functions(struct dri2_egl_display *dri2_dpy,
+struct dri2_egl_context *dri2_ctx)
+{
+ if (!dri2_dpy ||
ARB_gl_spirv adds the ability to use SPIR-V binaries, and a new
method, glSpecializeShader. From OpenGL 4.6 spec, section 7.2.1
"Shader Specialization", error table:
INVALID_VALUE is generated if does not name a valid
entry point for .
INVALID_VALUE is generated if any element of
On Wed, Jan 17, 2018 at 10:47 AM, Timothy Arceri wrote:
> Without this count will always be greater than 4 and we will always
> set the writemask so the loop can never exit.
>
> Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
> ---
>
Why would this not work for dvec3? That is 6 elements, the intention
when writing this code was to do a 4 32-bit component store (hence
count=4), and then a 2 32-bit component store afterwards. The only
reason this apparently fails now is because we update the writemask
wrong here (intepret it as
https://bugs.freedesktop.org/show_bug.cgi?id=104655
--- Comment #1 from omin...@autistici.org ---
Created attachment 136802
--> https://bugs.freedesktop.org/attachment.cgi?id=136802=edit
240 Hz right side screen distortion picture
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https://bugs.freedesktop.org/show_bug.cgi?id=104655
--- Comment #2 from omin...@autistici.org ---
Created attachment 136803
--> https://bugs.freedesktop.org/attachment.cgi?id=136803=edit
240 Hz right side screen distortion video
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On 17/01/18 20:47, Timothy Arceri wrote:
Reseting to 4 would have only worked for dvec4, subtracting 4
from the original count will instead give us 6 when working with a
Sorry that should be: "give us 2 when working with a dvec3"
dvec3.
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file
https://bugs.freedesktop.org/show_bug.cgi?id=104655
Nicolai Hähnle changed:
What|Removed |Added
QA Contact|mesa-dev@lists.freedesktop. |
On 15.01.2018 13:31, Tapani Pälli wrote:
Hello;
Here's a refactored series of EGL_ANDROID_blob_cache. Now cache
functions are stored in disk_cache struct and the functionality
called within existing disk_cache put/get code. Problems/errors
that existed with earlier series are gone.
On Android
On 17.01.2018 06:18, Brian Paul wrote:
Both state->prog->info.inputs_read and state->InputsBound are GLbitfield64
so it seems that the OR of those values should be of the same type.
I'm not sure this fixes any actual issues though.
It's certainly less surprising this way.
Reviewed-by: Nicolai
On 17.01.2018 01:23, Jordan Justen wrote:
On 2018-01-16 13:57:37, Kenneth Graunke wrote:
On Tuesday, January 16, 2018 11:18:13 AM PST Emil Velikov wrote:
Hi all,
As you've know the Mesa 18.0.0 release plan has been available for a while
on the mesa3d.org website [1].
In case you've missed it
On 12.01.2018 03:55, Timothy Arceri wrote:
This shares mode code and calls the new shared load_tess_varyings()
s/mode/more/?
abi so that the radeonsi nir path now supports tcs output loads.
---
src/amd/common/ac_nir_to_llvm.c | 126 +---
1 file
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