Re: [Mesa-dev] [Mesa-stable] [PATCH] meson: don't use compiler.has_header

On Thu, 2018-03-29 at 11:20 -0700, Dylan Baker wrote: > This should be nominated for stable > Queued for next 18.0 stable release. J.A. > Quoting Dylan Baker (2018-03-12 11:23:23) > > Meson's compiler.has_header is completely useless, it only checks that a > > header exists, not

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

https://bugs.freedesktop.org/show_bug.cgi?id=105567 --- Comment #13 from Emil Velikov --- No sane project should depend on the .la files - that's why distros/packaging tools remove them by default. The only instances that come to mind are ones that use the libtools DL

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

https://bugs.freedesktop.org/show_bug.cgi?id=105567 --- Comment #12 from charlie --- Also, after the patch was applied, there was an odd behaviour when switching to an absolute path in my config. The install "remembered" my old config as if it used an old meson compiling

[Mesa-dev] [PATCH 1/3] nvc0: set current bufctx to nvc0->bufctx at the end of nvc0_draw_vbo()

It seems nvc0_hw_get_query_result_resource() expects nvc0->bufctx or nvc0->bufctx_* to be in effect. This is not guaranteed because nvc0_draw_vbo() previously set the current bufctx to NULL. Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 2

[Mesa-dev] [PATCH 0/3] nvc0: Various improvements to nvc0_hw_get_query_result_resource

This patch set applies improvements related to the query buffer object functionality of the nvc0 driver. Rhys Perry (3): nvc0: set current bufctx to nvc0->bufctx at the end of nvc0_draw_vbo() nvc0: rewrite query buffer write macro to output 64-bit predicates nvc0: use a macro to write query

[Mesa-dev] [PATCH 2/3] nvc0: rewrite query buffer write macro to output 64-bit predicates

Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/nvc0/mme/com9097.mme | 91 -- src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h | 64 --- src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 76 +++--- 3 files

[Mesa-dev] [PATCH 3/3] nvc0: use a macro to write query result availability to a buffer

Both the availability and result paths shared a bit of code so they were marged. Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/nvc0/mme/com9097.mme | 45 src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h | 34 ++

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

https://bugs.freedesktop.org/show_bug.cgi?id=105567 --- Comment #11 from charlie --- "1-2-bin-install_megadrivers-fix-DESTDIR-and--D--path.patch" allows files to be installed to DESTDIR when using absolute paths in config options. No extra driver files are generated other

Re: [Mesa-dev] [PATCH 1/3] radv: add radv_init_dcc_control_reg() helper

Reviewed-by: Bas Nieuwenhuizen On Wed, Apr 11, 2018 at 2:09 PM, Samuel Pitoiset wrote: > And add some comments. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 84

Re: [Mesa-dev] [PATCH] glsl: remove unreachable assert()

On 11/04/18 20:50, Emil Velikov wrote: On 10 April 2018 at 18:10, Jason Ekstrand wrote: On Tue, Apr 10, 2018 at 10:05 AM, Emil Velikov wrote: On 10 April 2018 at 17:53, Ivan Kalvachev wrote: On 3/28/18, Emil Velikov

[Mesa-dev] [PATCH 1/3] radv: add radv_init_dcc_control_reg() helper

And add some comments. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 84 ++-- 1 file changed, 52 insertions(+), 32 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 3/3] radv: always initialize DCC metadata to 0xFFFFFFFF

Not sure where the magic 0x20202020 value comes from but it's used since a while. AMDVLK also always initializes to 0x. When DCC for MSAA textures is enabled in my experimental branch, this appears to fix some CTS tests. No regressions on Polaris. Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH 2/3] radv: add radv_decompress_resolve_{subpass}_src() helpers

This helper shares common code before resolving using either a fragment or a compute shader. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta.h| 7 src/amd/vulkan/radv_meta_resolve.c| 58 +++

Re: [Mesa-dev] [PATCH 3/5] ac/nir: fix atomic compare-and-swap

Reviewed-by: Samuel Pitoiset On 04/11/2018 12:56 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle The LLVM instruction returns { i32, i1 }, where the i1 indicates success. We're only interested in the first part, which is the loaded value.

Re: [Mesa-dev] [PATCH] glsl: remove unreachable assert()

On 4/11/18, Ivan Kalvachev wrote: > On 4/11/18, Emil Velikov wrote: >> On 10 April 2018 at 18:10, Jason Ekstrand wrote: >>> On Tue, Apr 10, 2018 at 10:05 AM, Emil Velikov >>> >>> wrote: On

Re: [Mesa-dev] [PATCH] glsl: remove unreachable assert()

On 4/11/18, Emil Velikov wrote: > On 10 April 2018 at 18:10, Jason Ekstrand wrote: >> On Tue, Apr 10, 2018 at 10:05 AM, Emil Velikov >> wrote: >>> >>> On 10 April 2018 at 17:53, Ivan Kalvachev

[Mesa-dev] [PATCH 4/5] ac/nir: use ac_build_image_opcode for image intrinsics

From: Nicolai Hähnle So that we'll use the dimension-aware intrinsics in the future. --- src/amd/common/ac_llvm_build.c | 22 - src/amd/common/ac_llvm_build.h | 6 -- src/amd/common/ac_nir_to_llvm.c | 190 +--- 3 files

[Mesa-dev] [PATCH 5/5] amd/common: use the dimension-aware image intrinsics on LLVM 7+

From: Nicolai Hähnle Requires LLVM trunk r329166. --- src/amd/common/ac_llvm_build.c | 189 +++-- 1 file changed, 165 insertions(+), 24 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index

[Mesa-dev] [PATCH 2/5] amd/common: pass address components individually to ac_build_image_intrinsic

From: Nicolai Hähnle This is in preparation for the new image intrinsics. --- src/amd/common/ac_llvm_build.c | 101 +- src/amd/common/ac_llvm_build.h | 14 +- src/amd/common/ac_nir_to_llvm.c| 365

[Mesa-dev] [PATCH 3/5] radeonsi: generate image load/store/atomic ops using ac_build_image_opcode

From: Nicolai Hähnle In preparation of dimension-aware LLVM image intrinsics. --- src/amd/common/ac_llvm_build.c | 105 +++--- src/amd/common/ac_llvm_build.h | 37 +++- src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.h |

[Mesa-dev] [PATCH 0/5] amd/common: use dimension-aware image intrinsics for LLVM

Hi all, one of the things I've been recently working on is a new set of image intrinsics in LLVM to have explicit parameters for all the different components of the address argument. This is motivated by the A16 feature in gfx9, which allows address components (coordinates, explicit derivatives)

[Mesa-dev] [PATCH 1/5] amd/common: pass new enum ac_image_dim to ac_build_image_opcode

From: Nicolai Hähnle This is in preparation for the new, dimension-aware LLVM image intrinsics. --- src/amd/common/ac_llvm_build.c| 10 - src/amd/common/ac_llvm_build.h| 13 +- src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 1/5] glsl: prevent spurious Valgrind errors when serializing NIR

From: Nicolai Hähnle It looks as if the structure fields array is fully initialized below, but in fact at least gcc in debug builds will not actually overwrite the unused bits of bit fields. --- src/compiler/glsl_types.cpp | 6 -- 1 file changed, 4 insertions(+), 2

[Mesa-dev] [PATCH 3/5] ac/nir: fix atomic compare-and-swap

From: Nicolai Hähnle The LLVM instruction returns { i32, i1 }, where the i1 indicates success. We're only interested in the first part, which is the loaded value. Fixes dEQP-GLES31.functional.compute.shared_var.atomic.compswap.* --- src/amd/common/ac_nir_to_llvm.c | 1

[Mesa-dev] [PATCH 2/5] radeonsi: fix error paths of si_texture_transfer_map

From: Nicolai Hähnle trans is zero-initialized, but trans->resource is setup immediately so needs to be dereferenced. --- src/gallium/drivers/radeonsi/si_texture.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git

[Mesa-dev] [PATCH 5/5] radeonsi/nir: fix crash in test involving the sample mask

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 8c62d53e2ad..3e224b083e6 100644 ---

[Mesa-dev] [PATCH 4/5] radeonsi/nir: set FS properties only when scanning a fragment shader

From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader_nir.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index c0e08c79a56..b4fba8b8812 100644

[Mesa-dev] [PATCH 0/5] glsl,radeonsi/nir: misc fixes

Hi all, just a collection of random fixes I've accumulated over time, most of them stuff that I ran into while testing out NIR stuff. Please review! Thanks, Nicolai ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH] glsl: remove unreachable assert()

On 10 April 2018 at 18:10, Jason Ekstrand wrote: > On Tue, Apr 10, 2018 at 10:05 AM, Emil Velikov > wrote: >> >> On 10 April 2018 at 17:53, Ivan Kalvachev wrote: >> > On 3/28/18, Emil Velikov wrote:

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/vec4: Fix null destination register in 3-source instructions

On 04/11/2018 11:02 AM, Tapani Pälli wrote: On 04/11/2018 10:42 AM, Juan A. Suarez Romero wrote: On Fri, 2018-03-23 at 13:54 -0700, Ian Romanick wrote: From: Ian Romanick A recent commit (see below) triggered some cases where conditional modifier propagation and

Re: [Mesa-dev] [PATCH] ac/nir: Add workaround for GFX9 buffer views.

On Wed, Apr 4, 2018 at 10:19 PM, Bas Nieuwenhuizen wrote: > On GFX9 whether the buffer size is interpreted as elements or bytes > depends on whether IDXEN is enabled in the instruction. If the index > is a constant zero, LLVM optimizes IDXEN to 0. > > Now the size in

Re: [Mesa-dev] [PATCH] radv: Enable RB+ on Raven.

Reviewed-by: Samuel Pitoiset On 04/11/2018 01:37 AM, Bas Nieuwenhuizen wrote: --- src/amd/vulkan/radv_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

Re: [Mesa-dev] [Mesa-stable] [PATCH] egl/wayland: Make swrast display_sync the correct queue

On Thu, 2018-03-22 at 16:45 +, Eric Engestrom wrote: > On Thursday, 2018-03-22 15:28:49 +, Daniel Stone wrote: > > On 22 March 2018 at 15:20, Derek Foreman wrote: > > > commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface > > > queues, but the

Re: [Mesa-dev] [PATCH] radv: advertise 8 bits of subpixel precision for viewports

Agreed. Reviewed-by: Samuel Pitoiset On 04/11/2018 12:11 AM, Józef Kucia wrote: This is what radeonsi does. --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/vec4: Fix null destination register in 3-source instructions

On 04/11/2018 10:42 AM, Juan A. Suarez Romero wrote: On Fri, 2018-03-23 at 13:54 -0700, Ian Romanick wrote: From: Ian Romanick A recent commit (see below) triggered some cases where conditional modifier propagation and dead code elimination would cause a MAD

Re: [Mesa-dev] [PATCH] vulkan: fix build issue on android (both anv/radv)

Reviewed-by: Bas Nieuwenhuizen On Wed, Apr 11, 2018 at 9:29 AM, Tapani Pälli wrote: > Fixes linking errors against: > >anv_GetPhysicalDeviceImageFormatProperties2KHR >radv_GetPhysicalDeviceImageFormatProperties2KHR > > Signed-off-by:

Re: [Mesa-dev] [PATCH v2] dri3: Prevent multiple freeing of buffers.

Hi, Tested on KBL GT2. Before the patch, there are few dozen compiz segfaults during ~3 hours of testing. With the patched version there are no segfaults. Tested-by: Eero Tamminen - Eero On 10.04.2018 10:44, Sergii Romantsov wrote: Commit 3160cb86aa92

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/vec4: Fix null destination register in 3-source instructions

On Fri, 2018-03-23 at 13:54 -0700, Ian Romanick wrote: > From: Ian Romanick > > A recent commit (see below) triggered some cases where conditional > modifier propagation and dead code elimination would cause a MAD > instruction like the following to be generated: > >

[Mesa-dev] [PATCH] vulkan: fix build issue on android (both anv/radv)

Fixes linking errors against: anv_GetPhysicalDeviceImageFormatProperties2KHR radv_GetPhysicalDeviceImageFormatProperties2KHR Signed-off-by: Tapani Pälli --- src/amd/vulkan/radv_android.c | 6 +++--- src/intel/vulkan/anv_android.c | 4 ++-- 2 files changed, 5

Re: [Mesa-dev] How about vulkan status in Mesa

> -Original Message- > From: Palli, Tapani > Sent: Wednesday, April 11, 2018 3:15 PM > > On 04/11/2018 10:04 AM, Yuan, Feng wrote: > > > >> -Original Message- > >> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On > >> Behalf Of Tapani Pälli > >> > >> On

[Mesa-dev] [PATCH 05/11] intel/compiler: implement conversions from 16-bit int/float to bool

--- src/intel/compiler/brw_fs_nir.cpp | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5c414e45b61..ad31f7c82dc 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 11/11] anv/device: expose shaderInt16 support in gen8+

--- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 7522b7865c2..306d5beff7d 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -759,7 +759,7 @@

[Mesa-dev] [PATCH 08/11] intel/compiler: fix brw_negate_immediate for 16-bit types

From: Jose Maria Casanova Crespo 16-bit immediates are replicated in each word of a 32-bit value so we need to negate both. --- src/intel/compiler/brw_shader.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_shader.cpp

[Mesa-dev] [PATCH 06/11] nir/constant_folding: support 16-bit constants

From: Jose Maria Casanova Crespo --- src/compiler/nir/nir_opt_constant_folding.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index d6be807b3dc..b63660ea4da 100644 ---

[Mesa-dev] [PATCH 10/11] anv/pipeline: support SpvCapabilityInt16 in gen8+

--- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e64602d2844..be935363869 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -144,6 +144,7 @@

[Mesa-dev] [PATCH 09/11] compiler/spirv: add implementation to check for SpvCapabilityInt16 support

--- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index ababe520b2d..15a8910c597 100644 --- a/src/compiler/shader_info.h +++

[Mesa-dev] [PATCH 02/11] intel/compiler: fix isign for 16-bit integers

We need to use 16-bit constants with 16-bit instructions, otherwise we get the following validation error: "Destination stride must be equal to the ratio of the sizes of the execution data type to the destination type" Because the execution data type is 4B due to the 32-bit integer constant.

[Mesa-dev] [PATCH 00/11] anv: add shaderInt16 support

This series implements support for the shaderInt16 capability, which allows Vulkan applications to use 16-bit integers in shaders. A branch with these patches can be found in the 'itoral/shaderInt16ForReview' branch of the Igalia mesa repository at https://github.com/Igalia/mesa.git A lot of the

[Mesa-dev] [PATCH 01/11] intel/compiler: lower 16-bit integer extended math instructions

The hardware doesn't support 16-bit integer types, so we need to implement these using 32-bit integer instructions and then convert the result back to 16-bit. --- src/intel/Makefile.sources| 1 + src/intel/compiler/brw_nir.c | 2 +

[Mesa-dev] [PATCH 07/11] intel/compiler: implement nir_instr_type_load_const for 16-bit constants

From: Jose Maria Casanova Crespo --- src/intel/compiler/brw_fs_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index ad31f7c82dc..822a1ac4227 100644 ---

[Mesa-dev] [PATCH 04/11] intel/compiler: implement conversion between float/int 16-bit types

--- src/intel/compiler/brw_fs_nir.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5e0dd37eefd..5c414e45b61 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -791,10

[Mesa-dev] [PATCH 03/11] i965/compiler: handle conversion to smaller type in the lowering pass for that

The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. --- src/intel/compiler/brw_fs_lower_conversions.cpp | 5 - src/intel/compiler/brw_fs_nir.cpp | 14 +++--- 2 files changed, 7 insertions(+), 12

Re: [Mesa-dev] How about vulkan status in Mesa

On 04/11/2018 10:04 AM, Yuan, Feng wrote: -Original Message- From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf Of Tapani Pälli On 04/11/2018 09:01 AM, Yuan, Feng wrote: Hi, We have an image processing project libxcam (https://github.com/intel/libxcam/wiki)

Re: [Mesa-dev] How about vulkan status in Mesa

> -Original Message- > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf Of > Tapani Pälli > > On 04/11/2018 09:01 AM, Yuan, Feng wrote: > > Hi, > > > > We have an image processing project libxcam > > (https://github.com/intel/libxcam/wiki) which has been based on

Re: [Mesa-dev] How about vulkan status in Mesa

On 04/11/2018 09:01 AM, Yuan, Feng wrote: Hi, We have an image processing project libxcam (https://github.com/intel/libxcam/wiki) which has been based on OpenCL to support amount of features. Recently, we decide to porting kernels to GLES compute-shader language and based on Vulkan APIs.

Re: [Mesa-dev] [PATCH v2 1/3] nir: remove leftover return value when lowering to SSA

On Tue, Apr 10, 2018 at 11:13:38PM -0700, Caio Marcelo de Oliveira Filho wrote: > The return value was needed to make use of the old nir_foreach_block > helper, but not needed anymore with the macro version. Then go one > step further and move the foreach directly into the register variable > uses

[Mesa-dev] [PATCH v2 3/3] nir: simplify node matching code when lowering to SSA

The matching code doesn't make real use of the return value. The main function return value is ignored, and while the worker function propagate its return value, the actual callback never returns false. v2: Style fixes. (Jason) --- src/compiler/nir/nir_lower_vars_to_ssa.c | 67

[Mesa-dev] [PATCH v2 2/3] nir: remove unnecessary check when lowering to SSA

Only fully-qualified direct derefs, collected in direct_deref_nodes, are checked for aliasing, so it is already known up front that they have only array derefs of type direct. Reviewed-by: Jason Ekstrand --- This is really the same as v1, but with Reviewed-by and resent

[Mesa-dev] [PATCH v2 1/3] nir: remove leftover return value when lowering to SSA

The return value was needed to make use of the old nir_foreach_block helper, but not needed anymore with the macro version. Then go one step further and move the foreach directly into the register variable uses function. v2: Move foreach to register_variable_uses(). (Jason) Reviewed-by: Jason

Re: [Mesa-dev] [PATCH 3/3] nir: simplify node matching code when lowering to SSA

On Tue, Apr 10, 2018 at 10:15:45PM -0700, Jason Ekstrand wrote: > On Tue, Apr 10, 2018 at 12:52 PM, Caio Marcelo de Oliveira Filho < > caio.olive...@intel.com> wrote: > > > The matching code doesn't make real use of the return value. The main > > function return value is ignored, and while the

[Mesa-dev] How about vulkan status in Mesa

Hi, We have an image processing project libxcam (https://github.com/intel/libxcam/wiki) which has been based on OpenCL to support amount of features. Recently, we decide to porting kernels to GLES compute-shader language and based on Vulkan APIs. Certainly the driver is Mesa. There are my

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