Re: [Mesa-dev] issues with split llvm libraries and llvmpipe and failing to load library
On 12.02.2016 00:05, Nicolai Hähnle wrote: > On 10.02.2016 22:59, Dave Airlie wrote: >> >> So in Fedora rawhide we are now building llvm 3.7.1 into the lots of >> little shared libraries format. > > Barring all the other problems, are you sure this is a good idea? I > remember somebody mentioning that at least LLVM's own test suite runs > much slower in this build configuration. I didn't measure the LLVM testsuite wrt this, but I did measure that the split shared libraries increase the runtime of a single piglit test by about 0.02s, which for a full piglit run adds up to about 400 CPU core seconds, i.e. about 6.667 CPU core minutes. > I don't know whether this is "only" due to a slower startup time in > the dynamic linker or also due to slower compile times at runtime, but > it's probably worth measuring. I didn't investigate it in detail, but I assume it's the former. I don't know of any other significant difference between the two cases I measured. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/9] Types, types, and more types
On 2016-02-11 22:16:18, Jason Ekstrand wrote: > This little series expands the GLSL type system in preparation for SPIR-V. > The first few patches are to glsl_types and add a bare sampler type, > function types, and an image type helper. The rest flesh out the nir_types > C wrappers so that we can do almost anything from C that we can from C++. > > Jason Ekstrand (9): > glsl/types: Rename sampler_type to sampled_type > glsl/types: Add a bare "sampler" type > glsl/types: Add support for function types > glsl/types: Add a helper for getting image types 1-4 Reviewed-by: Jordan Justen > glsl/types: Expose glsl_struct_field and glsl_function_param to C > nir/types: Add helpers for function types > nir/types: Add helpers for working with sampler and image types > nir/types: Add a few more glsl_type_is_ functions > nir/types: Add more type constructor functions > > src/compiler/builtin_type_macros.h | 1 + > src/compiler/glsl/ast_to_hir.cpp| 5 +- > src/compiler/glsl/builtin_functions.cpp | 4 +- > src/compiler/glsl/ir.cpp| 2 +- > src/compiler/glsl/ir_clone.cpp | 1 + > src/compiler/glsl/link_uniform_initializers.cpp | 1 + > src/compiler/glsl_types.cpp | 204 > +++- > src/compiler/glsl_types.h | 38 - > src/compiler/nir_types.cpp | 144 + > src/compiler/nir_types.h| 38 + > src/mesa/drivers/dri/i965/brw_fs.cpp| 1 + > src/mesa/drivers/dri/i965/brw_fs_nir.cpp| 2 +- > src/mesa/drivers/dri/i965/brw_shader.cpp| 1 + > src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 + > src/mesa/program/ir_to_mesa.cpp | 2 + > src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 + > 16 files changed, 428 insertions(+), 18 deletions(-) > > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/4] i965: Consider tessellation in get_pipeline_state_l3_weights.
On Thursday, February 11, 2016 11:28:44 PM PST Francisco Jerez wrote:
> Kenneth Graunke writes:
>
> > I think this was just missed; Curro and I were probably writing
> > code simultaneously and forgot to combine them at the end.
> >
> > Signed-off-by: Kenneth Graunke
> > Reviewed-by: Jordan Justen
> > ---
> > src/mesa/drivers/dri/i965/gen7_l3_state.c | 7 ++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/
dri/i965/gen7_l3_state.c
> > index 0c1813f..c4babc2 100644
> > --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > @@ -298,7 +298,12 @@ static struct brw_l3_weights
> > get_pipeline_state_l3_weights(const struct brw_context *brw)
> > {
> > const struct brw_stage_state *stage_states[] = {
> > - &brw->vs.base, &brw->gs.base, &brw->wm.base, &brw->cs.base
> > + [MESA_SHADER_VERTEX] = &brw->vs.base,
> > + [MESA_SHADER_TESS_CTRL] = &brw->tcs.base,
> > + [MESA_SHADER_TESS_EVAL] = &brw->tes.base,
> > + [MESA_SHADER_GEOMETRY] = &brw->gs.base,
> > + [MESA_SHADER_FRAGMENT] = &brw->wm.base,
> > + [MESA_SHADER_COMPUTE] = &brw->cs.base
>
> Because the ordering of the stage_states entries is fully immaterial now
> (its just a set of brw_stage_state structs with no ordering implied),
> the designated initializers are pretty much just noise, would you mind
> leaving them out? With that changed this patch is:
>
> Reviewed-by: Francisco Jerez
Ah, sorry, I pushed it a few hours ago with Jordan's review...
The order definitely doesn't matter, but I thought the designated
initializers made it easy to see that they were all there.
I'm happy to remove them if you prefer, though. Want me to send
a follow-up patch to do that?
--Ken
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Re: [Mesa-dev] [PATCH 2/4] i965: Consider tessellation in get_pipeline_state_l3_weights.
Kenneth Graunke writes:
> I think this was just missed; Curro and I were probably writing
> code simultaneously and forgot to combine them at the end.
>
> Signed-off-by: Kenneth Graunke
> Reviewed-by: Jordan Justen
> ---
> src/mesa/drivers/dri/i965/gen7_l3_state.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> index 0c1813f..c4babc2 100644
> --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> @@ -298,7 +298,12 @@ static struct brw_l3_weights
> get_pipeline_state_l3_weights(const struct brw_context *brw)
> {
> const struct brw_stage_state *stage_states[] = {
> - &brw->vs.base, &brw->gs.base, &brw->wm.base, &brw->cs.base
> + [MESA_SHADER_VERTEX] = &brw->vs.base,
> + [MESA_SHADER_TESS_CTRL] = &brw->tcs.base,
> + [MESA_SHADER_TESS_EVAL] = &brw->tes.base,
> + [MESA_SHADER_GEOMETRY] = &brw->gs.base,
> + [MESA_SHADER_FRAGMENT] = &brw->wm.base,
> + [MESA_SHADER_COMPUTE] = &brw->cs.base
Because the ordering of the stage_states entries is fully immaterial now
(its just a set of brw_stage_state structs with no ordering implied),
the designated initializers are pretty much just noise, would you mind
leaving them out? With that changed this patch is:
Reviewed-by: Francisco Jerez
> };
> bool needs_dc = false, needs_slm = false;
>
> --
> 2.7.0
>
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Re: [Mesa-dev] [v2 03/19] i965: Don't try to create aux buffer for non-msrt aux-buffer
On Thu, Feb 11, 2016 at 01:41:47PM -0800, Ben Widawsky wrote:
> On Thu, Feb 11, 2016 at 08:33:56PM +0200, Topi Pohjolainen wrote:
> > In addition to simply calling miptree_create() the higher level
> > call intel_miptree_create() also considers if the buffer should
> > be associated with an auxiliary buffer based on the given format.
> >
> > Here we are allocating an auxiliary buffer which in turn has such
> > format that would mislead intel_miptree_create_layout() later on
> > to try to associate the auxiliary buffer with an auxiliary buffer.
> > To prevent this the actual buffer creation logic was split out
> > into its own function. Lets invoke that instead.
> >
> > v2 (Ben): Do not signal msaa layout with explicit argument but
> > using layout_flags instead.
> >
> > Signed-off-by: Topi Pohjolainen
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 20 ++--
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index e8b3116..e1cf15b 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -1541,16 +1541,16 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context
> > *brw,
> > if (brw->gen >= 8) {
> >layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
> > }
> > - mt->mcs_mt = intel_miptree_create(brw,
> > - mt->target,
> > - format,
> > - mt->first_level,
> > - mt->last_level,
> > - mcs_width,
> > - mcs_height,
> > - mt->logical_depth0,
> > - 0 /* num_samples */,
> > - layout_flags);
> > + mt->mcs_mt = miptree_create(brw,
> > + mt->target,
> > + format,
> > + mt->first_level,
> > + mt->last_level,
> > + mcs_width,
> > + mcs_height,
> > + mt->logical_depth0,
> > + 0 /* num_samples */,
> > + layout_flags);
> >
> > return mt->mcs_mt;
> > }
>
> Perhaps I am missing something here, but don't you need to have
> mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; ?
You are correct that it gets dropped - but it gets dropped for auxiliary
miptree where it doesn't make any difference. Fast clear is tracked in the
parent miptree and it's fast_clear_state is set as before. I toyed earlier
with the idea of having "lighter, needed members only" data type for
auxiliary buffers but didn't pursue that after all.
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Re: [Mesa-dev] [PATCH] i965: Make brw_clear_cache NULL out stale program pointers.
Kenneth Graunke writes: > The L3 partitioning code tries to look at all programs - both render > programs (VS/TCS/TES/GS/FS) and compute (CS). > > After calling brw_clear_cache, all prog_data pointers are invalid and > point to freed data. The intention was that flagging the dirty bits for > all programs would cause the next draw call to re-run the atoms for each > program stage, uploading new programs and installing new, valid pointers. > > However, this doesn't quite work in our new multi-pipeline world. When > drawing or dispatching a compute workload, we only consider the programs > for the appropriate pipeline: drawing sets up VS/TCS/TES/GS/FS, but not > CS, and vice versa. This leaves pointers dangling a bit longer than > intended. > > The L3 configuration code tries to inspect the prog_data for all shader > stages, so that we avoid having to reconfigure it when swapping back and > forth between render and compute workloads. So we can't have dangling > pointers. > > The fix is simple: have brw_clear_cache NULL out stale prog_data > pointers, making it safe to inspect. The next L3 configuration pass > will see either the render shaders or compute shader as missing for > one go around, but will pick them up when both pipelines have run. > > In other words, we'll simply reconfigure L3 twice, which is safe, > if a tiny bit wasteful - but then again, we just threw every compiled > shader we had on the floor and started recompiling the from scratch, > which is massively more wasteful, so it's not much of a concern. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790 > Signed-off-by: Kenneth Graunke > Cc: Francisco Jerez > Cc: Jordan Justen > --- > src/mesa/drivers/dri/i965/brw_state_cache.c | 15 +++ > 1 file changed, 15 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c > b/src/mesa/drivers/dri/i965/brw_state_cache.c > index ce178aa..c6aa134 100644 > --- a/src/mesa/drivers/dri/i965/brw_state_cache.c > +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c > @@ -393,6 +393,21 @@ brw_clear_cache(struct brw_context *brw, struct > brw_cache *cache) > brw->state.pipelines[BRW_RENDER_PIPELINE].brw = ~0ull; > brw->state.pipelines[BRW_COMPUTE_PIPELINE].mesa = ~0; > brw->state.pipelines[BRW_COMPUTE_PIPELINE].brw = ~0ull; > + > + /* Also, NULL out any stale program pointers. */ > + brw->vs.prog_data = NULL; > + brw->vs.base.prog_data = NULL; > + brw->tcs.prog_data = NULL; > + brw->tcs.base.prog_data = NULL; > + brw->tes.prog_data = NULL; > + brw->tes.base.prog_data = NULL; > + brw->gs.prog_data = NULL; > + brw->gs.base.prog_data = NULL; > + brw->wm.prog_data = NULL; > + brw->wm.base.prog_data = NULL; > + brw->cs.prog_data = NULL; > + brw->cs.base.prog_data = NULL; > + Thanks, this seems far more convincing, Reviewed-by: Francisco Jerez > intel_batchbuffer_flush(brw); > } > > -- > 2.7.0 signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
Matt Turner writes: > On Thu, Feb 11, 2016 at 7:31 PM, Francisco Jerez > wrote: >> Matt Turner writes: >> >>> On Thu, Feb 11, 2016 at 3:33 PM, Francisco Jerez >>> wrote: Would be really nice if we could also get rid of reg_offset as we're at it. reg and subreg_offset basically represent the same thing but with different units, couldn't we just have a single offset field in bytes? Should it be part of brw_reg or backend_reg? I think I would lean towards backend_reg. In that case does it make sense to move this into brw_reg now only to move it back to backend_reg later on? >>> >>> That would be nice. >>> >>> I'm just not sure how to do it. brw_reg has to have the subnr field, >>> and it's nice if that's the field the higher levels use too. >>> >> I guess at this point brw_reg is just an implementation detail of >> backend_reg, if some of it doesn't make sense at the IR level >> (e.g. because the IR wants more than 5 bits of sub-(V)GRF offset) >> there's no need to keep the IR tied up to the lower-level brw_reg >> representation. > > Do you have an example of where we might want a subreg_offset >= 32? reg_offset is basically a subreg_offset in 32B units, any use of reg_offset is a good example I guess. ;) > > I think using brw_reg is nice... it pretty simply contains the bits > that are common to the IR and the hardware. I'm not finding this limiting. I don't think it's limiting, but it's silly and error-prone to have two different fields with the exact same semantics but different units. It means anytime you need to find out what a register reads or writes you need to add two terms, and anytime you need to specify a register region you need to split up the offset in two terms (or use some of the helpers we have for that purpose, e.g. byte_offset(), *or* assume that your offset is a multiple of 32b as some places do which will blow up when we start doing sub-dword types more extensively). signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Make brw_clear_cache NULL out stale program pointers.
Reviewed-by: Jordan Justen On 2016-02-11 22:56:42, Kenneth Graunke wrote: > The L3 partitioning code tries to look at all programs - both render > programs (VS/TCS/TES/GS/FS) and compute (CS). > > After calling brw_clear_cache, all prog_data pointers are invalid and > point to freed data. The intention was that flagging the dirty bits for > all programs would cause the next draw call to re-run the atoms for each > program stage, uploading new programs and installing new, valid pointers. > > However, this doesn't quite work in our new multi-pipeline world. When > drawing or dispatching a compute workload, we only consider the programs > for the appropriate pipeline: drawing sets up VS/TCS/TES/GS/FS, but not > CS, and vice versa. This leaves pointers dangling a bit longer than > intended. > > The L3 configuration code tries to inspect the prog_data for all shader > stages, so that we avoid having to reconfigure it when swapping back and > forth between render and compute workloads. So we can't have dangling > pointers. > > The fix is simple: have brw_clear_cache NULL out stale prog_data > pointers, making it safe to inspect. The next L3 configuration pass > will see either the render shaders or compute shader as missing for > one go around, but will pick them up when both pipelines have run. > > In other words, we'll simply reconfigure L3 twice, which is safe, > if a tiny bit wasteful - but then again, we just threw every compiled > shader we had on the floor and started recompiling the from scratch, > which is massively more wasteful, so it's not much of a concern. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790 > Signed-off-by: Kenneth Graunke > Cc: Francisco Jerez > Cc: Jordan Justen > --- > src/mesa/drivers/dri/i965/brw_state_cache.c | 15 +++ > 1 file changed, 15 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c > b/src/mesa/drivers/dri/i965/brw_state_cache.c > index ce178aa..c6aa134 100644 > --- a/src/mesa/drivers/dri/i965/brw_state_cache.c > +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c > @@ -393,6 +393,21 @@ brw_clear_cache(struct brw_context *brw, struct > brw_cache *cache) > brw->state.pipelines[BRW_RENDER_PIPELINE].brw = ~0ull; > brw->state.pipelines[BRW_COMPUTE_PIPELINE].mesa = ~0; > brw->state.pipelines[BRW_COMPUTE_PIPELINE].brw = ~0ull; > + > + /* Also, NULL out any stale program pointers. */ > + brw->vs.prog_data = NULL; > + brw->vs.base.prog_data = NULL; > + brw->tcs.prog_data = NULL; > + brw->tcs.base.prog_data = NULL; > + brw->tes.prog_data = NULL; > + brw->tes.base.prog_data = NULL; > + brw->gs.prog_data = NULL; > + brw->gs.base.prog_data = NULL; > + brw->wm.prog_data = NULL; > + brw->wm.base.prog_data = NULL; > + brw->cs.prog_data = NULL; > + brw->cs.base.prog_data = NULL; > + > intel_batchbuffer_flush(brw); > } > > -- > 2.7.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nir: Lower ldexp to arithmetic.
This is a port of Matt's GLSL IR lowering pass to NIR. It's required
because we translate SPIR-V directly to NIR, bypassing GLSL IR.
I haven't introduced a lower_ldexp flag, as I believe all current NIR
consumers would set the flag. i965 wants this, vc4 doesn't implement
this feature, and st_glsl_to_tgsi currently lowers ldexp
unconditionally anyway.
v2: Use fabs and not iabs.
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir_opt_algebraic.py | 63 +++
1 file changed, 63 insertions(+)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index cc2c229..edab390 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -1,4 +1,5 @@
#! /usr/bin/env python
+# -*- encoding: utf-8 -*-
#
# Copyright (C) 2014 Intel Corporation
#
@@ -346,6 +347,68 @@ for op in ['flt', 'fge', 'feq', 'fne',
('bcsel', 'a', (op, 'd', 'b'), (op, 'd', 'c'))),
]
+def ldexp_to_arith(x, exp):
+ """
+ Translates
+ ldexp x exp
+ into
+
+ extracted_biased_exp = rshift(bitcast_f2i(abs(x)), exp_shift);
+ resulting_biased_exp = extracted_biased_exp + exp;
+
+ if (resulting_biased_exp < 1) {
+ return copysign(0.0, x);
+ }
+
+ return bitcast_u2f((bitcast_f2u(x) & sign_mantissa_mask) |
+ lshift(i2u(resulting_biased_exp), exp_shift));
+
+ which we can't actually implement as such, since NIR doesn't have
+ vectorized if-statements. We actually implement it without branches
+ using conditional-select:
+
+ extracted_biased_exp = rshift(bitcast_f2i(abs(x)), exp_shift);
+ resulting_biased_exp = extracted_biased_exp + exp;
+
+ is_not_zero_or_underflow = gequal(resulting_biased_exp, 1);
+ x = csel(is_not_zero_or_underflow, x, copysign(0.0f, x));
+ resulting_biased_exp = csel(is_not_zero_or_underflow,
+ resulting_biased_exp, 0);
+
+ return bitcast_u2f((bitcast_f2u(x) & sign_mantissa_mask) |
+ lshift(i2u(resulting_biased_exp), exp_shift));
+ """
+
+ sign_mask = 0x8000
+ exp_shift = 23
+ exp_width = 8
+
+ # Extract the biased exponent from .
+ extracted_biased_exp = ('ushr', ('fabs', x), exp_shift)
+ resulting_biased_exp = ('iadd', extracted_biased_exp, exp)
+
+ # Test if result is ±0.0, subnormal, or underflow by checking if the
+ # resulting biased exponent would be less than 0x1. If so, the result is
+ # 0.0 with the sign of x. (Actually, invert the conditions so that
+ # immediate values are the second arguments, which is better for i965)
+ zero_sign_x = ('iand', x, sign_mask)
+
+ is_not_zero_or_underflow = ('ige', resulting_biased_exp, 0x1)
+
+ # We could test for overflows by checking if the resulting biased exponent
+ # would be greater than 0xFE. Turns out we don't need to because the GLSL
+ # spec says:
+ #
+ #"If this product is too large to be represented in the
+ # floating-point type, the result is undefined."
+
+ return ('bitfield_insert',
+ ('bcsel', is_not_zero_or_underflow, x, zero_sign_x),
+ ('bcsel', is_not_zero_or_underflow, resulting_biased_exp, 0),
+ exp_shift, exp_width)
+
+optimizations += [(('ldexp', 'x', 'exp'), ldexp_to_arith('x', 'exp'))]
+
# This section contains "late" optimizations that should be run after the
# regular optimizations have finished. Optimizations should go here if
# they help code generation but do not necessarily produce code that is
--
2.7.1
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[Mesa-dev] [PATCH] i965: Make brw_clear_cache NULL out stale program pointers.
The L3 partitioning code tries to look at all programs - both render programs (VS/TCS/TES/GS/FS) and compute (CS). After calling brw_clear_cache, all prog_data pointers are invalid and point to freed data. The intention was that flagging the dirty bits for all programs would cause the next draw call to re-run the atoms for each program stage, uploading new programs and installing new, valid pointers. However, this doesn't quite work in our new multi-pipeline world. When drawing or dispatching a compute workload, we only consider the programs for the appropriate pipeline: drawing sets up VS/TCS/TES/GS/FS, but not CS, and vice versa. This leaves pointers dangling a bit longer than intended. The L3 configuration code tries to inspect the prog_data for all shader stages, so that we avoid having to reconfigure it when swapping back and forth between render and compute workloads. So we can't have dangling pointers. The fix is simple: have brw_clear_cache NULL out stale prog_data pointers, making it safe to inspect. The next L3 configuration pass will see either the render shaders or compute shader as missing for one go around, but will pick them up when both pipelines have run. In other words, we'll simply reconfigure L3 twice, which is safe, if a tiny bit wasteful - but then again, we just threw every compiled shader we had on the floor and started recompiling the from scratch, which is massively more wasteful, so it's not much of a concern. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790 Signed-off-by: Kenneth Graunke Cc: Francisco Jerez Cc: Jordan Justen --- src/mesa/drivers/dri/i965/brw_state_cache.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index ce178aa..c6aa134 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -393,6 +393,21 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache) brw->state.pipelines[BRW_RENDER_PIPELINE].brw = ~0ull; brw->state.pipelines[BRW_COMPUTE_PIPELINE].mesa = ~0; brw->state.pipelines[BRW_COMPUTE_PIPELINE].brw = ~0ull; + + /* Also, NULL out any stale program pointers. */ + brw->vs.prog_data = NULL; + brw->vs.base.prog_data = NULL; + brw->tcs.prog_data = NULL; + brw->tcs.base.prog_data = NULL; + brw->tes.prog_data = NULL; + brw->tes.base.prog_data = NULL; + brw->gs.prog_data = NULL; + brw->gs.base.prog_data = NULL; + brw->wm.prog_data = NULL; + brw->wm.base.prog_data = NULL; + brw->cs.prog_data = NULL; + brw->cs.base.prog_data = NULL; + intel_batchbuffer_flush(brw); } -- 2.7.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC] vc4: Remove logically dead variable 'handled_qinst_cond'
Rhys Kidd writes: > Variable no longer is read, and always set to true. > > Accordingly, the later assert() serves no active current purpose. The prior > limb of the test 'qinst->cond == QPU_COND_ALWAYS' will never trigger an > assert() > as is. If it did previously define a relevant test, this should be revisited > in a subsequent patch. Looks like just a typo, was supposed to be set to false at the top. Only the default case handles a cond on the qinst so far, so we want to be sure that we didn't try to put a cond on any other type of qinst. signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 8/9] nir/types: Add a few more glsl_type_is_ functions
---
src/compiler/nir_types.cpp | 18 ++
src/compiler/nir_types.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 89f1be5..2942810 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -158,6 +158,12 @@ glsl_type_is_void(const glsl_type *type)
}
bool
+glsl_type_is_error(const glsl_type *type)
+{
+ return type->is_error();
+}
+
+bool
glsl_type_is_vector(const struct glsl_type *type)
{
return type->is_vector();
@@ -182,6 +188,18 @@ glsl_type_is_matrix(const struct glsl_type *type)
}
bool
+glsl_type_is_array(const struct glsl_type *type)
+{
+ return type->is_array();
+}
+
+bool
+glsl_type_is_struct(const struct glsl_type *type)
+{
+ return type->is_record() || type->is_interface();
+}
+
+bool
glsl_type_is_sampler(const struct glsl_type *type)
{
return type->is_sampler();
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index e16dc4b..48927da 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -78,10 +78,13 @@ unsigned glsl_get_record_location_offset(const struct
glsl_type *type,
unsigned length);
bool glsl_type_is_void(const struct glsl_type *type);
+bool glsl_type_is_error(const struct glsl_type *type);
bool glsl_type_is_vector(const struct glsl_type *type);
bool glsl_type_is_scalar(const struct glsl_type *type);
bool glsl_type_is_vector_or_scalar(const struct glsl_type *type);
bool glsl_type_is_matrix(const struct glsl_type *type);
+bool glsl_type_is_array(const struct glsl_type *type);
+bool glsl_type_is_struct(const struct glsl_type *type);
bool glsl_type_is_sampler(const struct glsl_type *type);
bool glsl_type_is_image(const struct glsl_type *type);
bool glsl_sampler_type_is_shadow(const struct glsl_type *type);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 7/9] nir/types: Add helpers for working with sampler and image types
---
src/compiler/nir_types.cpp | 61 ++
src/compiler/nir_types.h | 14 +++
2 files changed, 75 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 17950cc..89f1be5 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -130,6 +130,20 @@ glsl_get_struct_elem_name(const struct glsl_type *type,
unsigned index)
return type->fields.structure[index].name;
}
+glsl_sampler_dim
+glsl_get_sampler_dim(const struct glsl_type *type)
+{
+ assert(glsl_type_is_sampler(type) || glsl_type_is_image(type));
+ return (glsl_sampler_dim)type->sampler_dimensionality;
+}
+
+glsl_base_type
+glsl_get_sampler_result_type(const struct glsl_type *type)
+{
+ assert(glsl_type_is_sampler(type) || glsl_type_is_image(type));
+ return (glsl_base_type)type->sampled_type;
+}
+
unsigned
glsl_get_record_location_offset(const struct glsl_type *type,
unsigned length)
@@ -167,6 +181,32 @@ glsl_type_is_matrix(const struct glsl_type *type)
return type->is_matrix();
}
+bool
+glsl_type_is_sampler(const struct glsl_type *type)
+{
+ return type->is_sampler();
+}
+
+bool
+glsl_type_is_image(const struct glsl_type *type)
+{
+ return type->is_image();
+}
+
+bool
+glsl_sampler_type_is_shadow(const struct glsl_type *type)
+{
+ assert(glsl_type_is_sampler(type));
+ return type->sampler_shadow;
+}
+
+bool
+glsl_sampler_type_is_array(const struct glsl_type *type)
+{
+ assert(glsl_type_is_sampler(type) || glsl_type_is_image(type));
+ return type->sampler_array;
+}
+
const glsl_type *
glsl_void_type(void)
{
@@ -204,6 +244,27 @@ glsl_array_type(const glsl_type *base, unsigned elements)
}
const glsl_type *
+const struct glsl_type *
+glsl_sampler_type(enum glsl_sampler_dim dim, bool is_shadow, bool is_array,
+ enum glsl_base_type base_type)
+{
+ return glsl_type::get_sampler_instance(dim, is_shadow, is_array, base_type);
+}
+
+const struct glsl_type *
+glsl_bare_sampler_type()
+{
+ return glsl_type::sampler_type;
+}
+
+const struct glsl_type *
+glsl_image_type(enum glsl_sampler_dim dim, bool is_array,
+enum glsl_base_type base_type)
+{
+ return glsl_type::get_image_instance(dim, is_array, base_type);
+}
+
+const glsl_type *
glsl_function_type(const glsl_type *return_type,
const glsl_function_param *params, unsigned num_params)
{
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 98228a0..e16dc4b 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -71,6 +71,9 @@ unsigned glsl_get_aoa_size(const struct glsl_type *type);
const char *glsl_get_struct_elem_name(const struct glsl_type *type,
unsigned index);
+enum glsl_sampler_dim glsl_get_sampler_dim(const struct glsl_type *type);
+enum glsl_base_type glsl_get_sampler_result_type(const struct glsl_type *type);
+
unsigned glsl_get_record_location_offset(const struct glsl_type *type,
unsigned length);
@@ -79,6 +82,10 @@ bool glsl_type_is_vector(const struct glsl_type *type);
bool glsl_type_is_scalar(const struct glsl_type *type);
bool glsl_type_is_vector_or_scalar(const struct glsl_type *type);
bool glsl_type_is_matrix(const struct glsl_type *type);
+bool glsl_type_is_sampler(const struct glsl_type *type);
+bool glsl_type_is_image(const struct glsl_type *type);
+bool glsl_sampler_type_is_shadow(const struct glsl_type *type);
+bool glsl_sampler_type_is_array(const struct glsl_type *type);
const struct glsl_type *glsl_void_type(void);
const struct glsl_type *glsl_float_type(void);
@@ -87,6 +94,13 @@ const struct glsl_type *glsl_vec4_type(void);
const struct glsl_type *glsl_uint_type(void);
const struct glsl_type *glsl_array_type(const struct glsl_type *base,
unsigned elements);
+const struct glsl_type *glsl_sampler_type(enum glsl_sampler_dim dim,
+ bool is_shadow, bool is_array,
+ enum glsl_base_type base_type);
+const struct glsl_type *glsl_bare_sampler_type();
+const struct glsl_type *glsl_image_type(enum glsl_sampler_dim dim,
+bool is_array,
+enum glsl_base_type base_type);
const struct glsl_type * glsl_function_type(const struct glsl_type
*return_type,
const struct glsl_function_param
*params,
unsigned num_params);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 5/9] glsl/types: Expose glsl_struct_field and glsl_function_param to C
---
src/compiler/glsl_types.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index b0ef031..2f612d8 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -820,6 +820,10 @@ private:
/*@}*/
};
+#undef DECL_TYPE
+#undef STRUCT_TYPE
+#endif /* __cplusplus */
+
struct glsl_struct_field {
const struct glsl_type *type;
const char *name;
@@ -877,6 +881,7 @@ struct glsl_struct_field {
unsigned image_volatile:1;
unsigned image_restrict:1;
+#ifdef __cplusplus
glsl_struct_field(const struct glsl_type *_type, const char *_name)
: type(_type), name(_name), location(-1), interpolation(0), centroid(0),
sample(0), matrix_layout(GLSL_MATRIX_LAYOUT_INHERITED), patch(0),
@@ -890,6 +895,7 @@ struct glsl_struct_field {
{
/* empty */
}
+#endif
};
struct glsl_function_param {
@@ -905,8 +911,4 @@ glsl_align(unsigned int a, unsigned int align)
return (a + align - 1) / align * align;
}
-#undef DECL_TYPE
-#undef STRUCT_TYPE
-#endif /* __cplusplus */
-
#endif /* GLSL_TYPES_H */
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 2/9] glsl/types: Add a bare "sampler" type
This is to be used by SPIR-V for representing a sampler that isn't attached to any particular image. In SPIR-V, all of the interesting bits such as dimensionality, sampled type, etc. come from the image, the bare "sampler" type simply uses a sampled type of VOID and 0 values for the rest. --- src/compiler/builtin_type_macros.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/builtin_type_macros.h b/src/compiler/builtin_type_macros.h index 7bd2e4e..da3f19e 100644 --- a/src/compiler/builtin_type_macros.h +++ b/src/compiler/builtin_type_macros.h @@ -78,6 +78,7 @@ DECL_TYPE(dmat3x4, GL_DOUBLE_MAT3x4, GLSL_TYPE_DOUBLE, 4, 3) DECL_TYPE(dmat4x2, GL_DOUBLE_MAT4x2, GLSL_TYPE_DOUBLE, 2, 4) DECL_TYPE(dmat4x3, GL_DOUBLE_MAT4x3, GLSL_TYPE_DOUBLE, 3, 4) +DECL_TYPE(sampler, GL_SAMPLER_1D, GLSL_TYPE_SAMPLER, GLSL_SAMPLER_DIM_1D, 0, 0, GLSL_TYPE_VOID) DECL_TYPE(sampler1D, GL_SAMPLER_1D, GLSL_TYPE_SAMPLER, GLSL_SAMPLER_DIM_1D, 0, 0, GLSL_TYPE_FLOAT) DECL_TYPE(sampler2D, GL_SAMPLER_2D, GLSL_TYPE_SAMPLER, GLSL_SAMPLER_DIM_2D, 0, 0, GLSL_TYPE_FLOAT) DECL_TYPE(sampler3D, GL_SAMPLER_3D, GLSL_TYPE_SAMPLER, GLSL_SAMPLER_DIM_3D, 0, 0, GLSL_TYPE_FLOAT) -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 0/9] Types, types, and more types
This little series expands the GLSL type system in preparation for SPIR-V. The first few patches are to glsl_types and add a bare sampler type, function types, and an image type helper. The rest flesh out the nir_types C wrappers so that we can do almost anything from C that we can from C++. Jason Ekstrand (9): glsl/types: Rename sampler_type to sampled_type glsl/types: Add a bare "sampler" type glsl/types: Add support for function types glsl/types: Add a helper for getting image types glsl/types: Expose glsl_struct_field and glsl_function_param to C nir/types: Add helpers for function types nir/types: Add helpers for working with sampler and image types nir/types: Add a few more glsl_type_is_ functions nir/types: Add more type constructor functions src/compiler/builtin_type_macros.h | 1 + src/compiler/glsl/ast_to_hir.cpp| 5 +- src/compiler/glsl/builtin_functions.cpp | 4 +- src/compiler/glsl/ir.cpp| 2 +- src/compiler/glsl/ir_clone.cpp | 1 + src/compiler/glsl/link_uniform_initializers.cpp | 1 + src/compiler/glsl_types.cpp | 204 +++- src/compiler/glsl_types.h | 38 - src/compiler/nir_types.cpp | 144 + src/compiler/nir_types.h| 38 + src/mesa/drivers/dri/i965/brw_fs.cpp| 1 + src/mesa/drivers/dri/i965/brw_fs_nir.cpp| 2 +- src/mesa/drivers/dri/i965/brw_shader.cpp| 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 + src/mesa/program/ir_to_mesa.cpp | 2 + src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 + 16 files changed, 428 insertions(+), 18 deletions(-) -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 9/9] nir/types: Add more type constructor functions
---
src/compiler/nir_types.cpp | 46 ++
src/compiler/nir_types.h | 12
2 files changed, 58 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 2942810..3669cfe 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -250,18 +250,56 @@ glsl_vec4_type(void)
}
const glsl_type *
+glsl_int_type(void)
+{
+ return glsl_type::int_type;
+}
+
+const glsl_type *
glsl_uint_type(void)
{
return glsl_type::uint_type;
}
const glsl_type *
+glsl_bool_type(void)
+{
+ return glsl_type::bool_type;
+}
+
+const glsl_type *
+glsl_scalar_type(enum glsl_base_type base_type)
+{
+ return glsl_type::get_instance(base_type, 1, 1);
+}
+
+const glsl_type *
+glsl_vector_type(enum glsl_base_type base_type, unsigned components)
+{
+ assert(components > 1 && components <= 4);
+ return glsl_type::get_instance(base_type, components, 1);
+}
+
+const glsl_type *
+glsl_matrix_type(enum glsl_base_type base_type, unsigned rows, unsigned
columns)
+{
+ assert(rows > 1 && rows <= 4 && columns >= 1 && columns <= 4);
+ return glsl_type::get_instance(base_type, rows, columns);
+}
+
+const glsl_type *
glsl_array_type(const glsl_type *base, unsigned elements)
{
return glsl_type::get_array_instance(base, elements);
}
const glsl_type *
+glsl_struct_type(const glsl_struct_field *fields,
+ unsigned num_fields, const char *name)
+{
+ return glsl_type::get_record_instance(fields, num_fields, name);
+}
+
const struct glsl_type *
glsl_sampler_type(enum glsl_sampler_dim dim, bool is_shadow, bool is_array,
enum glsl_base_type base_type)
@@ -288,3 +326,11 @@ glsl_function_type(const glsl_type *return_type,
{
return glsl_type::get_function_instance(return_type, params, num_params);
}
+
+const glsl_type *
+glsl_transposed_type(const struct glsl_type *type)
+{
+ assert(glsl_type_is_matrix(type));
+ return glsl_type::get_instance(type->base_type, type->matrix_columns,
+ type->vector_elements);
+}
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 48927da..18d64b7 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -94,9 +94,19 @@ const struct glsl_type *glsl_void_type(void);
const struct glsl_type *glsl_float_type(void);
const struct glsl_type *glsl_vec_type(unsigned n);
const struct glsl_type *glsl_vec4_type(void);
+const struct glsl_type *glsl_int_type(void);
const struct glsl_type *glsl_uint_type(void);
+const struct glsl_type *glsl_bool_type(void);
+
+const struct glsl_type *glsl_scalar_type(enum glsl_base_type base_type);
+const struct glsl_type *glsl_vector_type(enum glsl_base_type base_type,
+ unsigned components);
+const struct glsl_type *glsl_matrix_type(enum glsl_base_type base_type,
+ unsigned rows, unsigned columns);
const struct glsl_type *glsl_array_type(const struct glsl_type *base,
unsigned elements);
+const struct glsl_type *glsl_struct_type(const struct glsl_struct_field
*fields,
+ unsigned num_fields, const char
*name);
const struct glsl_type *glsl_sampler_type(enum glsl_sampler_dim dim,
bool is_shadow, bool is_array,
enum glsl_base_type base_type);
@@ -108,6 +118,8 @@ const struct glsl_type * glsl_function_type(const struct
glsl_type *return_type,
const struct glsl_function_param
*params,
unsigned num_params);
+const struct glsl_type *glsl_transposed_type(const struct glsl_type *type);
+
#ifdef __cplusplus
}
#endif
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 6/9] nir/types: Add helpers for function types
---
src/compiler/nir_types.cpp | 19 +++
src/compiler/nir_types.h | 9 +
2 files changed, 28 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index a87dcd8..17950cc 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -70,6 +70,18 @@ glsl_get_struct_field(const glsl_type *type, unsigned index)
return type->fields.structure[index].type;
}
+const glsl_type *
+glsl_get_function_return_type(const glsl_type *type)
+{
+ return type->fields.parameters[0].type;
+}
+
+const glsl_function_param *
+glsl_get_function_param(const glsl_type *type, unsigned index)
+{
+ return &type->fields.parameters[index + 1];
+}
+
const struct glsl_type *
glsl_get_column_type(const struct glsl_type *type)
{
@@ -190,3 +202,10 @@ glsl_array_type(const glsl_type *base, unsigned elements)
{
return glsl_type::get_array_instance(base, elements);
}
+
+const glsl_type *
+glsl_function_type(const glsl_type *return_type,
+ const glsl_function_param *params, unsigned num_params)
+{
+ return glsl_type::get_function_instance(return_type, params, num_params);
+}
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 32fc766..98228a0 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -50,6 +50,12 @@ const struct glsl_type *glsl_get_array_element(const struct
glsl_type *type);
const struct glsl_type *glsl_get_column_type(const struct glsl_type *type);
+const struct glsl_type *
+glsl_get_function_return_type(const struct glsl_type *type);
+
+const struct glsl_function_param *
+glsl_get_function_param(const struct glsl_type *type, unsigned index);
+
enum glsl_base_type glsl_get_base_type(const struct glsl_type *type);
unsigned glsl_get_vector_elements(const struct glsl_type *type);
@@ -81,6 +87,9 @@ const struct glsl_type *glsl_vec4_type(void);
const struct glsl_type *glsl_uint_type(void);
const struct glsl_type *glsl_array_type(const struct glsl_type *base,
unsigned elements);
+const struct glsl_type * glsl_function_type(const struct glsl_type
*return_type,
+const struct glsl_function_param
*params,
+unsigned num_params);
#ifdef __cplusplus
}
--
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[Mesa-dev] [PATCH 4/9] glsl/types: Add a helper for getting image types
---
src/compiler/glsl_types.cpp | 87 +
src/compiler/glsl_types.h | 2 ++
2 files changed, 89 insertions(+)
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 901baa3..c549230 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -720,6 +720,93 @@ glsl_type::get_sampler_instance(enum glsl_sampler_dim dim,
}
const glsl_type *
+glsl_type::get_image_instance(enum glsl_sampler_dim dim,
+ bool array, glsl_base_type type)
+{
+ switch (type) {
+ case GLSL_TYPE_FLOAT:
+ switch (dim) {
+ case GLSL_SAMPLER_DIM_1D:
+ return (array ? image1DArray_type : image1D_type);
+ case GLSL_SAMPLER_DIM_2D:
+ return (array ? image2DArray_type : image2D_type);
+ case GLSL_SAMPLER_DIM_3D:
+ return image3D_type;
+ case GLSL_SAMPLER_DIM_CUBE:
+ return (array ? imageCubeArray_type : imageCube_type);
+ case GLSL_SAMPLER_DIM_RECT:
+ if (array)
+return error_type;
+ else
+return image2DRect_type;
+ case GLSL_SAMPLER_DIM_BUF:
+ if (array)
+return error_type;
+ else
+return imageBuffer_type;
+ case GLSL_SAMPLER_DIM_MS:
+ return (array ? image2DMSArray_type : image2DMS_type);
+ case GLSL_SAMPLER_DIM_EXTERNAL:
+ return error_type;
+ }
+ case GLSL_TYPE_INT:
+ switch (dim) {
+ case GLSL_SAMPLER_DIM_1D:
+ return (array ? iimage1DArray_type : iimage1D_type);
+ case GLSL_SAMPLER_DIM_2D:
+ return (array ? iimage2DArray_type : iimage2D_type);
+ case GLSL_SAMPLER_DIM_3D:
+ if (array)
+return error_type;
+ return iimage3D_type;
+ case GLSL_SAMPLER_DIM_CUBE:
+ return (array ? iimageCubeArray_type : iimageCube_type);
+ case GLSL_SAMPLER_DIM_RECT:
+ if (array)
+return error_type;
+ return iimage2DRect_type;
+ case GLSL_SAMPLER_DIM_BUF:
+ if (array)
+return error_type;
+ return iimageBuffer_type;
+ case GLSL_SAMPLER_DIM_MS:
+ return (array ? iimage2DMSArray_type : iimage2DMS_type);
+ case GLSL_SAMPLER_DIM_EXTERNAL:
+ return error_type;
+ }
+ case GLSL_TYPE_UINT:
+ switch (dim) {
+ case GLSL_SAMPLER_DIM_1D:
+ return (array ? uimage1DArray_type : uimage1D_type);
+ case GLSL_SAMPLER_DIM_2D:
+ return (array ? uimage2DArray_type : uimage2D_type);
+ case GLSL_SAMPLER_DIM_3D:
+ if (array)
+return error_type;
+ return uimage3D_type;
+ case GLSL_SAMPLER_DIM_CUBE:
+ return (array ? uimageCubeArray_type : uimageCube_type);
+ case GLSL_SAMPLER_DIM_RECT:
+ if (array)
+return error_type;
+ return uimage2DRect_type;
+ case GLSL_SAMPLER_DIM_BUF:
+ if (array)
+return error_type;
+ return uimageBuffer_type;
+ case GLSL_SAMPLER_DIM_MS:
+ return (array ? uimage2DMSArray_type : uimage2DMS_type);
+ case GLSL_SAMPLER_DIM_EXTERNAL:
+ return error_type;
+ }
+ default:
+ return error_type;
+ }
+
+ unreachable("switch statement above should be complete");
+}
+
+const glsl_type *
glsl_type::get_array_instance(const glsl_type *base, unsigned array_size)
{
/* Generate a name using the base type pointer in the key. This is
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index 7bc0827..b0ef031 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -251,6 +251,8 @@ struct glsl_type {
bool array,
glsl_base_type type);
+ static const glsl_type *get_image_instance(enum glsl_sampler_dim dim,
+ bool array, glsl_base_type type);
/**
* Get the instance of an array type
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 3/9] glsl/types: Add support for function types
SPIR-V has a concept of a function type that's used fairly heavily. We
could special-case function types in SPIR-V -> NIR but it's easier if we
just add support to glsl_types.
---
src/compiler/glsl/ast_to_hir.cpp| 1 +
src/compiler/glsl/ir_clone.cpp | 1 +
src/compiler/glsl/link_uniform_initializers.cpp | 1 +
src/compiler/glsl_types.cpp | 105
src/compiler/glsl_types.h | 24 +-
src/mesa/drivers/dri/i965/brw_fs.cpp| 1 +
src/mesa/drivers/dri/i965/brw_shader.cpp| 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 +
src/mesa/program/ir_to_mesa.cpp | 2 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 +
10 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 3996b01..b639378 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -1135,6 +1135,7 @@ do_comparison(void *mem_ctx, int operation, ir_rvalue
*op0, ir_rvalue *op1)
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_ATOMIC_UINT:
case GLSL_TYPE_SUBROUTINE:
+ case GLSL_TYPE_FUNCTION:
/* I assume a comparison of a struct containing a sampler just
* ignores the sampler present in the type.
*/
diff --git a/src/compiler/glsl/ir_clone.cpp b/src/compiler/glsl/ir_clone.cpp
index 0965b0d..43b 100644
--- a/src/compiler/glsl/ir_clone.cpp
+++ b/src/compiler/glsl/ir_clone.cpp
@@ -373,6 +373,7 @@ ir_constant::clone(void *mem_ctx, struct hash_table *ht)
const
case GLSL_TYPE_ERROR:
case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_INTERFACE:
+ case GLSL_TYPE_FUNCTION:
assert(!"Should not get here.");
break;
}
diff --git a/src/compiler/glsl/link_uniform_initializers.cpp
b/src/compiler/glsl/link_uniform_initializers.cpp
index 58d21e5..3609f81 100644
--- a/src/compiler/glsl/link_uniform_initializers.cpp
+++ b/src/compiler/glsl/link_uniform_initializers.cpp
@@ -90,6 +90,7 @@ copy_constant_to_storage(union gl_constant_value *storage,
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_VOID:
case GLSL_TYPE_SUBROUTINE:
+ case GLSL_TYPE_FUNCTION:
case GLSL_TYPE_ERROR:
/* All other types should have already been filtered by other
* paths in the caller.
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index f412f89..901baa3 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -32,6 +32,7 @@ mtx_t glsl_type::mutex = _MTX_INITIALIZER_NP;
hash_table *glsl_type::array_types = NULL;
hash_table *glsl_type::record_types = NULL;
hash_table *glsl_type::interface_types = NULL;
+hash_table *glsl_type::function_types = NULL;
hash_table *glsl_type::subroutine_types = NULL;
void *glsl_type::mem_ctx = NULL;
@@ -174,6 +175,39 @@ glsl_type::glsl_type(const glsl_struct_field *fields,
unsigned num_fields,
mtx_unlock(&glsl_type::mutex);
}
+glsl_type::glsl_type(const glsl_type *return_type,
+ const glsl_function_param *params, unsigned num_params) :
+ gl_type(0),
+ base_type(GLSL_TYPE_FUNCTION),
+ sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
+ sampled_type(0), interface_packing(0),
+ vector_elements(0), matrix_columns(0),
+ length(num_params)
+{
+ unsigned int i;
+
+ mtx_lock(&glsl_type::mutex);
+
+ init_ralloc_type_ctx();
+
+ this->fields.parameters = rzalloc_array(this->mem_ctx,
+ glsl_function_param, num_params +
1);
+
+ /* We store the return type as the first parameter */
+ this->fields.parameters[0].type = return_type;
+ this->fields.parameters[0].in = false;
+ this->fields.parameters[0].out = true;
+
+ /* We store the i'th parameter in slot i+1 */
+ for (i = 0; i < length; i++) {
+ this->fields.parameters[i + 1].type = params[i].type;
+ this->fields.parameters[i + 1].in = params[i].in;
+ this->fields.parameters[i + 1].out = params[i].out;
+ }
+
+ mtx_unlock(&glsl_type::mutex);
+}
+
glsl_type::glsl_type(const char *subroutine_name) :
gl_type(0),
base_type(GLSL_TYPE_SUBROUTINE),
@@ -929,6 +963,74 @@ glsl_type::get_subroutine_instance(const char
*subroutine_name)
}
+static bool
+function_key_compare(const void *a, const void *b)
+{
+ const glsl_type *const key1 = (glsl_type *) a;
+ const glsl_type *const key2 = (glsl_type *) b;
+
+ if (key1->length != key2->length)
+ return 1;
+
+ return memcmp(key1->fields.parameters, key2->fields.parameters,
+ (key1->length + 1) * sizeof(*key1->fields.parameters)) == 0;
+}
+
+
+static uint32_t
+function_key_hash(const void *a)
+{
+ const glsl_type *const key = (glsl_type *) a;
+ char hash_key[128];
+ unsigned size = 0;
+
+ size = snprintf(hash_key, sizeof(hash_key), "%08x", key->length);
+
+ for (unsigned i = 0; i < key->length; i++) {
+
[Mesa-dev] [PATCH 1/9] glsl/types: Rename sampler_type to sampled_type
It's a bit more descriptive since it is the base type that you get when you
sample from it. Also, the next commit adds a bare "sampler" type and we
need glsl_type::sampler_type available for a public static member.
---
src/compiler/glsl/ast_to_hir.cpp | 4 ++--
src/compiler/glsl/builtin_functions.cpp | 4 ++--
src/compiler/glsl/ir.cpp | 2 +-
src/compiler/glsl_types.cpp | 12 ++--
src/compiler/glsl_types.h| 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index dbeb5c0..3996b01 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -2267,7 +2267,7 @@ get_type_name_for_precision_qualifier(const glsl_type
*type)
type->sampler_array + 2 * type->sampler_shadow;
const unsigned offset = type->base_type == GLSL_TYPE_SAMPLER ? 0 : 4;
assert(type_idx < 4);
- switch (type->sampler_type) {
+ switch (type->sampled_type) {
case GLSL_TYPE_FLOAT:
switch (type->sampler_dimensionality) {
case GLSL_SAMPLER_DIM_1D: {
@@ -2953,7 +2953,7 @@ apply_image_qualifier_to_variable(const struct
ast_type_qualifier *qual,
"used on image function parameters");
}
- if (qual->image_base_type != base_type->sampler_type) {
+ if (qual->image_base_type != base_type->sampled_type) {
_mesa_glsl_error(loc, state, "format qualifier doesn't match the "
"base data type of the image");
}
diff --git a/src/compiler/glsl/builtin_functions.cpp
b/src/compiler/glsl/builtin_functions.cpp
index 5512a33..f488434 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -2921,7 +2921,7 @@ builtin_builder::add_image_function(const char *name,
ir_function *f = new(mem_ctx) ir_function(name);
for (unsigned i = 0; i < ARRAY_SIZE(types); ++i) {
- if ((types[i]->sampler_type != GLSL_TYPE_FLOAT ||
+ if ((types[i]->sampled_type != GLSL_TYPE_FLOAT ||
(flags & IMAGE_FUNCTION_SUPPORTS_FLOAT_DATA_TYPE)) &&
(types[i]->sampler_dimensionality == GLSL_SAMPLER_DIM_MS ||
!(flags & IMAGE_FUNCTION_MS_ONLY)))
@@ -5238,7 +5238,7 @@ builtin_builder::_image_prototype(const glsl_type
*image_type,
unsigned flags)
{
const glsl_type *data_type = glsl_type::get_instance(
- image_type->sampler_type,
+ image_type->sampled_type,
(flags & IMAGE_FUNCTION_HAS_VECTOR_DATA_TYPE ? 4 : 1),
1);
const glsl_type *ret_type = (flags & IMAGE_FUNCTION_RETURNS_VOID ?
diff --git a/src/compiler/glsl/ir.cpp b/src/compiler/glsl/ir.cpp
index 5debca3..c7a2496 100644
--- a/src/compiler/glsl/ir.cpp
+++ b/src/compiler/glsl/ir.cpp
@@ -1442,7 +1442,7 @@ ir_texture::set_sampler(ir_dereference *sampler, const
glsl_type *type)
assert(sampler->type->base_type == GLSL_TYPE_SAMPLER);
assert(sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS);
} else {
- assert(sampler->type->sampler_type == (int) type->base_type);
+ assert(sampler->type->sampled_type == (int) type->base_type);
if (sampler->type->sampler_shadow)
assert(type->vector_elements == 4 || type->vector_elements == 1);
else
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 1458ad3..f412f89 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -50,7 +50,7 @@ glsl_type::glsl_type(GLenum gl_type,
gl_type(gl_type),
base_type(base_type),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
- sampler_type(0), interface_packing(0),
+ sampled_type(0), interface_packing(0),
vector_elements(vector_elements), matrix_columns(matrix_columns),
length(0)
{
@@ -74,7 +74,7 @@ glsl_type::glsl_type(GLenum gl_type, glsl_base_type base_type,
gl_type(gl_type),
base_type(base_type),
sampler_dimensionality(dim), sampler_shadow(shadow),
- sampler_array(array), sampler_type(type), interface_packing(0),
+ sampler_array(array), sampled_type(type), interface_packing(0),
length(0)
{
mtx_lock(&glsl_type::mutex);
@@ -100,7 +100,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields,
unsigned num_fields,
gl_type(0),
base_type(GLSL_TYPE_STRUCT),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
- sampler_type(0), interface_packing(0),
+ sampled_type(0), interface_packing(0),
vector_elements(0), matrix_columns(0),
length(num_fields)
{
@@ -140,7 +140,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields,
unsigned num_fields,
gl_type(0),
base_type(GLSL_TYPE_INTERFACE),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
- sampler_type(0), interface_packing((unsigned) packing),
+ sampl
Re: [Mesa-dev] [PATCH 6/7] glx: remove incorrect refcounting of DRIdrawable
On 12.02.2016 05:58, Miklós Máté wrote: > On 02/09/2016 05:02 PM, Ian Romanick wrote: >> On 02/08/2016 05:11 PM, Ian Romanick wrote: >>> On 02/05/2016 01:11 PM, Miklós Máté wrote: dri drawables must never be released when unbound from a context as long as their corresponding glx objects (window, pixmap, pbuffer) still exist >>> I'd really like to have Kristian weigh in, since DRI2 was his design, >>> and this is all his code being affected. That said, I'm a little unsure >>> about this change. >>> >>> The DRI drawables and associated resources will still get freed when the >>> application eventually calls glXDestroyPBuffer or glXDestroyWindow. >>> >>> But I'm not 100% sure what will happen with GLX 1.2 applications... >>> there are no glXDestroy* functions in GLX 1.2. In that case the >>> application will have a soft leak because calling XDestroyWindow won't >>> do anything on the client (or server?) for the DRI resources. I suspect >>> that's what this code was trying to prevent. >> And this commit affirms that: >> >> commit bf69ce37f0dcbb479078ee676d5100ac63e20750 >> Author: Stéphane Marchesin >> Date: Wed Jun 15 15:09:12 2011 -0700 >> >> glx: implement drawable refcounting. >> The current dri context unbind logic will leak drawables >> until the process >> dies (they will then get released by the GEM code). There are two >> ways to fix >> this: either always call driReleaseDrawables every time we unbind >> a context >> (but that costs us round trips to the X server at getbuffers() >> time) or >> implement proper drawable refcounting. This patch implements the >> latter. >> Signed-off-by: Antoine Labour >> Signed-off-by: Stéphane Marchesin >> Reviewed-by: Adam Jackson >> >> Since we don't have any way to know when the corresponding GLX object >> ceases to exist, we don't know when it's safe to destroy the DRI >> object. I don't know how we can not leak and not prematurely destroy >> the object. :( > That commit message exaggerates a little when it says "proper > refcounting", because it only refcounts on bind (in driFetchDrawable), > but not on create/destroy. With current Mesa the following happens: > create glXPbuffer: dri drawable is created, refcount=0 > bind it: refcount++ > unbind it: refcount--, drawable is destroyed > bind again: create new drawable, refcount=1 > unbind again: refcount--, drawable is destroyed > etc. Could that be fixed by starting with refcount=1 instead of 0? > They also say that "current unbind logic will leak drawables until the > process dies", which is simply not true. The glXDestroy* calls properly > dispose of the corresponding dri objects. > > With GLX 1.3 the dri drawables are correctly created and destroyed along > with their corresponding glx objects even without the above commit. IMHO > if someone deliberately uses GLX 1.2 or earlier, they know what they are > doing (1.3 was released in 1998). I'd say that it's never safe to > destroy a dri object until it's explicitly destroyed by the user, so I'm > still convinced that my patch is correct. Unless I'm missing something, one issue I see with your patch is that a DRI drawable could be destroyed while it's still current for a context. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 1/4] mapi_abi: Allow more dynamic entries
On 02/12/2016 07:32 AM, Matt Turner wrote: On Thu, Feb 11, 2016 at 9:27 PM, Tapani Pälli wrote: On 02/12/2016 02:04 AM, Emil Velikov wrote: On 11 February 2016 at 12:03, Tapani Pälli wrote: From: Bernard Kilarski Here we should have justification why this is needed. If there is a program affected (or bugzilla ticket opened) do mentioned it as well please. These patches are part of bigger set (which I try to help to reduce) from a internal customer branch with rather exotic stack and components. I'm not sure if there's anything better than "we need more dynamic entries to be available, current range is not enough" for justification here, does that suffice? No... we want to understand the code we're maintaining, and that means having justification for changes that go into Mesa. Well .. I guess in this case it's rather simple though. This is not about changing functionality but resizing a hardcoded table of available entries to be bigger so that caller of API can utilize more slots in dispatch table. This is how I understand the change. // Tapani ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/4] egl_dri2: set correct error code if swapbuffers fails
On Thu, Feb 11, 2016 at 4:03 AM, Tapani Pälli wrote:
> From: Daniel Czarnowski
>
> Signed-off-by: Matt Roper
> Cc: "11.0 11.1" ---
> src/egl/drivers/dri2/platform_x11.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/egl/drivers/dri2/platform_x11.c
> b/src/egl/drivers/dri2/platform_x11.c
> index 931ee51..7a26c38 100644
> --- a/src/egl/drivers/dri2/platform_x11.c
> +++ b/src/egl/drivers/dri2/platform_x11.c
> @@ -872,7 +872,11 @@ dri2_x11_swap_buffers(_EGLDriver *drv, _EGLDisplay
> *disp, _EGLSurface *draw)
> struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
>
> if (dri2_dpy->dri2) {
> - return dri2_x11_swap_buffers_msc(drv, disp, draw, 0, 0, 0) != -1;
> + if (dri2_x11_swap_buffers_msc(drv, disp, draw, 0, 0, 0) != -1)
Braces around nested if
> + return EGL_TRUE;
> + /* Swap failed with a window drawable. */
> + _eglError(EGL_BAD_NATIVE_WINDOW, __FUNCTION__);
> + return EGL_FALSE;
> } else {
>assert(dri2_dpy->swrast);
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Re: [Mesa-dev] [Mesa-stable] [PATCH 4/4] glx: fix error code when there is no context bound
On 02/12/2016 02:54 AM, Emil Velikov wrote:
On 11 February 2016 at 12:04, Tapani Pälli wrote:
From: Bernard Kilarski
Signed-off-by: Bernard Kilarski
Signed-off-by: Matt Roper
Cc: "11.0 11.1" psc, attribute, value);
@@ -166,7 +166,7 @@ glXQueryCurrentRendererStringMESA(int attribute)
{
struct glx_context *gc = __glXGetCurrentContext();
- if (gc == NULL)
+ if (gc == NULL || gc == &dummyContext)
Unless I'm missing something __glXGetCurrentContext() can never return
NULL, right ?
This was my initial impression also ... but I'm not sure what happens
here but unit tests (glx-test) for some reason completely explode if you
take out the null check and try running 'make check'.
I think that is why also the dummyContext is introduced in those tests.
I played around a bit with this change and linking phase with glx-test
starts to print quite weird errors, actually complete unrelated ones, I
guess because it cannot find the 'extern' declared 'dummyContext'. I'm
not sure if this is actually problem with the tests rather than this code.
In that case I see two possible solutions
- Swap all the NULL checks, for == &dummyContext (some commit
message would be great) or
- Drop the null checks in this patch, and explain why we do that only
here (the xid and vtable are implicitly zeroed for dummyContext, thus
things will just work).
Leaning for the latter for stable as it's shorter. Although doing the
former on top (for master alone) also sounds like a good idea imho.
return False;
return __glXQueryRendererString(gc->psc, attribute);
diff --git a/src/glx/tests/query_renderer_unittest.cpp
b/src/glx/tests/query_renderer_unittest.cpp
index 2f3c4ef..4c96260 100644
--- a/src/glx/tests/query_renderer_unittest.cpp
+++ b/src/glx/tests/query_renderer_unittest.cpp
@@ -40,6 +40,10 @@ struct attribute_test_vector {
#define E(x) { # x, x }
+/* This is necessary so that we don't have to link with glxcurrent.c
+ * which would require us to link with X libraries and what not.
+ */
+struct glx_context dummyContext;
Perhaps we should initialize it (like in glxcurrent.c) for
consistency, if anything else ?
-Emil
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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/4] mapi_abi: Allow more dynamic entries
On Thu, Feb 11, 2016 at 9:27 PM, Tapani Pälli wrote: > > > On 02/12/2016 02:04 AM, Emil Velikov wrote: >> >> On 11 February 2016 at 12:03, Tapani Pälli wrote: >>> >>> From: Bernard Kilarski >>> >> Here we should have justification why this is needed. If there is a >> program affected (or bugzilla ticket opened) do mentioned it as well >> please. >> > > These patches are part of bigger set (which I try to help to reduce) from a > internal customer branch with rather exotic stack and components. I'm not > sure if there's anything better than "we need more dynamic entries to be > available, current range is not enough" for justification here, does that > suffice? No... we want to understand the code we're maintaining, and that means having justification for changes that go into Mesa. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 3/4] egl_dri2: set correct error code if swapbuffers fails
On 02/12/2016 02:13 AM, Emil Velikov wrote:
On 11 February 2016 at 12:03, Tapani Pälli wrote:
From: Daniel Czarnowski
Signed-off-by: Matt Roper
Cc: "11.0 11.1" dri2) {
- return dri2_x11_swap_buffers_msc(drv, disp, draw, 0, 0, 0) != -1;
+ if (dri2_x11_swap_buffers_msc(drv, disp, draw, 0, 0, 0) != -1)
+ return EGL_TRUE;
+ /* Swap failed with a window drawable. */
+ _eglError(EGL_BAD_NATIVE_WINDOW, __FUNCTION__);
+ return EGL_FALSE;
Looking at the implementation of dri2_x11_swap_buffers_msc() and I'm
wondering if failing xcb_dri2_swap_buffers_reply() really means
"failed with window drawable". Can you please elaborate a bit and
stick it in the commit message ?
I can add here something like "A return value of '-1' means that there
was error during swap with a window drawable"? It's maybe not obvious as
dri2_x11_swap_buffers_msc is undocumented but it can be seen by
inspecting the function.
// Tapani
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Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
On Thu, Feb 11, 2016 at 7:31 PM, Francisco Jerez wrote: > Matt Turner writes: > >> On Thu, Feb 11, 2016 at 3:33 PM, Francisco Jerez >> wrote: >>> Would be really nice if we could also get rid of reg_offset as we're at >>> it. reg and subreg_offset basically represent the same thing but with >>> different units, couldn't we just have a single offset field in bytes? >>> Should it be part of brw_reg or backend_reg? I think I would lean >>> towards backend_reg. In that case does it make sense to move this into >>> brw_reg now only to move it back to backend_reg later on? >> >> That would be nice. >> >> I'm just not sure how to do it. brw_reg has to have the subnr field, >> and it's nice if that's the field the higher levels use too. >> > I guess at this point brw_reg is just an implementation detail of > backend_reg, if some of it doesn't make sense at the IR level > (e.g. because the IR wants more than 5 bits of sub-(V)GRF offset) > there's no need to keep the IR tied up to the lower-level brw_reg > representation. Do you have an example of where we might want a subreg_offset >= 32? I think using brw_reg is nice... it pretty simply contains the bits that are common to the IR and the hardware. I'm not finding this limiting. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 1/4] mapi_abi: Allow more dynamic entries
On 02/12/2016 02:04 AM, Emil Velikov wrote: On 11 February 2016 at 12:03, Tapani Pälli wrote: From: Bernard Kilarski Here we should have justification why this is needed. If there is a program affected (or bugzilla ticket opened) do mentioned it as well please. These patches are part of bigger set (which I try to help to reduce) from a internal customer branch with rather exotic stack and components. I'm not sure if there's anything better than "we need more dynamic entries to be available, current range is not enough" for justification here, does that suffice? // Tapani ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 2/4] egl_dri2: NULL check for xcb_dri2_get_buffers_reply()
On 02/12/2016 02:03 AM, Emil Velikov wrote: On 11 February 2016 at 12:03, Tapani Pälli wrote: From: Daniel Czarnowski Without the check, unsuccessful xcb_dri2_get_buffers_reply(...) causes segmentation fault in dri2_get_buffers. Signed-off-by: Matt Roper Cc: "11.0 11.1" Reviewed-by: Emil Velikov --- src/egl/drivers/dri2/platform_x11.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/platform_x11.c index 08cbf2d..931ee51 100644 --- a/src/egl/drivers/dri2/platform_x11.c +++ b/src/egl/drivers/dri2/platform_x11.c @@ -472,6 +472,8 @@ dri2_x11_get_buffers(__DRIdrawable * driDrawable, dri2_surf->drawable, count, count, attachments); reply = xcb_dri2_get_buffers_reply (dri2_dpy->conn, cookie, NULL); + if (reply == NULL) + return NULL; Looks great guys. Out of curiosity - did you notice this during inspection, or there was an application that triggered it ? Afaics there are a few other cases where we don't null check the reply before using it. Namely: src/egl/drivers/dri2/platform_x11.c:dri2_create_image_khr_pixmap(), buffers_reply -> bugzilla 93667 src/gallium/auxiliary/vl/vl_winsys_dri.c:vl_dri2_get_flush_reply(), "buffers_reply" Can you send patch(es) for those or shall I ? Feel free to go for these Emil. // Tapani ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC] vc4: Remove logically dead variable 'handled_qinst_cond'
Variable no longer is read, and always set to true.
Accordingly, the later assert() serves no active current purpose. The prior
limb of the test 'qinst->cond == QPU_COND_ALWAYS' will never trigger an assert()
as is. If it did previously define a relevant test, this should be revisited
in a subsequent patch.
Found with GCC warning:
mesa/src/gallium/drivers/vc4/vc4_qpu_emit.c: In function 'vc4_generate_code':
mesa/src/gallium/drivers/vc4/vc4_qpu_emit.c:315:22: warning: variable
'handled_qinst_cond' set but not used [-Wunused-but-set-variable]
bool handled_qinst_cond = true;
^
Signed-off-by: Rhys Kidd
---
src/gallium/drivers/vc4/vc4_qpu_emit.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c
b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index b06702af..2cac65e 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -312,8 +312,6 @@ vc4_generate_code(struct vc4_context *vc4, struct
vc4_compile *c)
break;
}
-bool handled_qinst_cond = true;
-
switch (qinst->op) {
case QOP_RCP:
case QOP_RSQ:
@@ -477,15 +475,11 @@ vc4_generate_code(struct vc4_context *vc4, struct
vc4_compile *c)
src[0], src[1]) | unpack);
set_last_cond_add(c, qinst->cond);
}
-handled_qinst_cond = true;
set_last_dst_pack(c, qinst);
break;
}
-assert(qinst->cond == QPU_COND_ALWAYS ||
- handled_qinst_cond);
-
if (qinst->sf) {
assert(!qir_is_multi_instruction(qinst));
*last_inst(c) |= QPU_SF;
--
2.5.0
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[Mesa-dev] [PATCH] vc4: Add missing braces in initializer
Silences the following GCC warning:
mesa/src/gallium/drivers/vc4/vc4_qir_schedule.c: In function
'qir_schedule_instructions':
mesa/src/gallium/drivers/vc4/vc4_qir_schedule.c:578:16: warning: missing braces
around initializer [-Wmissing-braces]
struct schedule_state state = { 0 };
^
Signed-off-by: Rhys Kidd
---
src/gallium/drivers/vc4/vc4_qir_schedule.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc4/vc4_qir_schedule.c
b/src/gallium/drivers/vc4/vc4_qir_schedule.c
index 2f280c5..ee1e9aa 100644
--- a/src/gallium/drivers/vc4/vc4_qir_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qir_schedule.c
@@ -575,7 +575,7 @@ void
qir_schedule_instructions(struct vc4_compile *c)
{
void *mem_ctx = ralloc_context(NULL);
-struct schedule_state state = { 0 };
+struct schedule_state state = { { 0 } };
if (debug) {
fprintf(stderr, "Pre-schedule instructions\n");
--
2.5.0
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[Mesa-dev] [Bug 94078] swrast-on-vgem not supported in dri3
https://bugs.freedesktop.org/show_bug.cgi?id=94078 --- Comment #2 from Dave Airlie --- yes I don't think this bug has been diagnosed except via handwaving yet. Though it does appear mutter is crashing inside glClear after my 5m of investigating. However further investigating is blocked on some llvm build problems in rawhide that I'm trying to clear first. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/4] i965: Make L3 partitioning code only use the current pipeline's shaders.
On Wednesday, February 10, 2016 12:10:41 PM PST Francisco Jerez wrote: > Kenneth Graunke writes: > > > When uploading state for the compute pipeline, we don't want to > > look at VS/TCS/TES/GS/FS programs, as they might be stale, and > > aren't relevant anyway. Likewise, the render pipeline shouldn't > > look at CS. > > The intended behaviour of this function is to look at the whole pipeline > state. The reason is that reprogramming the L3 is expensive and > selecting an L3 configuration that works for the whole pipeline avoids > an unnecessary L3 reprogramming on pipeline select if the bound shader > programs didn't change (or changed to a different program with the > similar L3 requirements). > > Regardless of its performance implications, it doesn't seem correct to > do this unless you can guarantee that the pipeline state is evaluated > again after pipeline select, which I don't think is the case right now. > > Anyway it seems like this is hiding a bug elsewhere. It smells rather > fishy that the brw_context structure can suddenly lose its consistency > anytime. brw_state_cache_check_size() frees the stage prog data > structures pointed to by the context and then leaves dangling pointers > pointing at the deallocated storage -- that seems like the real bug to > me. You need to set the prog data pointers to NULL when they become > invalid. If you do that get_pipeline_state_l3_weights() won't look at > them until the program switches back to the pipeline they belong to, at > which point the invalidated prog data structures will be regenerated and > BRW_NEW_XS_PROG_DATA will be signaled causing the L3 configuration to be > reevaluated. That makes a lot of sense. I've written a patch to do that instead, and it too solves the problem. I'll send it out shortly, assuming it passes the usual regression testing. --Ken signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 94078] swrast-on-vgem not supported in dri3
https://bugs.freedesktop.org/show_bug.cgi?id=94078 --- Comment #1 from Michel Dänzer --- Note that Xwayland (and by extension gnome-shell) should work perfectly fine without glamor/DRI3, so fixing the crash should be significantly easier than making glamor/DRI3 work with swrast. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
Matt Turner writes: > On Thu, Feb 11, 2016 at 3:33 PM, Francisco Jerez > wrote: >> Would be really nice if we could also get rid of reg_offset as we're at >> it. reg and subreg_offset basically represent the same thing but with >> different units, couldn't we just have a single offset field in bytes? >> Should it be part of brw_reg or backend_reg? I think I would lean >> towards backend_reg. In that case does it make sense to move this into >> brw_reg now only to move it back to backend_reg later on? > > That would be nice. > > I'm just not sure how to do it. brw_reg has to have the subnr field, > and it's nice if that's the field the higher levels use too. > I guess at this point brw_reg is just an implementation detail of backend_reg, if some of it doesn't make sense at the IR level (e.g. because the IR wants more than 5 bits of sub-(V)GRF offset) there's no need to keep the IR tied up to the lower-level brw_reg representation. > I wonder -- is it possible that we could just get rid of reg_offset > too? For gathering data we have load_payload, so it's not useful > there. I think it's mainly useful for accessing elements of texturing > results. Is doubt there is a way we could avoid that though? signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
Kenneth Graunke writes: > On Thursday, February 11, 2016 5:49:55 PM PST Matt Turner wrote: >> On Thu, Feb 11, 2016 at 3:33 PM, Francisco Jerez > wrote: >> > Would be really nice if we could also get rid of reg_offset as we're at >> > it. reg and subreg_offset basically represent the same thing but with >> > different units, couldn't we just have a single offset field in bytes? >> > Should it be part of brw_reg or backend_reg? I think I would lean >> > towards backend_reg. In that case does it make sense to move this into >> > brw_reg now only to move it back to backend_reg later on? >> >> That would be nice. >> >> I'm just not sure how to do it. brw_reg has to have the subnr field, >> and it's nice if that's the field the higher levels use too. >> >> I wonder -- is it possible that we could just get rid of reg_offset >> too? For gathering data we have load_payload, so it's not useful >> there. I think it's mainly useful for accessing elements of texturing >> results. Is doubt there is a way we could avoid that though? > > I disagree - I don't think this would be nice at all. > > When we designed the IR, we needed something to handle cases like > texturing results, where we actually need to store a whole vec4, > and can't break it into separate scalar components. (Note that > messages used MRFs; we didn't even know about send-from-GRF.) > > To handle this, Eric created an abstraction of "virtual registers with > size > 1", where we basically have an array of registers, each of which > holds a single scalar value. It can be thought of as a vecN, and > reg_offset is the array index - v[i] - selecting each of the logically > contiguous components. reg_offset only makes sense on these large > virtual registers - it has no meaning for real hardware registers. > > In contrast, subreg_offset (which came later) offered a way to access > particular channels of a single hardware register, such as g0.2. We > added this later to make the IR more expressive. > > While these are both offsets, they serve very different purposes. > That hasn't been the case for a while, reg_offset is expressed in multiples of a GRF, IOW it's just subreg_offset in different units, there's no point in keeping both of them around, and it makes things unnecessarily difficult and error-prone to have to take both of them into account anytime you need to find out e.g. what region of a VGRF a backend_reg refers to. One of them needs to die IMO. > Replacing subreg_offset with subnr makes a lot of sense to me, as > both are basically a way to provide a byte offset for the start of > a register region, allowing unaligned register access. But reg_offset > is a different beast. > > If you want to be rid of it, then perhaps we should consider removing > the "VGRF of size > 1" abstraction. One could imagine a system where > we allocate separate VRFs for each scalar value, but record that > "VRFs 4, 12, and 63 need to be contiguous", passing that information > to the register allocator. There are certainly other fine approaches. > I don't think I see what the benefit would be of replacing multi-component VGRFs with such a thing. Definitely a lot more work than unifying reg_ and subreg_offset. > I would also humbly request that you wait until FP64 lands before making > any major changes. It's very easy to conflate type size, number of SIMD > channels, and register offsets, and a lot of the FP64 work is fixing > places that are confused about that. I'd really like to avoid making > our Igalia friends' lives harder by making them rebase 100 patches on > IR redesigns. > > --Ken signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
On Thursday, February 11, 2016 5:49:55 PM PST Matt Turner wrote: > On Thu, Feb 11, 2016 at 3:33 PM, Francisco Jerez wrote: > > Would be really nice if we could also get rid of reg_offset as we're at > > it. reg and subreg_offset basically represent the same thing but with > > different units, couldn't we just have a single offset field in bytes? > > Should it be part of brw_reg or backend_reg? I think I would lean > > towards backend_reg. In that case does it make sense to move this into > > brw_reg now only to move it back to backend_reg later on? > > That would be nice. > > I'm just not sure how to do it. brw_reg has to have the subnr field, > and it's nice if that's the field the higher levels use too. > > I wonder -- is it possible that we could just get rid of reg_offset > too? For gathering data we have load_payload, so it's not useful > there. I think it's mainly useful for accessing elements of texturing > results. Is doubt there is a way we could avoid that though? I disagree - I don't think this would be nice at all. When we designed the IR, we needed something to handle cases like texturing results, where we actually need to store a whole vec4, and can't break it into separate scalar components. (Note that messages used MRFs; we didn't even know about send-from-GRF.) To handle this, Eric created an abstraction of "virtual registers with size > 1", where we basically have an array of registers, each of which holds a single scalar value. It can be thought of as a vecN, and reg_offset is the array index - v[i] - selecting each of the logically contiguous components. reg_offset only makes sense on these large virtual registers - it has no meaning for real hardware registers. In contrast, subreg_offset (which came later) offered a way to access particular channels of a single hardware register, such as g0.2. We added this later to make the IR more expressive. While these are both offsets, they serve very different purposes. Replacing subreg_offset with subnr makes a lot of sense to me, as both are basically a way to provide a byte offset for the start of a register region, allowing unaligned register access. But reg_offset is a different beast. If you want to be rid of it, then perhaps we should consider removing the "VGRF of size > 1" abstraction. One could imagine a system where we allocate separate VRFs for each scalar value, but record that "VRFs 4, 12, and 63 need to be contiguous", passing that information to the register allocator. There are certainly other fine approaches. I would also humbly request that you wait until FP64 lands before making any major changes. It's very easy to conflate type size, number of SIMD channels, and register offsets, and a lot of the FP64 work is fixing places that are confused about that. I'd really like to avoid making our Igalia friends' lives harder by making them rebase 100 patches on IR redesigns. --Ken signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 4/4] glx: fix error code when there is no context bound
On Thu, Feb 11, 2016 at 4:54 PM, Emil Velikov wrote:
> On 11 February 2016 at 12:04, Tapani Pälli wrote:
>> From: Bernard Kilarski
>>
>> Signed-off-by: Bernard Kilarski
>> Signed-off-by: Matt Roper
>> Cc: "11.0 11.1" > ---
>> src/glx/glxcmds.c | 2 +-
>> src/glx/query_renderer.c | 4 ++--
>> src/glx/tests/query_renderer_unittest.cpp | 4
>> 3 files changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
>> index 93e8db5..4db67ec 100644
>> --- a/src/glx/glxcmds.c
>> +++ b/src/glx/glxcmds.c
>> @@ -1727,7 +1727,7 @@ __glXSwapIntervalSGI(int interval)
>> CARD32 *interval_ptr;
>> CARD8 opcode;
>>
>> - if (gc == NULL) {
>> + if (gc == NULL || gc == &dummyContext) {
>>return GLX_BAD_CONTEXT;
>> }
>>
>> diff --git a/src/glx/query_renderer.c b/src/glx/query_renderer.c
>> index 9108ec2..d49b8fe 100644
>> --- a/src/glx/query_renderer.c
>> +++ b/src/glx/query_renderer.c
>> @@ -106,7 +106,7 @@ glXQueryCurrentRendererIntegerMESA(int attribute,
>> unsigned int *value)
>> {
>> struct glx_context *gc = __glXGetCurrentContext();
>>
>> - if (gc == NULL)
>> + if (gc == NULL || gc == &dummyContext)
>>return False;
>>
>> return __glXQueryRendererInteger(gc->psc, attribute, value);
>> @@ -166,7 +166,7 @@ glXQueryCurrentRendererStringMESA(int attribute)
>> {
>> struct glx_context *gc = __glXGetCurrentContext();
>>
>> - if (gc == NULL)
>> + if (gc == NULL || gc == &dummyContext)
> Unless I'm missing something __glXGetCurrentContext() can never return
> NULL, right ?
>
> In that case I see two possible solutions
> - Swap all the NULL checks, for == &dummyContext (some commit
> message would be great) or
> - Drop the null checks in this patch, and explain why we do that only
> here (the xid and vtable are implicitly zeroed for dummyContext, thus
> things will just work).
>
> Leaning for the latter for stable as it's shorter. Although doing the
> former on top (for master alone) also sounds like a good idea imho.
>
>>return False;
>>
>> return __glXQueryRendererString(gc->psc, attribute);
>> diff --git a/src/glx/tests/query_renderer_unittest.cpp
>> b/src/glx/tests/query_renderer_unittest.cpp
>> index 2f3c4ef..4c96260 100644
>> --- a/src/glx/tests/query_renderer_unittest.cpp
>> +++ b/src/glx/tests/query_renderer_unittest.cpp
>> @@ -40,6 +40,10 @@ struct attribute_test_vector {
>> #define E(x) { # x, x }
>>
>>
>> +/* This is necessary so that we don't have to link with glxcurrent.c
>> + * which would require us to link with X libraries and what not.
>> + */
>> +struct glx_context dummyContext;
>>
> Perhaps we should initialize it (like in glxcurrent.c) for
> consistency, if anything else ?
Global variables are initialized. :)
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Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
On Thu, Feb 11, 2016 at 3:33 PM, Francisco Jerez wrote: > Would be really nice if we could also get rid of reg_offset as we're at > it. reg and subreg_offset basically represent the same thing but with > different units, couldn't we just have a single offset field in bytes? > Should it be part of brw_reg or backend_reg? I think I would lean > towards backend_reg. In that case does it make sense to move this into > brw_reg now only to move it back to backend_reg later on? That would be nice. I'm just not sure how to do it. brw_reg has to have the subnr field, and it's nice if that's the field the higher levels use too. I wonder -- is it possible that we could just get rid of reg_offset too? For gathering data we have load_payload, so it's not useful there. I think it's mainly useful for accessing elements of texturing results. Is doubt there is a way we could avoid that though? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: allow DEPTH_STENCIL_TEXTURE_MODE queries in GLES 3.1 contexts
On Thu, Feb 11, 2016 at 03:22:35PM -0500, Ilia Mirkin wrote:
Reviewed-by: Nanley Chery
> This fixes
>
> dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.depth_stencil_mode_integer
>
> and a few related tests.
>
> Signed-off-by: Ilia Mirkin
> ---
> src/mesa/main/texparam.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
> index 89f286c..ed83830 100644
> --- a/src/mesa/main/texparam.c
> +++ b/src/mesa/main/texparam.c
> @@ -500,9 +500,7 @@ set_tex_parameteri(struct gl_context *ctx,
>goto invalid_pname;
>
> case GL_DEPTH_STENCIL_TEXTURE_MODE:
> - if ((_mesa_is_desktop_gl(ctx) &&
> - ctx->Extensions.ARB_stencil_texturing) ||
> - _mesa_is_gles31(ctx)) {
> + if (_mesa_has_ARB_stencil_texturing(ctx) || _mesa_is_gles31(ctx)) {
> bool stencil = params[0] == GL_STENCIL_INDEX;
> if (!stencil && params[0] != GL_DEPTH_COMPONENT)
> goto invalid_param;
> @@ -1819,7 +1817,7 @@ get_tex_parameterfv(struct gl_context *ctx,
> *params = (GLfloat) obj->DepthMode;
> break;
>case GL_DEPTH_STENCIL_TEXTURE_MODE:
> - if (!_mesa_is_desktop_gl(ctx) ||
> !ctx->Extensions.ARB_stencil_texturing)
> + if (!_mesa_has_ARB_stencil_texturing(ctx) && !_mesa_is_gles31(ctx))
> goto invalid_pname;
> *params = (GLfloat)
> (obj->StencilSampling ? GL_STENCIL_INDEX : GL_DEPTH_COMPONENT);
> @@ -2054,7 +2052,7 @@ get_tex_parameteriv(struct gl_context *ctx,
> *params = (GLint) obj->DepthMode;
> break;
>case GL_DEPTH_STENCIL_TEXTURE_MODE:
> - if (!_mesa_is_desktop_gl(ctx) ||
> !ctx->Extensions.ARB_stencil_texturing)
> + if (!_mesa_has_ARB_stencil_texturing(ctx) && !_mesa_is_gles31(ctx))
> goto invalid_pname;
> *params = (GLint)
> (obj->StencilSampling ? GL_STENCIL_INDEX : GL_DEPTH_COMPONENT);
> --
> 2.4.10
>
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[Mesa-dev] [PATCH] i965: Enable tiled mem_copy with sRGB-formatted resources
From: Nanley Chery
RGBA8 and BGRA8 unorm formats are compatible with the various
mem_copy functions. Their sRGB counterparts are also compatible
because they're also color-renderable (of importance when the
specified resource is a readbuffer) and they share the same
physical layout.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
index 2383401..3135458 100644
--- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
+++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
@@ -757,7 +757,9 @@ bool intel_get_memcpy(mesa_format tiledFormat, GLenum
format,
*cpp = 1;
*mem_copy = memcpy;
} else if ((tiledFormat == MESA_FORMAT_B8G8R8A8_UNORM) ||
- (tiledFormat == MESA_FORMAT_B8G8R8X8_UNORM)) {
+ (tiledFormat == MESA_FORMAT_B8G8R8X8_UNORM) ||
+ (tiledFormat == MESA_FORMAT_B8G8R8A8_SRGB) ||
+ (tiledFormat == MESA_FORMAT_B8G8R8X8_SRGB)) {
*cpp = 4;
if (format == GL_BGRA) {
*mem_copy = memcpy;
@@ -766,7 +768,9 @@ bool intel_get_memcpy(mesa_format tiledFormat, GLenum
format,
: rgba8_copy_aligned_src;
}
} else if ((tiledFormat == MESA_FORMAT_R8G8B8A8_UNORM) ||
- (tiledFormat == MESA_FORMAT_R8G8B8X8_UNORM)) {
+ (tiledFormat == MESA_FORMAT_R8G8B8X8_UNORM) ||
+ (tiledFormat == MESA_FORMAT_R8G8B8A8_SRGB) ||
+ (tiledFormat == MESA_FORMAT_R8G8B8X8_SRGB)) {
*cpp = 4;
if (format == GL_BGRA) {
/* Copying from RGBA to BGRA is the same as BGRA to RGBA so we can
--
2.7.1
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[Mesa-dev] [PATCH] glsl: reject explicit location on atomic counter uniforms
This fixes
dEQP-GLES31.functional.uniform_location.negative.atomic_fragment
dEQP-GLES31.functional.uniform_location.negative.atomic_vertex
Both of which have lines like
layout(location = 3, binding = 0, offset = 0) uniform atomic_uint uni0;
The ARB_explicit_uniform_location spec makes a very tangential mention
regarding atomic counters, but location isn't something that makes sense
with them.
Signed-off-by: Ilia Mirkin
---
Had no clue where to stick this check... this seemed like as good a place as
any.
src/compiler/glsl/ast_to_hir.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index dbeb5c0..9fce06b 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4179,6 +4179,11 @@ ast_declarator_list::hir(exec_list *instructions,
state->atomic_counter_offsets[qual_binding] = qual_offset;
}
}
+
+ if (type->qualifier.flags.q.explicit_location) {
+ _mesa_glsl_error(&loc, state,
+ "atomic counters cannot have an explicit location");
+ }
}
if (this->declarations.is_empty()) {
--
2.4.10
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Re: [Mesa-dev] [Mesa-stable] [PATCH 4/4] glx: fix error code when there is no context bound
On 11 February 2016 at 12:04, Tapani Pälli wrote:
> From: Bernard Kilarski
>
> Signed-off-by: Bernard Kilarski
> Signed-off-by: Matt Roper
> Cc: "11.0 11.1" ---
> src/glx/glxcmds.c | 2 +-
> src/glx/query_renderer.c | 4 ++--
> src/glx/tests/query_renderer_unittest.cpp | 4
> 3 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
> index 93e8db5..4db67ec 100644
> --- a/src/glx/glxcmds.c
> +++ b/src/glx/glxcmds.c
> @@ -1727,7 +1727,7 @@ __glXSwapIntervalSGI(int interval)
> CARD32 *interval_ptr;
> CARD8 opcode;
>
> - if (gc == NULL) {
> + if (gc == NULL || gc == &dummyContext) {
>return GLX_BAD_CONTEXT;
> }
>
> diff --git a/src/glx/query_renderer.c b/src/glx/query_renderer.c
> index 9108ec2..d49b8fe 100644
> --- a/src/glx/query_renderer.c
> +++ b/src/glx/query_renderer.c
> @@ -106,7 +106,7 @@ glXQueryCurrentRendererIntegerMESA(int attribute,
> unsigned int *value)
> {
> struct glx_context *gc = __glXGetCurrentContext();
>
> - if (gc == NULL)
> + if (gc == NULL || gc == &dummyContext)
>return False;
>
> return __glXQueryRendererInteger(gc->psc, attribute, value);
> @@ -166,7 +166,7 @@ glXQueryCurrentRendererStringMESA(int attribute)
> {
> struct glx_context *gc = __glXGetCurrentContext();
>
> - if (gc == NULL)
> + if (gc == NULL || gc == &dummyContext)
Unless I'm missing something __glXGetCurrentContext() can never return
NULL, right ?
In that case I see two possible solutions
- Swap all the NULL checks, for == &dummyContext (some commit
message would be great) or
- Drop the null checks in this patch, and explain why we do that only
here (the xid and vtable are implicitly zeroed for dummyContext, thus
things will just work).
Leaning for the latter for stable as it's shorter. Although doing the
former on top (for master alone) also sounds like a good idea imho.
>return False;
>
> return __glXQueryRendererString(gc->psc, attribute);
> diff --git a/src/glx/tests/query_renderer_unittest.cpp
> b/src/glx/tests/query_renderer_unittest.cpp
> index 2f3c4ef..4c96260 100644
> --- a/src/glx/tests/query_renderer_unittest.cpp
> +++ b/src/glx/tests/query_renderer_unittest.cpp
> @@ -40,6 +40,10 @@ struct attribute_test_vector {
> #define E(x) { # x, x }
>
>
> +/* This is necessary so that we don't have to link with glxcurrent.c
> + * which would require us to link with X libraries and what not.
> + */
> +struct glx_context dummyContext;
>
Perhaps we should initialize it (like in glxcurrent.c) for
consistency, if anything else ?
-Emil
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[Mesa-dev] [PATCH 1/3] i965/vec4: Initialize force_writemask_all in vec4_builder().
---
src/mesa/drivers/dri/i965/brw_vec4_builder.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
index be1427c..5d4b452 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
@@ -66,7 +66,8 @@ namespace brw {
* instruction passed as argument.
*/
vec4_builder(backend_shader *shader, bblock_t *block, instruction *inst)
:
- shader(shader), block(block), cursor(inst)
+ shader(shader), block(block), cursor(inst),
+ force_writemask_all(inst->force_writemask_all)
{
annotation.str = inst->annotation;
annotation.ir = inst->ir;
--
2.4.10
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[Mesa-dev] [PATCH 3/3] i965: Make emit_minmax return an instruction*.
And use it in brw_fs_nir.cpp.
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 6 +++---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 ++
src/mesa/drivers/dri/i965/brw_vec4_builder.h | 8 +---
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index bb94c3d..9a3cc3a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -369,14 +369,14 @@ namespace brw {
*
* Generally useful to get the minimum or maximum of two values.
*/
- void
+ instruction *
emit_minmax(const dst_reg &dst, const src_reg &src0,
const src_reg &src1, brw_conditional_mod mod) const
{
assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
- set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
- fix_unsigned_negate(src1)));
+ return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
+ fix_unsigned_negate(src1)));
}
/**
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 3014dbb..bea4db6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -950,16 +950,14 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
case nir_op_fmin:
case nir_op_imin:
case nir_op_umin:
- inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
- inst->conditional_mod = BRW_CONDITIONAL_L;
+ inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_L);
inst->saturate = instr->dest.saturate;
break;
case nir_op_fmax:
case nir_op_imax:
case nir_op_umax:
- inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
- inst->conditional_mod = BRW_CONDITIONAL_GE;
+ inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_GE);
inst->saturate = instr->dest.saturate;
break;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
index a0b390b..3a8617e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
@@ -299,12 +299,14 @@ namespace brw {
*
* Generally useful to get the minimum or maximum of two values.
*/
- void
+ instruction *
emit_minmax(const dst_reg &dst, const src_reg &src0,
const src_reg &src1, brw_conditional_mod mod) const
{
- set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
- fix_unsigned_negate(src1)));
+ assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
+
+ return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
+ fix_unsigned_negate(src1)));
}
/**
--
2.4.10
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[Mesa-dev] [PATCH 2/3] i965: Lower min/max after optimization on Gen4/5.
Gen4/5's SEL instruction cannot use conditional modifiers, so min/max
are implemented as CMP + SEL. Handling that after optimization lets us
CSE more.
On Ironlake:
total instructions in shared programs: 6426035 -> 6422753 (-0.05%)
instructions in affected programs: 326604 -> 323322 (-1.00%)
helped: 1411
total cycles in shared programs: 129184700 -> 129101586 (-0.06%)
cycles in affected programs: 18950290 -> 18867176 (-0.44%)
helped: 2419
HURT: 328
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 37 +
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_builder.h | 10 ++-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 20 +++---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 38 ++
src/mesa/drivers/dri/i965/brw_vec4.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_builder.h | 10 ++-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 14 ++
8 files changed, 88 insertions(+), 44 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0ce7ed1..e83f0ba 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3475,6 +3475,36 @@ fs_visitor::lower_integer_multiplication()
return progress;
}
+bool
+fs_visitor::lower_minmax()
+{
+ assert(devinfo->gen < 6);
+
+ bool progress = false;
+
+ foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
+ const fs_builder ibld(this, block, inst);
+
+ if (inst->opcode == BRW_OPCODE_SEL &&
+ inst->predicate == BRW_PREDICATE_NONE) {
+ assert(inst->conditional_mod == BRW_CONDITIONAL_GE ||
+inst->conditional_mod == BRW_CONDITIONAL_L);
+
+ ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1],
+ inst->conditional_mod);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ inst->conditional_mod = BRW_CONDITIONAL_NONE;
+
+ progress = true;
+ }
+ }
+
+ if (progress)
+ invalidate_live_intervals();
+
+ return progress;
+}
+
static void
setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key,
fs_reg *dst, fs_reg color, unsigned components)
@@ -5132,6 +5162,13 @@ fs_visitor::optimize()
OPT(opt_combine_constants);
OPT(lower_integer_multiplication);
+ if (devinfo->gen <= 5 && OPT(lower_minmax)) {
+ OPT(opt_cmod_propagation);
+ OPT(opt_cse);
+ OPT(opt_copy_propagate);
+ OPT(dead_code_eliminate);
+ }
+
lower_uniform_pull_constant_loads();
validate();
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 4a26ac1..16fccf6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -175,6 +175,7 @@ public:
bool lower_load_payload();
bool lower_logical_sends();
bool lower_integer_multiplication();
+ bool lower_minmax();
bool lower_simd_width();
bool opt_combine_constants();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index dd3c383..bb94c3d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -375,14 +375,8 @@ namespace brw {
{
assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
- if (shader->devinfo->gen >= 6) {
-set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
- fix_unsigned_negate(src1)));
- } else {
-CMP(null_reg_d(), src0, src1, mod);
-set_predicate(BRW_PREDICATE_NORMAL,
- SEL(dst, src0, src1));
- }
+ set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
+ fix_unsigned_negate(src1)));
}
/**
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 1fc21e4..3014dbb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -950,28 +950,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
case nir_op_fmin:
case nir_op_imin:
case nir_op_umin:
- if (devinfo->gen >= 6) {
- inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
- inst->conditional_mod = BRW_CONDITIONAL_L;
- } else {
- bld.CMP(bld.null_reg_d(), op[0], op[1], BRW_CONDITIONAL_L);
- inst = bld.SEL(result, op[0], op[1]);
- inst->predicate = BRW_PREDICATE_NORMAL;
- }
+ inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
+ inst->conditional_mod = BRW_CONDITIONAL_L;
inst->saturate = instr->dest.saturate;
break;
case nir_op_fmax:
case nir_op_imax:
case nir_op_umax:
- if (devinfo->gen >= 6) {
- inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
- inst->conditional_
Re: [Mesa-dev] [Mesa-stable] [PATCH 3/4] egl_dri2: set correct error code if swapbuffers fails
On 11 February 2016 at 12:03, Tapani Pälli wrote:
> From: Daniel Czarnowski
>
> Signed-off-by: Matt Roper
> Cc: "11.0 11.1" ---
> src/egl/drivers/dri2/platform_x11.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/egl/drivers/dri2/platform_x11.c
> b/src/egl/drivers/dri2/platform_x11.c
> index 931ee51..7a26c38 100644
> --- a/src/egl/drivers/dri2/platform_x11.c
> +++ b/src/egl/drivers/dri2/platform_x11.c
> @@ -872,7 +872,11 @@ dri2_x11_swap_buffers(_EGLDriver *drv, _EGLDisplay
> *disp, _EGLSurface *draw)
> struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
>
> if (dri2_dpy->dri2) {
> - return dri2_x11_swap_buffers_msc(drv, disp, draw, 0, 0, 0) != -1;
> + if (dri2_x11_swap_buffers_msc(drv, disp, draw, 0, 0, 0) != -1)
> + return EGL_TRUE;
> + /* Swap failed with a window drawable. */
> + _eglError(EGL_BAD_NATIVE_WINDOW, __FUNCTION__);
> + return EGL_FALSE;
Looking at the implementation of dri2_x11_swap_buffers_msc() and I'm
wondering if failing xcb_dri2_swap_buffers_reply() really means
"failed with window drawable". Can you please elaborate a bit and
stick it in the commit message ?
-Emil
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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/4] mapi_abi: Allow more dynamic entries
On 11 February 2016 at 12:03, Tapani Pälli wrote: > From: Bernard Kilarski > Here we should have justification why this is needed. If there is a program affected (or bugzilla ticket opened) do mentioned it as well please. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 2/4] egl_dri2: NULL check for xcb_dri2_get_buffers_reply()
On 11 February 2016 at 12:03, Tapani Pälli wrote: > From: Daniel Czarnowski > > Without the check, unsuccessful xcb_dri2_get_buffers_reply(...) causes > segmentation fault in dri2_get_buffers. > > Signed-off-by: Matt Roper > Cc: "11.0 11.1" > --- > src/egl/drivers/dri2/platform_x11.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/egl/drivers/dri2/platform_x11.c > b/src/egl/drivers/dri2/platform_x11.c > index 08cbf2d..931ee51 100644 > --- a/src/egl/drivers/dri2/platform_x11.c > +++ b/src/egl/drivers/dri2/platform_x11.c > @@ -472,6 +472,8 @@ dri2_x11_get_buffers(__DRIdrawable * driDrawable, > dri2_surf->drawable, > count, count, attachments); > reply = xcb_dri2_get_buffers_reply (dri2_dpy->conn, cookie, NULL); > + if (reply == NULL) > + return NULL; Looks great guys. Out of curiosity - did you notice this during inspection, or there was an application that triggered it ? Afaics there are a few other cases where we don't null check the reply before using it. Namely: src/egl/drivers/dri2/platform_x11.c:dri2_create_image_khr_pixmap(), buffers_reply -> bugzilla 93667 src/gallium/auxiliary/vl/vl_winsys_dri.c:vl_dri2_get_flush_reply(), "buffers_reply" Can you send patch(es) for those or shall I ? -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [v2] Compression support for single-sampled
On Thu, Feb 11, 2016 at 08:33:53PM +0200, Topi Pohjolainen wrote: > This series enables compression for single sampled color surfaces, > also referred to as "lossless compression". This is yet only for > driver internal use easing pressure on memory bandwidth and caches > when writing, blending and sampling surfaces uing gpu. > > As a side effect the need for color buffer resolves after fast > clears is also decreased. Current understanding is that sampling > engine doesn't understand meta data (auxiliary buffer) for single > sampled fast cleared surfaces. However, if the meta data is written > with lossless compression enabled, even sampling engine is capable > of reading both the color buffer and the auxiliary, and resolves > can be omitted in those case. > > The final enabling patch is dependent on earlier two-patch series > fixing state restore mechanism in i965-meta operations. > > v2 (Ben): Use combination of msaa_layout and number of samples >instead of introducing explicit type for lossless >compression. > Other than the comments I left, patch 6, 7, 9, 10 are: Reviewed-by: Ben Widawsky I wouldn't mind a small comment in patch 6 about why INTEL_MSAA_LAYOUT_NONE is fast clear (it seems like the resolve has such a comment)... up to you. A few months from now I can imagine myself looking at it and being WTF. 6 and 9 would be a logical pair to squash IMO. I'm going to start back up tomorrow at patch #11. I want to take a bit of a break. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [v2 08/19] i965: Refactor resolving of auxiliary mode
On Thu, Feb 11, 2016 at 08:34:01PM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 62
> --
> 1 file changed, 29 insertions(+), 33 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index fc8f701..0a52815 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -197,6 +197,28 @@ gen8_emit_fast_clear_color(struct brw_context *brw,
>surf[7] |= mt->fast_clear_color_value;
> }
>
> +static uint32_t
> +gen8_get_aux_mode(const struct brw_context *brw,
> + const struct intel_mipmap_tree *mt,
> + uint32_t surf_type)
What are we going to need surf_type for? It doesn't seem like something that
should be part of this determination, but perhaps there's something later?
> +{
> + if (mt->mcs_mt == NULL)
> + return GEN8_SURFACE_AUX_MODE_NONE;
> +
> + /*
> +* From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
> +* "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
> +*
> +* From the hardware spec for GEN9:
> +* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
> +* 16 must be used."
> +*/
> + if (brw->gen >= 9 || mt->num_samples == 1)
> + assert(mt->halign == 16);
> +
> + return GEN8_SURFACE_AUX_MODE_MCS;
> +}
> +
> static void
> gen8_emit_texture_surface_state(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> @@ -209,13 +231,13 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
> bool rw, bool for_gather)
> {
> const unsigned depth = max_layer - min_layer;
> - struct intel_mipmap_tree *aux_mt = NULL;
> - uint32_t aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
> + struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
> uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
> int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
> unsigned tiling_mode, pitch;
> const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
> const uint32_t surf_type = translate_tex_target(target);
> + uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
>
> if (mt->format == MESA_FORMAT_S_UINT8) {
>tiling_mode = GEN8_SURFACE_TILING_W;
> @@ -229,20 +251,9 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
> * buffer should always have been resolved before it is used as a texture
> * so there is no need for it.
> */
> - if (mt->mcs_mt && mt->num_samples > 1) {
> - aux_mt = mt->mcs_mt;
> - aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
> -
> - /*
> - * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
> - * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
> - *
> - * From the hardware spec for GEN9:
> - * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
> HALIGN
> - * 16 must be used."
> - */
> - if (brw->gen >= 9 || mt->num_samples == 1)
> - assert(mt->halign == 16);
> + if (mt->num_samples <= 1) {
> + aux_mt = NULL;
> + aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
What I meant earlier which probably wasn't clearly articulated is I think this
could be wrapped into gen8_get_aux_mode() more sensibly. Perhaps though you
wanted to keep the refactor as minimally invasive as possible.
> }
>
> uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
> @@ -418,8 +429,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
> struct gl_context *ctx = &brw->ctx;
> struct intel_renderbuffer *irb = intel_renderbuffer(rb);
> struct intel_mipmap_tree *mt = irb->mt;
> - struct intel_mipmap_tree *aux_mt = NULL;
> - uint32_t aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
> unsigned width = mt->logical_width0;
> unsigned height = mt->logical_height0;
> unsigned pitch = mt->pitch;
> @@ -472,21 +481,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
> __func__, _mesa_get_format_name(rb_format));
> }
>
> - if (mt->mcs_mt) {
> - aux_mt = mt->mcs_mt;
> - aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
> -
> - /*
> - * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
> - * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
> - *
> - * From the hardware spec for GEN9:
> - * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
> HALIGN
> - * 16 must be used."
> - */
> - if (brw->gen >= 9 || mt->num_samples == 1)
> - assert(mt->halign == 16);
> - }
> + struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
pretty sure you could const this too if you wanted. It shouldn't be changing
after this point.
> + const uint32_t aux_mode = gen8_get_aux_
Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
Kenneth Graunke writes:
> On Thursday, February 11, 2016 1:49:21 PM PST Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.cpp | 31 ++
> +---
>> .../drivers/dri/i965/brw_fs_combine_constants.cpp | 13 +
>> .../drivers/dri/i965/brw_fs_copy_propagation.cpp | 14 +-
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 9 ++-
>> src/mesa/drivers/dri/i965/brw_ir_fs.h | 13 +++--
>> 6 files changed, 35 insertions(+), 47 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/
> i965/brw_fs.cpp
>> index 41a3f81..6ee590e 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -432,7 +432,6 @@ fs_reg::fs_reg(struct ::brw_reg reg) :
>> backend_reg(reg)
>> {
>> this->reg_offset = 0;
>> - this->subreg_offset = 0;
>> this->reladdr = NULL;
>> this->stride = 1;
>> if (this->file == IMM &&
>> @@ -447,7 +446,6 @@ bool
>> fs_reg::equals(const fs_reg &r) const
>> {
>> return (this->backend_reg::equals(r) &&
>> - subreg_offset == r.subreg_offset &&
>> !reladdr && !r.reladdr &&
>> stride == r.stride);
>> }
>> @@ -456,7 +454,8 @@ fs_reg &
>> fs_reg::set_smear(unsigned subreg)
>> {
>> assert(file != ARF && file != FIXED_GRF && file != IMM);
>> - subreg_offset = subreg * type_sz(type);
>> + assert(subreg * type_sz(type) < (1 << 5)); /* subnr is 5 bits */
>> + subnr = subreg * type_sz(type);
>> stride = 0;
>> return *this;
>> }
>> @@ -1513,7 +1512,7 @@ fs_visitor::assign_curb_setup()
>> assert(inst->src[i].stride == 0);
>> inst->src[i] = byte_offset(
>> retype(brw_reg, inst->src[i].type),
>> - inst->src[i].subreg_offset);
>> + inst->src[i].subnr);
>> }
>>}
>> }
>> @@ -1653,7 +1652,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
> *inst)
>> unsigned width = inst->src[i].stride == 0 ? 1 : inst->exec_size;
>> struct brw_reg reg =
>> stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst-
>>src[i].type),
>> - inst->src[i].subreg_offset),
>> + inst->src[i].subnr),
>> inst->exec_size * inst->src[i].stride,
>> width, inst->src[i].stride);
>> reg.abs = inst->src[i].abs;
>> @@ -2597,7 +2596,7 @@ fs_visitor::compute_to_mrf()
>>inst->dst.type != inst->src[0].type ||
>>inst->src[0].abs || inst->src[0].negate ||
>>!inst->src[0].is_contiguous() ||
>> - inst->src[0].subreg_offset)
>> + inst->src[0].subnr)
>> continue;
>>
>>/* Work out which hardware MRF registers are written by this
>> @@ -3367,7 +3366,7 @@ fs_visitor::lower_integer_multiplication()
>> assert(src1_1_w.stride == 1);
>> src1_1_w.stride = 2;
>>}
>> - src1_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
>> + src1_1_w.subnr += type_sz(BRW_REGISTER_TYPE_UW);
>> }
>> ibld.MUL(low, inst->src[0], src1_0_w);
>> ibld.MUL(high, inst->src[0], src1_1_w);
>> @@ -3386,7 +3385,7 @@ fs_visitor::lower_integer_multiplication()
>>assert(src0_1_w.stride == 1);
>>src0_1_w.stride = 2;
>> }
>> - src0_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
>> + src0_1_w.subnr += type_sz(BRW_REGISTER_TYPE_UW);
>>
>> ibld.MUL(low, src0_0_w, inst->src[1]);
>> ibld.MUL(high, src0_1_w, inst->src[1]);
>> @@ -3394,14 +3393,14 @@ fs_visitor::lower_integer_multiplication()
>>
>> fs_reg dst = inst->dst;
>> dst.type = BRW_REGISTER_TYPE_UW;
>> -dst.subreg_offset = 2;
>> +dst.subnr = 2;
>> dst.stride = 2;
>>
>> high.type = BRW_REGISTER_TYPE_UW;
>> high.stride = 2;
>>
>> low.type = BRW_REGISTER_TYPE_UW;
>> -low.subreg_offset = 2;
>> +low.subnr = 2;
>> low.stride = 2;
>>
>> ibld.ADD(dst, low, high);
>> @@ -4642,9 +4641,9 @@ fs_visitor::dump_instruction(backend_instruction
> *be_inst, FILE *file)
>> case VGRF:
>>fprintf(file, "vgrf%d", inst->dst.nr);
>>if (alloc.sizes[inst->dst.nr] != inst->regs_written ||
>> - inst->dst.subreg_offset)
>> + inst->dst.subnr)
>> fprintf(file, "+%d.%d",
>> - inst->dst.reg_offset, inst->dst.subreg_offset);
>> + inst->dst.reg_offset, inst->dst.subnr);
>>break;
>> case FIXED_GRF:
>>fprintf(file, "g%d", inst->dst.nr);
>> @@ -4698,9 +4697,9 @@ fs_visitor::dump_instruc
[Mesa-dev] [PATCH] glsl: replace _strtoui64() with strtoull() for MSVC
Now that MSVC 2013 is required we can remove this. --- src/compiler/glsl/glsl_lexer.ll | 4 1 file changed, 4 deletions(-) diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/compiler/glsl/glsl_lexer.ll index e59f93e..9704fc7 100644 --- a/src/compiler/glsl/glsl_lexer.ll +++ b/src/compiler/glsl/glsl_lexer.ll @@ -113,11 +113,7 @@ literal_integer(char *text, int len, struct _mesa_glsl_parse_state *state, if (base == 16) digits += 2; -#ifdef _MSC_VER - unsigned __int64 value = _strtoui64(digits, NULL, base); -#else unsigned long long value = strtoull(digits, NULL, base); -#endif lval->n = (int)value; -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
On Thursday, February 11, 2016 1:49:21 PM PST Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 31 ++
+---
> .../drivers/dri/i965/brw_fs_combine_constants.cpp | 13 +
> .../drivers/dri/i965/brw_fs_copy_propagation.cpp | 14 +-
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 9 ++-
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 13 +++--
> 6 files changed, 35 insertions(+), 47 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/
i965/brw_fs.cpp
> index 41a3f81..6ee590e 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -432,7 +432,6 @@ fs_reg::fs_reg(struct ::brw_reg reg) :
> backend_reg(reg)
> {
> this->reg_offset = 0;
> - this->subreg_offset = 0;
> this->reladdr = NULL;
> this->stride = 1;
> if (this->file == IMM &&
> @@ -447,7 +446,6 @@ bool
> fs_reg::equals(const fs_reg &r) const
> {
> return (this->backend_reg::equals(r) &&
> - subreg_offset == r.subreg_offset &&
> !reladdr && !r.reladdr &&
> stride == r.stride);
> }
> @@ -456,7 +454,8 @@ fs_reg &
> fs_reg::set_smear(unsigned subreg)
> {
> assert(file != ARF && file != FIXED_GRF && file != IMM);
> - subreg_offset = subreg * type_sz(type);
> + assert(subreg * type_sz(type) < (1 << 5)); /* subnr is 5 bits */
> + subnr = subreg * type_sz(type);
> stride = 0;
> return *this;
> }
> @@ -1513,7 +1512,7 @@ fs_visitor::assign_curb_setup()
> assert(inst->src[i].stride == 0);
> inst->src[i] = byte_offset(
> retype(brw_reg, inst->src[i].type),
> - inst->src[i].subreg_offset);
> + inst->src[i].subnr);
>}
>}
> }
> @@ -1653,7 +1652,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst)
> unsigned width = inst->src[i].stride == 0 ? 1 : inst->exec_size;
> struct brw_reg reg =
> stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst-
>src[i].type),
> - inst->src[i].subreg_offset),
> + inst->src[i].subnr),
> inst->exec_size * inst->src[i].stride,
> width, inst->src[i].stride);
> reg.abs = inst->src[i].abs;
> @@ -2597,7 +2596,7 @@ fs_visitor::compute_to_mrf()
> inst->dst.type != inst->src[0].type ||
> inst->src[0].abs || inst->src[0].negate ||
>!inst->src[0].is_contiguous() ||
> - inst->src[0].subreg_offset)
> + inst->src[0].subnr)
>continue;
>
>/* Work out which hardware MRF registers are written by this
> @@ -3367,7 +3366,7 @@ fs_visitor::lower_integer_multiplication()
> assert(src1_1_w.stride == 1);
> src1_1_w.stride = 2;
>}
> - src1_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
> + src1_1_w.subnr += type_sz(BRW_REGISTER_TYPE_UW);
> }
> ibld.MUL(low, inst->src[0], src1_0_w);
> ibld.MUL(high, inst->src[0], src1_1_w);
> @@ -3386,7 +3385,7 @@ fs_visitor::lower_integer_multiplication()
>assert(src0_1_w.stride == 1);
>src0_1_w.stride = 2;
> }
> - src0_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
> + src0_1_w.subnr += type_sz(BRW_REGISTER_TYPE_UW);
>
> ibld.MUL(low, src0_0_w, inst->src[1]);
> ibld.MUL(high, src0_1_w, inst->src[1]);
> @@ -3394,14 +3393,14 @@ fs_visitor::lower_integer_multiplication()
>
> fs_reg dst = inst->dst;
> dst.type = BRW_REGISTER_TYPE_UW;
> -dst.subreg_offset = 2;
> +dst.subnr = 2;
> dst.stride = 2;
>
> high.type = BRW_REGISTER_TYPE_UW;
> high.stride = 2;
>
> low.type = BRW_REGISTER_TYPE_UW;
> -low.subreg_offset = 2;
> +low.subnr = 2;
> low.stride = 2;
>
> ibld.ADD(dst, low, high);
> @@ -4642,9 +4641,9 @@ fs_visitor::dump_instruction(backend_instruction
*be_inst, FILE *file)
> case VGRF:
>fprintf(file, "vgrf%d", inst->dst.nr);
>if (alloc.sizes[inst->dst.nr] != inst->regs_written ||
> - inst->dst.subreg_offset)
> + inst->dst.subnr)
> fprintf(file, "+%d.%d",
> - inst->dst.reg_offset, inst->dst.subreg_offset);
> + inst->dst.reg_offset, inst->dst.subnr);
>break;
> case FIXED_GRF:
>fprintf(file, "g%d", inst->dst.nr);
> @@ -4698,9 +4697,9 @@ fs_visitor::dump_instruction(backend_instruction
*be_inst, FILE *file)
>case VGRF:
> fprintf(file, "vgrf%d", inst->src[i].nr);
> if (alloc.siz
Re: [Mesa-dev] [PATCH] radeonsi: fix build with LLVM 3.6
Reviewed-by: Nicolai Hähnle On 11.02.2016 11:50, Marek Olšák wrote: From: Marek Olšák Broken by this cleanup: 3dc1cb0cc7605a2f3128311f5a6052f740fc7b0d --- src/gallium/drivers/radeonsi/si_shader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index baa1090..19c427a 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -4336,7 +4336,7 @@ static void si_init_shader_ctx(struct si_shader_context *ctx, ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context); ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context); ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context); - ctx->i128 = LLVMInt128TypeInContext(ctx->radeon_bld.gallivm.context); + ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128); ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context); ctx->v16i8 = LLVMVectorType(ctx->i8, 16); ctx->v4i32 = LLVMVectorType(ctx->i32, 4); ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] include, gallium: Remove pre-MSVC 2013 compatibility.
On 11 February 2016 at 13:02, Jose Fonseca wrote: > --- > Makefile.am | 1 - > include/c99/inttypes.h| 305 > -- > include/c99/stdbool.h | 46 - > include/c99/stdint.h | 247 > include/c99_compat.h | 8 +- > include/c99_math.h| 49 + > src/gallium/auxiliary/util/u_cpu_detect.c | 3 +- > 7 files changed, 10 insertions(+), 649 deletions(-) > delete mode 100644 include/c99/inttypes.h > delete mode 100644 include/c99/stdbool.h > delete mode 100644 include/c99/stdint.h > Seems like I was too late for the fun - there's a couple of cases in src/util/u_atomic.h and src/mesa/main/imports.h. Thank you Jose and everyone else involved behind the scenes, for all the work to make this happen ! -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: create validated miptree starting with the first known layer
This is effectively a revert of 8037c0b69 (i965: Always allocate validated miptrees from level 0). Unfortunately the first level's images may not be set, and there is no way to know what their size is. We were retrieving the size of the base level's image, but using that to build a miptree of that size for level 0. This meant that intel_miptree_match_image would fail since the first_level of the miptree was set to 0 but the local_width/height/depth0 were set for the base level's dimensions. This fixes a number of assertion failures in dEQP of the form dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8.base_level.* For some reason the plain 2D case didn't hit the assertions in question. Signed-off-by: Ilia Mirkin Cc: Eric Anholt --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 2cf9c13..f2975c6 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -140,7 +140,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) intelObj->mt = intel_miptree_create(brw, intelObj->base.Target, firstImage->base.Base.TexFormat, - 0, /* first_level */ + validate_first_level, validate_last_level, width, height, -- 2.4.10 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 7/7] mesa: optimize out the realloc from glCopyTexImagexD()
On 02/05/2016 10:26 PM, Ilia Mirkin wrote:
On Fri, Feb 5, 2016 at 4:11 PM, Miklós Máté wrote:
v2: comment about the purpose of the code
---
src/mesa/main/teximage.c | 32
1 file changed, 32 insertions(+)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 50141be..cac05d5 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -3486,6 +3486,21 @@ formats_differ_in_component_sizes(mesa_format f1,
mesa_format f2)
return GL_FALSE;
}
+static GLboolean
+canAvoidRealloc(struct gl_texture_image *texImage, GLenum internalFormat,
+ GLint x, GLint y, GLsizei width, GLsizei height, GLint border)
+{
+ if (texImage->InternalFormat != internalFormat)
+ return false;
+ if (texImage->Border != border)
+ return false;
+ if (texImage->Width2 != width)
+ return false;
+ if (texImage->Height2 != height)
+ return false;
+ return true;
Also need to compare the texFormat no?
I don't know. I now added it to make sure everything is ok.
MM
+}
+
/**
* Implement the glCopyTexImage1/2D() functions.
*/
@@ -3526,6 +3541,23 @@ copyteximage(struct gl_context *ctx, GLuint dims,
texObj = _mesa_get_current_tex_object(ctx, target);
assert(texObj);
+ /* First check if reallocating the texture buffer can be avoided.
+* Without the realloc the copy can be 20x faster.
+*/
+ _mesa_lock_texture(ctx, texObj);
+ {
+ texImage = _mesa_select_tex_image(texObj, target, level);
+ if (texImage && canAvoidRealloc(texImage, internalFormat,
+ x, y, width, height, border)) {
+ _mesa_unlock_texture(ctx, texObj);
+ /*_mesa_debug(ctx, "using shortcut\n");*/
+ return _mesa_copy_texture_sub_image(ctx, dims, texObj, target, level,
+ 0, 0, 0, x, y, width, height, "CopyTexImage");
+ }
+ /*_mesa_debug(ctx, "can't shortcut\n");*/
+ }
+ _mesa_unlock_texture(ctx, texObj);
+
texFormat = _mesa_choose_texture_format(ctx, texObj, target, level,
internalFormat, GL_NONE, GL_NONE);
--
2.7.0
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Re: [Mesa-dev] [v2 05/19] i965: Add helper for detecting lossless compression
On Thu, Feb 11, 2016 at 08:33:58PM +0200, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 ++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4
> 2 files changed, 30 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 5f739d9..31de1ff 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -266,6 +266,32 @@ intel_miptree_supports_non_msrt_fast_clear(struct
> brw_context *brw,
>return true;
> }
>
> +/* On Gen9 support for color buffer compression was extended to single
> + * sampled surfaces. This is a helper considering both auxiliary buffer
> + * type and number of samples telling if the given miptree represents
> + * the new single sampled case - also called lossless compression.
> + */
> +bool
> +intel_miptree_is_lossless_compressed(const struct brw_context *brw,
> + const struct intel_mipmap_tree *mt)
> +{
> + /* Only available from Gen9 onwards. */
> + if (brw->gen < 9)
> + return false;
> +
> + /* Compression always requires auxiliary buffer. */
> + if (!mt->mcs_mt)
> + return false;
> +
> + /* Single sample compression is represented re-using msaa compression
> +* layout type: "Compressed Multisampled Surfaces".
> +*/
> + if (mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS)
> + return false;
> +
> + /* And finally distinguish between msaa and single sample case. */
> + return mt->num_samples <= 1;
> +}
>
> /**
> * Determine depth format corresponding to a depth+stencil format,
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 64f73ea..13d4d7e 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -667,6 +667,10 @@ intel_get_non_msrt_mcs_alignment(struct
> intel_mipmap_tree *mt,
> unsigned *width_px, unsigned *height);
>
> bool
> +intel_miptree_is_lossless_compressed(const struct brw_context *brw,
> + const struct intel_mipmap_tree *mt);
> +
> +bool
> intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> struct intel_mipmap_tree *mt);
>
So I take it this was one of the big changes from my feedback earlier. Do you
prefer this result, or what? I can live with the old thing if you want it.
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[Mesa-dev] [PATCH] i965/fs: Replace subreg_offset with brw_reg's subnr.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 31 +++---
.../drivers/dri/i965/brw_fs_combine_constants.cpp | 13 +
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 14 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 9 ++-
src/mesa/drivers/dri/i965/brw_ir_fs.h | 13 +++--
6 files changed, 35 insertions(+), 47 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 41a3f81..6ee590e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -432,7 +432,6 @@ fs_reg::fs_reg(struct ::brw_reg reg) :
backend_reg(reg)
{
this->reg_offset = 0;
- this->subreg_offset = 0;
this->reladdr = NULL;
this->stride = 1;
if (this->file == IMM &&
@@ -447,7 +446,6 @@ bool
fs_reg::equals(const fs_reg &r) const
{
return (this->backend_reg::equals(r) &&
- subreg_offset == r.subreg_offset &&
!reladdr && !r.reladdr &&
stride == r.stride);
}
@@ -456,7 +454,8 @@ fs_reg &
fs_reg::set_smear(unsigned subreg)
{
assert(file != ARF && file != FIXED_GRF && file != IMM);
- subreg_offset = subreg * type_sz(type);
+ assert(subreg * type_sz(type) < (1 << 5)); /* subnr is 5 bits */
+ subnr = subreg * type_sz(type);
stride = 0;
return *this;
}
@@ -1513,7 +1512,7 @@ fs_visitor::assign_curb_setup()
assert(inst->src[i].stride == 0);
inst->src[i] = byte_offset(
retype(brw_reg, inst->src[i].type),
- inst->src[i].subreg_offset);
+ inst->src[i].subnr);
}
}
}
@@ -1653,7 +1652,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst)
unsigned width = inst->src[i].stride == 0 ? 1 : inst->exec_size;
struct brw_reg reg =
stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type),
- inst->src[i].subreg_offset),
+ inst->src[i].subnr),
inst->exec_size * inst->src[i].stride,
width, inst->src[i].stride);
reg.abs = inst->src[i].abs;
@@ -2597,7 +2596,7 @@ fs_visitor::compute_to_mrf()
inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate ||
!inst->src[0].is_contiguous() ||
- inst->src[0].subreg_offset)
+ inst->src[0].subnr)
continue;
/* Work out which hardware MRF registers are written by this
@@ -3367,7 +3366,7 @@ fs_visitor::lower_integer_multiplication()
assert(src1_1_w.stride == 1);
src1_1_w.stride = 2;
}
- src1_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
+ src1_1_w.subnr += type_sz(BRW_REGISTER_TYPE_UW);
}
ibld.MUL(low, inst->src[0], src1_0_w);
ibld.MUL(high, inst->src[0], src1_1_w);
@@ -3386,7 +3385,7 @@ fs_visitor::lower_integer_multiplication()
assert(src0_1_w.stride == 1);
src0_1_w.stride = 2;
}
- src0_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
+ src0_1_w.subnr += type_sz(BRW_REGISTER_TYPE_UW);
ibld.MUL(low, src0_0_w, inst->src[1]);
ibld.MUL(high, src0_1_w, inst->src[1]);
@@ -3394,14 +3393,14 @@ fs_visitor::lower_integer_multiplication()
fs_reg dst = inst->dst;
dst.type = BRW_REGISTER_TYPE_UW;
-dst.subreg_offset = 2;
+dst.subnr = 2;
dst.stride = 2;
high.type = BRW_REGISTER_TYPE_UW;
high.stride = 2;
low.type = BRW_REGISTER_TYPE_UW;
-low.subreg_offset = 2;
+low.subnr = 2;
low.stride = 2;
ibld.ADD(dst, low, high);
@@ -4642,9 +4641,9 @@ fs_visitor::dump_instruction(backend_instruction
*be_inst, FILE *file)
case VGRF:
fprintf(file, "vgrf%d", inst->dst.nr);
if (alloc.sizes[inst->dst.nr] != inst->regs_written ||
- inst->dst.subreg_offset)
+ inst->dst.subnr)
fprintf(file, "+%d.%d",
- inst->dst.reg_offset, inst->dst.subreg_offset);
+ inst->dst.reg_offset, inst->dst.subnr);
break;
case FIXED_GRF:
fprintf(file, "g%d", inst->dst.nr);
@@ -4698,9 +4697,9 @@ fs_visitor::dump_instruction(backend_instruction
*be_inst, FILE *file)
case VGRF:
fprintf(file, "vgrf%d", inst->src[i].nr);
if (alloc.sizes[inst->src[i].nr] != (unsigned)inst->regs_read(i) ||
- inst->src[i].subreg_offset)
+ inst->src[i].subnr)
fprintf(file, "+%d.%d", inst->src[i].reg_offset,
-inst->src[i].subreg_offset);
+inst->src[i].subnr);
Re: [Mesa-dev] [v2 04/19] i965: Stop considering if msrt aux buffers need aux buffer
On Thu, Feb 11, 2016 at 08:33:57PM +0200, Topi Pohjolainen wrote: > Auxiliary buffers are always created with sample number of zero > which effectively prevents intel_miptree_create_layout() from trying > to associate auxiliary buffers with auxiliary buffers. > > Now that there is more direct path available lets start using it > instead and stop even checking for such (im)possibility. > > v2 (Ben): Do not signal msaa layout with explicit argument but > using layout_flags instead. > > Signed-off-by: Topi Pohjolainen > Reviewed-by: Ben Widawsky > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 20 ++-- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > index e1cf15b..5f739d9 100644 > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > @@ -1468,16 +1468,16 @@ intel_miptree_alloc_mcs(struct brw_context *brw, > */ > const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD | >MIPTREE_LAYOUT_TILING_Y; > - mt->mcs_mt = intel_miptree_create(brw, > - mt->target, > - format, > - mt->first_level, > - mt->last_level, > - mt->logical_width0, > - mt->logical_height0, > - mt->logical_depth0, > - 0 /* num_samples */, > - mcs_flags); > + mt->mcs_mt = miptree_create(brw, > + mt->target, > + format, > + mt->first_level, > + mt->last_level, > + mt->logical_width0, > + mt->logical_height0, > + mt->logical_depth0, > + 0 /* num_samples */, > + mcs_flags); > > /* From the Ivy Bridge PRM, Vol 2 Part 1 p326: > * This patch is a great step in getting rid of some unnecessary [strictly IMHO] recursion. Unfortunately, now an mcs miptree can't have it's own mcs miptree :P I think there is an issue with the last patch, but I'm fine with moving ahead on 1, 2, and this, now. Reviewed-by: Ben Widawsky ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [v2 03/19] i965: Don't try to create aux buffer for non-msrt aux-buffer
On Thu, Feb 11, 2016 at 08:33:56PM +0200, Topi Pohjolainen wrote:
> In addition to simply calling miptree_create() the higher level
> call intel_miptree_create() also considers if the buffer should
> be associated with an auxiliary buffer based on the given format.
>
> Here we are allocating an auxiliary buffer which in turn has such
> format that would mislead intel_miptree_create_layout() later on
> to try to associate the auxiliary buffer with an auxiliary buffer.
> To prevent this the actual buffer creation logic was split out
> into its own function. Lets invoke that instead.
>
> v2 (Ben): Do not signal msaa layout with explicit argument but
> using layout_flags instead.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index e8b3116..e1cf15b 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1541,16 +1541,16 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context
> *brw,
> if (brw->gen >= 8) {
>layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
> }
> - mt->mcs_mt = intel_miptree_create(brw,
> - mt->target,
> - format,
> - mt->first_level,
> - mt->last_level,
> - mcs_width,
> - mcs_height,
> - mt->logical_depth0,
> - 0 /* num_samples */,
> - layout_flags);
> + mt->mcs_mt = miptree_create(brw,
> + mt->target,
> + format,
> + mt->first_level,
> + mt->last_level,
> + mcs_width,
> + mcs_height,
> + mt->logical_depth0,
> + 0 /* num_samples */,
> + layout_flags);
>
> return mt->mcs_mt;
> }
Perhaps I am missing something here, but don't you need to have
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; ?
Otherwise, lgtm
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Re: [Mesa-dev] issues with split llvm libraries and llvmpipe and failing to load library
On 12 February 2016 at 01:51, Tom Stellard wrote: > On Thu, Feb 11, 2016 at 01:59:25PM +1000, Dave Airlie wrote: >> Hey, >> >> So in Fedora rawhide we are now building llvm 3.7.1 into the lots of >> little shared libraries format. >> > > This configuration is only recommended for developers. > > See the documentation for BUILD_SHARED_LIBS:BOOL here: > http://llvm.org/docs/CMake.html Interesting I'm fairly sure this wasn't always this way, and at one point the CMake guys were saying they should remove the super library. Ah well live and learn, back to super library it is. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 6/7] glx: remove incorrect refcounting of DRIdrawable
On 02/09/2016 05:02 PM, Ian Romanick wrote: On 02/08/2016 05:11 PM, Ian Romanick wrote: On 02/05/2016 01:11 PM, Miklós Máté wrote: dri drawables must never be released when unbound from a context as long as their corresponding glx objects (window, pixmap, pbuffer) still exist I'd really like to have Kristian weigh in, since DRI2 was his design, and this is all his code being affected. That said, I'm a little unsure about this change. The DRI drawables and associated resources will still get freed when the application eventually calls glXDestroyPBuffer or glXDestroyWindow. But I'm not 100% sure what will happen with GLX 1.2 applications... there are no glXDestroy* functions in GLX 1.2. In that case the application will have a soft leak because calling XDestroyWindow won't do anything on the client (or server?) for the DRI resources. I suspect that's what this code was trying to prevent. And this commit affirms that: commit bf69ce37f0dcbb479078ee676d5100ac63e20750 Author: Stéphane Marchesin Date: Wed Jun 15 15:09:12 2011 -0700 glx: implement drawable refcounting. The current dri context unbind logic will leak drawables until the process dies (they will then get released by the GEM code). There are two ways to fix this: either always call driReleaseDrawables every time we unbind a context (but that costs us round trips to the X server at getbuffers() time) or implement proper drawable refcounting. This patch implements the latter. Signed-off-by: Antoine Labour Signed-off-by: Stéphane Marchesin Reviewed-by: Adam Jackson Since we don't have any way to know when the corresponding GLX object ceases to exist, we don't know when it's safe to destroy the DRI object. I don't know how we can not leak and not prematurely destroy the object. :( That commit message exaggerates a little when it says "proper refcounting", because it only refcounts on bind (in driFetchDrawable), but not on create/destroy. With current Mesa the following happens: create glXPbuffer: dri drawable is created, refcount=0 bind it: refcount++ unbind it: refcount--, drawable is destroyed bind again: create new drawable, refcount=1 unbind again: refcount--, drawable is destroyed etc. They also say that "current unbind logic will leak drawables until the process dies", which is simply not true. The glXDestroy* calls properly dispose of the corresponding dri objects. With GLX 1.3 the dri drawables are correctly created and destroyed along with their corresponding glx objects even without the above commit. IMHO if someone deliberately uses GLX 1.2 or earlier, they know what they are doing (1.3 was released in 1998). I'd say that it's never safe to destroy a dri object until it's explicitly destroyed by the user, so I'm still convinced that my patch is correct. MM this fixes fd.o bug #93955 and disappearing characters in KotOR when soft shadows are enabled I think this is also a candidate for stable. Reference this in the commit message like: This fixes disappearing characters in KotOR when soft shadows are enabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93955 Cc: "11.1" --- src/glx/dri2_glx.c | 4 src/glx/dri3_glx.c | 4 src/glx/dri_common.c | 38 -- src/glx/dri_glx.c| 4 src/glx/drisw_glx.c | 4 src/glx/glxclient.h | 1 - 6 files changed, 55 deletions(-) diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c index 7710349..ebc878f 100644 --- a/src/glx/dri2_glx.c +++ b/src/glx/dri2_glx.c @@ -122,8 +122,6 @@ dri2_destroy_context(struct glx_context *context) struct dri2_context *pcp = (struct dri2_context *) context; struct dri2_screen *psc = (struct dri2_screen *) context->psc; - driReleaseDrawables(&pcp->base); - free((char *) context->extensions); (*psc->core->destroyContext) (pcp->driContext); @@ -145,8 +143,6 @@ dri2_bind_context(struct glx_context *context, struct glx_context *old, pdraw = (struct dri2_drawable *) driFetchDrawable(context, draw); pread = (struct dri2_drawable *) driFetchDrawable(context, read); - driReleaseDrawables(&pcp->base); - if (pdraw) dri_draw = pdraw->driDrawable; else if (draw != None) diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c index 6054ffc..38f5799 100644 --- a/src/glx/dri3_glx.c +++ b/src/glx/dri3_glx.c @@ -186,8 +186,6 @@ dri3_destroy_context(struct glx_context *context) struct dri3_context *pcp = (struct dri3_context *) context; struct dri3_screen *psc = (struct dri3_screen *) context->psc; - driReleaseDrawables(&pcp->base); - free((char *) context->extensions); (*psc->core->destroyContext) (pcp->driContext); @@ -206,8 +204,6 @@ dri3_bind_context(struct glx_context *context, struct glx_context *old, pdraw = (struct dri3_drawable *) driFetchDrawable(context, draw); pread = (struct dri3_drawable *) driFetchDraw
Re: [Mesa-dev] [PATCH 4/7] mesa: remove check_compatible() in make_current
On 02/09/2016 05:21 AM, Ian Romanick wrote:
On 02/05/2016 01:11 PM, Miklós Máté wrote:
this was marked for removal since 2007
ctx::Visual is also removed, since this was its only legit user
---
.../drivers/dri/radeon/radeon_common_context.c | 2 +-
src/mesa/main/blend.c | 4 +-
src/mesa/main/blend.h | 4 +-
src/mesa/main/context.c| 89 ++
src/mesa/main/mtypes.h | 7 --
src/mesa/main/pixel.c | 4 +-
src/mesa/main/pixel.h | 4 +-
7 files changed, 15 insertions(+), 99 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c
b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 4660d98..2989f63 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -604,7 +604,7 @@ GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
}
if(driDrawPriv == NULL && driReadPriv == NULL) {
- drfb = _mesa_create_framebuffer(&radeon->glCtx.Visual);
+ drfb = _mesa_get_incomplete_framebuffer();
readfb = drfb;
}
else {
diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index 2ae22e9..28e2dbf 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -921,7 +921,7 @@ _mesa_get_render_format(const struct gl_context *ctx,
mesa_format format)
* Initializes the related fields in the context color attribute group,
* __struct gl_contextRec::Color.
*/
-void _mesa_init_color( struct gl_context * ctx )
+void _mesa_init_color( struct gl_context * ctx, GLuint doubleBufferMode )
Mesa has changed it's style (years ago, at this point) to not have the
spaces after the ( or before the ). Since the prototype is being
updated anyway, this is a good time to fix the style.
I think I'd also prefer doubleBufferMode to be bool.
I have a bunch of comments below about the other changes, but I think
explicitly passing the double buffer mode around is a reasonable change.
{
GLuint i;
@@ -951,7 +951,7 @@ void _mesa_init_color( struct gl_context * ctx )
/* GL_FRONT is not possible on GLES. Instead GL_BACK will render to either
* the front or the back buffer depending on the config */
- if (ctx->Visual.doubleBufferMode || _mesa_is_gles(ctx)) {
+ if (doubleBufferMode || _mesa_is_gles(ctx)) {
ctx->Color.DrawBuffer[0] = GL_BACK;
}
else {
diff --git a/src/mesa/main/blend.h b/src/mesa/main/blend.h
index 8ab9e02..f4854a6 100644
--- a/src/mesa/main/blend.h
+++ b/src/mesa/main/blend.h
@@ -124,7 +124,7 @@ _mesa_update_clamp_vertex_color(struct gl_context *ctx,
extern mesa_format
_mesa_get_render_format(const struct gl_context *ctx, mesa_format format);
-extern void
-_mesa_init_color( struct gl_context * ctx );
+extern void
+_mesa_init_color( struct gl_context * ctx, GLuint doubleBufferMode );
Same comment here about fixing the spacing while changing the prototype.
#endif
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 8b415ed..2a512c6 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -796,7 +796,7 @@ check_context_limits(struct gl_context *ctx)
* functions for the more complex data structures.
*/
static GLboolean
-init_attrib_groups(struct gl_context *ctx)
+init_attrib_groups(struct gl_context *ctx, GLuint doubleBufferMode)
Same comment here about s/GLuint/bool/
{
assert(ctx);
@@ -810,7 +810,7 @@ init_attrib_groups(struct gl_context *ctx)
_mesa_init_accum( ctx );
_mesa_init_attrib( ctx );
_mesa_init_buffer_objects( ctx );
- _mesa_init_color( ctx );
+ _mesa_init_color( ctx, doubleBufferMode );
_mesa_init_current( ctx );
_mesa_init_depth( ctx );
_mesa_init_debug( ctx );
@@ -828,7 +828,7 @@ init_attrib_groups(struct gl_context *ctx)
_mesa_init_multisample( ctx );
_mesa_init_performance_monitors( ctx );
_mesa_init_pipeline( ctx );
- _mesa_init_pixel( ctx );
+ _mesa_init_pixel( ctx, doubleBufferMode );
Spaces.
_mesa_init_pixelstore( ctx );
_mesa_init_point( ctx );
_mesa_init_polygon( ctx );
@@ -1159,15 +1159,6 @@ _mesa_initialize_context(struct gl_context *ctx,
ctx->WinSysDrawBuffer = NULL;
ctx->WinSysReadBuffer = NULL;
- if (visual) {
- ctx->Visual = *visual;
- ctx->HasConfig = GL_TRUE;
- }
- else {
- memset(&ctx->Visual, 0, sizeof ctx->Visual);
- ctx->HasConfig = GL_FALSE;
- }
-
_mesa_override_gl_version(ctx);
/* misc one-time initializations */
@@ -1193,7 +1184,7 @@ _mesa_initialize_context(struct gl_context *ctx,
_mesa_reference_shared_state(ctx, &ctx->Shared, shared);
- if (!init_attrib_groups( ctx ))
+ if (!init_attrib_groups( ctx, visual->doubleBufferMode ))
Spaces.
goto fail;
[Mesa-dev] [PATCH] Rework the compatibility check of visuals in glXMakeCurrent
Now it follows the GLX 1.4 specification.
This fixes post-processing in SW:KotOR.
---
src/mesa/main/context.c | 44 +---
1 file changed, 13 insertions(+), 31 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 8b415ed..988fb40 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1524,13 +1524,9 @@ _mesa_copy_context( const struct gl_context *src, struct
gl_context *dst,
* Check if the given context can render into the given framebuffer
* by checking visual attributes.
*
- * Most of these tests could go away because Mesa is now pretty flexible
- * in terms of mixing rendering contexts with framebuffers. As long
- * as RGB vs. CI mode agree, we're probably good.
- *
* \return GL_TRUE if compatible, GL_FALSE otherwise.
*/
-static GLboolean
+static GLboolean
check_compatible(const struct gl_context *ctx,
const struct gl_framebuffer *buffer)
{
@@ -1540,32 +1536,18 @@ check_compatible(const struct gl_context *ctx,
if (buffer == _mesa_get_incomplete_framebuffer())
return GL_TRUE;
-#if 0
- /* disabling this fixes the fgl_glxgears pbuffer demo */
- if (ctxvis->doubleBufferMode && !bufvis->doubleBufferMode)
- return GL_FALSE;
-#endif
- if (ctxvis->stereoMode && !bufvis->stereoMode)
- return GL_FALSE;
- if (ctxvis->haveAccumBuffer && !bufvis->haveAccumBuffer)
- return GL_FALSE;
- if (ctxvis->haveDepthBuffer && !bufvis->haveDepthBuffer)
- return GL_FALSE;
- if (ctxvis->haveStencilBuffer && !bufvis->haveStencilBuffer)
- return GL_FALSE;
- if (ctxvis->redMask && ctxvis->redMask != bufvis->redMask)
- return GL_FALSE;
- if (ctxvis->greenMask && ctxvis->greenMask != bufvis->greenMask)
- return GL_FALSE;
- if (ctxvis->blueMask && ctxvis->blueMask != bufvis->blueMask)
- return GL_FALSE;
-#if 0
- /* disabled (see bug 11161) */
- if (ctxvis->depthBits && ctxvis->depthBits != bufvis->depthBits)
- return GL_FALSE;
-#endif
- if (ctxvis->stencilBits && ctxvis->stencilBits != bufvis->stencilBits)
- return GL_FALSE;
+#define check_component(foo) \
+ if (ctxvis->foo && bufvis->foo && \
+ ctxvis->foo != bufvis->foo) \
+ return GL_FALSE
+
+ check_component(redMask);
+ check_component(greenMask);
+ check_component(blueMask);
+ check_component(depthBits);
+ check_component(stencilBits);
+
+#undef check_component
return GL_TRUE;
}
--
2.7.0
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[Mesa-dev] [PATCH] mesa: default FixedSampleLocations to true when using a dummy image
GL_ARB_texture_multisample and GLES 3.1 expect the initial value to be GL_TRUE. This fixes dEQP-GLES31.functional.state_query.texture_level.texture_2d_multisample_array.fixed_sample_locations_integer and a few related tests. Signed-off-by: Ilia Mirkin --- src/mesa/main/texparam.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c index ed83830..c5f493f 100644 --- a/src/mesa/main/texparam.c +++ b/src/mesa/main/texparam.c @@ -1310,6 +1310,7 @@ get_tex_level_parameter_image(struct gl_context *ctx, dummy_image.TexFormat = MESA_FORMAT_NONE; dummy_image.InternalFormat = GL_RGBA; dummy_image._BaseFormat = GL_NONE; + dummy_image.FixedSampleLocations = GL_TRUE; img = &dummy_image; } -- 2.4.10 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [v2 02/19] i965: Separate miptree creation from auxiliary buffer setup
On Thu, Feb 11, 2016 at 08:33:55PM +0200, Topi Pohjolainen wrote:
> Currently the logic allocating and setting up miptrees is closely
> combined with decision making when to re-allocate buffers in
> X-tiled layout and when to associate colors with auxiliary buffers.
>
> These auxiliary buffers are in turn also represented as miptrees
> and are created by the same miptree creation logic calling itself
> recursively. This means considering in vain if the auxiliary buffers
> should be represented in X-tiled layout or if they should be
> associated with auxiliary buffers again.
> While this is somewhat unnecessary, this doesn't impose any problems
> currently. Miptrees for auxiliary buffers are created as simgle-sampled
> fusing the consideration for multi-sampled compression auxiliary
> buffers. The format in turn is such that is not applicable for
> single-sampled fast clears (that would require accompaning auxiliary
> buffer).
> But once the driver starts to support lossless compression of color
> buffers the auxiliary buffer will have a format that would itself
> be applicable for lossless compression. This would be rather
> difficult and ugly to detect in the current miptree creation logic,
> and therefore this patch seeks to separate the association logic
> from the general allocation and setup steps.
>
> v2 (Ben):
>- Do not reconsider for X-tiling in intel_miptree_create()
> as it was just forced to Y-tiling in miptree_create().
>- Do not drop checks for allocation failures.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 56
> +++
> 1 file changed, 39 insertions(+), 17 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 97dd3d9..e8b3116 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -609,17 +609,17 @@ intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt,
> unsigned *alignment,
> return size;
> }
>
> -struct intel_mipmap_tree *
> -intel_miptree_create(struct brw_context *brw,
> - GLenum target,
> - mesa_format format,
> - GLuint first_level,
> - GLuint last_level,
> - GLuint width0,
> - GLuint height0,
> - GLuint depth0,
> - GLuint num_samples,
> - uint32_t layout_flags)
> +static struct intel_mipmap_tree *
> +miptree_create(struct brw_context *brw,
> + GLenum target,
> + mesa_format format,
> + GLuint first_level,
> + GLuint last_level,
> + GLuint width0,
> + GLuint height0,
> + GLuint depth0,
> + GLuint num_samples,
> + uint32_t layout_flags)
> {
> struct intel_mipmap_tree *mt;
> mesa_format tex_format = format;
> @@ -644,12 +644,8 @@ intel_miptree_create(struct brw_context *brw,
>return NULL;
> }
>
> - bool y_or_x = false;
> -
> - if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) {
> - y_or_x = true;
> + if (mt->tiling == (I915_TILING_Y | I915_TILING_X))
>mt->tiling = I915_TILING_Y;
> - }
>
> if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
>alloc_flags |= BO_ALLOC_FOR_RENDER;
> @@ -682,11 +678,37 @@ intel_miptree_create(struct brw_context *brw,
>
> mt->pitch = pitch;
>
> + return mt;
> +}
> +
> +struct intel_mipmap_tree *
> +intel_miptree_create(struct brw_context *brw,
> + GLenum target,
> + mesa_format format,
> + GLuint first_level,
> + GLuint last_level,
> + GLuint width0,
> + GLuint height0,
> + GLuint depth0,
> + GLuint num_samples,
> + uint32_t layout_flags)
> +{
> + struct intel_mipmap_tree *mt = miptree_create(
> + brw, target, format,
> + first_level, last_level,
> + width0, height0, depth0, num_samples,
> + layout_flags);
> +
> /* If the BO is too large to fit in the aperture, we need to use the
> * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
> * handle Y-tiling, so we need to fall back to X.
> */
> - if (brw->gen < 6 && y_or_x && mt->bo->size >=
> brw->max_gtt_map_object_size) {
> + if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size &&
> + mt->tiling == I915_TILING_Y) {
> + unsigned long pitch = mt->pitch;
> + const uint32_t alloc_flags =
> + (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ?
> + BO_ALLOC_FOR_RENDER : 0;
>perf_debug("%dx%d miptr
Re: [Mesa-dev] [PATCH 2/3] i965/fs: Pass usage of depth, W, and sample mask through prog_data
On Thursday, February 11, 2016 10:04:27 AM PST Jason Ekstrand wrote:
> We really need to stop pulling information directly out of shaders for
> state setup. For one thing, if we want any sort of an on-disk shader
> cache, having all of this metadata in one place is going to be crucial.
> Also, passing it all through prog_data cleans up the compiler <-> state
> setup API substantially.
> ---
> src/mesa/drivers/dri/i965/brw_compiler.h | 3 +++
> src/mesa/drivers/dri/i965/brw_fs.cpp | 15 ++-
> src/mesa/drivers/dri/i965/brw_wm_iz.cpp | 7 ---
> src/mesa/drivers/dri/i965/brw_wm_state.c | 3 +--
> src/mesa/drivers/dri/i965/gen7_wm_state.c | 8 +++-
> src/mesa/drivers/dri/i965/gen8_ps_state.c | 5 +++--
> 6 files changed, 24 insertions(+), 17 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/
dri/i965/brw_compiler.h
> index 5e88310..b8423ec 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.h
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.h
> @@ -384,6 +384,9 @@ struct brw_wm_prog_data {
> bool uses_pos_offset;
> bool uses_omask;
> bool uses_kill;
> + bool uses_src_depth;
> + bool uses_src_w;
> + bool uses_sample_mask;
> bool pulls_bary;
> uint32_t prog_offset_16;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/
i965/brw_fs.cpp
> index c0af749..75761cb 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -4854,8 +4854,6 @@ fs_visitor::setup_fs_payload_gen6()
> brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
> brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
>
> - bool uses_depth =
> - (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> unsigned barycentric_interp_modes =
>(stage == MESA_SHADER_FRAGMENT) ?
>((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
> @@ -4884,7 +4882,9 @@ fs_visitor::setup_fs_payload_gen6()
> }
>
> /* R27: interpolated depth if uses source depth */
> - if (uses_depth) {
> + prog_data->uses_src_depth =
> + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> + if (prog_data->uses_src_depth) {
>payload.source_depth_reg = payload.num_regs;
>payload.num_regs++;
>if (dispatch_width == 16) {
> @@ -4892,8 +4892,11 @@ fs_visitor::setup_fs_payload_gen6()
> payload.num_regs++;
>}
> }
> +
> /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
> - if (uses_depth) {
> + prog_data->uses_src_w =
> + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> + if (prog_data->uses_src_w) {
>payload.source_w_reg = payload.num_regs;
>payload.num_regs++;
>if (dispatch_width == 16) {
> @@ -4910,7 +4913,9 @@ fs_visitor::setup_fs_payload_gen6()
> }
>
> /* R32: MSAA input coverage mask */
> - if (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) {
> + prog_data->uses_sample_mask =
> + (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
> + if (prog_data->uses_sample_mask) {
>assert(devinfo->gen >= 7);
>payload.sample_mask_in_reg = payload.num_regs;
>payload.num_regs++;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/
i965/brw_wm_iz.cpp
> index 9d9f4e4..bfd14f2 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
> @@ -123,12 +123,11 @@ static const struct {
> void fs_visitor::setup_fs_payload_gen4()
> {
> assert(stage == MESA_SHADER_FRAGMENT);
> + brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
> brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
> GLuint reg = 2;
> bool kill_stats_promoted_workaround = false;
> int lookup = key->iz_lookup;
> - bool uses_depth =
> - (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
>
> assert(lookup < IZ_BIT_MAX);
>
> @@ -143,7 +142,9 @@ void fs_visitor::setup_fs_payload_gen4()
>kill_stats_promoted_workaround = true;
> }
>
> - if (wm_iz_table[lookup].sd_present || uses_depth ||
> + prog_data->uses_src_depth =
> + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> + if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
> kill_stats_promoted_workaround) {
>payload.source_depth_reg = reg;
>reg += 2;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/
dri/i965/brw_wm_state.c
> index ec54ef2..6bf0a55 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
> @@ -175,8 +175,7 @@ brw_upload_wm_unit(struct brw_context *brw)
> }
>
> /* BRW_NEW_FRAGMENT_PROGRAM */
> - wm->wm5.program_uses_depth = (fp->Base.InputsRead &
> - (1 << VARYING_SLOT_POS)) != 0;
> + wm->wm5.program_uses_depth = prog_data->uses_src_depth;
> wm->w
[Mesa-dev] [PATCH] mesa: allow DEPTH_STENCIL_TEXTURE_MODE queries in GLES 3.1 contexts
This fixes
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.depth_stencil_mode_integer
and a few related tests.
Signed-off-by: Ilia Mirkin
---
src/mesa/main/texparam.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index 89f286c..ed83830 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -500,9 +500,7 @@ set_tex_parameteri(struct gl_context *ctx,
goto invalid_pname;
case GL_DEPTH_STENCIL_TEXTURE_MODE:
- if ((_mesa_is_desktop_gl(ctx) &&
- ctx->Extensions.ARB_stencil_texturing) ||
- _mesa_is_gles31(ctx)) {
+ if (_mesa_has_ARB_stencil_texturing(ctx) || _mesa_is_gles31(ctx)) {
bool stencil = params[0] == GL_STENCIL_INDEX;
if (!stencil && params[0] != GL_DEPTH_COMPONENT)
goto invalid_param;
@@ -1819,7 +1817,7 @@ get_tex_parameterfv(struct gl_context *ctx,
*params = (GLfloat) obj->DepthMode;
break;
case GL_DEPTH_STENCIL_TEXTURE_MODE:
- if (!_mesa_is_desktop_gl(ctx) ||
!ctx->Extensions.ARB_stencil_texturing)
+ if (!_mesa_has_ARB_stencil_texturing(ctx) && !_mesa_is_gles31(ctx))
goto invalid_pname;
*params = (GLfloat)
(obj->StencilSampling ? GL_STENCIL_INDEX : GL_DEPTH_COMPONENT);
@@ -2054,7 +2052,7 @@ get_tex_parameteriv(struct gl_context *ctx,
*params = (GLint) obj->DepthMode;
break;
case GL_DEPTH_STENCIL_TEXTURE_MODE:
- if (!_mesa_is_desktop_gl(ctx) ||
!ctx->Extensions.ARB_stencil_texturing)
+ if (!_mesa_has_ARB_stencil_texturing(ctx) && !_mesa_is_gles31(ctx))
goto invalid_pname;
*params = (GLint)
(obj->StencilSampling ? GL_STENCIL_INDEX : GL_DEPTH_COMPONENT);
--
2.4.10
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Re: [Mesa-dev] [PATCH 2/3] i965/fs: Pass usage of depth, W, and sample mask through prog_data
On Thursday, February 11, 2016 10:04:27 AM PST Jason Ekstrand wrote:
> We really need to stop pulling information directly out of shaders for
> state setup. For one thing, if we want any sort of an on-disk shader
> cache, having all of this metadata in one place is going to be crucial.
> Also, passing it all through prog_data cleans up the compiler <-> state
> setup API substantially.
> ---
> src/mesa/drivers/dri/i965/brw_compiler.h | 3 +++
> src/mesa/drivers/dri/i965/brw_fs.cpp | 15 ++-
> src/mesa/drivers/dri/i965/brw_wm_iz.cpp | 7 ---
> src/mesa/drivers/dri/i965/brw_wm_state.c | 3 +--
> src/mesa/drivers/dri/i965/gen7_wm_state.c | 8 +++-
> src/mesa/drivers/dri/i965/gen8_ps_state.c | 5 +++--
> 6 files changed, 24 insertions(+), 17 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/
dri/i965/brw_compiler.h
> index 5e88310..b8423ec 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.h
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.h
> @@ -384,6 +384,9 @@ struct brw_wm_prog_data {
> bool uses_pos_offset;
> bool uses_omask;
> bool uses_kill;
> + bool uses_src_depth;
> + bool uses_src_w;
> + bool uses_sample_mask;
> bool pulls_bary;
> uint32_t prog_offset_16;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/
i965/brw_fs.cpp
> index c0af749..75761cb 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -4854,8 +4854,6 @@ fs_visitor::setup_fs_payload_gen6()
> brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
> brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
>
> - bool uses_depth =
> - (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> unsigned barycentric_interp_modes =
>(stage == MESA_SHADER_FRAGMENT) ?
>((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
> @@ -4884,7 +4882,9 @@ fs_visitor::setup_fs_payload_gen6()
> }
>
> /* R27: interpolated depth if uses source depth */
> - if (uses_depth) {
> + prog_data->uses_src_depth =
> + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> + if (prog_data->uses_src_depth) {
>payload.source_depth_reg = payload.num_regs;
>payload.num_regs++;
>if (dispatch_width == 16) {
> @@ -4892,8 +4892,11 @@ fs_visitor::setup_fs_payload_gen6()
> payload.num_regs++;
>}
> }
> +
> /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
> - if (uses_depth) {
> + prog_data->uses_src_w =
> + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> + if (prog_data->uses_src_w) {
>payload.source_w_reg = payload.num_regs;
>payload.num_regs++;
>if (dispatch_width == 16) {
> @@ -4910,7 +4913,9 @@ fs_visitor::setup_fs_payload_gen6()
> }
>
> /* R32: MSAA input coverage mask */
> - if (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) {
> + prog_data->uses_sample_mask =
> + (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
> + if (prog_data->uses_sample_mask) {
>assert(devinfo->gen >= 7);
>payload.sample_mask_in_reg = payload.num_regs;
>payload.num_regs++;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/
i965/brw_wm_iz.cpp
> index 9d9f4e4..bfd14f2 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
> @@ -123,12 +123,11 @@ static const struct {
> void fs_visitor::setup_fs_payload_gen4()
> {
> assert(stage == MESA_SHADER_FRAGMENT);
> + brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
> brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
> GLuint reg = 2;
> bool kill_stats_promoted_workaround = false;
> int lookup = key->iz_lookup;
> - bool uses_depth =
> - (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
>
> assert(lookup < IZ_BIT_MAX);
>
> @@ -143,7 +142,9 @@ void fs_visitor::setup_fs_payload_gen4()
>kill_stats_promoted_workaround = true;
> }
>
> - if (wm_iz_table[lookup].sd_present || uses_depth ||
> + prog_data->uses_src_depth =
> + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
> + if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
> kill_stats_promoted_workaround) {
>payload.source_depth_reg = reg;
>reg += 2;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/
dri/i965/brw_wm_state.c
> index ec54ef2..6bf0a55 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
> @@ -175,8 +175,7 @@ brw_upload_wm_unit(struct brw_context *brw)
> }
>
> /* BRW_NEW_FRAGMENT_PROGRAM */
> - wm->wm5.program_uses_depth = (fp->Base.InputsRead &
> - (1 << VARYING_SLOT_POS)) != 0;
> + wm->wm5.program_uses_depth = prog_data->uses_src_depth;
> wm->w
Re: [Mesa-dev] [PATCH v3 00/19] add compute shaders support
On 02/11/2016 08:03 PM, Marek Olšák wrote: BTW, all my Reviewed-by tags that I gave you for v1 and v2 now also apply to v3. Thanks for your time and patience. :-) Marek On Thu, Feb 11, 2016 at 12:21 PM, Marek Olšák wrote: Patches 3-4, 8-10, 12, 14-15: Reviewed-by: Marek Olšák Marek On Wed, Feb 10, 2016 at 7:10 PM, Samuel Pitoiset wrote: Hi, This series adds the core support for ARB_compute_shader which is required for OpenGL 4.3. This series is now based on mesa master since Ilia has pushed his work related to ssbo+atomics. In piglit, this passes all compute related tests except two of them which are related to ARB_shader_image_load_store (Ilia is currently working on it). In dEQP, there are 92 fails and 1383 passes. The list of fails are explained below. Importand changes from v3: - ARB_compute_shader is not exposed by default because compute shaders required images support... To use it, don't forget to set MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader (suggested by Ilia) - dump the TGSI compute program in the trace driver - correctly initialize pipe_grid_info for nv50/nvc0 Important changes from v2: - introduce TGSI_FILE_MEMORY and make use it instead of TGSI_FILE_BUFFER - add PIPE_SHADER_CAP_SUPPORTED_IRS and enable ARB_compute_shader only if the underlying driver supports TGSI - do not reserve a buffer for shared memory, that's useless Patches which still need to be reviewed: - gallium: add a new interface for pipe_context::launch_grid() (v1 only) - gallium: add indirect compute parameters to pipe_grid_info (v1 only) - gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS - tgsi/ureg: add shared variables support for compute shaders - st/mesa: add a second pipeline for compute (v1 only) - st/mesa: add intrinsics for shared variables (v1 only) - st/mesa: add mappings for compute shader sysvals (v1 only) - st/mesa: implement limits for ARB_compute_shader (v1 only) Only minor changes have been applied since the v1, but I just want to be sure that all patches are correctly Rb. The Gallium interface is now stable, so I will probably push this series this week if I don't get strong objections. :-) Please review, thanks! Ilia Mirkin (1): mesa: make compute maximums reflect driver-provided values Samuel Pitoiset (18): mesa: do not use a constant for MAX_COMPUTE_SHARED_SIZE mesa: store shared size in gl_compute_program mesa: add PROGRAM_MEMORY gallium/cso: add support for compute shaders gallium: add a new interface for pipe_context::launch_grid() gallium: add indirect compute parameters to pipe_grid_info gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS tgsi/ureg: add shared variables support for compute shaders st/mesa: add a second pipeline for compute st/mesa: add compute shader states st/mesa: add conversion for compute shaders st/mesa: add intrinsics for shared variables st/mesa: keep track of shared memory declarations st/mesa: add mappings for compute shader sysvals st/mesa: add state validation for compute shaders st/mesa: add compute program dispatch callbacks st/mesa: implement limits for ARB_compute_shader trace: add all compute related functions src/compiler/glsl/builtin_variables.cpp| 15 ++- src/compiler/glsl/glsl_parser_extras.cpp | 7 + src/compiler/glsl/glsl_parser_extras.h | 5 + src/compiler/glsl/main.cpp | 5 + src/gallium/auxiliary/cso_cache/cso_context.c | 30 + src/gallium/auxiliary/cso_cache/cso_context.h | 4 + src/gallium/auxiliary/gallivm/lp_bld_limits.h | 2 + src/gallium/auxiliary/tgsi/tgsi_build.c| 1 + src/gallium/auxiliary/tgsi/tgsi_dump.c | 5 + src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 + src/gallium/auxiliary/tgsi/tgsi_strings.c | 1 + src/gallium/auxiliary/tgsi/tgsi_text.c | 3 + src/gallium/auxiliary/tgsi/tgsi_ureg.c | 32 + src/gallium/auxiliary/tgsi/tgsi_ureg.h | 3 + src/gallium/docs/source/screen.rst | 2 + src/gallium/drivers/freedreno/freedreno_screen.c | 2 + src/gallium/drivers/ilo/ilo_gpgpu.c| 8 +- src/gallium/drivers/ilo/ilo_screen.c | 2 + src/gallium/drivers/nouveau/nv50/nv50_compute.c| 16 +-- src/gallium/drivers/nouveau/nv50/nv50_context.h| 3 +- .../drivers/nouveau/nv50/nv50_query_hw_sm.c| 12 +- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 19 ++- src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 6 +- .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 12 +- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 + src/gallium/drivers/nouveau/nvc0/nve4_compute.c| 10 +- src/gallium/drivers/r300/r300_screen.c | 4 + src/gallium/drivers/r600/evergreen_compute.c | 19 ++- src/gallium/drivers/r600/r600_pipe.c
[Mesa-dev] [PATCH 11/19] st/mesa: add compute shader states
Changes from v2:
- use as much common code as possible (eg. st_basic_variant)
Signed-off-by: Samuel Pitoiset
Reviewed-by: Marek Olšák (v1)
Reviewed-by: Ilia Mirkin (v1)
---
src/mesa/state_tracker/st_atom.c| 2 +-
src/mesa/state_tracker/st_atom.h| 1 +
src/mesa/state_tracker/st_atom_shader.c | 32
src/mesa/state_tracker/st_cb_program.c | 30 +++
src/mesa/state_tracker/st_context.c | 1 +
src/mesa/state_tracker/st_context.h | 3 ++
src/mesa/state_tracker/st_extensions.c | 7 ++-
src/mesa/state_tracker/st_program.c | 88 +
src/mesa/state_tracker/st_program.h | 41 +++
9 files changed, 202 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom.c b/src/mesa/state_tracker/st_atom.c
index 2d89512..3427a92 100644
--- a/src/mesa/state_tracker/st_atom.c
+++ b/src/mesa/state_tracker/st_atom.c
@@ -98,7 +98,7 @@ static const struct st_tracked_state *render_atoms[] =
*/
static const struct st_tracked_state *compute_atoms[] =
{
- /* will be updated in the next commit */
+ &st_update_cp,
};
diff --git a/src/mesa/state_tracker/st_atom.h b/src/mesa/state_tracker/st_atom.h
index 77e2163..ef33645 100644
--- a/src/mesa/state_tracker/st_atom.h
+++ b/src/mesa/state_tracker/st_atom.h
@@ -58,6 +58,7 @@ extern const struct st_tracked_state st_update_gp;
extern const struct st_tracked_state st_update_tep;
extern const struct st_tracked_state st_update_tcp;
extern const struct st_tracked_state st_update_vp;
+extern const struct st_tracked_state st_update_cp;
extern const struct st_tracked_state st_update_rasterizer;
extern const struct st_tracked_state st_update_polygon_stipple;
extern const struct st_tracked_state st_update_viewport;
diff --git a/src/mesa/state_tracker/st_atom_shader.c
b/src/mesa/state_tracker/st_atom_shader.c
index c8650a5..a88f035 100644
--- a/src/mesa/state_tracker/st_atom_shader.c
+++ b/src/mesa/state_tracker/st_atom_shader.c
@@ -255,3 +255,35 @@ const struct st_tracked_state st_update_tep = {
},
update_tep /* update */
};
+
+
+
+static void
+update_cp( struct st_context *st )
+{
+ struct st_compute_program *stcp;
+
+ if (!st->ctx->ComputeProgram._Current) {
+ cso_set_compute_shader_handle(st->cso_context, NULL);
+ return;
+ }
+
+ stcp = st_compute_program(st->ctx->ComputeProgram._Current);
+ assert(stcp->Base.Base.Target == GL_COMPUTE_PROGRAM_NV);
+
+ st->cp_variant = st_get_cp_variant(st, &stcp->tgsi, &stcp->variants);
+
+ st_reference_compprog(st, &st->cp, stcp);
+
+ cso_set_compute_shader_handle(st->cso_context,
+ st->cp_variant->driver_shader);
+}
+
+const struct st_tracked_state st_update_cp = {
+ "st_update_cp", /* name */
+ { /* dirty */
+ 0, /* mesa */
+ ST_NEW_COMPUTE_PROGRAM /* st */
+ },
+ update_cp /* update */
+};
diff --git a/src/mesa/state_tracker/st_cb_program.c
b/src/mesa/state_tracker/st_cb_program.c
index ca493d8..27cc0f3 100644
--- a/src/mesa/state_tracker/st_cb_program.c
+++ b/src/mesa/state_tracker/st_cb_program.c
@@ -74,6 +74,9 @@ st_bind_program(struct gl_context *ctx, GLenum target, struct
gl_program *prog)
case GL_TESS_EVALUATION_PROGRAM_NV:
st->dirty.st |= ST_NEW_TESSEVAL_PROGRAM;
break;
+ case GL_COMPUTE_PROGRAM_NV:
+ st->dirty_cp.st |= ST_NEW_COMPUTE_PROGRAM;
+ break;
}
}
@@ -92,6 +95,7 @@ st_use_program(struct gl_context *ctx, struct
gl_shader_program *shProg)
st->dirty.st |= ST_NEW_GEOMETRY_PROGRAM;
st->dirty.st |= ST_NEW_TESSCTRL_PROGRAM;
st->dirty.st |= ST_NEW_TESSEVAL_PROGRAM;
+ st->dirty_cp.st |= ST_NEW_COMPUTE_PROGRAM;
}
@@ -123,6 +127,10 @@ st_new_program(struct gl_context *ctx, GLenum target,
GLuint id)
struct st_tesseval_program *prog = ST_CALLOC_STRUCT(st_tesseval_program);
return _mesa_init_gl_program(&prog->Base.Base, target, id);
}
+ case GL_COMPUTE_PROGRAM_NV: {
+ struct st_compute_program *prog = ST_CALLOC_STRUCT(st_compute_program);
+ return _mesa_init_gl_program(&prog->Base.Base, target, id);
+ }
default:
assert(0);
return NULL;
@@ -195,6 +203,17 @@ st_delete_program(struct gl_context *ctx, struct
gl_program *prog)
free_glsl_to_tgsi_visitor(sttep->glsl_to_tgsi);
}
break;
+ case GL_COMPUTE_PROGRAM_NV:
+ {
+ struct st_compute_program *stcp =
+(struct st_compute_program *) prog;
+
+ st_release_cp_variants(st, stcp);
+
+ if (stcp->glsl_to_tgsi)
+free_glsl_to_tgsi_visitor(stcp->glsl_to_tgsi);
+ }
+ break;
default:
assert(0); /* problem */
}
@@ -272,6 +291,17 @@ st_program_string_notify( struct gl_context *ctx,
if (st->tep == sttep)
st->dirty.st |= ST_NEW_TESS
Re: [Mesa-dev] [PATCH 01/13] meta: Convert _mesa_meta_bind_fbo_image to take a gl_framebuffer instead of a GL API handle
On Thu, Feb 11, 2016 at 08:50:51PM +0200, Pohjolainen, Topi wrote: > On Wed, Feb 10, 2016 at 10:13:11PM -0800, Ian Romanick wrote: > > From: Ian Romanick > > > > Also change the name of the function to > > _mesa_meta_framebuffer_texture_image. The function is basically a > > wrapper around _mesa_framebuffer_texture (which is used to implement > > glFramebufferTexture1D and friends), so it makes sense for it's name to > > be similar to that. > > > > The next patch will clean _mesa_meta_framebuffer_texture_image up > > considerably. > > > > Signed-off-by: Ian Romanick > > I'm not super familiar with the logic, but I tried comparing the > implementation of the currently called functions to your changes. > > Patches 1-8 look good to me and are > > Reviewed-by: Topi Pohjolainen I can't actually spot anything amiss in the rest of the series either, therefore the rest: Reviewed-by: Topi Pohjolainen ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: allow multisampled format info to be returned on GLES 3.1
The restriction on multisampled integer texture formats only applies to
GLES 3.0, so don't apply it to GLES 3.1 contexts. This fixes a slew of
dEQP-GLES31.functional.state_query.internal_format.*
tests, which now all pass.
Signed-off-by: Ilia Mirkin
---
src/mesa/main/formatquery.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/formatquery.c b/src/mesa/main/formatquery.c
index 85f7b6b..cfadffd 100644
--- a/src/mesa/main/formatquery.c
+++ b/src/mesa/main/formatquery.c
@@ -131,7 +131,8 @@ _mesa_GetInternalformativ(GLenum target, GLenum
internalformat, GLenum pname,
internalformat, buffer);
break;
case GL_NUM_SAMPLE_COUNTS: {
- if (_mesa_is_gles3(ctx) && _mesa_is_enum_format_integer(internalformat))
{
+ if (_mesa_is_gles3(ctx) && !_mesa_is_gles31(ctx) &&
+ _mesa_is_enum_format_integer(internalformat)) {
/* From GL ES 3.0 specification, section 6.1.15 page 236: "Since
* multisampling is not supported for signed and unsigned integer
* internal formats, the value of NUM_SAMPLE_COUNTS will be zero
--
2.4.10
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Re: [Mesa-dev] [v2 01/19] i965: Isolate aligned dimensions for stencil only
On Thu, Feb 11, 2016 at 08:33:54PM +0200, Topi Pohjolainen wrote: > This makes the logic a little more explicit and helps to keep > subsequent patches easier to read. > > Suggested-by: Ben Widawsky > Signed-off-by: Topi Pohjolainen Reviewed-by: Ben Widawsky [snip] ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v3 00/19] add compute shaders support
BTW, all my Reviewed-by tags that I gave you for v1 and v2 now also apply to v3. Marek On Thu, Feb 11, 2016 at 12:21 PM, Marek Olšák wrote: > Patches 3-4, 8-10, 12, 14-15: > > Reviewed-by: Marek Olšák > > Marek > > On Wed, Feb 10, 2016 at 7:10 PM, Samuel Pitoiset > wrote: >> Hi, >> >> This series adds the core support for ARB_compute_shader which is required >> for >> OpenGL 4.3. This series is now based on mesa master since Ilia has pushed his >> work related to ssbo+atomics. >> >> In piglit, this passes all compute related tests except two of them which are >> related to ARB_shader_image_load_store (Ilia is currently working on it). >> >> In dEQP, there are 92 fails and 1383 passes. The list of fails are >> explained below. >> >> Importand changes from v3: >> - ARB_compute_shader is not exposed by default because compute shaders >>required images support... To use it, don't forget to set >>MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader (suggested by Ilia) >> - dump the TGSI compute program in the trace driver >> - correctly initialize pipe_grid_info for nv50/nvc0 >> >> Important changes from v2: >> - introduce TGSI_FILE_MEMORY and make use it instead of TGSI_FILE_BUFFER >> - add PIPE_SHADER_CAP_SUPPORTED_IRS and enable ARB_compute_shader only if >> the >> underlying driver supports TGSI >> - do not reserve a buffer for shared memory, that's useless >> >> Patches which still need to be reviewed: >> - gallium: add a new interface for pipe_context::launch_grid() (v1 only) >> - gallium: add indirect compute parameters to pipe_grid_info (v1 only) >> - gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS >> - tgsi/ureg: add shared variables support for compute shaders >> - st/mesa: add a second pipeline for compute (v1 only) >> - st/mesa: add intrinsics for shared variables (v1 only) >> - st/mesa: add mappings for compute shader sysvals (v1 only) >> - st/mesa: implement limits for ARB_compute_shader (v1 only) >> >> Only minor changes have been applied since the v1, but I just want to be sure >> that all patches are correctly Rb. The Gallium interface is now stable, so I >> will probably push this series this week if I don't get strong objections. >> :-) >> >> Please review, thanks! >> >> Ilia Mirkin (1): >> mesa: make compute maximums reflect driver-provided values >> >> Samuel Pitoiset (18): >> mesa: do not use a constant for MAX_COMPUTE_SHARED_SIZE >> mesa: store shared size in gl_compute_program >> mesa: add PROGRAM_MEMORY >> gallium/cso: add support for compute shaders >> gallium: add a new interface for pipe_context::launch_grid() >> gallium: add indirect compute parameters to pipe_grid_info >> gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS >> tgsi/ureg: add shared variables support for compute shaders >> st/mesa: add a second pipeline for compute >> st/mesa: add compute shader states >> st/mesa: add conversion for compute shaders >> st/mesa: add intrinsics for shared variables >> st/mesa: keep track of shared memory declarations >> st/mesa: add mappings for compute shader sysvals >> st/mesa: add state validation for compute shaders >> st/mesa: add compute program dispatch callbacks >> st/mesa: implement limits for ARB_compute_shader >> trace: add all compute related functions >> >> src/compiler/glsl/builtin_variables.cpp| 15 ++- >> src/compiler/glsl/glsl_parser_extras.cpp | 7 + >> src/compiler/glsl/glsl_parser_extras.h | 5 + >> src/compiler/glsl/main.cpp | 5 + >> src/gallium/auxiliary/cso_cache/cso_context.c | 30 + >> src/gallium/auxiliary/cso_cache/cso_context.h | 4 + >> src/gallium/auxiliary/gallivm/lp_bld_limits.h | 2 + >> src/gallium/auxiliary/tgsi/tgsi_build.c| 1 + >> src/gallium/auxiliary/tgsi/tgsi_dump.c | 5 + >> src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 + >> src/gallium/auxiliary/tgsi/tgsi_strings.c | 1 + >> src/gallium/auxiliary/tgsi/tgsi_text.c | 3 + >> src/gallium/auxiliary/tgsi/tgsi_ureg.c | 32 + >> src/gallium/auxiliary/tgsi/tgsi_ureg.h | 3 + >> src/gallium/docs/source/screen.rst | 2 + >> src/gallium/drivers/freedreno/freedreno_screen.c | 2 + >> src/gallium/drivers/ilo/ilo_gpgpu.c| 8 +- >> src/gallium/drivers/ilo/ilo_screen.c | 2 + >> src/gallium/drivers/nouveau/nv50/nv50_compute.c| 16 +-- >> src/gallium/drivers/nouveau/nv50/nv50_context.h| 3 +- >> .../drivers/nouveau/nv50/nv50_query_hw_sm.c| 12 +- >> src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 19 ++- >> src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 6 +- >> .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 12 +- >> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 + >> src/gallium/drivers/nouveau/nvc0/nve4_compute.c| 10 +- >> src/gallium/drivers/r300/r300_screen.
Re: [Mesa-dev] [PATCH] egl/wayland: Try to use wl_surface.damage_buffer for SwapBuffersWithDamage
On Thu, Feb 11, 2016 at 8:34 AM, Derek Foreman
wrote:
> Since commit d1314de293e9e4a63c35f094c3893aaaed8580b4 we ignore
> damage passed to SwapBuffersWithDamage.
>
> Wayland 1.10 now has functionality that allows us to properly
> process those damage rectangles, and a way to query if it's
> available.
>
> Now we can use wl_surface.damage_buffer and interpret the incoming
> damage as being in buffer co-ordinates.
>
> Signed-off-by: Derek Foreman
>
Reviewed-by: Jason Ekstrand
> ---
> src/egl/drivers/dri2/platform_wayland.c | 32
> +---
> 1 file changed, 29 insertions(+), 3 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/platform_wayland.c
> b/src/egl/drivers/dri2/platform_wayland.c
> index c2438f7..b5a5b59 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -653,6 +653,30 @@ create_wl_buffer(struct dri2_egl_surface *dri2_surf)
>&wl_buffer_listener, dri2_surf);
> }
>
> +static EGLBoolean
> +try_damage_buffer(struct dri2_egl_surface *dri2_surf,
> + const EGLint *rects,
> + EGLint n_rects)
> +{
> +#ifdef WL_SURFACE_DAMAGE_BUFFER_SINCE_VERSION
> + int i;
> +
> + if (wl_proxy_get_version((struct wl_proxy *)
> dri2_surf->wl_win->surface)
> + < WL_SURFACE_DAMAGE_BUFFER_SINCE_VERSION)
> + return EGL_FALSE;
> +
> + for (i = 0; i < n_rects; i++) {
> + const int *rect = &rects[i * 4];
> +
> + wl_surface_damage_buffer(dri2_surf->wl_win->surface,
> + rect[0],
> + dri2_surf->base.Height - rect[1] - rect[3],
> + rect[2], rect[3]);
> + }
> + return EGL_TRUE;
> +#endif
> + return EGL_FALSE;
> +}
> /**
> * Called via eglSwapBuffers(), drv->API.SwapBuffers().
> */
> @@ -703,10 +727,12 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
> dri2_surf->dx = 0;
> dri2_surf->dy = 0;
>
> - /* We deliberately ignore the damage region and post maximum damage,
> due to
> + /* If the compositor doesn't support damage_buffer, we deliberately
> +* ignore the damage region and post maximum damage, due to
> * https://bugs.freedesktop.org/78190 */
> - wl_surface_damage(dri2_surf->wl_win->surface,
> - 0, 0, INT32_MAX, INT32_MAX);
> + if (!n_rects || !try_damage_buffer(dri2_surf, rects, n_rects))
> + wl_surface_damage(dri2_surf->wl_win->surface,
> +0, 0, INT32_MAX, INT32_MAX);
>
> if (dri2_dpy->is_different_gpu) {
>_EGLContext *ctx = _eglGetCurrentContext();
> --
> 2.7.0
>
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Re: [Mesa-dev] [PATCH] i965: Rename optimizer debug 00 filename
On Thu, Feb 11, 2016 at 10:55 AM, Ben Widawsky wrote: > This allows ls, and scripts to get the file names in the correct order of > optimization. > > Cc: Chris Forbes > Cc: Matt Turner > Signed-off-by: Ben Widawsky > --- Thanks! I was going to send this too :) Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: Rename optimizer debug 00 filename
This allows ls, and scripts to get the file names in the correct order of
optimization.
Cc: Chris Forbes
Cc: Matt Turner
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0ce7ed1..ac2d608 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -5079,7 +5079,7 @@ fs_visitor::optimize()
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) {
char filename[64];
- snprintf(filename, 64, "%s%d-%s-00-start",
+ snprintf(filename, 64, "%s%d-%s-00-00-start",
stage_abbrev, dispatch_width, nir->info.name);
backend_shader::dump_instructions(filename);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 0d8c104..807ff60 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1869,7 +1869,7 @@ vec4_visitor::run()
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) {
char filename[64];
- snprintf(filename, 64, "%s-%s-00-start",
+ snprintf(filename, 64, "%s-%s-00-00-start",
stage_abbrev, nir->info.name);
backend_shader::dump_instructions(filename);
--
2.7.0
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Re: [Mesa-dev] [PATCH 1/3] configure: Eliminate MSVC2008 compatibility.
On 02/11/2016 05:02 AM, Jose Fonseca wrote: > We no longer need to build any part of Mesa with Windows SDK 7.0.7600 or > MSVC 2008. MSVC 2013 will be the oldest we support. > > In practice this means people are now free to declare variables in the > middle of blocks, on the whole Mesa tree. \o/ And there was much rejoicing! Hella-acked-by: Ian Romanick > Care should still be taken with variable length arrays and void pointer > arithmetic. > --- > configure.ac | 8 +--- > src/gallium/auxiliary/Makefile.am| 4 ++-- > src/gallium/drivers/llvmpipe/Makefile.am | 4 ++-- > src/gallium/drivers/softpipe/Makefile.am | 2 +- > src/gallium/drivers/trace/Makefile.am| 2 +- > src/util/Makefile.am | 2 +- > 6 files changed, 8 insertions(+), 14 deletions(-) > > diff --git a/configure.ac b/configure.ac > index b05f33d..5fd05ee 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -305,8 +305,7 @@ if test "x$GCC" = xyes; then > > # Flags to help ensure that certain portions of the code -- and only > those > # portions -- can be built with MSVC: > -# - src/util, src/gallium/auxiliary, and src/gallium/drivers/llvmpipe > needs > -# to build with Windows SDK 7.0.7600, which bundles MSVC 2008 > +# - src/util, src/gallium/auxiliary, rc/gallium/drivers/llvmpipe, and > # - non-Linux/Posix OpenGL portions needs to build on MSVC 2013 (which > # supports most of C99) > # - the rest has no compiler compiler restrictions > @@ -323,9 +322,6 @@ if test "x$GCC" = xyes; then > AC_MSG_RESULT([yes])], > AC_MSG_RESULT([no])); > CFLAGS="$save_CFLAGS" > - > -MSVC2008_COMPAT_CFLAGS="$MSVC2013_COMPAT_CFLAGS > -Werror=declaration-after-statement" > -MSVC2008_COMPAT_CXXFLAGS="$MSVC2013_COMPAT_CXXFLAGS" > fi > if test "x$GXX" = xyes; then > CXXFLAGS="$CXXFLAGS -Wall" > @@ -353,8 +349,6 @@ fi > > AC_SUBST([MSVC2013_COMPAT_CFLAGS]) > AC_SUBST([MSVC2013_COMPAT_CXXFLAGS]) > -AC_SUBST([MSVC2008_COMPAT_CFLAGS]) > -AC_SUBST([MSVC2008_COMPAT_CXXFLAGS]) > > dnl even if the compiler appears to support it, using visibility attributes > isn't > dnl going to do anything useful currently on cygwin apart from emit lots of > warnings > diff --git a/src/gallium/auxiliary/Makefile.am > b/src/gallium/auxiliary/Makefile.am > index 0ac5c98..82c2869 100644 > --- a/src/gallium/auxiliary/Makefile.am > +++ b/src/gallium/auxiliary/Makefile.am > @@ -8,11 +8,11 @@ AM_CFLAGS = \ > -I$(top_srcdir)/src/gallium/auxiliary/util \ > $(GALLIUM_CFLAGS) \ > $(VISIBILITY_CFLAGS) \ > - $(MSVC2008_COMPAT_CFLAGS) > + $(MSVC2013_COMPAT_CFLAGS) > > AM_CXXFLAGS = \ > $(VISIBILITY_CXXFLAGS) \ > - $(MSVC2008_COMPAT_CXXFLAGS) > + $(MSVC2013_COMPAT_CXXFLAGS) > > libgallium_nir_la_SOURCES = \ > $(NIR_SOURCES) > diff --git a/src/gallium/drivers/llvmpipe/Makefile.am > b/src/gallium/drivers/llvmpipe/Makefile.am > index 1d3853e..85ae0ae 100644 > --- a/src/gallium/drivers/llvmpipe/Makefile.am > +++ b/src/gallium/drivers/llvmpipe/Makefile.am > @@ -26,11 +26,11 @@ include $(top_srcdir)/src/gallium/Automake.inc > AM_CFLAGS = \ > $(GALLIUM_DRIVER_CFLAGS) \ > $(LLVM_CFLAGS) \ > - $(MSVC2008_COMPAT_CFLAGS) > + $(MSVC2013_COMPAT_CFLAGS) > AM_CXXFLAGS= \ > $(GALLIUM_DRIVER_CXXFLAGS) \ > $(LLVM_CXXFLAGS) \ > - $(MSVC2008_COMPAT_CXXFLAGS) > + $(MSVC2013_COMPAT_CXXFLAGS) > > noinst_LTLIBRARIES = libllvmpipe.la > > diff --git a/src/gallium/drivers/softpipe/Makefile.am > b/src/gallium/drivers/softpipe/Makefile.am > index 05126a5..fd77edc 100644 > --- a/src/gallium/drivers/softpipe/Makefile.am > +++ b/src/gallium/drivers/softpipe/Makefile.am > @@ -25,7 +25,7 @@ include $(top_srcdir)/src/gallium/Automake.inc > > AM_CFLAGS = \ > $(GALLIUM_DRIVER_CFLAGS) \ > - $(MSVC2008_COMPAT_CFLAGS) > + $(MSVC2013_COMPAT_CFLAGS) > > noinst_LTLIBRARIES = libsoftpipe.la > > diff --git a/src/gallium/drivers/trace/Makefile.am > b/src/gallium/drivers/trace/Makefile.am > index 6a8a74a..5640192 100644 > --- a/src/gallium/drivers/trace/Makefile.am > +++ b/src/gallium/drivers/trace/Makefile.am > @@ -3,7 +3,7 @@ include $(top_srcdir)/src/gallium/Automake.inc > > AM_CFLAGS = \ > $(GALLIUM_DRIVER_CFLAGS) \ > - $(MSVC2008_COMPAT_CFLAGS) > + $(MSVC2013_COMPAT_CFLAGS) > > noinst_LTLIBRARIES = libtrace.la > > diff --git a/src/util/Makefile.am b/src/util/Makefile.am > index e05a2c5..0935891 100644 > --- a/src/util/Makefile.am > +++ b/src/util/Makefile.am > @@ -38,7 +38,7 @@ libmesautil_la_CPPFLAGS = \ > -I$(top_srcdir)/src/gallium/auxiliary \ > $(SHA1_CFLAGS) \ > $(VISIBILITY_CFLAGS) \ > - $(MSVC2008_COMPAT_CFLAGS) > + $(MSVC2013_COMPAT_CFLAGS) > > libmesautil_la_SOURCES = \ > $(MESA_UTIL_FILES) \ > ___ mesa-dev mailing list mesa-dev@lists.freed
Re: [Mesa-dev] [PATCH 01/13] meta: Convert _mesa_meta_bind_fbo_image to take a gl_framebuffer instead of a GL API handle
On Wed, Feb 10, 2016 at 10:13:11PM -0800, Ian Romanick wrote: > From: Ian Romanick > > Also change the name of the function to > _mesa_meta_framebuffer_texture_image. The function is basically a > wrapper around _mesa_framebuffer_texture (which is used to implement > glFramebufferTexture1D and friends), so it makes sense for it's name to > be similar to that. > > The next patch will clean _mesa_meta_framebuffer_texture_image up > considerably. > > Signed-off-by: Ian Romanick I'm not super familiar with the logic, but I tried comparing the implementation of the currently called functions to your changes. Patches 1-8 look good to me and are Reviewed-by: Topi Pohjolainen ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [v2 18/19] i965: Add helper for lossless compression support
v2: Use explicitly against base type of GL_FLOAT instead of
using _mesa_is_format_integer_color(). Otherwise we miss
GL_UNSIGNED_NORMALIZED.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 22 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 6c233d8..e9fbeeb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -294,6 +294,28 @@ intel_miptree_is_lossless_compressed(const struct
brw_context *brw,
return mt->num_samples <= 1;
}
+bool
+intel_miptree_supports_lossless_compressed(mesa_format format)
+{
+ /* For now compression is only enabled for integer formats even though
+* there exist supported floating point formats also. This is a heuristic
+* decision based on current public benchmarks. In none of the cases these
+* formats provided any improvement but a few cases were seen to regress.
+* Hence these are left to to be enabled in the future when they are known
+* to improve things.
+*/
+ if (_mesa_get_format_datatype(format) == GL_FLOAT)
+ return false;
+
+ /* In principle, fast clear mechanism and lossless compression go hand in
+* hand. However, fast clear can be also used to clear srgb surfaces by
+* using equivalent linear format. This trick, however, can't be extended
+* to be used with lossless compression and therefore a check is needed to
+* see if the format really is linear.
+*/
+ return _mesa_get_srgb_format_linear(format) == format;
+}
+
/**
* Determine depth format corresponding to a depth+stencil format,
* for separate stencil.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7cdfb37..6ce9f75 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -679,6 +679,9 @@ intel_miptree_supports_non_msrt_fast_clear(struct
brw_context *brw,
const struct intel_mipmap_tree *mt);
bool
+intel_miptree_supports_lossless_compressed(mesa_format format);
+
+bool
intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt);
--
2.5.0
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[Mesa-dev] [v2 02/19] i965: Separate miptree creation from auxiliary buffer setup
Currently the logic allocating and setting up miptrees is closely
combined with decision making when to re-allocate buffers in
X-tiled layout and when to associate colors with auxiliary buffers.
These auxiliary buffers are in turn also represented as miptrees
and are created by the same miptree creation logic calling itself
recursively. This means considering in vain if the auxiliary buffers
should be represented in X-tiled layout or if they should be
associated with auxiliary buffers again.
While this is somewhat unnecessary, this doesn't impose any problems
currently. Miptrees for auxiliary buffers are created as simgle-sampled
fusing the consideration for multi-sampled compression auxiliary
buffers. The format in turn is such that is not applicable for
single-sampled fast clears (that would require accompaning auxiliary
buffer).
But once the driver starts to support lossless compression of color
buffers the auxiliary buffer will have a format that would itself
be applicable for lossless compression. This would be rather
difficult and ugly to detect in the current miptree creation logic,
and therefore this patch seeks to separate the association logic
from the general allocation and setup steps.
v2 (Ben):
- Do not reconsider for X-tiling in intel_miptree_create()
as it was just forced to Y-tiling in miptree_create().
- Do not drop checks for allocation failures.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 56 +++
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 97dd3d9..e8b3116 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -609,17 +609,17 @@ intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt,
unsigned *alignment,
return size;
}
-struct intel_mipmap_tree *
-intel_miptree_create(struct brw_context *brw,
- GLenum target,
- mesa_format format,
- GLuint first_level,
- GLuint last_level,
- GLuint width0,
- GLuint height0,
- GLuint depth0,
- GLuint num_samples,
- uint32_t layout_flags)
+static struct intel_mipmap_tree *
+miptree_create(struct brw_context *brw,
+ GLenum target,
+ mesa_format format,
+ GLuint first_level,
+ GLuint last_level,
+ GLuint width0,
+ GLuint height0,
+ GLuint depth0,
+ GLuint num_samples,
+ uint32_t layout_flags)
{
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
@@ -644,12 +644,8 @@ intel_miptree_create(struct brw_context *brw,
return NULL;
}
- bool y_or_x = false;
-
- if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) {
- y_or_x = true;
+ if (mt->tiling == (I915_TILING_Y | I915_TILING_X))
mt->tiling = I915_TILING_Y;
- }
if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
alloc_flags |= BO_ALLOC_FOR_RENDER;
@@ -682,11 +678,37 @@ intel_miptree_create(struct brw_context *brw,
mt->pitch = pitch;
+ return mt;
+}
+
+struct intel_mipmap_tree *
+intel_miptree_create(struct brw_context *brw,
+ GLenum target,
+ mesa_format format,
+ GLuint first_level,
+ GLuint last_level,
+ GLuint width0,
+ GLuint height0,
+ GLuint depth0,
+ GLuint num_samples,
+ uint32_t layout_flags)
+{
+ struct intel_mipmap_tree *mt = miptree_create(
+ brw, target, format,
+ first_level, last_level,
+ width0, height0, depth0, num_samples,
+ layout_flags);
+
/* If the BO is too large to fit in the aperture, we need to use the
* BLT engine to support it. Prior to Sandybridge, the BLT paths can't
* handle Y-tiling, so we need to fall back to X.
*/
- if (brw->gen < 6 && y_or_x && mt->bo->size >= brw->max_gtt_map_object_size)
{
+ if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size &&
+ mt->tiling == I915_TILING_Y) {
+ unsigned long pitch = mt->pitch;
+ const uint32_t alloc_flags =
+ (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ?
+ BO_ALLOC_FOR_RENDER : 0;
perf_debug("%dx%d miptree larger than aperture; falling back to
X-tiled\n",
mt->total_width, mt->total_height);
--
2.5.0
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[Mesa-dev] [v2 08/19] i965: Refactor resolving of auxiliary mode
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 62 --
1 file changed, 29 insertions(+), 33 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index fc8f701..0a52815 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -197,6 +197,28 @@ gen8_emit_fast_clear_color(struct brw_context *brw,
surf[7] |= mt->fast_clear_color_value;
}
+static uint32_t
+gen8_get_aux_mode(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ uint32_t surf_type)
+{
+ if (mt->mcs_mt == NULL)
+ return GEN8_SURFACE_AUX_MODE_NONE;
+
+ /*
+* From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
+* "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
+*
+* From the hardware spec for GEN9:
+* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
+* 16 must be used."
+*/
+ if (brw->gen >= 9 || mt->num_samples == 1)
+ assert(mt->halign == 16);
+
+ return GEN8_SURFACE_AUX_MODE_MCS;
+}
+
static void
gen8_emit_texture_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt,
@@ -209,13 +231,13 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
bool rw, bool for_gather)
{
const unsigned depth = max_layer - min_layer;
- struct intel_mipmap_tree *aux_mt = NULL;
- uint32_t aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
+ struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
unsigned tiling_mode, pitch;
const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
const uint32_t surf_type = translate_tex_target(target);
+ uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
if (mt->format == MESA_FORMAT_S_UINT8) {
tiling_mode = GEN8_SURFACE_TILING_W;
@@ -229,20 +251,9 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
* buffer should always have been resolved before it is used as a texture
* so there is no need for it.
*/
- if (mt->mcs_mt && mt->num_samples > 1) {
- aux_mt = mt->mcs_mt;
- aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
-
- /*
- * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
- * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
- *
- * From the hardware spec for GEN9:
- * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
- * 16 must be used."
- */
- if (brw->gen >= 9 || mt->num_samples == 1)
- assert(mt->halign == 16);
+ if (mt->num_samples <= 1) {
+ aux_mt = NULL;
+ aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
}
uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
@@ -418,8 +429,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
- struct intel_mipmap_tree *aux_mt = NULL;
- uint32_t aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
unsigned width = mt->logical_width0;
unsigned height = mt->logical_height0;
unsigned pitch = mt->pitch;
@@ -472,21 +481,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
__func__, _mesa_get_format_name(rb_format));
}
- if (mt->mcs_mt) {
- aux_mt = mt->mcs_mt;
- aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
-
- /*
- * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
- * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
- *
- * From the hardware spec for GEN9:
- * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
- * 16 must be used."
- */
- if (brw->gen >= 9 || mt->num_samples == 1)
- assert(mt->halign == 16);
- }
+ struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
+ const uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
--
2.5.0
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[Mesa-dev] [v2 15/19] i965/gen9: Refactor msrt mcs initialization
This will be re-used to initialize auxiliary buffers in lossless
compression case.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 ---
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 6c6fbef..a072268 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1449,6 +1449,27 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
}
+static void
+intel_miptree_init_mcs(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ int init_value)
+{
+ /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
+*
+* When MCS buffer is enabled and bound to MSRT, it is required that it
+* is cleared prior to any rendering.
+*
+* Since we don't use the MCS buffer for any purpose other than rendering,
+* it makes sense to just clear it immediately upon allocation.
+*
+* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
+*/
+ void *data = intel_miptree_map_raw(brw, mt->mcs_mt);
+ memset(data, init_value, mt->mcs_mt->total_height * mt->mcs_mt->pitch);
+ intel_miptree_unmap_raw(mt->mcs_mt);
+ mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
+}
+
static bool
intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
@@ -1505,20 +1526,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
0 /* num_samples */,
mcs_flags);
- /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
-*
-* When MCS buffer is enabled and bound to MSRT, it is required that it
-* is cleared prior to any rendering.
-*
-* Since we don't use the MCS buffer for any purpose other than rendering,
-* it makes sense to just clear it immediately upon allocation.
-*
-* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
-*/
- void *data = intel_miptree_map_raw(brw, mt->mcs_mt);
- memset(data, 0xff, mt->mcs_mt->total_height * mt->mcs_mt->pitch);
- intel_miptree_unmap_raw(mt->mcs_mt);
- mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
+ intel_miptree_init_mcs(brw, mt, 0xFF);
return mt->mcs_mt;
}
--
2.5.0
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[Mesa-dev] [v2 10/19] i965: Add means for limiting color resolves
Until now there has been only one type of color buffer that needs
to resolved - namely single sampled fast clear. As even the
sampler engine in GPU doesn't understand the associated meta data,
the color values need to be always resolved prior to reading them.
From SKL onwards there is new scheme supported called the lossless
compresson of single sampled color buffers. This is something that
is understood by the sampling engine and therefore resolving of
these types of buffers is not necessary before sampling.
This patch adds means to make the distinction when considering if
resolve is needed.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_context.c| 8
src/mesa/drivers/dri/i965/intel_blit.c | 4 ++--
src/mesa/drivers/dri/i965/intel_copy_image.c | 4 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 ++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 2 +-
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex_image.c| 2 +-
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +-
10 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c7cb394..e8c5e95 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -71,7 +71,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
* to destination color buffers, and the standard render path is
* fast-color-aware.
*/
- intel_miptree_resolve_color(brw, src_mt);
+ intel_miptree_resolve_color(brw, src_mt, 0);
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 44d2fe4..a5f7a2e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -208,7 +208,7 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
if (!tex_obj || !tex_obj->mt)
continue;
intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
- intel_miptree_resolve_color(brw, tex_obj->mt);
+ intel_miptree_resolve_color(brw, tex_obj->mt, 0);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
}
@@ -223,7 +223,7 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
tex_obj = intel_texture_object(u->TexObj);
if (tex_obj && tex_obj->mt) {
- intel_miptree_resolve_color(brw, tex_obj->mt);
+ intel_miptree_resolve_color(brw, tex_obj->mt, 0);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
}
}
@@ -252,7 +252,7 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
_mesa_get_srgb_format_linear(mt->format) == mt->format)
continue;
- intel_miptree_resolve_color(brw, mt);
+ intel_miptree_resolve_color(brw, mt, 0);
brw_render_cache_set_check_flush(brw, mt->bo);
}
}
@@ -1227,7 +1227,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
if (rb == NULL || rb->mt == NULL)
continue;
if (rb->mt->num_samples <= 1)
- intel_miptree_resolve_color(brw, rb->mt);
+ intel_miptree_resolve_color(brw, rb->mt, 0);
else
intel_renderbuffer_downsample(brw, rb);
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 6d29fbd..72cf9af 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -317,8 +317,8 @@ intel_miptree_blit(struct brw_context *brw,
*/
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
- intel_miptree_resolve_color(brw, src_mt);
- intel_miptree_resolve_color(brw, dst_mt);
+ intel_miptree_resolve_color(brw, src_mt, 0);
+ intel_miptree_resolve_color(brw, dst_mt, 0);
if (src_flip)
src_y = minify(src_mt->physical_height0, src_level -
src_mt->first_level) - src_y - height;
diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c
b/src/mesa/drivers/dri/i965/intel_copy_image.c
index dbbac1c..08b7623 100644
--- a/src/mesa/drivers/dri/i965/intel_copy_image.c
+++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
@@ -270,11 +270,11 @@ intel_copy_image_sub_data(struct gl_context *ctx,
*/
intel_miptree_all_slices_resolve_hiz(brw, src_mt);
intel_miptree_all_slices_resolve_depth(brw, src_mt);
- intel_miptree_resolve_color(brw, src_mt);
+ intel_miptree_resolve_color(brw, src_mt, 0);
intel_miptree_all_slices_resolve_hiz(brw, dst_mt);
intel_miptree_all_slices_resolve_depth(
[Mesa-dev] [v2 19/19] i965/gen9: Enable lossless compression
I tried first creating the auxiliary buffer the same time with the
color buffer. That, however, led me into a situation where we would
later create the rest of the mip-levels and the compression would
need to be disabled (it is only supported for single level buffers).
Here we try to create it on demand just before the hardware starts
to render. This is similar what we do with fast clear buffers,
their creation is deferred until the first clear.
This setup also gives the opportunity to detect if the miptree
represents the temporaty texture used internally in the mesa core.
This texture is mostly written by cpu and therefore enabling
compression for it doesn't make much sense.
Note that a heuristic is included. Floating point formats are not
enabled yet as they are only seen to hurt performance.
Some highlights with window system driver kept fixed to default
and only the application driver changing:
Manhattan: 8.32152% +/- 0.355881%
Offscreen: 9.09713% +/- 0.340763%
Glb trex: 8.46231% +/- 0.460624%
Offscreen: 9.31872% +/- 0.463743%
Numbers from our system where the driver is changed also for
the windowing environment:
GFXBench3_Manhattan 41.8 FPS 12.0 % 46.8 FPS
GFXBench3_Manhattan_OffScreen 48.7 FPS 9.0 % 53.1 FPS
GLBenchmark_Trex_FixedTime133.0 FPS 9.0 % 145.0 FPS
GLBenchmark_Trex_FixedTime_OffScreen 168.0 FPS 9.5 % 184.0 FPS
Unigine-heaven regresses: -2.31021% +/- 0.217207%. There are no color
resolves needed during the run so the hit comes from something else.
Perhaps the content is such that it doesn't really compress but
the additional work required of the hardware to maintain the
associated meta data slows us down.
v2 (Ben): Re-use msaa layout type for single sampled case.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 9 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d1c9b5a..f687418 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -485,6 +485,15 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
__func__, _mesa_get_format_name(rb_format));
}
+ /* Consider if lossless compression is supported but the needed
+* auxiliary buffer doesn't exist yet.
+*/
+ if (brw->gen >= 9 && mt->mcs_mt == NULL &&
+ intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
+ intel_miptree_supports_non_msrt_fast_clear(brw, mt) &&
+ intel_miptree_supports_lossless_compressed(mt->format))
+ intel_miptree_alloc_non_msrt_mcs(brw, mt);
+
struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
const uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e9fbeeb..ee15a2f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -788,7 +788,8 @@ intel_miptree_create(struct brw_context *brw,
/* If this miptree is capable of supporting fast color clears, set
* fast_clear_state appropriately to ensure that fast clears will occur.
* Allocation of the MCS miptree will be deferred until the first fast
-* clear actually occurs.
+* clear actually occurs or when compressed single sampled buffer is
+* written by the GPU for the first time.
*/
if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
@@ -1609,6 +1610,26 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
0 /* num_samples */,
layout_flags);
+ /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
+* used for lossless compression which requires similar initialisation
+* as multi-sample compression.
+*/
+ if (brw->gen >= 9 &&
+ intel_miptree_supports_lossless_compressed(mt->format)) {
+ /* Hardware sets the auxiliary buffer to all zeroes when it does full
+ * resolve. Initialize it accordingly in case the first renderer is
+ * cpu (or other none compression aware party).
+ *
+ * This is also explicitly stated in the spec (MCS Buffer for Render
+ * Target(s)):
+ * "If Software wants to enable Color Compression without Fast clear,
+ *Software needs to initialize MCS with zeros."
+ */
+ intel_miptree_init_mcs(brw, mt, 0);
+ mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
+ mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+ }
+
return mt->mcs_mt;
}
--
2.5.0
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[Mesa-dev] [v2 03/19] i965: Don't try to create aux buffer for non-msrt aux-buffer
In addition to simply calling miptree_create() the higher level
call intel_miptree_create() also considers if the buffer should
be associated with an auxiliary buffer based on the given format.
Here we are allocating an auxiliary buffer which in turn has such
format that would mislead intel_miptree_create_layout() later on
to try to associate the auxiliary buffer with an auxiliary buffer.
To prevent this the actual buffer creation logic was split out
into its own function. Lets invoke that instead.
v2 (Ben): Do not signal msaa layout with explicit argument but
using layout_flags instead.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e8b3116..e1cf15b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1541,16 +1541,16 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw,
if (brw->gen >= 8) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
}
- mt->mcs_mt = intel_miptree_create(brw,
- mt->target,
- format,
- mt->first_level,
- mt->last_level,
- mcs_width,
- mcs_height,
- mt->logical_depth0,
- 0 /* num_samples */,
- layout_flags);
+ mt->mcs_mt = miptree_create(brw,
+ mt->target,
+ format,
+ mt->first_level,
+ mt->last_level,
+ mcs_width,
+ mcs_height,
+ mt->logical_depth0,
+ 0 /* num_samples */,
+ layout_flags);
return mt->mcs_mt;
}
--
2.5.0
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[Mesa-dev] [v2 06/19] i965: Allow fast clear to be used with lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 93f1a85..09ffbb9 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -228,7 +228,8 @@ get_fast_clear_rect(struct brw_context *brw, struct
gl_framebuffer *fb,
unsigned int x_align, y_align;
unsigned int x_scaledown, y_scaledown;
- if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE) {
+ if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
+ intel_miptree_is_lossless_compressed(brw, irb->mt)) {
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p327):
*
--
2.5.0
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[Mesa-dev] [v2 17/19] i965/gen9: Setup MCS for compressed texture surfaces
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index e1a37d8..d1c9b5a 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -250,11 +250,12 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
pitch = mt->pitch;
}
- /* The MCS is not uploaded for single-sampled surfaces because the color
-* buffer should always have been resolved before it is used as a texture
-* so there is no need for it.
+ /* Prior to Gen9 MCS is not uploaded for single-sampled surfaces because
+* the color buffer should always have been resolved before it is used as
+* a texture so there is no need for it. On Gen9 it will be uploaded when
+* the surface is losslessly compressed (CCS_E).
*/
- if (mt->num_samples <= 1) {
+ if (mt->num_samples <= 1 && aux_mode != GEN9_SURFACE_AUX_MODE_CCS_E) {
aux_mt = NULL;
aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
}
--
2.5.0
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[Mesa-dev] [v2 13/19] i965: Set buffer cleared after actually clearing it
Subsequent patch will modify the surface state to set state to unresolved whenever the surface is used as render target. Color resolve itself will use the same surface setup path and marking the buffer as cleared after the draw call ensures that the state correct after the resolve Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index e92ae6c..6af6985 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c @@ -878,11 +878,12 @@ brw_meta_resolve_color(struct brw_context *brw, else set_fast_clear_op(brw, GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE); - mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; get_resolve_rect(brw, mt, &rect); brw_draw_rectlist(brw, &rect, 1); + mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; + set_fast_clear_op(brw, 0); use_rectlist(brw, false); -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [v2 01/19] i965: Isolate aligned dimensions for stencil only
This makes the logic a little more explicit and helps to keep
subsequent patches easier to read.
Suggested-by: Ben Widawsky
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 108dd87..97dd3d9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -624,7 +624,6 @@ intel_miptree_create(struct brw_context *brw,
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
mesa_format etc_format = MESA_FORMAT_NONE;
- GLuint total_width, total_height;
uint32_t alloc_flags = 0;
format = intel_lower_compressed_format(brw, format);
@@ -645,15 +644,6 @@ intel_miptree_create(struct brw_context *brw,
return NULL;
}
- total_width = mt->total_width;
- total_height = mt->total_height;
-
- if (format == MESA_FORMAT_S_UINT8) {
- /* Align to size of W tile, 64x64. */
- total_width = ALIGN(total_width, 64);
- total_height = ALIGN(total_height, 64);
- }
-
bool y_or_x = false;
if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) {
@@ -675,10 +665,19 @@ intel_miptree_create(struct brw_context *brw,
mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree",
size, alignment);
} else {
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
-total_width, total_height, mt->cpp,
-&mt->tiling, &pitch,
-alloc_flags);
+ if (format == MESA_FORMAT_S_UINT8) {
+ /* Align to size of W tile, 64x64. */
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ ALIGN(mt->total_width, 64),
+ ALIGN(mt->total_height, 64),
+ mt->cpp, &mt->tiling, &pitch,
+ alloc_flags);
+ } else {
+ mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->total_width, mt->total_height,
+ mt->cpp, &mt->tiling, &pitch,
+ alloc_flags);
+ }
}
mt->pitch = pitch;
@@ -694,7 +693,7 @@ intel_miptree_create(struct brw_context *brw,
mt->tiling = I915_TILING_X;
drm_intel_bo_unreference(mt->bo);
mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
- total_width, total_height, mt->cpp,
+ mt->total_width, mt->total_height, mt->cpp,
&mt->tiling, &pitch, alloc_flags);
mt->pitch = pitch;
}
--
2.5.0
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[Mesa-dev] [v2 09/19] i965: Resolve color buffer also in lossless compression case
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 31de1ff..8cdbfb4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2048,8 +2048,10 @@ intel_miptree_resolve_color(struct brw_context *brw,
case INTEL_FAST_CLEAR_STATE_UNRESOLVED:
case INTEL_FAST_CLEAR_STATE_CLEAR:
/* Fast color clear resolves only make sense for non-MSAA buffers. */
- if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE)
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
+ intel_miptree_is_lossless_compressed(brw, mt)) {
brw_meta_resolve_color(brw, mt);
+ }
break;
}
}
--
2.5.0
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[Mesa-dev] [v2 11/19] i965: Add a flag telling color resolve pass to ignore CCS_E
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.c | 12 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 +
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index a5f7a2e..b61036e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -208,7 +208,11 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
if (!tex_obj || !tex_obj->mt)
continue;
intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
- intel_miptree_resolve_color(brw, tex_obj->mt, 0);
+ /* Sampling engine understands lossless compression and resolving
+ * those surfaces should be skipped for performance reasons.
+ */
+ intel_miptree_resolve_color(brw, tex_obj->mt,
+ INTEL_MIPTREE_IGNORE_CCS_E);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
}
@@ -223,6 +227,12 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
tex_obj = intel_texture_object(u->TexObj);
if (tex_obj && tex_obj->mt) {
+ /* Access to images is implemented using indirect messages
+* against data port. Normal render target write understands
+* lossless compression but unfortunately the typed/untyped
+* read/write interface doesn't. Therefore the compressed
+* surfaces need to be resolved prior to accessing them.
+*/
intel_miptree_resolve_color(brw, tex_obj->mt, 0);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index dd1d8be..6c6fbef 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2041,7 +2041,13 @@ intel_miptree_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int flags)
{
- (void)flags;
+ /* From gen9 onwards there is new compression scheme for single sampled
+* surfaces called "lossless compressed". These don't need to be always
+* resolved.
+*/
+ if ((flags & INTEL_MIPTREE_IGNORE_CCS_E) &&
+ intel_miptree_is_lossless_compressed(brw, mt))
+ return;
switch (mt->fast_clear_state) {
case INTEL_FAST_CLEAR_STATE_NO_MCS:
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 155e507..a21f33f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -888,6 +888,15 @@ intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt)
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
}
+/**
+ * Flag values telling color resolve pass which special types of buffers
+ * can be ignored.
+ *
+ * INTEL_MIPTREE_IGNORE_CCS_E: Lossless compressed (single-sample
+ * compression scheme since gen9)
+ */
+#define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
+
void
intel_miptree_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
--
2.5.0
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[Mesa-dev] [v2 07/19] i965: Add resolve option for lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index fc8e157..b1fa559 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2727,6 +2727,7 @@ enum brw_wm_barycentric_interp_mode {
# define GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE (1 << 8)
# define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7)
# define GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE (1 << 6)
+# define GEN9_PS_RENDER_TARGET_RESOLVE_FULL (3 << 6)
# define HSW_PS_UAV_ACCESS_ENABLE (1 << 5)
# define GEN7_PS_POSOFFSET_NONE(0 << 3)
# define GEN7_PS_POSOFFSET_CENTROID(2 << 3)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 09ffbb9..e92ae6c 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -873,7 +873,10 @@ brw_meta_resolve_color(struct brw_context *brw,
* bits to let us select the type of resolve. For fast clear resolves, it
* turns out we can use the same value as pre-SKL though.
*/
- set_fast_clear_op(brw, GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE);
+ if (intel_miptree_is_lossless_compressed(brw, mt))
+ set_fast_clear_op(brw, GEN9_PS_RENDER_TARGET_RESOLVE_FULL);
+ else
+ set_fast_clear_op(brw, GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE);
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
get_resolve_rect(brw, mt, &rect);
--
2.5.0
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[Mesa-dev] [v2 04/19] i965: Stop considering if msrt aux buffers need aux buffer
Auxiliary buffers are always created with sample number of zero which effectively prevents intel_miptree_create_layout() from trying to associate auxiliary buffers with auxiliary buffers. Now that there is more direct path available lets start using it instead and stop even checking for such (im)possibility. v2 (Ben): Do not signal msaa layout with explicit argument but using layout_flags instead. Signed-off-by: Topi Pohjolainen Reviewed-by: Ben Widawsky --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index e1cf15b..5f739d9 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1468,16 +1468,16 @@ intel_miptree_alloc_mcs(struct brw_context *brw, */ const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y; - mt->mcs_mt = intel_miptree_create(brw, - mt->target, - format, - mt->first_level, - mt->last_level, - mt->logical_width0, - mt->logical_height0, - mt->logical_depth0, - 0 /* num_samples */, - mcs_flags); + mt->mcs_mt = miptree_create(brw, + mt->target, + format, + mt->first_level, + mt->last_level, + mt->logical_width0, + mt->logical_height0, + mt->logical_depth0, + 0 /* num_samples */, + mcs_flags); /* From the Ivy Bridge PRM, Vol 2 Part 1 p326: * -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [v2 14/19] i965/gen9: Prepare surface state setup for lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples instead of introducing explicit type for lossless compression (intel_miptree_is_lossless_compressed()). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/gen8_surface_state.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index b1fa559..f903335 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -656,6 +656,7 @@ #define GEN8_SURFACE_AUX_MODE_MCS 1 #define GEN8_SURFACE_AUX_MODE_APPEND2 #define GEN8_SURFACE_AUX_MODE_HIZ 3 +#define GEN9_SURFACE_AUX_MODE_CCS_E 5 /* Surface state DW7 */ #define GEN9_SURFACE_RT_COMPRESSION_SHIFT 30 diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 0a52815..e1a37d8 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -216,6 +216,9 @@ gen8_get_aux_mode(const struct brw_context *brw, if (brw->gen >= 9 || mt->num_samples == 1) assert(mt->halign == 16); + if (intel_miptree_is_lossless_compressed(brw, mt)) + return GEN9_SURFACE_AUX_MODE_CCS_E; + return GEN8_SURFACE_AUX_MODE_MCS; } @@ -484,6 +487,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, struct intel_mipmap_tree *aux_mt = mt->mcs_mt; const uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type); + if (aux_mode == GEN9_SURFACE_AUX_MODE_CCS_E) + mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED; + uint32_t *surf = allocate_surface_state(brw, &offset, surf_index); surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) | -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [v2 12/19] i965: Add a few assertions on lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples instead of introducing explicit type for lossless compression (intel_miptree_is_lossless_compressed()). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 5 + src/mesa/drivers/dri/i965/brw_context.c | 4 2 files changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index e8c5e95..05fff91 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -70,7 +70,12 @@ brw_blorp_blit_miptrees(struct brw_context *brw, * the destination buffer because we use the standard render path to render * to destination color buffers, and the standard render path is * fast-color-aware. +* Lossless compression is only introduced for gen9 onwards whereas +* blorp is not supported even for gen8. Therefore it should be impossible +* to end up here with single sampled compressed surfaces. */ + assert(!intel_miptree_is_lossless_compressed(brw, src_mt)); + assert(!intel_miptree_is_lossless_compressed(brw, dst_mt)); intel_miptree_resolve_color(brw, src_mt, 0); intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer); intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index b61036e..60acbba 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -262,6 +262,10 @@ intel_update_state(struct gl_context * ctx, GLuint new_state) _mesa_get_srgb_format_linear(mt->format) == mt->format) continue; + /* Lossless compression is not supported for SRGB formats, it + * should be impossible to get here with such surfaces. + */ + assert(!intel_miptree_is_lossless_compressed(brw, mt)); intel_miptree_resolve_color(brw, mt, 0); brw_render_cache_set_check_flush(brw, mt->bo); } -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
