Re: [Mesa-dev] [PATCH] radv: add fast color clear for b10g11r11

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Feb 15, 2017, at 03:28, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This is used in DOOM, so provide the fast clear path for it.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_formats.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/src/amd/vulkan/radv_formats.c
> b/src/amd/vulkan/radv_formats.c
> index 1188ee5..7902535 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -30,6 +30,7 @@
>  
>  #include "util/u_half.h"
>  #include "util/format_srgb.h"
> +#include "util/format_r11g11b10f.h"
>  
>  uint32_t radv_translate_buffer_dataformat(const struct
>  vk_format_description *desc,
> int first_non_void)
> @@ -954,6 +955,10 @@ bool radv_format_pack_clear_color(VkFormat format,
>   clear_vals[1] = 0;
>   clear_vals[0] = fui(value->float32[0]);
>   break;
> +   case VK_FORMAT_B10G11R11_UFLOAT_PACK32:
> +   clear_vals[0] = float3_to_r11g11b10f(value->float32);
> +   clear_vals[1] = 0;
> +   break;
>   default:
>   fprintf(stderr, "failed to fast clear %d\n", format);
>   return false;
> -- 
> 2.7.4
> 
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Re: [Mesa-dev] [PATCH 5/5] i965/fs: Remove hand-coded 64-bit packing optimizations

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 11:29 PM, Jason Ekstrand 
wrote:

> The optimization in unpack_64 is clearly subsumed with the opt_algebraic
> optimizations in the previous commit.  The pack optimization may not be
> quite handled by opt_algebraic but opt_algebraic should get the really
> bad cases.  Also, it's been broken since it was merged and we've never
> noticed so it must not be doing anything.
>

Ok, that's not quite fair.  It has been broken since it was merged but the
breakage is pretty hard to hit since it requires a NIR register.  However,
this doesn't really cause any regressions either since, prior to patch 1/5,
it was basically never getting triggered.

I did look at some of the shaders mentioned in the bug as being the reason
for this optimization and none of them were hurt by removing it (even after
it was fixed).  I think back-end copy-prop may have just gotten good enough
to make it not needed.


> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 50
> 
>  1 file changed, 50 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 91c14eb..9647300 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -1213,61 +1213,11 @@ fs_visitor::nir_emit_alu(const fs_builder ,
> nir_alu_instr *instr)
>break;
>
> case nir_op_pack_64_2x32_split:
> -  /* Optimize the common case where we are re-packing a double with
> -   * the result of a previous double unpack. In this case we can take
> the
> -   * 32-bit value to use in the re-pack from the original double and
> bypass
> -   * the unpack operation.
> -   */
> -  for (int i = 0; i < 2; i++) {
> - if (!instr->src[i].src.is_ssa)
> -continue;
> -
> - const nir_instr *parent_instr = instr->src[i].src.ssa->parent_
> instr;
> - if (parent_instr->type == nir_instr_type_alu)
> -continue;
> -
> - const nir_alu_instr *alu_parent = nir_instr_as_alu(parent_instr)
> ;
> - if (alu_parent->op == nir_op_unpack_64_2x32_split_x ||
> - alu_parent->op == nir_op_unpack_64_2x32_split_y)
> -continue;
> -
> - if (!alu_parent->src[0].src.is_ssa)
> -continue;
> -
> - op[i] = get_nir_src(alu_parent->src[0].src);
> - op[i] = offset(retype(op[i], BRW_REGISTER_TYPE_DF), bld,
> -alu_parent->src[0].swizzle[channel]);
> - if (alu_parent->op == nir_op_unpack_64_2x32_split_y)
> -op[i] = subscript(op[i], BRW_REGISTER_TYPE_UD, 1);
> - else
> -op[i] = subscript(op[i], BRW_REGISTER_TYPE_UD, 0);
> -  }
>bld.emit(FS_OPCODE_PACK, result, op[0], op[1]);
>break;
>
> case nir_op_unpack_64_2x32_split_x:
> case nir_op_unpack_64_2x32_split_y: {
> -  /* Optimize the common case where we are unpacking from a double we
> have
> -   * previously packed. In this case we can just bypass the pack
> operation
> -   * and source directly from its arguments.
> -   */
> -  unsigned index = (instr->op == nir_op_unpack_64_2x32_split_x) ? 0 :
> 1;
> -  if (instr->src[0].src.is_ssa) {
> - nir_instr *parent_instr = instr->src[0].src.ssa->parent_instr;
> - if (parent_instr->type == nir_instr_type_alu) {
> -nir_alu_instr *alu_parent = nir_instr_as_alu(parent_instr);
> -if (alu_parent->op == nir_op_pack_64_2x32_split &&
> -alu_parent->src[index].src.is_ssa) {
> -   op[0] = retype(get_nir_src(alu_parent->src[index].src),
> -  BRW_REGISTER_TYPE_UD);
> -   op[0] =
> -  offset(op[0], bld, alu_parent->src[index].
> swizzle[channel]);
> -   bld.MOV(result, op[0]);
> -   break;
> -}
> - }
> -  }
> -
>if (instr->op == nir_op_unpack_64_2x32_split_x)
>   bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 0));
>else
> --
> 2.5.0.400.gff86faf
>
>
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[Mesa-dev] [PATCH 3/5] nir: Rename lower_double_pack to lower_64bit_pack

[Jason Ekstrand]

There's nothing "double" about it other than, perhaps, the fact that it
packs two 32-bit values.
---
 src/compiler/Makefile.sources   | 2 +-
 src/compiler/nir/nir.h  | 2 +-
 .../nir/{nir_lower_double_packing.c => nir_lower_64bit_packing.c}   | 6 +++---
 src/mesa/drivers/dri/i965/brw_nir.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)
 rename src/compiler/nir/{nir_lower_double_packing.c => 
nir_lower_64bit_packing.c} (95%)

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index a8bb4d3..136947b 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -201,6 +201,7 @@ NIR_FILES = \
nir/nir_liveness.c \
nir/nir_loop_analyze.c \
nir/nir_loop_analyze.h \
+   nir/nir_lower_64bit_packing.c \
nir/nir_lower_alu_to_scalar.c \
nir/nir_lower_atomics.c \
nir/nir_lower_bitmap.c \
@@ -209,7 +210,6 @@ NIR_FILES = \
nir/nir_lower_clip_cull_distance_arrays.c \
nir/nir_lower_constant_initializers.c \
nir/nir_lower_double_ops.c \
-   nir/nir_lower_double_packing.c \
nir/nir_lower_drawpixels.c \
nir/nir_lower_global_vars_to_local.c \
nir/nir_lower_gs_intrinsics.c \
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 8bbc41d..9bf2d18 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2543,7 +2543,7 @@ typedef enum {
 } nir_lower_doubles_options;
 
 void nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options options);
-void nir_lower_double_pack(nir_shader *shader);
+void nir_lower_64bit_pack(nir_shader *shader);
 
 bool nir_normalize_cubemap_coords(nir_shader *shader);
 
diff --git a/src/compiler/nir/nir_lower_double_packing.c 
b/src/compiler/nir/nir_lower_64bit_packing.c
similarity index 95%
rename from src/compiler/nir/nir_lower_double_packing.c
rename to src/compiler/nir/nir_lower_64bit_packing.c
index 61c4ea6..0c94864 100644
--- a/src/compiler/nir/nir_lower_double_packing.c
+++ b/src/compiler/nir/nir_lower_64bit_packing.c
@@ -49,7 +49,7 @@ lower_unpack_64(nir_builder *b, nir_ssa_def *src)
 }
 
 static void
-lower_double_pack_impl(nir_function_impl *impl)
+lower_64bit_pack_impl(nir_function_impl *impl)
 {
nir_builder b;
nir_builder_init(, impl);
@@ -88,11 +88,11 @@ lower_double_pack_impl(nir_function_impl *impl)
 }
 
 void
-nir_lower_double_pack(nir_shader *shader)
+nir_lower_64bit_pack(nir_shader *shader)
 {
nir_foreach_function(function, shader) {
   if (function->impl)
- lower_double_pack_impl(function->impl);
+ lower_64bit_pack_impl(function->impl);
}
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 0a8d3a8..7470349 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -511,7 +511,7 @@ nir_optimize(nir_shader *nir, const struct brw_compiler 
*compiler,
nir_lower_dfract |
nir_lower_dround_even |
nir_lower_dmod);
-  OPT_V(nir_lower_double_pack);
+  OPT_V(nir_lower_64bit_pack);
} while (progress);
 
return nir;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/5] nir: Combine the int and double [un]pack opcodes

[Jason Ekstrand]

NIR is a typeless IR and the two opcodes, when considered bitwise, do
exactly the same thing.  There's no reason to have two versions.
---
 src/compiler/glsl/glsl_to_nir.cpp   | 10 ++-
 src/compiler/nir/nir_lower_alu_to_scalar.c  |  3 +-
 src/compiler/nir/nir_lower_double_ops.c | 22 +++---
 src/compiler/nir/nir_lower_double_packing.c | 46 -
 src/compiler/nir/nir_opcodes.py | 21 -
 src/compiler/nir/nir_opt_algebraic.py   |  2 +-
 src/compiler/spirv/vtn_glsl450.c|  4 +--
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp| 31 ++-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp  |  8 ++---
 9 files changed, 48 insertions(+), 99 deletions(-)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 96d8164..00f20da 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -1581,18 +1581,14 @@ nir_visitor::visit(ir_expression *ir)
   result = nir_unpack_half_2x16(, srcs[0]);
   break;
case ir_unop_pack_double_2x32:
-  result = nir_pack_double_2x32(, srcs[0]);
-  break;
-   case ir_unop_unpack_double_2x32:
-  result = nir_unpack_double_2x32(, srcs[0]);
-  break;
case ir_unop_pack_int_2x32:
case ir_unop_pack_uint_2x32:
-  result = nir_pack_int_2x32(, srcs[0]);
+  result = nir_pack_64_2x32(, srcs[0]);
   break;
+   case ir_unop_unpack_double_2x32:
case ir_unop_unpack_int_2x32:
case ir_unop_unpack_uint_2x32:
-  result = nir_unpack_int_2x32(, srcs[0]);
+  result = nir_unpack_64_2x32(, srcs[0]);
   break;
case ir_unop_bitfield_reverse:
   result = nir_bitfield_reverse(, srcs[0]);
diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c 
b/src/compiler/nir/nir_lower_alu_to_scalar.c
index 8a967c5..080d980 100644
--- a/src/compiler/nir/nir_lower_alu_to_scalar.c
+++ b/src/compiler/nir/nir_lower_alu_to_scalar.c
@@ -188,8 +188,7 @@ lower_alu_instr_scalar(nir_alu_instr *instr, nir_builder *b)
   return true;
}
 
-   case nir_op_unpack_double_2x32:
-   case nir_op_unpack_int_2x32:
+   case nir_op_unpack_64_2x32:
   return false;
 
   LOWER_REDUCTION(nir_op_fdot, nir_op_fmul, nir_op_fadd);
diff --git a/src/compiler/nir/nir_lower_double_ops.c 
b/src/compiler/nir/nir_lower_double_ops.c
index fdd0f44..ad96313 100644
--- a/src/compiler/nir/nir_lower_double_ops.c
+++ b/src/compiler/nir/nir_lower_double_ops.c
@@ -41,22 +41,22 @@ static nir_ssa_def *
 set_exponent(nir_builder *b, nir_ssa_def *src, nir_ssa_def *exp)
 {
/* Split into bits 0-31 and 32-63 */
-   nir_ssa_def *lo = nir_unpack_double_2x32_split_x(b, src);
-   nir_ssa_def *hi = nir_unpack_double_2x32_split_y(b, src);
+   nir_ssa_def *lo = nir_unpack_64_2x32_split_x(b, src);
+   nir_ssa_def *hi = nir_unpack_64_2x32_split_y(b, src);
 
/* The exponent is bits 52-62, or 20-30 of the high word, so set the 
exponent
 * to 1023
 */
nir_ssa_def *new_hi = nir_bfi(b, nir_imm_int(b, 0x7ff0), exp, hi);
/* recombine */
-   return nir_pack_double_2x32_split(b, lo, new_hi);
+   return nir_pack_64_2x32_split(b, lo, new_hi);
 }
 
 static nir_ssa_def *
 get_exponent(nir_builder *b, nir_ssa_def *src)
 {
/* get bits 32-63 */
-   nir_ssa_def *hi = nir_unpack_double_2x32_split_y(b, src);
+   nir_ssa_def *hi = nir_unpack_64_2x32_split_y(b, src);
 
/* extract bits 20-30 of the high word */
return nir_ubitfield_extract(b, hi, nir_imm_int(b, 20), nir_imm_int(b, 11));
@@ -67,7 +67,7 @@ get_exponent(nir_builder *b, nir_ssa_def *src)
 static nir_ssa_def *
 get_signed_inf(nir_builder *b, nir_ssa_def *zero)
 {
-   nir_ssa_def *zero_hi = nir_unpack_double_2x32_split_y(b, zero);
+   nir_ssa_def *zero_hi = nir_unpack_64_2x32_split_y(b, zero);
 
/* The bit pattern for infinity is 0x7ff0, where the sign bit
 * is the highest bit. Only the sign bit can be non-zero in the passed in
@@ -76,7 +76,7 @@ get_signed_inf(nir_builder *b, nir_ssa_def *zero)
 * bits and then pack it together with zero low 32 bits.
 */
nir_ssa_def *inf_hi = nir_ior(b, nir_imm_int(b, 0x7ff0), zero_hi);
-   return nir_pack_double_2x32_split(b, nir_imm_int(b, 0), inf_hi);
+   return nir_pack_64_2x32_split(b, nir_imm_int(b, 0), inf_hi);
 }
 
 /*
@@ -337,8 +337,8 @@ lower_trunc(nir_builder *b, nir_ssa_def *src)
  nir_imm_int(b, ~0),
  nir_isub(b, frac_bits, nir_imm_int(b, 32;
 
-   nir_ssa_def *src_lo = nir_unpack_double_2x32_split_x(b, src);
-   nir_ssa_def *src_hi = nir_unpack_double_2x32_split_y(b, src);
+   nir_ssa_def *src_lo = nir_unpack_64_2x32_split_x(b, src);
+   nir_ssa_def *src_hi = nir_unpack_64_2x32_split_y(b, src);
 
return
   nir_bcsel(b,
@@ -346,9 +346,9 @@ lower_trunc(nir_builder *b, nir_ssa_def *src)
 nir_imm_double(b, 0.0),
 nir_bcsel(b, nir_ige(b, unbiased_exp, nir_imm_int(b, 53)),
   

[Mesa-dev] [PATCH 1/5] i965/fs: Fix the inline nir_op_pack_double optimization

[Jason Ekstrand]

We can only do the optimization if the source *is* SSA.

Cc: "13.0 17.0" 
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 991c20f..94f2751 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1219,7 +1219,7 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
* the unpack operation.
*/
   for (int i = 0; i < 2; i++) {
- if (instr->src[i].src.is_ssa)
+ if (!instr->src[i].src.is_ssa)
 continue;
 
  const nir_instr *parent_instr = instr->src[i].src.ssa->parent_instr;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 5/5] i965/fs: Remove hand-coded 64-bit packing optimizations

[Jason Ekstrand]

The optimization in unpack_64 is clearly subsumed with the opt_algebraic
optimizations in the previous commit.  The pack optimization may not be
quite handled by opt_algebraic but opt_algebraic should get the really
bad cases.  Also, it's been broken since it was merged and we've never
noticed so it must not be doing anything.
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 50 
 1 file changed, 50 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 91c14eb..9647300 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1213,61 +1213,11 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   break;
 
case nir_op_pack_64_2x32_split:
-  /* Optimize the common case where we are re-packing a double with
-   * the result of a previous double unpack. In this case we can take the
-   * 32-bit value to use in the re-pack from the original double and bypass
-   * the unpack operation.
-   */
-  for (int i = 0; i < 2; i++) {
- if (!instr->src[i].src.is_ssa)
-continue;
-
- const nir_instr *parent_instr = instr->src[i].src.ssa->parent_instr;
- if (parent_instr->type == nir_instr_type_alu)
-continue;
-
- const nir_alu_instr *alu_parent = nir_instr_as_alu(parent_instr);
- if (alu_parent->op == nir_op_unpack_64_2x32_split_x ||
- alu_parent->op == nir_op_unpack_64_2x32_split_y)
-continue;
-
- if (!alu_parent->src[0].src.is_ssa)
-continue;
-
- op[i] = get_nir_src(alu_parent->src[0].src);
- op[i] = offset(retype(op[i], BRW_REGISTER_TYPE_DF), bld,
-alu_parent->src[0].swizzle[channel]);
- if (alu_parent->op == nir_op_unpack_64_2x32_split_y)
-op[i] = subscript(op[i], BRW_REGISTER_TYPE_UD, 1);
- else
-op[i] = subscript(op[i], BRW_REGISTER_TYPE_UD, 0);
-  }
   bld.emit(FS_OPCODE_PACK, result, op[0], op[1]);
   break;
 
case nir_op_unpack_64_2x32_split_x:
case nir_op_unpack_64_2x32_split_y: {
-  /* Optimize the common case where we are unpacking from a double we have
-   * previously packed. In this case we can just bypass the pack operation
-   * and source directly from its arguments.
-   */
-  unsigned index = (instr->op == nir_op_unpack_64_2x32_split_x) ? 0 : 1;
-  if (instr->src[0].src.is_ssa) {
- nir_instr *parent_instr = instr->src[0].src.ssa->parent_instr;
- if (parent_instr->type == nir_instr_type_alu) {
-nir_alu_instr *alu_parent = nir_instr_as_alu(parent_instr);
-if (alu_parent->op == nir_op_pack_64_2x32_split &&
-alu_parent->src[index].src.is_ssa) {
-   op[0] = retype(get_nir_src(alu_parent->src[index].src),
-  BRW_REGISTER_TYPE_UD);
-   op[0] =
-  offset(op[0], bld, alu_parent->src[index].swizzle[channel]);
-   bld.MOV(result, op[0]);
-   break;
-}
- }
-  }
-
   if (instr->op == nir_op_unpack_64_2x32_split_x)
  bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 0));
   else
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 4/5] nir/algebraic: Optimize 64bit pack/unpack

[Jason Ekstrand]

This reduces the instruction count in some fp64 and int64 piglit tests
---
 src/compiler/nir/nir_opt_algebraic.py | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 8a6dd07..d3eaa1f 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -306,6 +306,12 @@ optimizations = [
(('fabs', ('b2f', a)), ('b2f', a)),
(('iabs', ('b2i', a)), ('b2i', a)),
 
+   # Packing and then unpacking does nothing
+   (('unpack_64_2x32_split_x', ('pack_64_2x32_split', a, b)), a),
+   (('unpack_64_2x32_split_y', ('pack_64_2x32_split', a, b)), b),
+   (('pack_64_2x32_split', ('unpack_64_2x32_split_x', a),
+   ('unpack_64_2x32_split_y', a)), a),
+
# Byte extraction
(('ushr', a, 24), ('extract_u8', a, 3), '!options->lower_extract_byte'),
(('iand', 0xff, ('ushr', a, 16)), ('extract_u8', a, 2), 
'!options->lower_extract_byte'),
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 1/2] util: Add helpers for iterating over Vulkan extension structs

[Iago Toral]

Both patches are:

Reviewed-by: Iago Toral Quiroga 

On Tue, 2017-02-14 at 16:03 -0800, Jason Ekstrand wrote:
> ---
>  src/util/Makefile.sources |  3 ++-
>  src/util/vk_util.h| 43
> +++
>  2 files changed, 45 insertions(+), 1 deletion(-)
>  create mode 100644 src/util/vk_util.h
> 
> diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
> index a68a5fe..eec0311 100644
> --- a/src/util/Makefile.sources
> +++ b/src/util/Makefile.sources
> @@ -44,7 +44,8 @@ MESA_UTIL_FILES :=  \
>   u_endian.h \
>   u_vector.c \
>   u_vector.h \
> - vk_alloc.h
> + vk_alloc.h \
> + vk_utils.h
>  
>  MESA_UTIL_GENERATED_FILES = \
>   format_srgb.c
> diff --git a/src/util/vk_util.h b/src/util/vk_util.h
> new file mode 100644
> index 000..e0b5d0b
> --- /dev/null
> +++ b/src/util/vk_util.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice (including
> the next
> + * paragraph) shall be included in all copies or substantial
> portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#ifndef VK_UTIL_H
> +#define VK_UTIL_H
> +
> +/* common inlines and macros for vulkan drivers */
> +
> +#include 
> +
> +struct vk_struct_common {
> +VkStructureType sType;
> +struct vk_struct_common *pNext;
> +};
> +
> +#define vk_foreach_struct(__iter, __start) \
> +   for (struct vk_struct_common *__iter = (struct vk_struct_common
> *)(__start); \
> +__iter; __iter = __iter->pNext)
> +
> +#define vk_foreach_struct_const(__iter, __start) \
> +   for (const struct vk_struct_common *__iter = (const struct
> vk_struct_common *)(__start); \
> +__iter; __iter = __iter->pNext)
> +
> +#endif /* VK_UTIL_H */
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Re: [Mesa-dev] Query with respect to support of x32

[Haridasan, Sujith]

Hi Emil,

I tried with 13.0.4 version. The mesa demos are working fine with that version. 
Qt 5.6 has no luck. I am getting the bus error.
I will try with 17.0.x version and will update here. Now I am happy that mesa 
demos are working with version 13.

Thanks,
Sujith H



-Original Message-
From: Emil Velikov [mailto:emil.l.veli...@gmail.com] 
Sent: 14 February 2017 19:46
To: Haridasan, Sujith 
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] Query with respect to support of x32

Hi Sujith,

On 14 February 2017 at 13:12, Haridasan, Sujith  
wrote:
> Hi,
>
>
>
> I am using mesa 12.0.1 from yocto project 
> (http://git.yoctoproject.org/cgit/cgit.cgi/poky/tree/meta/recipes-graphics/mesa/mesa_12.0.1.bb?h=morty).
> While building core-image-sato ( which is the graphical image ), I 
> found that Qt5 examples for opengl are failing for x32. The target 
> machine used is intel-corei7-64. This is for minnowmax board. The 
> image uses mesa and below is the console log of one of the Qt5 example ran on 
> the target:
>
Keep in mind that the Mesa 12.0.x series is EOL. I would suggest using 13.0.x 
or 17.0.x although first testing git is the better thing to do.

If things still fail, fleshing out a simple test program (ideally one that does 
not depend on QT/other frameworks) and opening a bug [1] would be appreciated.
To track if it's driver related you can set LIBGL_ALWAYS_SOFTWARE=1 prior to 
starting your app. This will use the SW rasteriser, swrast_dri.so.

Cheers,
Emil

[1] https://bugs.freedesktop.org/
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Re: [Mesa-dev] [PATCH] anv: Rework the pipeline cache UUID

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 10:13 PM, Matt Turner  wrote:

> On Tue, Feb 14, 2017 at 3:52 PM, Jason Ekstrand 
> wrote:
> > The new version does a SHA1 sum of the timestamp together with the
> > device PCI ID.  This fixes a theoretical bug where, if you moved a drive
> > between machines, you could end up trying to use a pipeline cache from
> > one platform with a different platform.  Now we'll reject any cache that
> > is targeted at different hardware.
>
> I suspect that my patches from this morning brought this to the front
> of your mind. I would really rather you just make such a suggestion to
> me as a review comment than sending a conflicting patch before I have
> time to send v2.
>

Actually, they were completely coincidental.  What brought this to mind was
some work that I'm doing on a future feature that requires a bit more
UUIDing of things.  I realized there was a conflict but I figured that
switching from mtime to build-id and factoring in PCI ID were orthogonal
things.  I knew when I sent the patch that I would have to rebase it.  I'm
sorry if it came off as passive-aggressive or something.

In case I haven't said so, your figuring out the build-id stuff is very
much appreciated!  It's way better than mtime!

--Jason
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Re: [Mesa-dev] [PATCH] anv: Rework the pipeline cache UUID

[Matt Turner]

On Tue, Feb 14, 2017 at 3:52 PM, Jason Ekstrand  wrote:
> The new version does a SHA1 sum of the timestamp together with the
> device PCI ID.  This fixes a theoretical bug where, if you moved a drive
> between machines, you could end up trying to use a pipeline cache from
> one platform with a different platform.  Now we'll reject any cache that
> is targeted at different hardware.

I suspect that my patches from this morning brought this to the front
of your mind. I would really rather you just make such a suggestion to
me as a review comment than sending a conflicting patch before I have
time to send v2.
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Re: [Mesa-dev] [PATCH 3/3] spirv: add support for Int64 capability

[Jason Ekstrand]

It's entirely possible something important is missing but I don't see
anything wrong off-hand.  All three are

Reviewed-by: Jason Ekstrand 

Are there CTS tests for this?

On Feb 14, 2017 8:55 PM, "Dave Airlie"  wrote:

> From: Dave Airlie 
>
> This just adds the support at the spirv->nir level for the Int64
> cap.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/compiler/spirv/nir_spirv.h| 1 +
>  src/compiler/spirv/spirv_to_nir.c | 4 +++-
>  2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_
> spirv.h
> index e43e9b5..34cb5a5 100644
> --- a/src/compiler/spirv/nir_spirv.h
> +++ b/src/compiler/spirv/nir_spirv.h
> @@ -50,6 +50,7 @@ struct nir_spirv_supported_extensions {
> bool tessellation;
> bool draw_parameters;
> bool image_write_without_format;
> +   bool int64;
>  };
>
>  nir_function *spirv_to_nir(const uint32_t *words, size_t word_count,
> diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> index 7bd32ab..07a33ea 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -2669,7 +2669,6 @@ vtn_handle_preamble_instruction(struct vtn_builder
> *b, SpvOp opcode,
>case SpvCapabilityVector16:
>case SpvCapabilityFloat16Buffer:
>case SpvCapabilityFloat16:
> -  case SpvCapabilityInt64:
>case SpvCapabilityInt64Atomics:
>case SpvCapabilityAtomicStorage:
>case SpvCapabilityInt16:
> @@ -2687,6 +2686,9 @@ vtn_handle_preamble_instruction(struct vtn_builder
> *b, SpvOp opcode,
>case SpvCapabilityFloat64:
>   spv_check_supported(float64, cap);
>   break;
> +  case SpvCapabilityInt64:
> + spv_check_supported(int64, cap);
> + break;
>
>case SpvCapabilityAddresses:
>case SpvCapabilityKernel:
> --
> 2.7.4
>
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[Mesa-dev] [PATCH] radv: enable Int64 capability (v2)

[Dave Airlie]

From: Dave Airlie 

I'm not 100% sure this is all wired up but it looks like it is.

v2: actually enable extension.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_device.c   | 2 +-
 src/amd/vulkan/radv_pipeline.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 1132eeb..41ea3ab 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -468,7 +468,7 @@ void radv_GetPhysicalDeviceFeatures(
.shaderClipDistance   = true,
.shaderCullDistance   = true,
.shaderFloat64= true,
-   .shaderInt64  = false,
+   .shaderInt64  = true,
.shaderInt16  = false,
.alphaToOne   = true,
.variableMultisampleRate  = false,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index cbd846a..2e72902 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -208,7 +208,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
}
const struct nir_spirv_supported_extensions supported_ext = {
.draw_parameters = true,
-   .float64 = true
+   .float64 = true,
+   .int64 = true,
};
entry_point = spirv_to_nir(spirv, module->size / 4,
   spec_entries, num_spec_entries,
-- 
2.7.4

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[Mesa-dev] [PATCH] radv: enable Int64 capability

[Dave Airlie]

From: Dave Airlie 

I'm not 100% sure this is all wired up but it looks like it is.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_pipeline.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index cbd846a..2e72902 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -208,7 +208,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
}
const struct nir_spirv_supported_extensions supported_ext = {
.draw_parameters = true,
-   .float64 = true
+   .float64 = true,
+   .int64 = true,
};
entry_point = spirv_to_nir(spirv, module->size / 4,
   spec_entries, num_spec_entries,
-- 
2.7.4

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Re: [Mesa-dev] [PATCH mesa] egl: remove duplicate 0 assignment

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 02/15/2017 12:21 AM, Eric Engestrom wrote:

From: Eric Engestrom 

The memset on the line before already takes care of this.

Signed-off-by: Eric Engestrom 
---
  src/egl/main/eglimage.c | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/src/egl/main/eglimage.c b/src/egl/main/eglimage.c
index 818b5975cd..d062cbfe01 100644
--- a/src/egl/main/eglimage.c
+++ b/src/egl/main/eglimage.c
@@ -46,9 +46,6 @@ _eglParseImageAttribList(_EGLImageAttribs *attrs, _EGLDisplay 
*dpy,
 (void) dpy;
  
 memset(attrs, 0, sizeof(*attrs));

-   attrs->ImagePreserved = EGL_FALSE;
-   attrs->GLTextureLevel = 0;
-   attrs->GLTextureZOffset = 0;
  
 if (!attrib_list)

return err;



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[Mesa-dev] [PATCH 3/3] spirv: add support for Int64 capability

[Dave Airlie]

From: Dave Airlie 

This just adds the support at the spirv->nir level for the Int64
cap.

Signed-off-by: Dave Airlie 
---
 src/compiler/spirv/nir_spirv.h| 1 +
 src/compiler/spirv/spirv_to_nir.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index e43e9b5..34cb5a5 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -50,6 +50,7 @@ struct nir_spirv_supported_extensions {
bool tessellation;
bool draw_parameters;
bool image_write_without_format;
+   bool int64;
 };
 
 nir_function *spirv_to_nir(const uint32_t *words, size_t word_count,
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 7bd32ab..07a33ea 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2669,7 +2669,6 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
   case SpvCapabilityVector16:
   case SpvCapabilityFloat16Buffer:
   case SpvCapabilityFloat16:
-  case SpvCapabilityInt64:
   case SpvCapabilityInt64Atomics:
   case SpvCapabilityAtomicStorage:
   case SpvCapabilityInt16:
@@ -2687,6 +2686,9 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
   case SpvCapabilityFloat64:
  spv_check_supported(float64, cap);
  break;
+  case SpvCapabilityInt64:
+ spv_check_supported(int64, cap);
+ break;
 
   case SpvCapabilityAddresses:
   case SpvCapabilityKernel:
-- 
2.7.4

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[Mesa-dev] [PATCH 2/3] spirv/nir: add support for int64

[Dave Airlie]

From: Dave Airlie 

This adds the spirv->nir conversion for int64 types.

Signed-off-by: Dave Airlie 
---
 src/compiler/spirv/spirv_to_nir.c  | 18 +-
 src/compiler/spirv/vtn_variables.c | 16 +++-
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 7e7874a..7bd32ab 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -104,6 +104,8 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant 
*constant,
switch (glsl_get_base_type(type)) {
case GLSL_TYPE_INT:
case GLSL_TYPE_UINT:
+   case GLSL_TYPE_INT64:
+   case GLSL_TYPE_UINT64:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_DOUBLE: {
@@ -420,6 +422,8 @@ vtn_type_copy(struct vtn_builder *b, struct vtn_type *src)
   switch (glsl_get_base_type(src->type)) {
   case GLSL_TYPE_INT:
   case GLSL_TYPE_UINT:
+  case GLSL_TYPE_INT64:
+  case GLSL_TYPE_UINT64:
   case GLSL_TYPE_BOOL:
   case GLSL_TYPE_FLOAT:
   case GLSL_TYPE_DOUBLE:
@@ -715,8 +719,12 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   val->type->type = glsl_bool_type();
   break;
case SpvOpTypeInt: {
+  int bit_size = w[2];
   const bool signedness = w[3];
-  val->type->type = (signedness ? glsl_int_type() : glsl_uint_type());
+  if (bit_size == 64)
+ val->type->type = (signedness ? glsl_int64_t_type() : 
glsl_uint64_t_type());
+  else
+ val->type->type = (signedness ? glsl_int_type() : glsl_uint_type());
   break;
}
case SpvOpTypeFloat: {
@@ -917,6 +925,8 @@ vtn_null_constant(struct vtn_builder *b, const struct 
glsl_type *type)
switch (glsl_get_base_type(type)) {
case GLSL_TYPE_INT:
case GLSL_TYPE_UINT:
+   case GLSL_TYPE_INT64:
+   case GLSL_TYPE_UINT64:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_DOUBLE:
@@ -1071,6 +1081,8 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
   switch (glsl_get_base_type(val->const_type)) {
   case GLSL_TYPE_UINT:
   case GLSL_TYPE_INT:
+  case GLSL_TYPE_UINT64:
+  case GLSL_TYPE_INT64:
   case GLSL_TYPE_FLOAT:
   case GLSL_TYPE_BOOL:
   case GLSL_TYPE_DOUBLE: {
@@ -1208,6 +1220,8 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
 switch (glsl_get_base_type(type)) {
 case GLSL_TYPE_UINT:
 case GLSL_TYPE_INT:
+case GLSL_TYPE_UINT64:
+case GLSL_TYPE_INT64:
 case GLSL_TYPE_FLOAT:
 case GLSL_TYPE_DOUBLE:
 case GLSL_TYPE_BOOL:
@@ -1377,6 +1391,8 @@ vtn_create_ssa_value(struct vtn_builder *b, const struct 
glsl_type *type)
  switch (glsl_get_base_type(type)) {
  case GLSL_TYPE_INT:
  case GLSL_TYPE_UINT:
+ case GLSL_TYPE_INT64:
+ case GLSL_TYPE_UINT64:
  case GLSL_TYPE_BOOL:
  case GLSL_TYPE_FLOAT:
  case GLSL_TYPE_DOUBLE:
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 7b2dafb..f624509 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -115,6 +115,8 @@ vtn_access_chain_to_deref(struct vtn_builder *b, struct 
vtn_access_chain *chain)
   switch (base_type) {
   case GLSL_TYPE_UINT:
   case GLSL_TYPE_INT:
+  case GLSL_TYPE_UINT64:
+  case GLSL_TYPE_INT64:
   case GLSL_TYPE_FLOAT:
   case GLSL_TYPE_DOUBLE:
   case GLSL_TYPE_BOOL:
@@ -347,6 +349,8 @@ vtn_access_chain_to_offset(struct vtn_builder *b,
   switch (base_type) {
   case GLSL_TYPE_UINT:
   case GLSL_TYPE_INT:
+  case GLSL_TYPE_UINT64:
+  case GLSL_TYPE_INT64:
   case GLSL_TYPE_FLOAT:
   case GLSL_TYPE_DOUBLE:
   case GLSL_TYPE_BOOL:
@@ -395,6 +399,8 @@ vtn_type_block_size(struct vtn_type *type)
switch (base_type) {
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
+   case GLSL_TYPE_UINT64:
+   case GLSL_TYPE_INT64:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_DOUBLE: {
@@ -403,7 +409,9 @@ vtn_type_block_size(struct vtn_type *type)
   if (cols > 1) {
  assert(type->stride > 0);
  return type->stride * cols;
-  } else if (base_type == GLSL_TYPE_DOUBLE) {
+  } else if (base_type == GLSL_TYPE_DOUBLE ||
+base_type == GLSL_TYPE_UINT64 ||
+base_type == GLSL_TYPE_INT64) {
  return glsl_get_vector_elements(type->type) * 8;
   } else {
  return glsl_get_vector_elements(type->type) * 4;
@@ -526,6 +534,8 @@ _vtn_block_load_store(struct vtn_builder *b, 
nir_intrinsic_op op, bool load,
switch (base_type) {
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
+   case GLSL_TYPE_UINT64:
+   case GLSL_TYPE_INT64:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_BOOL:
@@ -738,6 +748,8 @@ 

[Mesa-dev] [PATCH 1/3] nir/types: add C accessors for 64-bit integer types.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 src/compiler/nir_types.cpp | 12 
 src/compiler/nir_types.h   |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index cc90efd..52fd0e9 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -289,6 +289,18 @@ glsl_uint_type(void)
 }
 
 const glsl_type *
+glsl_int64_t_type(void)
+{
+   return glsl_type::int64_t_type;
+}
+
+const glsl_type *
+glsl_uint64_t_type(void)
+{
+   return glsl_type::uint64_t_type;
+}
+
+const glsl_type *
 glsl_bool_type(void)
 {
return glsl_type::bool_type;
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index cafb8c1..e99b226 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -128,6 +128,8 @@ const struct glsl_type *glsl_dvec_type(unsigned n);
 const struct glsl_type *glsl_vec4_type(void);
 const struct glsl_type *glsl_int_type(void);
 const struct glsl_type *glsl_uint_type(void);
+const struct glsl_type *glsl_int64_t_type(void);
+const struct glsl_type *glsl_uint64_t_type(void);
 const struct glsl_type *glsl_bool_type(void);
 
 const struct glsl_type *glsl_scalar_type(enum glsl_base_type base_type);
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 4/6] gallium/radeon: fix performance of buffer readbacks

[Michel Dänzer]

On 14/02/17 11:09 PM, Marek Olšák wrote:
> On Tue, Feb 14, 2017 at 3:05 PM, Emil Velikov  
> wrote:
>> On 13 February 2017 at 03:24, Michel Dänzer  wrote:
>>> On 10/02/17 08:27 PM, Marek Olšák wrote:
 On Fri, Feb 10, 2017 at 12:22 PM, Emil Velikov  
 wrote:
>  On 9 February 2017 at 11:56, Marek Olšák  wrote:
>> From: Marek Olšák 
>>
>> We want cached GTT for all non-persistent read mappings.
>> Set level = 0 on purpose.
>>
>> Use dma_copy, because resource_copy_region causes a failure in the PBO
>> read of piglit/getteximage-luminance.
>>
>> If Rocket League used the READ flag, it should get cached GTT.
>>
> Does this patch resolve/mitigate the reported performance issues with
> Rocket League ?
>
> Strictly speaking performance patches are a no-go for stable, although
> we had exceptions in the past.
> I will pick this up, but for future do provide numbers which indicate
> the severity of the issue.

 It will help only if Rocket League is fixed to use GL_MAP_READ_BIT. It
 doesn't fix the current release of Rocket League.
>>>
>>> That's incorrect, it always used GL_MAP_READ_BIT. So this fix should
>>> (and reportedly does) help with unpatched Rocket League.
>>>
>>> As can be seen from https://bugs.freedesktop.org/show_bug.cgi?id=97879
>>> (which should have been referenced by the commit log :), the problem is
>>> freezes of up to several seconds, which makes the game essentially
>>> unplayable, especially for online multiplayer.
>>>
>>> OTOH the game itself has now been fixed to no longer run into the
>>> problem, and I suspect most users will probably get the game update
>>> before any future Mesa stable release.
>>>
>> I'm concerned about the reports that although this(?) commit makes the
>> stalls shorter, it also decreases performance (do to ~80%).
>>
>> Fabio (Oibaf) is fairly responsive so getting the extra patch in his
>> PPA should be trivial. I'd imagine that others, say padoka (Paulo),
>> would also gladly assist.
> 
> The lower performance might be due to the game using GL_MAP_READ_BIT
> even when the flag isn't necessary.

Yep, from the apitrace in the bug report it looks like it sets
GL_MAP_READ_BIT for most if not all glMapBuffer calls. Seems unlikely
that it actually reads from all mappings.


Also, it sounds like even if the framerate may be lower, it's still
actually playable now, whereas it wasn't before.


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Re: [Mesa-dev] [PATCH] r300g: only allow byteswapped formats on big endian

[Alex Deucher]

On Tue, Feb 14, 2017 at 10:27 PM, Michel Dänzer  wrote:
> On 14/02/17 08:25 PM, Marek Olšák wrote:
>> I've changed my mind. The patch can be merged if nobody disagrees.
>
> It would be nice to better understand what exactly the problem is. It
> seems unlikely that it's actually an endianness specific problem in the
> driver code, more likely an endianness specific problem in state tracker
> code, or maybe a non-endianness-specific problem in the driver code
> (which may or may not be possible to hit on big endian hosts as well).
>
> In other words, I suspect this isn't a fix for the actual problem, but
> just a workaround. That said, if you guys are happy with that, I'm not
> holding it up.

I tend to agree, but OTOH, r300 is pretty old and BE systems are
pretty few and far between these days.  Neither of which are conducive
to spending much time on them.  Someone with an interest in BE systems
really needs to step up and fix up endian handling in mesa for real.

Alex
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Re: [Mesa-dev] [PATCH] r300g: only allow byteswapped formats on big endian

[Michel Dänzer]

On 14/02/17 08:25 PM, Marek Olšák wrote:
> I've changed my mind. The patch can be merged if nobody disagrees.

It would be nice to better understand what exactly the problem is. It
seems unlikely that it's actually an endianness specific problem in the
driver code, more likely an endianness specific problem in state tracker
code, or maybe a non-endianness-specific problem in the driver code
(which may or may not be possible to hit on big endian hosts as well).

In other words, I suspect this isn't a fix for the actual problem, but
just a workaround. That said, if you guys are happy with that, I'm not
holding it up.


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[Mesa-dev] [PATCH] radv: add fast color clear for b10g11r11

[Dave Airlie]

From: Dave Airlie 

This is used in DOOM, so provide the fast clear path for it.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_formats.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 1188ee5..7902535 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -30,6 +30,7 @@
 
 #include "util/u_half.h"
 #include "util/format_srgb.h"
+#include "util/format_r11g11b10f.h"
 
 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description 
*desc,
  int first_non_void)
@@ -954,6 +955,10 @@ bool radv_format_pack_clear_color(VkFormat format,
clear_vals[1] = 0;
clear_vals[0] = fui(value->float32[0]);
break;
+   case VK_FORMAT_B10G11R11_UFLOAT_PACK32:
+   clear_vals[0] = float3_to_r11g11b10f(value->float32);
+   clear_vals[1] = 0;
+   break;
default:
fprintf(stderr, "failed to fast clear %d\n", format);
return false;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/2] i965/ps: Use ForceThreadDispatchEnable instead of AccessUAV.

[Kenneth Graunke]

On Monday, February 13, 2017 6:58:39 PM PST Jason Ekstrand wrote:
> On Mon, Feb 13, 2017 at 6:35 PM, Francisco Jerez 
> wrote:
> 
> > Jason Ekstrand  writes:
> >
> > > The AccessUAV bit is not quite what we want because it's more about
> > > coherency between storage operations than it is about dispatch.  Also,
> > > the 3DSTATE_PS_EXTRA::PixelShaderHasUAV bit seems to cause hangs on
> > > Broadwell for unknown reasons so it's best to just leave it off.  The
> > > 3DSTATE_WM::ForceThreadDispatchEnable bit, on the other hand, does
> > > exactly what we want and seems to work fine.
> > > ---
> > >  src/mesa/drivers/dri/i965/brw_defines.h   |  2 ++
> > >  src/mesa/drivers/dri/i965/gen8_ps_state.c | 52
> > ++-
> > >  2 files changed, 19 insertions(+), 35 deletions(-)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> > b/src/mesa/drivers/dri/i965/brw_defines.h
> > > index 3c5c6c4..9ad36ca 100644
> > > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > > @@ -2733,6 +2733,8 @@ enum brw_barycentric_mode {
> > >  # define GEN7_WM_MSDISPMODE_PERSAMPLE(0 << 31)
> > >  # define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31)
> > >  # define HSW_WM_UAV_ONLY(1 << 30)
> > > +# define GEN8_WM_FORCE_THREAD_DISPATCH_OFF  (1 << 19)
> > > +# define GEN8_WM_FORCE_THREAD_DISPATCH_ON   (2 << 19)
> > >
> > >  #define _3DSTATE_PS  0x7820 /* GEN7+ */
> > >  /* DW1: kernel pointer */
> > > diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > > index 0346826..cca57e6 100644
> > > --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > > +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > > @@ -74,39 +74,6 @@ gen8_upload_ps_extra(struct brw_context *brw,
> > > if (brw->gen >= 9 && prog_data->pulls_bary)
> > >dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
> > >
> > > -   /* The stricter cross-primitive coherency guarantees that the
> > hardware
> > > -* gives us with the "Accesses UAV" bit set for at least one shader
> > stage
> > > -* and the "UAV coherency required" bit set on the 3DPRIMITIVE
> > command are
> > > -* redundant within the current image, atomic counter and SSBO GL
> > APIs,
> > > -* which all have very loose ordering and coherency requirements and
> > > -* generally rely on the application to insert explicit barriers
> > when a
> > > -* shader invocation is expected to see the memory writes performed
> > by the
> > > -* invocations of some previous primitive.  Regardless of the value
> > of "UAV
> > > -* coherency required", the "Accesses UAV" bits will implicitly
> > cause an in
> > > -* most cases useless DC flush when the lowermost stage with the bit
> > set
> > > -* finishes execution.
> > > -*
> > > -* It would be nice to disable it, but in some cases we can't
> > because on
> > > -* Gen8+ it also has an influence on rasterization via the PS
> > UAV-only
> > > -* signal (which could be set independently from the coherency
> > mechanism in
> > > -* the 3DSTATE_WM command on Gen7), and because in some cases it will
> > > -* determine whether the hardware skips execution of the fragment
> > shader or
> > > -* not via the ThreadDispatchEnable signal.  However if we know that
> > > -* GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
> > > -* GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make
> > any
> > > -* difference so we may just disable it here.
> > > -*
> > > -* Gen8 hardware tries to compute ThreadDispatchEnable for us but
> > doesn't
> > > -* take into account KillPixels when no depth or stencil writes are
> > enabled.
> > > -* In order for occlusion queries to work correctly with no
> > attachments, we
> > > -* need to force-enable here.
> > > -*
> > > -* BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
> > _NEW_COLOR
> > > -*/
> > > -   if ((prog_data->has_side_effects || prog_data->uses_kill) &&
> > > -   !brw_color_buffer_write_enabled(brw))
> > > -  dw1 |= GEN8_PSX_SHADER_HAS_UAV;
> > > -
> > > if (prog_data->computed_stencil) {
> > >assert(brw->gen >= 9);
> > >dw1 |= GEN9_PSX_SHADER_COMPUTES_STENCIL;
> > > @@ -127,7 +94,6 @@ upload_ps_extra(struct brw_context *brw)
> > >
> > >  const struct brw_tracked_state gen8_ps_extra = {
> > > .dirty = {
> > > -  .mesa  = _NEW_BUFFERS | _NEW_COLOR,
> > >.brw   = BRW_NEW_BLORP |
> > > BRW_NEW_CONTEXT |
> > > BRW_NEW_FRAGMENT_PROGRAM |
> > > @@ -169,6 +135,20 @@ upload_wm_state(struct brw_context *brw)
> > > else if (wm_prog_data->has_side_effects)
> > >dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
> > >
> > > +   /* In most cases, the computation 

[Mesa-dev] [Bug 99467] [radv] DOOM 2016 + wine. Green screen everywhere (but can be started)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99467

--- Comment #16 from Dave Airlie  ---
I've pushed a new radv-wip-doom-wine branch which clears VRAM on kernels 4.9
and above.

If you can test this with a kernel > 4.9 and see if the colors are still
randomly crap.

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[Mesa-dev] [PATCH] r300g: only allow byteswapped formats on big endian

[cosiekvfj]

Hi. Im the user affected by this bug. I can do more testing if needed.
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Re: [Mesa-dev] [PATCH] radv: query cmds should mark a cmd buffer as having draws.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan 

On 02/15/2017 11:00 AM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This fixes a regression with the remove non-draw cmd buffers in
> queries.
> 
> Fixes: 8b47b97215a radv: detect command buffers that do no work and drop them 
> (v2)
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_query.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
> index a29a05d..fd5d065 100644
> --- a/src/amd/vulkan/radv_query.c
> +++ b/src/amd/vulkan/radv_query.c
> @@ -211,6 +211,7 @@ void radv_CmdCopyQueryPoolResults(
>  
>   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
>   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 
> 8);
> + cmd_buffer->no_draws = false;
>  
>   for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
>   unsigned query = firstQuery + i;
> @@ -310,6 +311,7 @@ void radv_CmdBeginQuery(
>   va += pool->stride * query;
>  
>   cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
> + cmd_buffer->no_draws = false;
>  
>   switch (pool->type) {
>   case VK_QUERY_TYPE_OCCLUSION:
> @@ -343,6 +345,7 @@ void radv_CmdEndQuery(
>   va += pool->stride * query;
>  
>   cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
> + cmd_buffer->no_draws = false;
>  
>   switch (pool->type) {
>   case VK_QUERY_TYPE_OCCLUSION:
> @@ -394,6 +397,7 @@ void radv_CmdWriteTimestamp(
>   uint64_t query_va = va + pool->stride * query;
>  
>   cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5);
> + cmd_buffer->no_draws = false;
>  
>   MAYBE_UNUSED unsigned cdw_max = 
> radeon_check_space(cmd_buffer->device->ws, cs, 12);
>  
> 



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Re: [Mesa-dev] [PATCH 0/3] radv: Support image operations without format.

[Edward O'Callaghan]

This series LGTM,
Reviewed-by: Edward O'Callaghan 

On 02/15/2017 11:36 AM, Bas Nieuwenhuizen wrote:
> No regressions on CTS 1.0.2 mustpass, though I don't think there are
> tests for these extensions. I checked there were no references to the
> format in the nir->LLVM conversion though.
> 
> Bas Nieuwenhuizen (3):
>   radv: Add support for shaderStorageImageWriteWithoutFormat.
>   spirv: Add support for SpvCapabilityStorageImageReadWithoutFormat.
>   radv: Add support for shaderStorageImageReadWithoutFormat.
> 
>  src/amd/vulkan/radv_device.c  | 4 ++--
>  src/amd/vulkan/radv_pipeline.c| 4 +++-
>  src/compiler/spirv/nir_spirv.h| 1 +
>  src/compiler/spirv/spirv_to_nir.c | 5 -
>  4 files changed, 10 insertions(+), 4 deletions(-)
> 



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Re: [Mesa-dev] [PATCH 0/3] radv: Support image operations without format.

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 4:36 PM, Bas Nieuwenhuizen 
wrote:

> No regressions on CTS 1.0.2 mustpass, though I don't think there are
> tests for these extensions. I checked there were no references to the
> format in the nir->LLVM conversion though.
>

It's pretty easy to tweak the load_store CTS tests to not provide a
format.  That's what I did for testing.  It's better than nothing.


> Bas Nieuwenhuizen (3):
>   radv: Add support for shaderStorageImageWriteWithoutFormat.
>   spirv: Add support for SpvCapabilityStorageImageReadWithoutFormat.
>   radv: Add support for shaderStorageImageReadWithoutFormat.
>
>  src/amd/vulkan/radv_device.c  | 4 ++--
>  src/amd/vulkan/radv_pipeline.c| 4 +++-
>  src/compiler/spirv/nir_spirv.h| 1 +
>  src/compiler/spirv/spirv_to_nir.c | 5 -
>  4 files changed, 10 insertions(+), 4 deletions(-)
>
> --
> 2.11.1
>
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[Mesa-dev] [Bug 99817] [softpipe] piglit glsl-fs-tan-1 regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99817

Francisco Jerez  changed:

   What|Removed |Added

 CC||curroje...@riseup.net

--- Comment #2 from Francisco Jerez  ---
Created attachment 129616
  --> https://bugs.freedesktop.org/attachment.cgi?id=129616=edit
0001-st-glsl_to_tgsi-Translate-ir_unop_neg-into-MOV-with-.patch

Here's a (largely untested) potential fix.

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[Mesa-dev] [PATCH 3/3] radv: Add support for shaderStorageImageReadWithoutFormat.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c   | 2 +-
 src/amd/vulkan/radv_pipeline.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9185ef16dc0..be0d9d933fc 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -463,7 +463,7 @@ void radv_GetPhysicalDeviceFeatures(
.shaderSampledImageArrayDynamicIndexing   = true,
.shaderStorageBufferArrayDynamicIndexing  = true,
.shaderStorageImageArrayDynamicIndexing   = true,
-   .shaderStorageImageReadWithoutFormat  = false,
+   .shaderStorageImageReadWithoutFormat  = true,
.shaderStorageImageWriteWithoutFormat = true,
.shaderClipDistance   = true,
.shaderCullDistance   = true,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 060ff4f90b0..50da89acbbd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -209,6 +209,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
const struct nir_spirv_supported_extensions supported_ext = {
.draw_parameters = true,
.float64 = true,
+   .image_read_without_format = true,
.image_write_without_format = true,
};
entry_point = spirv_to_nir(spirv, module->size / 4,
-- 
2.11.1

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[Mesa-dev] [PATCH 2/3] spirv: Add support for SpvCapabilityStorageImageReadWithoutFormat.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen 
---
 src/compiler/spirv/nir_spirv.h| 1 +
 src/compiler/spirv/spirv_to_nir.c | 5 -
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index e43e9b53825..8864a8f73d7 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -49,6 +49,7 @@ struct nir_spirv_supported_extensions {
bool image_ms_array;
bool tessellation;
bool draw_parameters;
+   bool image_read_without_format;
bool image_write_without_format;
 };
 
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 7e7874a5e49..8108e1030bf 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2663,7 +2663,6 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
   case SpvCapabilitySparseResidency:
   case SpvCapabilityMinLod:
   case SpvCapabilityTransformFeedback:
-  case SpvCapabilityStorageImageReadWithoutFormat:
  vtn_warn("Unsupported SPIR-V capability: %s",
   spirv_capability_to_string(cap));
  break;
@@ -2699,6 +2698,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
  spv_check_supported(draw_parameters, cap);
  break;
 
+  case SpvCapabilityStorageImageReadWithoutFormat:
+ spv_check_supported(image_read_without_format, cap);
+ break;
+
   case SpvCapabilityStorageImageWriteWithoutFormat:
  spv_check_supported(image_write_without_format, cap);
  break;
-- 
2.11.1

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[Mesa-dev] [PATCH 0/3] radv: Support image operations without format.

[Bas Nieuwenhuizen]

No regressions on CTS 1.0.2 mustpass, though I don't think there are
tests for these extensions. I checked there were no references to the
format in the nir->LLVM conversion though.

Bas Nieuwenhuizen (3):
  radv: Add support for shaderStorageImageWriteWithoutFormat.
  spirv: Add support for SpvCapabilityStorageImageReadWithoutFormat.
  radv: Add support for shaderStorageImageReadWithoutFormat.

 src/amd/vulkan/radv_device.c  | 4 ++--
 src/amd/vulkan/radv_pipeline.c| 4 +++-
 src/compiler/spirv/nir_spirv.h| 1 +
 src/compiler/spirv/spirv_to_nir.c | 5 -
 4 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.11.1

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[Mesa-dev] [PATCH 1/3] radv: Add support for shaderStorageImageWriteWithoutFormat.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c   | 2 +-
 src/amd/vulkan/radv_pipeline.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 1132eeb52d7..9185ef16dc0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -464,7 +464,7 @@ void radv_GetPhysicalDeviceFeatures(
.shaderStorageBufferArrayDynamicIndexing  = true,
.shaderStorageImageArrayDynamicIndexing   = true,
.shaderStorageImageReadWithoutFormat  = false,
-   .shaderStorageImageWriteWithoutFormat = false,
+   .shaderStorageImageWriteWithoutFormat = true,
.shaderClipDistance   = true,
.shaderCullDistance   = true,
.shaderFloat64= true,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 53f06acc092..060ff4f90b0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -208,7 +208,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
}
const struct nir_spirv_supported_extensions supported_ext = {
.draw_parameters = true,
-   .float64 = true
+   .float64 = true,
+   .image_write_without_format = true,
};
entry_point = spirv_to_nir(spirv, module->size / 4,
   spec_entries, num_spec_entries,
-- 
2.11.1

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[Mesa-dev] [Bug 99817] [softpipe] piglit glsl-fs-tan-1 regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99817

--- Comment #1 from Francisco Jerez  ---
This seems to be caused by the atan() built-in implementation now using
ir_triop_csel instead of control flow, which is translated incorrectly by the
mesa state tracker on drivers with native integer support when one of the
arguments is floating point and has a source modifier enabled, because
glsl_to_tgsi emits an integer UCMP instruction in that case, which has
different (integer) modifier semantics.

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Re: [Mesa-dev] [PATCH] radv: also fixup event emission to not get culled.

[Bas Nieuwenhuizen]

r-b for now.

On Wed, Feb 15, 2017, at 01:16, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This is possibly a bad idea, I might have to consider a better one.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 681b5a3..4269186 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -2890,6 +2890,7 @@ static void write_event(struct radv_cmd_buffer
> *cmd_buffer,
>   uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
>  
>   cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
> +   cmd_buffer->no_draws = false;
>  
>   MAYBE_UNUSED unsigned cdw_max = 
> radeon_check_space(cmd_buffer->device->ws, cs, 12);
>  
> -- 
> 2.7.4
> 
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[Mesa-dev] [PATCH] radv: also fixup event emission to not get culled.

[Dave Airlie]

From: Dave Airlie 

This is possibly a bad idea, I might have to consider a better one.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 681b5a3..4269186 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2890,6 +2890,7 @@ static void write_event(struct radv_cmd_buffer 
*cmd_buffer,
uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
 
cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
+   cmd_buffer->no_draws = false;
 
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cs, 12);
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/2] util: Add helpers for iterating over Vulkan extension structs

[Dave Airlie]

Reviewed-by: Dave Airlie 

Thanks for making it useful for radv :-)

Dave.

On 15 February 2017 at 10:03, Jason Ekstrand  wrote:


> ---
>  src/util/Makefile.sources |  3 ++-
>  src/util/vk_util.h| 43 +++
>  2 files changed, 45 insertions(+), 1 deletion(-)
>  create mode 100644 src/util/vk_util.h
>
> diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
> index a68a5fe..eec0311 100644
> --- a/src/util/Makefile.sources
> +++ b/src/util/Makefile.sources
> @@ -44,7 +44,8 @@ MESA_UTIL_FILES :=\
> u_endian.h \
> u_vector.c \
> u_vector.h \
> -   vk_alloc.h
> +   vk_alloc.h \
> +   vk_utils.h
>
>  MESA_UTIL_GENERATED_FILES = \
> format_srgb.c
> diff --git a/src/util/vk_util.h b/src/util/vk_util.h
> new file mode 100644
> index 000..e0b5d0b
> --- /dev/null
> +++ b/src/util/vk_util.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#ifndef VK_UTIL_H
> +#define VK_UTIL_H
> +
> +/* common inlines and macros for vulkan drivers */
> +
> +#include 
> +
> +struct vk_struct_common {
> +VkStructureType sType;
> +struct vk_struct_common *pNext;
> +};
> +
> +#define vk_foreach_struct(__iter, __start) \
> +   for (struct vk_struct_common *__iter = (struct vk_struct_common 
> *)(__start); \
> +__iter; __iter = __iter->pNext)
> +
> +#define vk_foreach_struct_const(__iter, __start) \
> +   for (const struct vk_struct_common *__iter = (const struct 
> vk_struct_common *)(__start); \
> +__iter; __iter = __iter->pNext)
> +
> +#endif /* VK_UTIL_H */
> --
> 2.5.0.400.gff86faf
>
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[Mesa-dev] [PATCH 2/2] anv: Use vk_foreach_struct for handling extension structs

[Jason Ekstrand]

---
 src/intel/vulkan/anv_device.c  | 27 +--
 src/intel/vulkan/anv_formats.c | 16 
 src/intel/vulkan/anv_private.h |  5 -
 3 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 57d70b6..d1a6cc8 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -33,6 +33,7 @@
 #include "anv_private.h"
 #include "util/strtod.h"
 #include "util/debug.h"
+#include "util/vk_util.h"
 
 #include "genxml/gen7_pack.h"
 
@@ -511,10 +512,10 @@ void anv_GetPhysicalDeviceFeatures2KHR(
 {
anv_GetPhysicalDeviceFeatures(physicalDevice, >features);
 
-   for (struct anv_common *c = pFeatures->pNext; c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   vk_foreach_struct(ext, pFeatures->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -669,10 +670,10 @@ void anv_GetPhysicalDeviceProperties2KHR(
 {
anv_GetPhysicalDeviceProperties(physicalDevice, >properties);
 
-   for (struct anv_common *c = pProperties->pNext; c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   vk_foreach_struct(ext, pProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -746,11 +747,10 @@ void anv_GetPhysicalDeviceQueueFamilyProperties2KHR(
anv_get_queue_family_properties(phys_dev,
  >queueFamilyProperties);
 
-   for (struct anv_common *c = pQueueFamilyProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   vk_foreach_struct(ext, pQueueFamilyProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -815,11 +815,10 @@ void anv_GetPhysicalDeviceMemoryProperties2KHR(
anv_GetPhysicalDeviceMemoryProperties(physicalDevice,
  >memoryProperties);
 
-   for (struct anv_common *c = pMemoryProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   vk_foreach_struct(ext, pMemoryProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 0e84960..6005791 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -24,6 +24,8 @@
 #include "anv_private.h"
 #include "vk_format_info.h"
 
+#include "util/vk_util.h"
+
 /*
  * gcc-4 and earlier don't allow compound literals where a constant
  * is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
@@ -470,11 +472,10 @@ void anv_GetPhysicalDeviceFormatProperties2KHR(
anv_GetPhysicalDeviceFormatProperties(physicalDevice, format,
  >formatProperties);
 
-   for (struct anv_common *c = pFormatProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   vk_foreach_struct(ext, pFormatProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -668,11 +669,10 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2KHR(
if (result != VK_SUCCESS)
   return result;
 
-   for (struct anv_common *c = pImageFormatProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   vk_foreach_struct(ext, pImageFormatProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index ec791a4..c33318ad 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1876,11 +1876,6 @@ void anv_dump_finish(void);
 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
   struct anv_framebuffer *fb);
 
-struct anv_common {
-VkStructureType sType;
-struct anv_common *pNext;
-};
-
 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType)  \
\
static inline struct __anv_type *   \
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/2] util: Add helpers for iterating over Vulkan extension structs

[Jason Ekstrand]

---
 src/util/Makefile.sources |  3 ++-
 src/util/vk_util.h| 43 +++
 2 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 src/util/vk_util.h

diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
index a68a5fe..eec0311 100644
--- a/src/util/Makefile.sources
+++ b/src/util/Makefile.sources
@@ -44,7 +44,8 @@ MESA_UTIL_FILES :=\
u_endian.h \
u_vector.c \
u_vector.h \
-   vk_alloc.h
+   vk_alloc.h \
+   vk_utils.h
 
 MESA_UTIL_GENERATED_FILES = \
format_srgb.c
diff --git a/src/util/vk_util.h b/src/util/vk_util.h
new file mode 100644
index 000..e0b5d0b
--- /dev/null
+++ b/src/util/vk_util.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#ifndef VK_UTIL_H
+#define VK_UTIL_H
+
+/* common inlines and macros for vulkan drivers */
+
+#include 
+
+struct vk_struct_common {
+VkStructureType sType;
+struct vk_struct_common *pNext;
+};
+
+#define vk_foreach_struct(__iter, __start) \
+   for (struct vk_struct_common *__iter = (struct vk_struct_common 
*)(__start); \
+__iter; __iter = __iter->pNext)
+
+#define vk_foreach_struct_const(__iter, __start) \
+   for (const struct vk_struct_common *__iter = (const struct vk_struct_common 
*)(__start); \
+__iter; __iter = __iter->pNext)
+
+#endif /* VK_UTIL_H */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH] radv: query cmds should mark a cmd buffer as having draws.

[Dave Airlie]

From: Dave Airlie 

This fixes a regression with the remove non-draw cmd buffers in
queries.

Fixes: 8b47b97215a radv: detect command buffers that do no work and drop them 
(v2)
Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_query.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index a29a05d..fd5d065 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -211,6 +211,7 @@ void radv_CmdCopyQueryPoolResults(
 
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 
8);
+   cmd_buffer->no_draws = false;
 
for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
unsigned query = firstQuery + i;
@@ -310,6 +311,7 @@ void radv_CmdBeginQuery(
va += pool->stride * query;
 
cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
+   cmd_buffer->no_draws = false;
 
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
@@ -343,6 +345,7 @@ void radv_CmdEndQuery(
va += pool->stride * query;
 
cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
+   cmd_buffer->no_draws = false;
 
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
@@ -394,6 +397,7 @@ void radv_CmdWriteTimestamp(
uint64_t query_va = va + pool->stride * query;
 
cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5);
+   cmd_buffer->no_draws = false;
 
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cs, 12);
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/3] gallivm: Improve debug output (V2)

[Roland Scheidegger]

Am 14.02.2017 um 22:16 schrieb Ben Crocker:
> Improve debug output from gallivm_compile_module and
> lp_build_create_jit_compiler_for_module, printing the
> -mcpu and -mattr options passed to LLC.
> 
> V2: enclose MAttrs debug_printf block and llc -mcpu debug_printf
> in "if (gallivm_debug & )..."
> 
> Signed-off-by: Ben Crocker 
> Cc: 12.0 13.0 17.0 
> ---
>  src/gallium/auxiliary/gallivm/lp_bld_init.c   |  5 -
>  src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 14 ++
>  2 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c 
> b/src/gallium/auxiliary/gallivm/lp_bld_init.c
> index d1b2369..fed43e9 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
> @@ -606,7 +606,10 @@ gallivm_compile_module(struct gallivm_state *gallivm)
>util_snprintf(filename, sizeof(filename), "ir_%s.bc", 
> gallivm->module_name);
>LLVMWriteBitcodeToFile(gallivm->module, filename);
>debug_printf("%s written\n", filename);
> -  debug_printf("Invoke as \"llc -o - %s\"\n", filename);
> +  debug_printf("Invoke as \"llc %s%s -o - %s\"\n",
> +   (HAVE_LLVM >= 0x0305) ? "[-mcpu=<-mcpu option] " : "",
> +   "[-mattr=<-mattr option(s)>]",
> +   filename);
> }
>  
> if (USE_MCJIT) {
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp 
> b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> index 21d9e15..13f9a4d 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> @@ -101,6 +101,7 @@
>  #include "util/u_cpu_detect.h"
>  
>  #include "lp_bld_misc.h"
> +#include "lp_bld_debug.h"
>  
>  namespace {
>  
> @@ -627,6 +628,16 @@ 
> lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
>  
> builder.setMAttrs(MAttrs);
>  
> +   if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | 
> GALLIVM_DEBUG_DUMP_BC)) {
> +  int n = MAttrs.size();
> +  if (n > 0) {
> + debug_printf("llc -mattr option(s): ");
> + for (int i = 0; i < n; i++)
> +debug_printf("%s%s", MAttrs[i].c_str(), (i < n - 1) ? "," : "");
> + debug_printf("\n");
> +  }
> +   }
> +
>  #if HAVE_LLVM >= 0x0305
> StringRef MCPU = llvm::sys::getHostCPUName();
> /*
> @@ -642,6 +653,9 @@ 
> lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
>  * can't handle. Not entirely sure if we really need to do anything yet.
>  */
> builder.setMCPU(MCPU);
> +   if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | 
> GALLIVM_DEBUG_DUMP_BC)) {
> +  debug_printf("llc -mcpu option: %s\n", MCPU.str().c_str());
> +   }
>  #endif
>  
> ShaderMemoryManager *MM = NULL;
> 

Looks great.
Reviewed-by: Roland Scheidegger 


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[Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

Provides the ability to read the .note.gnu.build-id section of ELF
binaries, which is inserted by the --build-id=... flag to ld.
---
 configure.ac  |   2 +
 src/util/Makefile.sources |   2 +
 src/util/build_id.c   | 110 ++
 src/util/build_id.h   |  34 ++
 4 files changed, 148 insertions(+)
 create mode 100644 src/util/build_id.c
 create mode 100644 src/util/build_id.h

diff --git a/configure.ac b/configure.ac
index f001743..99c74f0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -768,6 +768,8 @@ LIBS="$LIBS $DLOPEN_LIBS"
 AC_CHECK_FUNCS([dladdr])
 LIBS="$save_LIBS"
 
+AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES -DHAVE_DL_ITERATE_PHDR"])
+
 case "$host_os" in
 darwin*)
 ;;
diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
index a68a5fe..4c12e5f 100644
--- a/src/util/Makefile.sources
+++ b/src/util/Makefile.sources
@@ -2,6 +2,8 @@ MESA_UTIL_FILES :=  \
bitscan.c \
bitscan.h \
bitset.h \
+   build_id.c \
+   build_id.h \
crc32.c \
crc32.h \
debug.c \
diff --git a/src/util/build_id.c b/src/util/build_id.c
new file mode 100644
index 000..80cafe9
--- /dev/null
+++ b/src/util/build_id.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_DL_ITERATE_PHDR
+#include 
+#include 
+#include 
+
+#include "build_id.h"
+
+#define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
+
+struct build_id_note {
+   ElfW(Nhdr) nhdr;
+
+   char name[4]; /* Note name for build-id is "GNU\0" */
+   uint8_t build_id[0];
+};
+
+struct callback_data {
+   const char *filename;
+   struct build_id_note *note;
+};
+
+static int
+build_id_find_nhdr_callback(struct dl_phdr_info *info, size_t size, void 
*data_)
+{
+   struct callback_data *data = data_;
+
+   char *ptr = strstr(info->dlpi_name, data->filename);
+   if (ptr == NULL || ptr[strlen(data->filename)] != '\0')
+  return 0;
+
+   for (unsigned i = 0; i < info->dlpi_phnum; i++) {
+  if (info->dlpi_phdr[i].p_type != PT_NOTE)
+ continue;
+
+  struct build_id_note *note = (void *)(info->dlpi_addr +
+info->dlpi_phdr[i].p_vaddr);
+  ptrdiff_t len = info->dlpi_phdr[i].p_filesz;
+
+  while (len >= sizeof(struct build_id_note)) {
+ if (note->nhdr.n_type == NT_GNU_BUILD_ID &&
+note->nhdr.n_descsz != 0 &&
+note->nhdr.n_namesz == 4 &&
+memcmp(note->name, "GNU", 4) == 0) {
+data->note = note;
+return 1;
+ }
+
+ size_t offset = sizeof(ElfW(Nhdr)) +
+ ALIGN(note->nhdr.n_namesz, 4) +
+ ALIGN(note->nhdr.n_descsz, 4);
+ note = (struct build_id_note *)((char *)note + offset);
+ len -= offset;
+  }
+   }
+
+   return 0;
+}
+
+const struct build_id_note *
+build_id_find_nhdr(const char *filename)
+{
+   struct callback_data data = {
+  .filename = filename,
+  .note = NULL,
+   };
+
+   if (dl_iterate_phdr(build_id_find_nhdr_callback, )) {
+  return data.note;
+   } else {
+  return NULL;
+   }
+}
+
+unsigned
+build_id_length(const struct build_id_note *note)
+{
+   return note->nhdr.n_descsz;
+}
+
+void
+build_id_read(const struct build_id_note *note,
+  unsigned char *build_id, size_t n)
+{
+   memcpy(build_id, note->build_id, n);
+}
+
+#endif
diff --git a/src/util/build_id.h b/src/util/build_id.h
new file mode 100644
index 000..20db4ac
--- /dev/null
+++ b/src/util/build_id.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without 

[Mesa-dev] [PATCH 2/2] anv: Use build-id for pipeline cache UUID.

[Matt Turner]

The --build-id=... ld flag has been present since binutils-2.18,
released 28 Aug 2007.
---
 src/intel/vulkan/Makefile.am  |  1 +
 src/intel/vulkan/anv_device.c | 28 +++-
 2 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index 95f276e..4197b0e 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -165,6 +165,7 @@ libvulkan_intel_la_LDFLAGS = \
-module \
-no-undefined \
-avoid-version \
+   -Wl,--build-id=sha1 \
$(BSYMBOLIC) \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 91ee67f..b52287c 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -21,18 +21,17 @@
  * IN THE SOFTWARE.
  */
 
-#include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
 #include "anv_private.h"
 #include "util/strtod.h"
 #include "util/debug.h"
+#include "util/build_id.h"
 
 #include "genxml/gen7_pack.h"
 
@@ -55,30 +54,17 @@ compiler_perf_log(void *data, const char *fmt, ...)
 }
 
 static bool
-anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
-{
-   Dl_info info;
-   struct stat st;
-   if (!dladdr(ptr, ) || !info.dli_fname)
-  return false;
-
-   if (stat(info.dli_fname, ))
-  return false;
-
-   *timestamp = st.st_mtim.tv_sec;
-   return true;
-}
-
-static bool
 anv_device_get_cache_uuid(void *uuid)
 {
-   uint32_t timestamp;
+   const struct build_id_note *note = build_id_find_nhdr("libvulkan_intel.so");
+   if (!note)
+  return false;
 
-   memset(uuid, 0, VK_UUID_SIZE);
-   if (!anv_get_function_timestamp(anv_device_get_cache_uuid, ))
+   unsigned len = build_id_length(note);
+   if (len < VK_UUID_SIZE)
   return false;
 
-   snprintf(uuid, VK_UUID_SIZE, "anv-%d", timestamp);
+   build_id_read(note, uuid, VK_UUID_SIZE);
return true;
 }
 
-- 
2.10.2

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] anv: Rework the pipeline cache UUID

[Jason Ekstrand]

The new version does a SHA1 sum of the timestamp together with the
device PCI ID.  This fixes a theoretical bug where, if you moved a drive
between machines, you could end up trying to use a pipeline cache from
one platform with a different platform.  Now we'll reject any cache that
is targeted at different hardware.

Cc: "13.0 17.0" 
---
 src/intel/vulkan/anv_device.c | 36 +---
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 82c2d6f..4e06670 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -31,6 +31,7 @@
 #include 
 
 #include "anv_private.h"
+#include "util/mesa-sha1.h"
 #include "util/strtod.h"
 #include "util/debug.h"
 
@@ -69,17 +70,30 @@ anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
return true;
 }
 
-static bool
-anv_device_get_cache_uuid(void *uuid)
+static VkResult
+anv_physical_device_init_uuid(struct anv_physical_device *device)
 {
uint32_t timestamp;
+   if (!anv_get_function_timestamp(anv_physical_device_init_uuid, )) 
{
+  return vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
+"cannot generate UUID");
+   }
 
-   memset(uuid, 0, VK_UUID_SIZE);
-   if (!anv_get_function_timestamp(anv_device_get_cache_uuid, ))
-  return false;
+   unsigned char sha1[20];
+   struct mesa_sha1 *sha1_ctx = _mesa_sha1_init();
+   if (sha1_ctx == NULL) {
+  return vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
+   "cannot generate UUID");
+   }
 
-   snprintf(uuid, VK_UUID_SIZE, "anv-%d", timestamp);
-   return true;
+   _mesa_sha1_update(sha1_ctx, , sizeof(timestamp));
+   _mesa_sha1_update(sha1_ctx, >chipset_id, 
sizeof(device->chipset_id));
+
+   _mesa_sha1_final(sha1_ctx, sha1);
+
+   memcpy(device->uuid, sha1, VK_UUID_SIZE);
+
+   return VK_SUCCESS;
 }
 
 static VkResult
@@ -163,11 +177,11 @@ anv_physical_device_init(struct anv_physical_device 
*device,
   goto fail;
}
 
-   if (!anv_device_get_cache_uuid(device->uuid)) {
-  result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
- "cannot generate UUID");
+   /* Initialize the physical device UUID */
+   result = anv_physical_device_init_uuid(device);
+   if (result != VK_SUCCESS)
   goto fail;
-   }
+
bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X);
 
/* GENs prior to 8 do not support EU/Subslice info */
-- 
2.5.0.400.gff86faf

___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] anv: Add a pair of foreach_struct macros

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 3:41 PM, Dave Airlie  wrote:

> On 15 February 2017 at 09:16, Jason Ekstrand  wrote:
> > These make iterating over Vulkan extension structs much cleaner.
>
> src/util/vk_utils.h maybe :-)
>
> vk_struct_common and vk_foreach_struct
>

Sure, I can do that if you want.


> Dave.
>
> > ---
> >  src/intel/vulkan/anv_device.c  | 26 --
> >  src/intel/vulkan/anv_formats.c | 14 ++
> >  src/intel/vulkan/anv_private.h |  8 
> >  3 files changed, 26 insertions(+), 22 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_device.c
> b/src/intel/vulkan/anv_device.c
> > index 46b83a3..7c2f816 100644
> > --- a/src/intel/vulkan/anv_device.c
> > +++ b/src/intel/vulkan/anv_device.c
> > @@ -511,10 +511,10 @@ void anv_GetPhysicalDeviceFeatures2KHR(
> >  {
> > anv_GetPhysicalDeviceFeatures(physicalDevice, >features);
> >
> > -   for (struct anv_common *c = pFeatures->pNext; c != NULL; c =
> c->pNext) {
> > -  switch (c->sType) {
> > +   anv_foreach_struct(ext, pFeatures->pNext) {
> > +  switch (ext->sType) {
> >default:
> > - anv_debug_ignored_stype(c->sType);
> > + anv_debug_ignored_stype(ext->sType);
> >   break;
> >}
> > }
> > @@ -669,10 +669,10 @@ void anv_GetPhysicalDeviceProperties2KHR(
> >  {
> > anv_GetPhysicalDeviceProperties(physicalDevice,
> >properties);
> >
> > -   for (struct anv_common *c = pProperties->pNext; c != NULL; c =
> c->pNext) {
> > -  switch (c->sType) {
> > +   anv_foreach_struct(ext, pProperties->pNext) {
> > +  switch (ext->sType) {
> >default:
> > - anv_debug_ignored_stype(c->sType);
> > + anv_debug_ignored_stype(ext->sType);
> >   break;
> >}
> > }
> > @@ -746,11 +746,10 @@ void anv_GetPhysicalDeviceQueueFamilyPr
> operties2KHR(
> > anv_get_queue_family_properties(phys_dev,
> >   >queueFamilyProperties);
> >
> > -   for (struct anv_common *c = pQueueFamilyProperties->pNext;
> > -c != NULL; c = c->pNext) {
> > -  switch (c->sType) {
> > +   anv_foreach_struct(ext, pQueueFamilyProperties->pNext) {
> > +  switch (ext->sType) {
> >default:
> > - anv_debug_ignored_stype(c->sType);
> > + anv_debug_ignored_stype(ext->sType);
> >   break;
> >}
> > }
> > @@ -815,11 +814,10 @@ void anv_GetPhysicalDeviceMemoryProperties2KHR(
> > anv_GetPhysicalDeviceMemoryProperties(physicalDevice,
> >   >
> memoryProperties);
> >
> > -   for (struct anv_common *c = pMemoryProperties->pNext;
> > -c != NULL; c = c->pNext) {
> > -  switch (c->sType) {
> > +   anv_foreach_struct(ext, pMemoryProperties->pNext) {
> > +  switch (ext->sType) {
> >default:
> > - anv_debug_ignored_stype(c->sType);
> > + anv_debug_ignored_stype(ext->sType);
> >   break;
> >}
> > }
> > diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> formats.c
> > index 0e84960..735d518 100644
> > --- a/src/intel/vulkan/anv_formats.c
> > +++ b/src/intel/vulkan/anv_formats.c
> > @@ -470,11 +470,10 @@ void anv_GetPhysicalDeviceFormatProperties2KHR(
> > anv_GetPhysicalDeviceFormatProperties(physicalDevice, format,
> >   >
> formatProperties);
> >
> > -   for (struct anv_common *c = pFormatProperties->pNext;
> > -c != NULL; c = c->pNext) {
> > -  switch (c->sType) {
> > +   anv_foreach_struct(ext, pFormatProperties->pNext) {
> > +  switch (ext->sType) {
> >default:
> > - anv_debug_ignored_stype(c->sType);
> > + anv_debug_ignored_stype(ext->sType);
> >   break;
> >}
> > }
> > @@ -668,11 +667,10 @@ VkResult anv_GetPhysicalDeviceImageFormatPr
> operties2KHR(
> > if (result != VK_SUCCESS)
> >return result;
> >
> > -   for (struct anv_common *c = pImageFormatProperties->pNext;
> > -c != NULL; c = c->pNext) {
> > -  switch (c->sType) {
> > +   anv_foreach_struct(ext, pImageFormatProperties->pNext) {
> > +  switch (ext->sType) {
> >default:
> > - anv_debug_ignored_stype(c->sType);
> > + anv_debug_ignored_stype(ext->sType);
> >   break;
> >}
> > }
> > diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_
> private.h
> > index ec791a4..527f20f 100644
> > --- a/src/intel/vulkan/anv_private.h
> > +++ b/src/intel/vulkan/anv_private.h
> > @@ -1881,6 +1881,14 @@ struct anv_common {
> >  struct anv_common *pNext;
> >  };
> >
> > +#define anv_foreach_struct(__iter, __start)
> \
> > +   for (struct anv_common *__iter = (struct anv_common *)(__start);
> \
> > +__iter; __iter = __iter->pNext)
> > +
> > +#define anv_foreach_struct_const(__iter, __start)
> \
> > +   for (const struct anv_common *__iter = (struct anv_common
> *)(__start);  \
> > +__iter; __iter = 

Re: [Mesa-dev] [PATCH] anv: Add a pair of foreach_struct macros

[Dave Airlie]

On 15 February 2017 at 09:16, Jason Ekstrand  wrote:
> These make iterating over Vulkan extension structs much cleaner.

src/util/vk_utils.h maybe :-)

vk_struct_common and vk_foreach_struct

Dave.

> ---
>  src/intel/vulkan/anv_device.c  | 26 --
>  src/intel/vulkan/anv_formats.c | 14 ++
>  src/intel/vulkan/anv_private.h |  8 
>  3 files changed, 26 insertions(+), 22 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 46b83a3..7c2f816 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -511,10 +511,10 @@ void anv_GetPhysicalDeviceFeatures2KHR(
>  {
> anv_GetPhysicalDeviceFeatures(physicalDevice, >features);
>
> -   for (struct anv_common *c = pFeatures->pNext; c != NULL; c = c->pNext) {
> -  switch (c->sType) {
> +   anv_foreach_struct(ext, pFeatures->pNext) {
> +  switch (ext->sType) {
>default:
> - anv_debug_ignored_stype(c->sType);
> + anv_debug_ignored_stype(ext->sType);
>   break;
>}
> }
> @@ -669,10 +669,10 @@ void anv_GetPhysicalDeviceProperties2KHR(
>  {
> anv_GetPhysicalDeviceProperties(physicalDevice, >properties);
>
> -   for (struct anv_common *c = pProperties->pNext; c != NULL; c = c->pNext) {
> -  switch (c->sType) {
> +   anv_foreach_struct(ext, pProperties->pNext) {
> +  switch (ext->sType) {
>default:
> - anv_debug_ignored_stype(c->sType);
> + anv_debug_ignored_stype(ext->sType);
>   break;
>}
> }
> @@ -746,11 +746,10 @@ void anv_GetPhysicalDeviceQueueFamilyProperties2KHR(
> anv_get_queue_family_properties(phys_dev,
>   >queueFamilyProperties);
>
> -   for (struct anv_common *c = pQueueFamilyProperties->pNext;
> -c != NULL; c = c->pNext) {
> -  switch (c->sType) {
> +   anv_foreach_struct(ext, pQueueFamilyProperties->pNext) {
> +  switch (ext->sType) {
>default:
> - anv_debug_ignored_stype(c->sType);
> + anv_debug_ignored_stype(ext->sType);
>   break;
>}
> }
> @@ -815,11 +814,10 @@ void anv_GetPhysicalDeviceMemoryProperties2KHR(
> anv_GetPhysicalDeviceMemoryProperties(physicalDevice,
>   
> >memoryProperties);
>
> -   for (struct anv_common *c = pMemoryProperties->pNext;
> -c != NULL; c = c->pNext) {
> -  switch (c->sType) {
> +   anv_foreach_struct(ext, pMemoryProperties->pNext) {
> +  switch (ext->sType) {
>default:
> - anv_debug_ignored_stype(c->sType);
> + anv_debug_ignored_stype(ext->sType);
>   break;
>}
> }
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
> index 0e84960..735d518 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -470,11 +470,10 @@ void anv_GetPhysicalDeviceFormatProperties2KHR(
> anv_GetPhysicalDeviceFormatProperties(physicalDevice, format,
>   
> >formatProperties);
>
> -   for (struct anv_common *c = pFormatProperties->pNext;
> -c != NULL; c = c->pNext) {
> -  switch (c->sType) {
> +   anv_foreach_struct(ext, pFormatProperties->pNext) {
> +  switch (ext->sType) {
>default:
> - anv_debug_ignored_stype(c->sType);
> + anv_debug_ignored_stype(ext->sType);
>   break;
>}
> }
> @@ -668,11 +667,10 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2KHR(
> if (result != VK_SUCCESS)
>return result;
>
> -   for (struct anv_common *c = pImageFormatProperties->pNext;
> -c != NULL; c = c->pNext) {
> -  switch (c->sType) {
> +   anv_foreach_struct(ext, pImageFormatProperties->pNext) {
> +  switch (ext->sType) {
>default:
> - anv_debug_ignored_stype(c->sType);
> + anv_debug_ignored_stype(ext->sType);
>   break;
>}
> }
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index ec791a4..527f20f 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -1881,6 +1881,14 @@ struct anv_common {
>  struct anv_common *pNext;
>  };
>
> +#define anv_foreach_struct(__iter, __start)\
> +   for (struct anv_common *__iter = (struct anv_common *)(__start);\
> +__iter; __iter = __iter->pNext)
> +
> +#define anv_foreach_struct_const(__iter, __start)  \
> +   for (const struct anv_common *__iter = (struct anv_common *)(__start);  \
> +__iter; __iter = __iter->pNext)
> +
>  #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType)  \
> \
> static inline struct __anv_type *   \
> --
> 2.5.0.400.gff86faf
>
> ___

[Mesa-dev] [PATCH] anv: Add a pair of foreach_struct macros

[Jason Ekstrand]

These make iterating over Vulkan extension structs much cleaner.
---
 src/intel/vulkan/anv_device.c  | 26 --
 src/intel/vulkan/anv_formats.c | 14 ++
 src/intel/vulkan/anv_private.h |  8 
 3 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 46b83a3..7c2f816 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -511,10 +511,10 @@ void anv_GetPhysicalDeviceFeatures2KHR(
 {
anv_GetPhysicalDeviceFeatures(physicalDevice, >features);
 
-   for (struct anv_common *c = pFeatures->pNext; c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   anv_foreach_struct(ext, pFeatures->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -669,10 +669,10 @@ void anv_GetPhysicalDeviceProperties2KHR(
 {
anv_GetPhysicalDeviceProperties(physicalDevice, >properties);
 
-   for (struct anv_common *c = pProperties->pNext; c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   anv_foreach_struct(ext, pProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -746,11 +746,10 @@ void anv_GetPhysicalDeviceQueueFamilyProperties2KHR(
anv_get_queue_family_properties(phys_dev,
  >queueFamilyProperties);
 
-   for (struct anv_common *c = pQueueFamilyProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   anv_foreach_struct(ext, pQueueFamilyProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -815,11 +814,10 @@ void anv_GetPhysicalDeviceMemoryProperties2KHR(
anv_GetPhysicalDeviceMemoryProperties(physicalDevice,
  >memoryProperties);
 
-   for (struct anv_common *c = pMemoryProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   anv_foreach_struct(ext, pMemoryProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 0e84960..735d518 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -470,11 +470,10 @@ void anv_GetPhysicalDeviceFormatProperties2KHR(
anv_GetPhysicalDeviceFormatProperties(physicalDevice, format,
  >formatProperties);
 
-   for (struct anv_common *c = pFormatProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   anv_foreach_struct(ext, pFormatProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
@@ -668,11 +667,10 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2KHR(
if (result != VK_SUCCESS)
   return result;
 
-   for (struct anv_common *c = pImageFormatProperties->pNext;
-c != NULL; c = c->pNext) {
-  switch (c->sType) {
+   anv_foreach_struct(ext, pImageFormatProperties->pNext) {
+  switch (ext->sType) {
   default:
- anv_debug_ignored_stype(c->sType);
+ anv_debug_ignored_stype(ext->sType);
  break;
   }
}
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index ec791a4..527f20f 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1881,6 +1881,14 @@ struct anv_common {
 struct anv_common *pNext;
 };
 
+#define anv_foreach_struct(__iter, __start)\
+   for (struct anv_common *__iter = (struct anv_common *)(__start);\
+__iter; __iter = __iter->pNext)
+
+#define anv_foreach_struct_const(__iter, __start)  \
+   for (const struct anv_common *__iter = (struct anv_common *)(__start);  \
+__iter; __iter = __iter->pNext)
+
 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType)  \
\
static inline struct __anv_type *   \
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

On Tue, Feb 14, 2017 at 12:43 PM, Nicholas Miell  wrote:
> On 02/14/2017 12:30 PM, Chad Versace wrote:
>>
>> On Tue 14 Feb 2017, Matt Turner wrote:
>>>
>>> Provides the ability to read the .note.gnu.build-id section of ELF
>>> binaries, which is inserted by the --build-id=... flag to ld.
>>> ---
>>> configure.ac | 2 +
>>> src/util/Makefile.sources | 2 +
>>> src/util/build_id.c | 109
>>> ++
>>> src/util/build_id.h | 56 
>>> 4 files changed, 169 insertions(+)
>>> create mode 100644 src/util/build_id.c
>>> create mode 100644 src/util/build_id.h
>>
>>
>>
>>> +AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES
>>> -DHAVE_DL_ITERATE_PHDR"])
>>
>>
>> Nice. I wasn't aware of dl_iterate_phdr(). My code for querying the
>> build-id was less slick. It used open(2) on the library, then manually
>> parsed the ElfW(Ehdr) and ElfW(Shdr) to find the build-id node.
>
>
> I also reinvented the build ID lookup wheel and just to record this
> knowledge publicly for posterity:
>
> The struct link_map l_addr field seems to corresponds to the struct
> dl_phdr_info dlpi_addr field.
>
> You can retrieve the struct link_map for a symbol by passing the
> RTLD_DL_LINKMAP flag to dladdr1() or for a library handle returned by
> dlopen() by passing RTLD_DI_LINKMAP to dlinfo().
>
> This means you can find the note section for a loaded library directly
> without having to resort to string comparisons against library names,
which
> is probably more future-proof.

That's really neat. Thanks for the information.

It doesn't look like the BSDs or musl libc support RTLD_DL_LINKMAP. In the
interest of avoiding future problems I'll stick with the string comparison
for now.
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Re: [Mesa-dev] [PATCH 32/32] r600/radeonsi: enable glsl/tgsi on-disk cache

[Marek Olšák]

On Tue, Feb 14, 2017 at 11:47 PM, Timothy Arceri  wrote:
>
>
> On 15/02/17 08:35, Marek Olšák wrote:
>>
>> On Tue, Feb 14, 2017 at 9:53 PM, Timothy Arceri 
>> wrote:
>>>
>>> On 15/02/17 02:14, Marek Olšák wrote:
>>>
 On Tue, Feb 14, 2017 at 1:52 AM, Timothy Arceri 
 wrote:
>
> ---
>src/gallium/drivers/r600/r600_pipe.c  | 10 ++
>src/gallium/drivers/radeon/r600_pipe_common.c |  2 +-
>src/gallium/drivers/radeon/r600_pipe_common.h |  1 +
>src/gallium/drivers/radeonsi/si_pipe.c| 11 +++
>src/gallium/include/pipe/p_screen.h   |  3 +++
>src/mesa/state_tracker/st_context.c   |  2 ++
>6 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.c
> b/src/gallium/drivers/r600/r600_pipe.c
> index 5290f40..bdd8c0a 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -600,6 +600,7 @@ static void r600_destroy_screen(struct pipe_screen*
> pscreen)
>   compute_memory_pool_delete(rscreen->global_pool);
>   }
>
> +   disk_cache_destroy(rscreen->b.b.disk_shader_cache);
>   r600_destroy_common_screen(>b);
>}
>
> @@ -633,6 +634,15 @@ struct pipe_screen *r600_screen_create(struct
> radeon_winsys *ws)
>   return NULL;
>   }
>
> +   uint32_t mesa_timestamp;
> +   if (disk_cache_get_function_timestamp(r600_screen_create,
> _timestamp)) {
> +   char *timestamp_str;
> +   if (asprintf(_str, "%u", mesa_timestamp) !=
> -1)
> {
> +   rscreen->b.b.disk_shader_cache =
> disk_cache_create(r600_get_chip_name(>b), timestamp_str);
> +   free(timestamp_str);
> +   }
> +   }
> +
>   if (rscreen->b.info.chip_class >= EVERGREEN) {
>   rscreen->b.b.is_format_supported =
> evergreen_is_format_supported;
>   } else {
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 95a6a48..4e5582f 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -722,7 +722,7 @@ static const char* r600_get_device_vendor(struct
> pipe_screen* pscreen)
>   return "AMD";
>}
>
> -static const char* r600_get_chip_name(struct r600_common_screen
> *rscreen)
> +const char* r600_get_chip_name(struct r600_common_screen *rscreen)
>{
>   switch (rscreen->info.family) {
>   case CHIP_R600: return "AMD R600";
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 6eff9aa..0449d4d 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -765,6 +765,7 @@ void radeon_save_cs(struct radeon_winsys *ws,
> struct
> radeon_winsys_cs *cs,
>   struct radeon_saved_cs *saved);
>void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
>bool r600_check_device_reset(struct r600_common_context *rctx);
> +const char* r600_get_chip_name(struct r600_common_screen *rscreen);
>
>/* r600_gpu_load.c */
>void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 853d850..0bb95b1 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -712,6 +712,7 @@ static void si_destroy_screen(struct pipe_screen*
> pscreen)
>   }
>   }
>   pipe_mutex_destroy(sscreen->shader_parts_mutex);
> +   disk_cache_destroy(sscreen->b.b.disk_shader_cache);
>   si_destroy_shader_cache(sscreen);
>   r600_destroy_common_screen(>b);
>}
> @@ -801,6 +802,16 @@ struct pipe_screen *radeonsi_screen_create(struct
> radeon_winsys *ws)
>   return NULL;
>   }
>
> +   uint32_t mesa_timestamp, llvm_timestamp;
> +   if (disk_cache_get_function_timestamp(radeonsi_screen_create,
> _timestamp) &&
> +
> disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
> _timestamp)) {
> +   char *timestamp_str;
> +   if (asprintf(_str, "%u_%u", mesa_timestamp,
> llvm_timestamp) != -1) {
> +   sscreen->b.b.disk_shader_cache =
> disk_cache_create(r600_get_chip_name(>b), timestamp_str);

 Can you 

[Mesa-dev] [PATCH mesa v2] docs: fix gamma correction link

[Eric Engestrom]

From: Eric Engestrom 

That link has been dead for 15 years...
We could link to Archive.org [1] to get the last time this page existed,
but I feel like Wikipedia is a better choice.

[1] 
http://web.archive.org/web/20021211151318/http://www.inforamp.net/~poynton/notes/colour_and_gamma/GammaFAQ.html

Signed-off-by: Eric Engestrom 
---
v2: fix link name as well
---
 docs/xlibdriver.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/xlibdriver.html b/docs/xlibdriver.html
index fc8c201fcd..c6d6b58e7c 100644
--- a/docs/xlibdriver.html
+++ b/docs/xlibdriver.html
@@ -172,8 +172,8 @@
 
 
 For more information about gamma correction see:
-http://www.inforamp.net/~poynton/notes/colour_and_gamma/GammaFAQ.html;>
-the Gamma FAQ
+https://en.wikipedia.org/wiki/Gamma_correction;>Wikipedia
+article on Gamma_correction
 
 
 
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH 32/32] r600/radeonsi: enable glsl/tgsi on-disk cache

[Timothy Arceri]

On 15/02/17 08:35, Marek Olšák wrote:

On Tue, Feb 14, 2017 at 9:53 PM, Timothy Arceri  wrote:

On 15/02/17 02:14, Marek Olšák wrote:


On Tue, Feb 14, 2017 at 1:52 AM, Timothy Arceri 
wrote:

---
   src/gallium/drivers/r600/r600_pipe.c  | 10 ++
   src/gallium/drivers/radeon/r600_pipe_common.c |  2 +-
   src/gallium/drivers/radeon/r600_pipe_common.h |  1 +
   src/gallium/drivers/radeonsi/si_pipe.c| 11 +++
   src/gallium/include/pipe/p_screen.h   |  3 +++
   src/mesa/state_tracker/st_context.c   |  2 ++
   6 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 5290f40..bdd8c0a 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -600,6 +600,7 @@ static void r600_destroy_screen(struct pipe_screen*
pscreen)
  compute_memory_pool_delete(rscreen->global_pool);
  }

+   disk_cache_destroy(rscreen->b.b.disk_shader_cache);
  r600_destroy_common_screen(>b);
   }

@@ -633,6 +634,15 @@ struct pipe_screen *r600_screen_create(struct
radeon_winsys *ws)
  return NULL;
  }

+   uint32_t mesa_timestamp;
+   if (disk_cache_get_function_timestamp(r600_screen_create,
_timestamp)) {
+   char *timestamp_str;
+   if (asprintf(_str, "%u", mesa_timestamp) != -1)
{
+   rscreen->b.b.disk_shader_cache =
disk_cache_create(r600_get_chip_name(>b), timestamp_str);
+   free(timestamp_str);
+   }
+   }
+
  if (rscreen->b.info.chip_class >= EVERGREEN) {
  rscreen->b.b.is_format_supported =
evergreen_is_format_supported;
  } else {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 95a6a48..4e5582f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -722,7 +722,7 @@ static const char* r600_get_device_vendor(struct
pipe_screen* pscreen)
  return "AMD";
   }

-static const char* r600_get_chip_name(struct r600_common_screen
*rscreen)
+const char* r600_get_chip_name(struct r600_common_screen *rscreen)
   {
  switch (rscreen->info.family) {
  case CHIP_R600: return "AMD R600";
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 6eff9aa..0449d4d 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -765,6 +765,7 @@ void radeon_save_cs(struct radeon_winsys *ws, struct
radeon_winsys_cs *cs,
  struct radeon_saved_cs *saved);
   void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
   bool r600_check_device_reset(struct r600_common_context *rctx);
+const char* r600_get_chip_name(struct r600_common_screen *rscreen);

   /* r600_gpu_load.c */
   void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 853d850..0bb95b1 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -712,6 +712,7 @@ static void si_destroy_screen(struct pipe_screen*
pscreen)
  }
  }
  pipe_mutex_destroy(sscreen->shader_parts_mutex);
+   disk_cache_destroy(sscreen->b.b.disk_shader_cache);
  si_destroy_shader_cache(sscreen);
  r600_destroy_common_screen(>b);
   }
@@ -801,6 +802,16 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws)
  return NULL;
  }

+   uint32_t mesa_timestamp, llvm_timestamp;
+   if (disk_cache_get_function_timestamp(radeonsi_screen_create,
_timestamp) &&
+
disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
_timestamp)) {
+   char *timestamp_str;
+   if (asprintf(_str, "%u_%u", mesa_timestamp,
llvm_timestamp) != -1) {
+   sscreen->b.b.disk_shader_cache =
disk_cache_create(r600_get_chip_name(>b), timestamp_str);

Can you please at least make some effort to get close to 80 chars per
line even though it's not strictly required in this driver?


+   free(timestamp_str);
+   }
+   }
+
  si_handle_env_var_force_family(sscreen);

  if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS",
false))
diff --git a/src/gallium/include/pipe/p_screen.h
b/src/gallium/include/pipe/p_screen.h
index b6203f1..6fd527f 100644
--- a/src/gallium/include/pipe/p_screen.h
+++ b/src/gallium/include/pipe/p_screen.h
@@ -42,6 +42,7 @@
   #include "pipe/p_format.h"
   #include "pipe/p_defines.h"
   #include "pipe/p_video_enums.h"
+#include "util/disk_cache.h"



@@ -318,6 +319,8 @@ struct pipe_screen {
  const void 

[Mesa-dev] [Bug 99817] [softpipe] piglit glsl-fs-tan-1 regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99817

Bug ID: 99817
   Summary: [softpipe] piglit glsl-fs-tan-1 regression
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: regression
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org

mesa: 924a8cbb408e7dd110d172093908f99926b7970d (master 17.1.0-devel)

$ ./bin/shader_runner tests/shaders/glsl-fs-atan-1.shader_test -auto
Probe color at (0,0)
  Expected: 0.125000 0.125000 0.125000 0.125000
  Observed: 0.211765 0.211765 0.211765 0.211765
Test failure on line 27
Probe color at (125,0)
  Expected: 0.25 0.25 0.25 0.25
  Observed: 0.043137 0.043137 0.043137 0.043137
Test failure on line 28
Probe color at (249,0)
  Expected: 0.375000 0.375000 0.375000 0.375000
  Observed: 0.00 0.00 0.00 0.00
Test failure on line 29
PIGLIT: {"result": "fail" }

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Re: [Mesa-dev] [PATCH 5/6] docs/submittingpatches: assorted grammar fixes

[Ben Crocker]

- Original Message -
> From: "Emil Velikov" 
> To: mesa-dev@lists.freedesktop.org
> Cc: "emil l velikov" , "Ben Crocker" 
> 
> Sent: Monday, February 13, 2017 8:42:22 AM
> Subject: [PATCH 5/6] docs/submittingpatches: assorted grammar fixes
> 
> From: Emil Velikov 
> 
> Cc: Ben Crocker 
> Suggested-by: Ben Crocker 
> Signed-off-by: Emil Velikov 
> ---
> Thanks for the suggestions Ben. Feel free to let us know/send patches if
> you spot anything else that looks odd.
> ---

You're welcome!
These changes look good to me.

-- Ben

>  docs/submittingpatches.html | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/docs/submittingpatches.html b/docs/submittingpatches.html
> index d38ccad872..f8380b0a54 100644
> --- a/docs/submittingpatches.html
> +++ b/docs/submittingpatches.html
> @@ -72,7 +72,7 @@ if needed.  For example:
>  platform.
>  
>  A "Signed-off-by:" line is not required, but not discouraged either.
> -If a patch address a bugzilla issue, that should be noted in the
> +If a patch addresses a bugzilla issue, that should be noted in the
>  patch comment.  For example:
>  
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89689
> @@ -205,7 +205,7 @@ as the issues are resolved first.
>  Nominating a commit for a stable branch
>  
>  
> -There are three ways to nominate patch for inclusion of the stable branch
> and
> +There are three ways to nominate a patch for inclusion in the stable branch
> and
>  release.
>  
>  
> @@ -247,7 +247,7 @@ exclusively for the older branch.
>  This "CC" syntax for patch nomination will cause patches to automatically be
>  copied to the mesa-stable@ mailing list when you use "git send-email" to
>  send
>  patches to the mesa-dev@ mailing list. If you prefer using --suppress-cc
>  that
> -won't have any effect negative effect on the patch nomination.
> +won't have any negative effect on the patch nomination.
>  
>  
>  Note: by removing the tag [as the commit is pushed] the patch is
> @@ -283,7 +283,7 @@ be rejected:
>  
>  
>Patch introduces a regression. Any reported build breakage or other
> -  regression caused by a particular patch, (game no longer work, piglit test
> +  regression caused by a particular patch, (game no longer works, piglit
> test
>changes from PASS to FAIL), is justification for rejecting a patch.
>  
>Patch is too large, (say, larger than 100 lines)
> @@ -322,7 +322,7 @@ be rejected:
>Note: As an exception to this rule, the stable-release manager may accept
>hardware-enabling "features". For example, backports of new code to
>support
>a newly-developed hardware product can be accepted if they can be
>reasonably
> -  determined to not have effects on other hardware.
> +  determined not to have effects on other hardware.
>  
>Patch is a performance optimization. As a rule, performance patches
>are
>not candidates for the stable branch. The only exception might be a case
> --
> 2.11.0
> 
> 
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[Mesa-dev] [PATCH mesa] egl: remove duplicate 0 assignment

[Eric Engestrom]

From: Eric Engestrom 

The memset on the line before already takes care of this.

Signed-off-by: Eric Engestrom 
---
 src/egl/main/eglimage.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/egl/main/eglimage.c b/src/egl/main/eglimage.c
index 818b5975cd..d062cbfe01 100644
--- a/src/egl/main/eglimage.c
+++ b/src/egl/main/eglimage.c
@@ -46,9 +46,6 @@ _eglParseImageAttribList(_EGLImageAttribs *attrs, _EGLDisplay 
*dpy,
(void) dpy;
 
memset(attrs, 0, sizeof(*attrs));
-   attrs->ImagePreserved = EGL_FALSE;
-   attrs->GLTextureLevel = 0;
-   attrs->GLTextureZOffset = 0;
 
if (!attrib_list)
   return err;
-- 
Cheers,
  Eric
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Re: [Mesa-dev] [PATCH v2 6/7] genxml: Add the CACHE_MODE_0 register on gen9

[Nanley Chery]

On Fri, Feb 10, 2017 at 11:02:20AM -0800, Jason Ekstrand wrote:
> Reviewed-by: Lionel Landwerlin 
> ---
>  src/intel/genxml/gen9.xml | 28 
>  1 file changed, 28 insertions(+)
> 

I know this is already upstream, but thought I might as well chime in -
this looks good to me.

-Nanley

> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> index 671322b..ec29d13 100644
> --- a/src/intel/genxml/gen9.xml
> +++ b/src/intel/genxml/gen9.xml
> @@ -3471,4 +3471,32 @@
>  
>
>  
> +  
> +
> + end="1" type="bool"/>
> + end="2" type="bool"/>
> +
> +
> + type="uint">
> +  
> +  
> +  
> +
> + type="bool"/>
> + type="bool"/>
> + start="12" end="14" type="uint"/>
> +
> +
> + type="bool"/>
> + end="17" type="bool"/>
> + start="18" end="18" type="bool"/>
> +
> + type="bool"/>
> + type="uint"/>
> + type="bool"/>
> + end="27" type="bool"/>
> + start="28" end="30" type="uint"/>
> +
> +  
> +
>  
> -- 
> 2.5.0.400.gff86faf
> 
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[Mesa-dev] [PATCH mesa] docs: add link to gallium doc

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 docs/sourcedocs.html | 5 +
 1 file changed, 5 insertions(+)

diff --git a/docs/sourcedocs.html b/docs/sourcedocs.html
index 454ea7d677..660dcb2ef0 100644
--- a/docs/sourcedocs.html
+++ b/docs/sourcedocs.html
@@ -41,6 +41,11 @@
 here
 
 
+
+Gallium is also documented using Sphinx. The generated output can be found
+https://gallium.readthedocs.io;>on Gallium.ReadTheDocs.io.
+
+
 
 
 
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH v2 2/7] genxml: Add the CACHE_MODE_1 register on gen8

[Nanley Chery]

On Tue, Feb 14, 2017 at 02:18:56PM -0800, Nanley Chery wrote:
> On Fri, Feb 10, 2017 at 11:02:16AM -0800, Jason Ekstrand wrote:
> > Reviewed-by: Lionel Landwerlin 
> > ---
> >  src/intel/genxml/gen8.xml | 21 +
> >  1 file changed, 21 insertions(+)
> 
> There are some unsigned integers that could be made booleans, but I
> can't see this mattering anytime soon.
> 
> This patch is
> Reviewed-by: Nanley Chery 
> 

Whoops, looks like this is already upstream! :)

> > 
> > diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> > index 970e637..32ed764 100644
> > --- a/src/intel/genxml/gen8.xml
> > +++ b/src/intel/genxml/gen8.xml
> > @@ -3200,4 +3200,25 @@
> >  
> >
> >  
> > +  
> > + > type="bool"/>
> > + > end="3" type="bool"/>
> > +
> > + > type="bool"/>
> > + > type="uint"/>
> > +
> > +
> > + > type="uint"/>
> > + > type="uint"/>
> > + > end="18" type="bool"/>
> > + > start="19" end="19" type="bool"/>
> > +
> > + > end="22" type="bool"/>
> > + > type="uint"/>
> > +
> > + > type="uint"/>
> > + > type="uint"/>
> > + > end="30" type="uint"/>
> > +  
> > +
> >  
> > -- 
> > 2.5.0.400.gff86faf
> > 
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [PATCH v2 2/7] genxml: Add the CACHE_MODE_1 register on gen8

[Nanley Chery]

On Fri, Feb 10, 2017 at 11:02:16AM -0800, Jason Ekstrand wrote:
> Reviewed-by: Lionel Landwerlin 
> ---
>  src/intel/genxml/gen8.xml | 21 +
>  1 file changed, 21 insertions(+)

There are some unsigned integers that could be made booleans, but I
can't see this mattering anytime soon.

This patch is
Reviewed-by: Nanley Chery 

> 
> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> index 970e637..32ed764 100644
> --- a/src/intel/genxml/gen8.xml
> +++ b/src/intel/genxml/gen8.xml
> @@ -3200,4 +3200,25 @@
>  
>
>  
> +  
> + type="bool"/>
> + end="3" type="bool"/>
> +
> + type="bool"/>
> + type="uint"/>
> +
> +
> +
> + type="uint"/>
> + end="18" type="bool"/>
> + start="19" end="19" type="bool"/>
> +
> + end="22" type="bool"/>
> + type="uint"/>
> +
> +
> + type="uint"/>
> + type="uint"/>
> +  
> +
>  
> -- 
> 2.5.0.400.gff86faf
> 
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[Mesa-dev] [PATCH 1/2] i965: Add an OUT_BATCH64() macro.

[Kenneth Graunke]

This is more convenient than OUT_BATCH'ing both halves.

Signed-off-by: Kenneth Graunke 
Cc: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/gen8_depth_state.c  | 3 +--
 src/mesa/drivers/dri/i965/gen8_ds_state.c | 3 +--
 src/mesa/drivers/dri/i965/gen8_gs_state.c | 3 +--
 src/mesa/drivers/dri/i965/gen8_hs_state.c | 3 +--
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 3 +--
 src/mesa/drivers/dri/i965/gen8_vs_state.c | 3 +--
 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 1 +
 7 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index a7e61354fd5..c085246bc92 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -72,8 +72,7 @@ emit_depth_packets(struct brw_context *brw,
   OUT_RELOC64(depth_mt->bo,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
} else {
-  OUT_BATCH(0);
-  OUT_BATCH(0);
+  OUT_BATCH64(0);
}
OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c 
b/src/mesa/drivers/dri/i965/gen8_ds_state.c
index ee2f82e1098..55738fd1ffc 100644
--- a/src/mesa/drivers/dri/i965/gen8_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c
@@ -56,8 +56,7 @@ gen8_upload_ds_state(struct brw_context *brw)
  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  ffs(stage_state->per_thread_scratch) - 11);
   } else {
- OUT_BATCH(0);
- OUT_BATCH(0);
+ OUT_BATCH64(0);
   }
   OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg,
   GEN7_DS_DISPATCH_START_GRF) |
diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c 
b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index 2b74f1bd575..31c6f89bc13 100644
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -63,8 +63,7 @@ gen8_upload_gs_state(struct brw_context *brw)
  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  ffs(stage_state->per_thread_scratch) - 11);
   } else {
- OUT_BATCH(0);
- OUT_BATCH(0);
+ OUT_BATCH64(0);
   }
 
   /* DW6 */
diff --git a/src/mesa/drivers/dri/i965/gen8_hs_state.c 
b/src/mesa/drivers/dri/i965/gen8_hs_state.c
index ee47e5e54a0..dbdd19b1f5c 100644
--- a/src/mesa/drivers/dri/i965/gen8_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_hs_state.c
@@ -57,8 +57,7 @@ gen8_upload_hs_state(struct brw_context *brw)
  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  ffs(stage_state->per_thread_scratch) - 11);
   } else {
- OUT_BATCH(0);
- OUT_BATCH(0);
+ OUT_BATCH64(0);
   }
   OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
 SET_FIELD(prog_data->dispatch_grf_start_reg,
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c 
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 03468267ce6..9b1a78c6ee6 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -269,8 +269,7 @@ gen8_upload_ps_state(struct brw_context *brw,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
   ffs(stage_state->per_thread_scratch) - 11);
} else {
-  OUT_BATCH(0);
-  OUT_BATCH(0);
+  OUT_BATCH64(0);
}
OUT_BATCH(dw6);
OUT_BATCH(dw7);
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c 
b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 7b66da4b17c..a2b08fe92a0 100644
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -62,8 +62,7 @@ upload_vs_state(struct brw_context *brw)
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
   ffs(stage_state->per_thread_scratch) - 11);
} else {
-  OUT_BATCH(0);
-  OUT_BATCH(0);
+  OUT_BATCH64(0);
}
 
OUT_BATCH((prog_data->dispatch_grf_start_reg <<
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index bf7cadfc4d6..da8f7e561f4 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -161,6 +161,7 @@ intel_batchbuffer_advance(struct brw_context *brw)
 
 #define OUT_BATCH(d) *__map++ = (d)
 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
+#define OUT_BATCH64(d) *((uint64_t *) __map) = (d); __map += 2
 
 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {\
uint32_t __offset = (__map - brw->batch.map) * 4;  \
-- 
2.11.1

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[Mesa-dev] [PATCH 2/2] i965: Make a helper for emitting 3DSTATE_CONSTANT_XS packets.

[Kenneth Graunke]

This separates the logic from filling out a 3DSTATE_CONSTANT_XS
packet from the decisions about what to put in the various buffers.

It also should make it easier to use more than one buffer, should
we decide to do so.  It also provides a nice place to enforce the
various restrictions via assertions.

By marking the helper as inline, the code for unused buffers should
be constant folded away.

Signed-off-by: Kenneth Graunke 
Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/gen6_constant_state.c | 169 +---
 1 file changed, 118 insertions(+), 51 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c 
b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 6c0c32b26f7..7e6fa92ecf2 100644
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -27,6 +27,97 @@
 #include "intel_batchbuffer.h"
 #include "program/prog_parameter.h"
 
+#define F(RELOC, BATCH, buf, x) \
+   if (buf) { \
+  RELOC(buf, I915_GEM_DOMAIN_RENDER, 0, x); \
+   } else { \
+  BATCH(x); \
+   }
+#define OUT_PTR64(buf, x) F(OUT_RELOC64, OUT_BATCH64, buf, x)
+#define OUT_PTR(buf, x)   F(OUT_RELOC,   OUT_BATCH,   buf, x)
+
+static inline void
+emit_3dstate_constant(struct brw_context *brw,
+  uint32_t opcode,
+  uint32_t mocs,
+  drm_intel_bo *bufs[4],
+  uint16_t read_lengths[4],
+  uint64_t offsets[4])
+{
+   /* Buffer 0 is relative to Dynamic State Base Address, which we program
+* to the start of the batch buffer.  All others are graphics virtual
+* addresses regardless of the INSTPM settings.
+*/
+   assert(bufs[0] == NULL || bufs[0] == brw->batch.bo);
+
+   assert(read_lengths[0] == 0 || bufs[0] != NULL);
+   assert(read_lengths[1] == 0 || bufs[1] != NULL);
+   assert(read_lengths[2] == 0 || bufs[2] != NULL);
+   assert(read_lengths[3] == 0 || bufs[3] != NULL);
+
+   if (brw->gen >= 8) {
+  BEGIN_BATCH(11);
+  OUT_BATCH(opcode << 16 | (11 - 2));
+  OUT_BATCH(read_lengths[0] | read_lengths[1] << 16);
+  OUT_BATCH(read_lengths[2] | read_lengths[3] << 16);
+  OUT_BATCH64(offsets[0]);
+  OUT_PTR64(bufs[1], offsets[1]);
+  OUT_PTR64(bufs[2], offsets[2]);
+  OUT_PTR64(bufs[3], offsets[3]);
+  ADVANCE_BATCH();
+   } else if (brw->gen == 7) {
+  /* From the Ivybridge PRM, Volume 2, Part 1, Page 112:
+   * "Constant buffers must be enabled in order from Constant Buffer 0 to
+   *  Constant Buffer 3 within this command.  For example, it is not
+   *  allowed to enable Constant Buffer 1 by programming a non-zero value
+   *  in the VS Constant Buffer 1 Read Length without a non-zero value in
+   *  VS Constant Buffer 0 Read Length."
+   *
+   * Haswell removes this restriction.
+   */
+  if (!brw->is_haswell) {
+ assert(read_lengths[3] == 0 || (read_lengths[2] > 0 &&
+ read_lengths[1] > 0 &&
+ read_lengths[0] > 0));
+ assert(read_lengths[2] == 0 || (read_lengths[1] > 0 &&
+ read_lengths[0] > 0));
+ assert(read_lengths[1] == 0 || read_lengths[0] > 0);
+  }
+
+  BEGIN_BATCH(7);
+  OUT_BATCH(opcode << 16 | (7 - 2));
+  OUT_BATCH(read_lengths[0] | read_lengths[1] << 16);
+  OUT_BATCH(read_lengths[2] | read_lengths[3] << 16);
+  OUT_BATCH(offsets[0]);
+  OUT_PTR(bufs[1], offsets[1]);
+  OUT_PTR(bufs[2], offsets[2]);
+  OUT_PTR(bufs[3], offsets[3]);
+  ADVANCE_BATCH();
+   } else if (brw->gen == 6) {
+  /* From the Sandybridge PRM, Volume 2, Part 1, Page 138:
+   * "The sum of all four read length fields (each incremented to
+   *  represent the actual read length) must be less than or equal
+   *  to 32."
+   */
+  assert(read_lengths[0] + read_lengths[1] +
+ read_lengths[2] + read_lengths[3] < 32);
+
+  BEGIN_BATCH(5);
+  OUT_BATCH(opcode << 16 | (5 - 2) |
+(read_lengths[0] ? GEN6_CONSTANT_BUFFER_0_ENABLE : 0) |
+(read_lengths[1] ? GEN6_CONSTANT_BUFFER_1_ENABLE : 0) |
+(read_lengths[2] ? GEN6_CONSTANT_BUFFER_2_ENABLE : 0) |
+(read_lengths[3] ? GEN6_CONSTANT_BUFFER_3_ENABLE : 0));
+  OUT_BATCH(offsets[0] | (read_lengths[0] - 1));
+  OUT_PTR(bufs[1], offsets[1] | (read_lengths[1] - 1));
+  OUT_PTR(bufs[2], offsets[2] | (read_lengths[2] - 1));
+  OUT_PTR(bufs[3], offsets[3] | (read_lengths[3] - 1));
+  ADVANCE_BATCH();
+   } else {
+  unreachable("unhandled gen in emit_3dstate_constant");
+   }
+}
+
 void
 gen7_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
@@ -37,60 +128,36 @@ gen7_upload_constant_state(struct brw_context *brw,
/* 

Re: [Mesa-dev] [PATCH 32/32] r600/radeonsi: enable glsl/tgsi on-disk cache

[Marek Olšák]

On Tue, Feb 14, 2017 at 9:53 PM, Timothy Arceri  wrote:
> On 15/02/17 02:14, Marek Olšák wrote:
>
>> On Tue, Feb 14, 2017 at 1:52 AM, Timothy Arceri 
>> wrote:
>>>
>>> ---
>>>   src/gallium/drivers/r600/r600_pipe.c  | 10 ++
>>>   src/gallium/drivers/radeon/r600_pipe_common.c |  2 +-
>>>   src/gallium/drivers/radeon/r600_pipe_common.h |  1 +
>>>   src/gallium/drivers/radeonsi/si_pipe.c| 11 +++
>>>   src/gallium/include/pipe/p_screen.h   |  3 +++
>>>   src/mesa/state_tracker/st_context.c   |  2 ++
>>>   6 files changed, 28 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/src/gallium/drivers/r600/r600_pipe.c
>>> b/src/gallium/drivers/r600/r600_pipe.c
>>> index 5290f40..bdd8c0a 100644
>>> --- a/src/gallium/drivers/r600/r600_pipe.c
>>> +++ b/src/gallium/drivers/r600/r600_pipe.c
>>> @@ -600,6 +600,7 @@ static void r600_destroy_screen(struct pipe_screen*
>>> pscreen)
>>>  compute_memory_pool_delete(rscreen->global_pool);
>>>  }
>>>
>>> +   disk_cache_destroy(rscreen->b.b.disk_shader_cache);
>>>  r600_destroy_common_screen(>b);
>>>   }
>>>
>>> @@ -633,6 +634,15 @@ struct pipe_screen *r600_screen_create(struct
>>> radeon_winsys *ws)
>>>  return NULL;
>>>  }
>>>
>>> +   uint32_t mesa_timestamp;
>>> +   if (disk_cache_get_function_timestamp(r600_screen_create,
>>> _timestamp)) {
>>> +   char *timestamp_str;
>>> +   if (asprintf(_str, "%u", mesa_timestamp) != -1)
>>> {
>>> +   rscreen->b.b.disk_shader_cache =
>>> disk_cache_create(r600_get_chip_name(>b), timestamp_str);
>>> +   free(timestamp_str);
>>> +   }
>>> +   }
>>> +
>>>  if (rscreen->b.info.chip_class >= EVERGREEN) {
>>>  rscreen->b.b.is_format_supported =
>>> evergreen_is_format_supported;
>>>  } else {
>>> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
>>> b/src/gallium/drivers/radeon/r600_pipe_common.c
>>> index 95a6a48..4e5582f 100644
>>> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
>>> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
>>> @@ -722,7 +722,7 @@ static const char* r600_get_device_vendor(struct
>>> pipe_screen* pscreen)
>>>  return "AMD";
>>>   }
>>>
>>> -static const char* r600_get_chip_name(struct r600_common_screen
>>> *rscreen)
>>> +const char* r600_get_chip_name(struct r600_common_screen *rscreen)
>>>   {
>>>  switch (rscreen->info.family) {
>>>  case CHIP_R600: return "AMD R600";
>>> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
>>> b/src/gallium/drivers/radeon/r600_pipe_common.h
>>> index 6eff9aa..0449d4d 100644
>>> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
>>> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
>>> @@ -765,6 +765,7 @@ void radeon_save_cs(struct radeon_winsys *ws, struct
>>> radeon_winsys_cs *cs,
>>>  struct radeon_saved_cs *saved);
>>>   void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
>>>   bool r600_check_device_reset(struct r600_common_context *rctx);
>>> +const char* r600_get_chip_name(struct r600_common_screen *rscreen);
>>>
>>>   /* r600_gpu_load.c */
>>>   void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
>>> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
>>> b/src/gallium/drivers/radeonsi/si_pipe.c
>>> index 853d850..0bb95b1 100644
>>> --- a/src/gallium/drivers/radeonsi/si_pipe.c
>>> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
>>> @@ -712,6 +712,7 @@ static void si_destroy_screen(struct pipe_screen*
>>> pscreen)
>>>  }
>>>  }
>>>  pipe_mutex_destroy(sscreen->shader_parts_mutex);
>>> +   disk_cache_destroy(sscreen->b.b.disk_shader_cache);
>>>  si_destroy_shader_cache(sscreen);
>>>  r600_destroy_common_screen(>b);
>>>   }
>>> @@ -801,6 +802,16 @@ struct pipe_screen *radeonsi_screen_create(struct
>>> radeon_winsys *ws)
>>>  return NULL;
>>>  }
>>>
>>> +   uint32_t mesa_timestamp, llvm_timestamp;
>>> +   if (disk_cache_get_function_timestamp(radeonsi_screen_create,
>>> _timestamp) &&
>>> +
>>> disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
>>> _timestamp)) {
>>> +   char *timestamp_str;
>>> +   if (asprintf(_str, "%u_%u", mesa_timestamp,
>>> llvm_timestamp) != -1) {
>>> +   sscreen->b.b.disk_shader_cache =
>>> disk_cache_create(r600_get_chip_name(>b), timestamp_str);
>>
>> Can you please at least make some effort to get close to 80 chars per
>> line even though it's not strictly required in this driver?
>>
>>> +   free(timestamp_str);
>>> +   }
>>> +   }
>>> +
>>>  si_handle_env_var_force_family(sscreen);
>>>
>>>  if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS",
>>> false))
>>> diff --git 

[Mesa-dev] [PATCH 1/3] gallivm: Improve debug output (V2)

[Ben Crocker]

Improve debug output from gallivm_compile_module and
lp_build_create_jit_compiler_for_module, printing the
-mcpu and -mattr options passed to LLC.

V2: enclose MAttrs debug_printf block and llc -mcpu debug_printf
in "if (gallivm_debug & )..."

Signed-off-by: Ben Crocker 
Cc: 12.0 13.0 17.0 
---
 src/gallium/auxiliary/gallivm/lp_bld_init.c   |  5 -
 src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 14 ++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c 
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index d1b2369..fed43e9 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -606,7 +606,10 @@ gallivm_compile_module(struct gallivm_state *gallivm)
   util_snprintf(filename, sizeof(filename), "ir_%s.bc", 
gallivm->module_name);
   LLVMWriteBitcodeToFile(gallivm->module, filename);
   debug_printf("%s written\n", filename);
-  debug_printf("Invoke as \"llc -o - %s\"\n", filename);
+  debug_printf("Invoke as \"llc %s%s -o - %s\"\n",
+   (HAVE_LLVM >= 0x0305) ? "[-mcpu=<-mcpu option] " : "",
+   "[-mattr=<-mattr option(s)>]",
+   filename);
}
 
if (USE_MCJIT) {
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp 
b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index 21d9e15..13f9a4d 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -101,6 +101,7 @@
 #include "util/u_cpu_detect.h"
 
 #include "lp_bld_misc.h"
+#include "lp_bld_debug.h"
 
 namespace {
 
@@ -627,6 +628,16 @@ 
lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
 
builder.setMAttrs(MAttrs);
 
+   if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | 
GALLIVM_DEBUG_DUMP_BC)) {
+  int n = MAttrs.size();
+  if (n > 0) {
+ debug_printf("llc -mattr option(s): ");
+ for (int i = 0; i < n; i++)
+debug_printf("%s%s", MAttrs[i].c_str(), (i < n - 1) ? "," : "");
+ debug_printf("\n");
+  }
+   }
+
 #if HAVE_LLVM >= 0x0305
StringRef MCPU = llvm::sys::getHostCPUName();
/*
@@ -642,6 +653,9 @@ 
lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
 * can't handle. Not entirely sure if we really need to do anything yet.
 */
builder.setMCPU(MCPU);
+   if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | 
GALLIVM_DEBUG_DUMP_BC)) {
+  debug_printf("llc -mcpu option: %s\n", MCPU.str().c_str());
+   }
 #endif
 
ShaderMemoryManager *MM = NULL;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 11:34 AM, Chad Versace 
wrote:

> On Tue 14 Feb 2017, Matt Turner wrote:
> > On Tue, Feb 14, 2017 at 11:21 AM, Matt Turner 
> wrote:
> > > On Tue, Feb 14, 2017 at 11:18 AM, Matt Turner 
> wrote:
> > >> On Tue, Feb 14, 2017 at 10:59 AM, Jason Ekstrand <
> ja...@jlekstrand.net> wrote:
> > >>> I'm not sure how I feel about the silent fall-backs.  At least in
> the Vulkan
> > >>> driver, we should fail to compile if we can't get build-id.
> Otherwise,
> > >>> you'll end up compiling a driver that will always fail device
> creation.
> > >>
> > >> That was really an attempt to preempt questions about Windows.
> > >>
> > >> I am happy to drop it.
> > >
> > > Think-o. No, it's necessary for systems that don't have
> > > dl_iterate_phdr (Windows, AFAIK).
> >
> > I promise I'll stop replying to myself after this...
> >
> > I guess dropping the fallback and simply wrapping build_id.c in
> > HAVE_DL_ITERATE_PHDR is sufficient? Windows will build an empty source
> > file, which is fine because no code should ever attempt to use it on
> > Windows; and there would be no chance of the Vulkan driver calling
> > (non-existent) fallback code.
>
> I'm in favor of dropping the fallback stubs.
>

I don't really care too much how it works so long as anv fails to compile.
I could see the stubs maybe being useful if you wanted to have the shader
cache stuff silently and automatically fall back to disabled.  Or, the
shader cache stuff could have a #if.  It doesn't matter to me.
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Re: [Mesa-dev] [PATCH v2 7/7] anv: Implement the Skylake stencil PMA optimization

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 11:01 AM, Nanley Chery 
wrote:

> On Tue, Feb 14, 2017 at 10:53:37AM -0800, Jason Ekstrand wrote:
> > On Tue, Feb 14, 2017 at 10:35 AM, Nanley Chery 
> > wrote:
> >
> > > On Mon, Feb 13, 2017 at 08:45:47PM -0800, Jason Ekstrand wrote:
> > > > On Mon, Feb 13, 2017 at 6:13 PM, Jason Ekstrand <
> ja...@jlekstrand.net>
> > > > wrote:
> > > >
> > > > > On Mon, Feb 13, 2017 at 5:00 PM, Nanley Chery <
> nanleych...@gmail.com>
> > > > > wrote:
> > > > >
> > > > >> On Fri, Feb 10, 2017 at 11:02:21AM -0800, Jason Ekstrand wrote:
> > > > >> > This improves the performance of Dota 2 on my Sky Lake Skull
> Canyon
> > > > >> > machine by about 2-3%.
> > > > >> >
> > > > >>
> > > > >> This patch looks good. Could we compare our setup and testing in
> the
> > > > >> office? I can't reproduce these numbers.
> > > > >>
> > > > >
> > > > > I'll have to do more runs.  At the moment, I'm not seeing a large
> boost
> > > > > but I'll get a larger sample size and see if it's visible.
> > > > >
> > > >
> > > > I did a bunch more runs.  It looks like it helps somewhere between 0
> and
> > > > 1%.  Not as much as I saw earlier, but it's definitely non-negative.
> > > >
> > >
> > > Although I've confirmed that the fix is enabled in Dota 2, I'm also not
> > > seeing any major changes on my SKL GT4. I get positive and negative
> > > changes in FPS, but it's all < 1% and seemingly noise.
> > >
> > > With the commit message updated with your new findings, this patch is
> > > Reviewed-by: Nanley Chery 
> > >
> >
> > Here's what I wrote:
> >
> > Unfortunately, this doesn't substantially improve the performance of
> any
> > known apps.  With Dota 2 on my Sky Lake gt4, it seems help by
> somewhere
> > between 0% and 1% but there's enough noise that it's hard to get a
> clear
> > picture.
> >
>
> Looks good to me.
>

Cool!  Thanks for your careful review!


> -Nanley
>
> >
> >
> > > > --Jason
> > > >
> > > >
> > > > > --Jason
> > > > >
> > > > >
> > > > >> -Nanley
> > > > >>
> > > > >> > Reviewed-by: Lionel Landwerlin 
> > > > >> > ---
> > > > >> >  src/intel/vulkan/anv_private.h |   1 +
> > > > >> >  src/intel/vulkan/gen8_cmd_buffer.c | 157
> > > > >> -
> > > > >> >  src/intel/vulkan/genX_pipeline.c   |   6 +-
> > > > >> >  3 files changed, 158 insertions(+), 6 deletions(-)
> > > > >> >
> > > > >> > diff --git a/src/intel/vulkan/anv_private.h
> > > > >> b/src/intel/vulkan/anv_private.h
> > > > >> > index fa6032e..25c9c93 100644
> > > > >> > --- a/src/intel/vulkan/anv_private.h
> > > > >> > +++ b/src/intel/vulkan/anv_private.h
> > > > >> > @@ -1482,6 +1482,7 @@ struct anv_pipeline {
> > > > >> > bool writes_depth;
> > > > >> > bool
>  depth_test_enable;
> > > > >> > bool writes_stencil;
> > > > >> > +   bool
> > >  stencil_test_enable;
> > > > >> > bool
>  depth_clamp_enable;
> > > > >> > bool kill_pixel;
> > > > >> >
> > > > >> > diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
> > > > >> b/src/intel/vulkan/gen8_cmd_buffer.c
> > > > >> > index 0628f3a..59fd537 100644
> > > > >> > --- a/src/intel/vulkan/gen8_cmd_buffer.c
> > > > >> > +++ b/src/intel/vulkan/gen8_cmd_buffer.c
> > > > >> > @@ -157,16 +157,39 @@ __emit_sf_state(struct anv_cmd_buffer
> > > *cmd_buffer)
> > > > >> >  void
> > > > >> >  genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer
> *cmd_buffer,
> > > > >> bool enable)
> > > > >> >  {
> > > > >> > -#if GEN_GEN == 8
> > > > >> > if (cmd_buffer->state.pma_fix_enabled == enable)
> > > > >> >return;
> > > > >> >
> > > > >> > +   cmd_buffer->state.pma_fix_enabled = enable;
> > > > >> > +
> > > > >> > +   /* According to the Broadwell PIPE_CONTROL documentation,
> > > software
> > > > >> should
> > > > >> > +* emit a PIPE_CONTROL with the CS Stall and Depth Cache
> Flush
> > > bits
> > > > >> set
> > > > >> > +* prior to the LRI.  If stencil buffer writes are enabled,
> > > then a
> > > > >> Render
> > > > >> > +* Cache Flush is also necessary.
> > > > >> > +*
> > > > >> > +* The Skylake docs say to use a depth stall rather than a
> > > command
> > > > >> > +* streamer stall.  However, the hardware seems to violently
> > > > >> disagree.
> > > > >> > +* A full command streamer stall seems to be needed in both
> > > cases.
> > > > >> > +*/
> > > > >> > anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc)
> {
> > > > >> >pc.DepthCacheFlushEnable = true;
> > > > >> >pc.CommandStreamerStallEnable = true;
> > > > >> >pc.RenderTargetCacheFlushEnable = true;
> > > > >> > }
> > > > >> >
> > > > >> > +#if GEN_GEN == 9
> > > > >> > +
> > > > >> > +   uint32_t cache_mode;
> > > > >> > +   anv_pack_struct(_mode, GENX(CACHE_MODE_0),
> > > > >> > +  

Re: [Mesa-dev] [PATCH 2/2] anv: Use build-id for pipeline cache UUID.

[Chad Versace]

On Tue 14 Feb 2017, Kenneth Graunke wrote:
> On Tuesday, February 14, 2017 12:38:45 PM PST Chad Versace wrote:
> > On Tue 14 Feb 2017, Matt Turner wrote:
> > 
> > 
> > >  static bool
> > > -anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
> > > +anv_device_get_cache_uuid(void *uuid)
> > >  {
> > > -   Dl_info info;
> > > -   struct stat st;
> > > -   if (!dladdr(ptr, ) || !info.dli_fname)
> > > +   const struct note *note = build_id_find_nhdr("libvulkan_intel.so");
> > > +   if (!note)
> > >return false;
> > >  
> > > -   if (stat(info.dli_fname, ))
> > > +   unsigned len = build_id_length(note);
> > > +   if (len < VK_UUID_SIZE)
> > >return false;
> > >  
> > > -   *timestamp = st.st_mtim.tv_sec;
> > > -   return true;
> > > -}
> > > -
> > > -static bool
> > > -anv_device_get_cache_uuid(void *uuid)
> > > -{
> > > -   uint32_t timestamp;
> > > -
> > > -   memset(uuid, 0, VK_UUID_SIZE);
> > > -   if (!anv_get_function_timestamp(anv_device_get_cache_uuid, 
> > > ))
> > > +   unsigned char *build_id = malloc(len);
> > > +   if (!build_id)
> > >return false;
> > >  
> > > -   snprintf(uuid, VK_UUID_SIZE, "anv-%d", timestamp);
> > > +   build_id_read(note, build_id);
> > > +
> > > +   memcpy(uuid, build_id, VK_UUID_SIZE);
> > > +   free(build_id);
> > 
> > The Vulkan spec frowns on memory allocations when not needed. If you
> > must allocate memory here, then it should be through the VkInstance
> > allocation callbacks. However, it's best to avoid the allocation by
> > adding a size_t parameter, à la snprintf, to build_id_read().
> > 
> > Otherwise, the patch looks good to me.
> 
> You're worried about the performance of anv_physical_device_init()?
> This doesn't happen on lookup...just driver start up...

I'm not worried about performance here. That would be foolish.

I'm concerned about complying the expectations provided to advanced
users by the Vulkan spec. Anvil has a good record of meeting those
expectations so far. There are exactly 4 calls to malloc in
src/intel/vulkan and, arguably, there should be only 2.

$ git grep malloc src/intel/vulkan

# correct and needed
anv_device.c:   return malloc(size);

# ok. this is debug code
anv_dump.c:   uint8_t *row = malloc(image->extent.width * 3);

# we should fix these
anv_pipeline.c:  spec_entries = malloc(num_spec_entries * 
sizeof(*spec_entries));
anv_pipeline.c: malloc(prog_data->nr_params * sizeof(union 
gl_constant_value *));
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Re: [Mesa-dev] [PATCH 32/32] r600/radeonsi: enable glsl/tgsi on-disk cache

[Timothy Arceri]

On 15/02/17 02:14, Marek Olšák wrote:


On Tue, Feb 14, 2017 at 1:52 AM, Timothy Arceri  wrote:

---
  src/gallium/drivers/r600/r600_pipe.c  | 10 ++
  src/gallium/drivers/radeon/r600_pipe_common.c |  2 +-
  src/gallium/drivers/radeon/r600_pipe_common.h |  1 +
  src/gallium/drivers/radeonsi/si_pipe.c| 11 +++
  src/gallium/include/pipe/p_screen.h   |  3 +++
  src/mesa/state_tracker/st_context.c   |  2 ++
  6 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 5290f40..bdd8c0a 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -600,6 +600,7 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
 compute_memory_pool_delete(rscreen->global_pool);
 }

+   disk_cache_destroy(rscreen->b.b.disk_shader_cache);
 r600_destroy_common_screen(>b);
  }

@@ -633,6 +634,15 @@ struct pipe_screen *r600_screen_create(struct 
radeon_winsys *ws)
 return NULL;
 }

+   uint32_t mesa_timestamp;
+   if (disk_cache_get_function_timestamp(r600_screen_create, 
_timestamp)) {
+   char *timestamp_str;
+   if (asprintf(_str, "%u", mesa_timestamp) != -1) {
+   rscreen->b.b.disk_shader_cache = 
disk_cache_create(r600_get_chip_name(>b), timestamp_str);
+   free(timestamp_str);
+   }
+   }
+
 if (rscreen->b.info.chip_class >= EVERGREEN) {
 rscreen->b.b.is_format_supported = 
evergreen_is_format_supported;
 } else {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 95a6a48..4e5582f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -722,7 +722,7 @@ static const char* r600_get_device_vendor(struct 
pipe_screen* pscreen)
 return "AMD";
  }

-static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
+const char* r600_get_chip_name(struct r600_common_screen *rscreen)
  {
 switch (rscreen->info.family) {
 case CHIP_R600: return "AMD R600";
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 6eff9aa..0449d4d 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -765,6 +765,7 @@ void radeon_save_cs(struct radeon_winsys *ws, struct 
radeon_winsys_cs *cs,
 struct radeon_saved_cs *saved);
  void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
  bool r600_check_device_reset(struct r600_common_context *rctx);
+const char* r600_get_chip_name(struct r600_common_screen *rscreen);

  /* r600_gpu_load.c */
  void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 853d850..0bb95b1 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -712,6 +712,7 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 }
 }
 pipe_mutex_destroy(sscreen->shader_parts_mutex);
+   disk_cache_destroy(sscreen->b.b.disk_shader_cache);
 si_destroy_shader_cache(sscreen);
 r600_destroy_common_screen(>b);
  }
@@ -801,6 +802,16 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws)
 return NULL;
 }

+   uint32_t mesa_timestamp, llvm_timestamp;
+   if (disk_cache_get_function_timestamp(radeonsi_screen_create, _timestamp) 
&&
+   disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, 
_timestamp)) {
+   char *timestamp_str;
+   if (asprintf(_str, "%u_%u", mesa_timestamp, 
llvm_timestamp) != -1) {
+   sscreen->b.b.disk_shader_cache = 
disk_cache_create(r600_get_chip_name(>b), timestamp_str);

Can you please at least make some effort to get close to 80 chars per
line even though it's not strictly required in this driver?


+   free(timestamp_str);
+   }
+   }
+
 si_handle_env_var_force_family(sscreen);

 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
diff --git a/src/gallium/include/pipe/p_screen.h 
b/src/gallium/include/pipe/p_screen.h
index b6203f1..6fd527f 100644
--- a/src/gallium/include/pipe/p_screen.h
+++ b/src/gallium/include/pipe/p_screen.h
@@ -42,6 +42,7 @@
  #include "pipe/p_format.h"
  #include "pipe/p_defines.h"
  #include "pipe/p_video_enums.h"
+#include "util/disk_cache.h"



@@ -318,6 +319,8 @@ struct pipe_screen {
 const void *(*get_compiler_options)(struct pipe_screen *screen,
enum pipe_shader_ir ir,

Re: [Mesa-dev] [PATCH 2/2] anv: Use build-id for pipeline cache UUID.

[Kenneth Graunke]

On Tuesday, February 14, 2017 12:38:45 PM PST Chad Versace wrote:
> On Tue 14 Feb 2017, Matt Turner wrote:
> 
> 
> >  static bool
> > -anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
> > +anv_device_get_cache_uuid(void *uuid)
> >  {
> > -   Dl_info info;
> > -   struct stat st;
> > -   if (!dladdr(ptr, ) || !info.dli_fname)
> > +   const struct note *note = build_id_find_nhdr("libvulkan_intel.so");
> > +   if (!note)
> >return false;
> >  
> > -   if (stat(info.dli_fname, ))
> > +   unsigned len = build_id_length(note);
> > +   if (len < VK_UUID_SIZE)
> >return false;
> >  
> > -   *timestamp = st.st_mtim.tv_sec;
> > -   return true;
> > -}
> > -
> > -static bool
> > -anv_device_get_cache_uuid(void *uuid)
> > -{
> > -   uint32_t timestamp;
> > -
> > -   memset(uuid, 0, VK_UUID_SIZE);
> > -   if (!anv_get_function_timestamp(anv_device_get_cache_uuid, ))
> > +   unsigned char *build_id = malloc(len);
> > +   if (!build_id)
> >return false;
> >  
> > -   snprintf(uuid, VK_UUID_SIZE, "anv-%d", timestamp);
> > +   build_id_read(note, build_id);
> > +
> > +   memcpy(uuid, build_id, VK_UUID_SIZE);
> > +   free(build_id);
> 
> The Vulkan spec frowns on memory allocations when not needed. If you
> must allocate memory here, then it should be through the VkInstance
> allocation callbacks. However, it's best to avoid the allocation by
> adding a size_t parameter, à la snprintf, to build_id_read().
> 
> Otherwise, the patch looks good to me.

You're worried about the performance of anv_physical_device_init()?
This doesn't happen on lookup...just driver start up...

--Ken


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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Nicholas Miell]

On 02/14/2017 12:30 PM, Chad Versace wrote:

On Tue 14 Feb 2017, Matt Turner wrote:

Provides the ability to read the .note.gnu.build-id section of ELF
binaries, which is inserted by the --build-id=... flag to ld.
---
 configure.ac  |   2 +
 src/util/Makefile.sources |   2 +
 src/util/build_id.c   | 109 ++
 src/util/build_id.h   |  56 
 4 files changed, 169 insertions(+)
 create mode 100644 src/util/build_id.c
 create mode 100644 src/util/build_id.h




+AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES -DHAVE_DL_ITERATE_PHDR"])


Nice. I wasn't aware of dl_iterate_phdr(). My code for querying the
build-id was less slick. It used open(2) on the library, then manually
parsed the ElfW(Ehdr) and ElfW(Shdr) to find the build-id node.


I also reinvented the build ID lookup wheel and just to record this 
knowledge publicly for posterity:


The struct link_map l_addr field seems to corresponds to the struct 
dl_phdr_info dlpi_addr field.


You can retrieve the struct link_map for a symbol by passing the 
RTLD_DL_LINKMAP flag to dladdr1() or for a library handle returned by 
dlopen() by passing RTLD_DI_LINKMAP to dlinfo().


This means you can find the note section for a loaded library directly 
without having to resort to string comparisons against library names, 
which is probably more future-proof.

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Re: [Mesa-dev] [PATCH 2/2] anv: Use build-id for pipeline cache UUID.

[Chad Versace]

On Tue 14 Feb 2017, Matt Turner wrote:


>  static bool
> -anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
> +anv_device_get_cache_uuid(void *uuid)
>  {
> -   Dl_info info;
> -   struct stat st;
> -   if (!dladdr(ptr, ) || !info.dli_fname)
> +   const struct note *note = build_id_find_nhdr("libvulkan_intel.so");
> +   if (!note)
>return false;
>  
> -   if (stat(info.dli_fname, ))
> +   unsigned len = build_id_length(note);
> +   if (len < VK_UUID_SIZE)
>return false;
>  
> -   *timestamp = st.st_mtim.tv_sec;
> -   return true;
> -}
> -
> -static bool
> -anv_device_get_cache_uuid(void *uuid)
> -{
> -   uint32_t timestamp;
> -
> -   memset(uuid, 0, VK_UUID_SIZE);
> -   if (!anv_get_function_timestamp(anv_device_get_cache_uuid, ))
> +   unsigned char *build_id = malloc(len);
> +   if (!build_id)
>return false;
>  
> -   snprintf(uuid, VK_UUID_SIZE, "anv-%d", timestamp);
> +   build_id_read(note, build_id);
> +
> +   memcpy(uuid, build_id, VK_UUID_SIZE);
> +   free(build_id);

The Vulkan spec frowns on memory allocations when not needed. If you
must allocate memory here, then it should be through the VkInstance
allocation callbacks. However, it's best to avoid the allocation by
adding a size_t parameter, à la snprintf, to build_id_read().

Otherwise, the patch looks good to me.

> return true;
>  }
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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Chad Versace]

On Tue 14 Feb 2017, Matt Turner wrote:
> Provides the ability to read the .note.gnu.build-id section of ELF
> binaries, which is inserted by the --build-id=... flag to ld.
> ---
>  configure.ac  |   2 +
>  src/util/Makefile.sources |   2 +
>  src/util/build_id.c   | 109 
> ++
>  src/util/build_id.h   |  56 
>  4 files changed, 169 insertions(+)
>  create mode 100644 src/util/build_id.c
>  create mode 100644 src/util/build_id.h


> +AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES -DHAVE_DL_ITERATE_PHDR"])

Nice. I wasn't aware of dl_iterate_phdr(). My code for querying the
build-id was less slick. It used open(2) on the library, then manually
parsed the ElfW(Ehdr) and ElfW(Shdr) to find the build-id node.


> diff --git a/src/util/build_id.c b/src/util/build_id.c
> new file mode 100644
> index 000..a2e21b7
> --- /dev/null
> +++ b/src/util/build_id.c


> +#define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
> +
> +struct note {
> +   ElfW(Nhdr) nhdr;
> +
> +   char name[4];

Because nothing requires ElfW(Nhdr).n_namesz to be 4, please a comment
here explaining that we hardcoded 4 because the note name is "GNU".

> +   uint8_t build_id[0];
> +};
> +
> +struct callback_data {
> +   const char *name;
> +   struct note *note;
> +};
> +
> +static int
> +build_id_find_nhdr_callback(struct dl_phdr_info *info, size_t size, void 
> *data_)
> +{

This function looks correct to me.

> +   struct callback_data *data = data_;
> +
> +   char *ptr = strstr(info->dlpi_name, data->name);
> +   if (ptr == NULL || ptr[strlen(data->name)] != '\0')
> +  return 0;
> +
> +   for (unsigned i = 0; i < info->dlpi_phnum; i++) {
> +  if (info->dlpi_phdr[i].p_type != PT_NOTE)
> + continue;
> +
> +  struct note *note = (void *)(info->dlpi_addr +
> +   info->dlpi_phdr[i].p_vaddr);

> +  ptrdiff_t len = info->dlpi_phdr[i].p_filesz;

I was initially worried that the len should use p_memsz instead of
p_filesz. But the elf manpage says it's ok; if p_memsz > p_filesz, then
the excess bytes are mere padding.

> +
> +  while (len >= sizeof(struct note)) {
> + if (note->nhdr.n_type == NT_GNU_BUILD_ID &&
> +note->nhdr.n_descsz != 0 &&
> +note->nhdr.n_namesz == 4 &&
> +memcmp(note->name, "GNU", 4) == 0) {
> +data->note = note;
> +return 1;
> + }
> +
> + size_t offset = sizeof(ElfW(Nhdr)) +
> + ALIGN(note->nhdr.n_namesz, 4) +
> + ALIGN(note->nhdr.n_descsz, 4);
> + note = (struct note *)((char *)note + offset);
> + len -= offset;
> +  }
> +   }
> +
> +   return 0;
> +}
> +
> +const struct note *
> +build_id_find_nhdr(const char *name)

Please rename the 'name' parameter to be clearer. I was confused,
thinking that name was the name of ELF section for the note. It wasn't
until I read patch 2, and saw name="libvulkan.so" instead
name=".note.gnu.build-id" that I was able to understand this patch.

> +{
> +   struct callback_data data = {
> +  .name = name,
> +  .note = NULL,
> +   };
> +
> +   if (dl_iterate_phdr(build_id_find_nhdr_callback, )) {
> +  return data.note;
> +   } else {
> +  return NULL;
> +   }
> +}
> +
> +unsigned
> +build_id_length(const struct note *note)
> +{
> +   return note->nhdr.n_descsz;
> +}
> +
> +void
> +build_id_read(const struct note *note, unsigned char *build_id)
> +{

As I explain in patch 2, I think this function needs a 'size' parameter,
à la snprintf, due to Vulkan weirdness regarding restrictons on usage of
malloc.

> +   memcpy(build_id, note->build_id, note->nhdr.n_descsz);
> +}

> diff --git a/src/util/build_id.h b/src/util/build_id.h
> new file mode 100644
> index 000..0eaecf9
> --- /dev/null
> +++ b/src/util/build_id.h


> +struct note;

Please namespace struct note. Please :)

My only hard request is the size_t parameter for build_id_read(). My
other comments are just minor nits, that you can ignore.
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Re: [Mesa-dev] [PATCH] anv/entrypoints: Only generate entrypoints for supported features

[Jason Ekstrand]

On Feb 14, 2017 11:13 AM, "Emil Velikov"  wrote:

On 14 February 2017 at 18:26, Jason Ekstrand  wrote:
> This changes the way anv_entrypoints_gen.py works from generating a
> table containing every single entrypoint in the XML to just the ones
> that we actually need.  There's no reason for us to burn entrypoint
> table space on a bunch of NV extensions we never plan to implement.

JFYI: Tapani mentioned that the conversion to XML 'magically' got
things working on Android-ia.
Might be worth checking if the latter requires (and/or uses ?) some
other extensions/entry points.


I have no idea what's going on with android.  If they need another
entrypoint or two, it should be easy enough to AF them to the whitelist.
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Re: [Mesa-dev] [PATCH] radv: fixup IA_MULTI_VGT_PARAM handling.

[Bas Nieuwenhuizen]

On Tue, Feb 14, 2017, at 21:03, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This ports the remains of the workarounds from radeonsi for
> the non-TESS cases. It should provide equivalent workarounds
> for hawaii and bonarie.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 23 +++-
>  src/amd/vulkan/radv_pipeline.c   | 22 +++-
>  src/amd/vulkan/radv_private.h| 12 +--
>  src/amd/vulkan/si_cmd_buffer.c   | 78
>  +---
>  4 files changed, 104 insertions(+), 31 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 8f2e984..19d9ef8 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1267,7 +1267,7 @@ radv_flush_constants(struct radv_cmd_buffer
> *cmd_buffer,
>  }
>  
>  static void
> -radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
> +radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool
> instanced_or_indirect_draw, uint32_t count)
>  {

Rename count to vertex_count or something that at least tells what it
counts. With that

Reviewed-by: Bas Nieuwenhuizen 

>   struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
>   struct radv_device *device = cmd_buffer->device;
> @@ -1332,6 +1332,15 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer
> *cmd_buffer)
>   if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
>   radv_emit_scissor(cmd_buffer);
>  
> +   ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer,
> instanced_or_indirect_draw, count);
> +   if (cmd_buffer->state.last_ia_multi_vgt_param !=
> ia_multi_vgt_param) {
> +   if
> (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
> +   radeon_set_context_reg_idx(cmd_buffer->cs,
> R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
> +   else
> +   radeon_set_context_reg(cmd_buffer->cs,
> R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
> +   cmd_buffer->state.last_ia_multi_vgt_param =
> ia_multi_vgt_param;
> +   }
> +
>   if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
>   uint32_t stages = 0;
>  
> @@ -1341,15 +1350,12 @@ radv_cmd_buffer_flush_state(struct
> radv_cmd_buffer *cmd_buffer)
>   S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
>  
>   radeon_set_context_reg(cmd_buffer->cs, 
> R_028B54_VGT_SHADER_STAGES_EN, stages);
> -   ia_multi_vgt_param =
> si_get_ia_multi_vgt_param(cmd_buffer);
>  
>   if (cmd_buffer->device->physical_device->rad_info.chip_class >= 
> CIK) {
> -   radeon_set_context_reg_idx(cmd_buffer->cs,
> R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
>   radeon_set_context_reg_idx(cmd_buffer->cs, 
> R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
>   radeon_set_uconfig_reg_idx(cmd_buffer->cs, 
> R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
>   } else {
>   radeon_set_config_reg(cmd_buffer->cs, 
> R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
> -   radeon_set_context_reg(cmd_buffer->cs,
> R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
>   radeon_set_context_reg(cmd_buffer->cs, 
> R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
>   }
>   radeon_set_context_reg(cmd_buffer->cs, 
> R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
> @@ -2188,7 +2194,8 @@ void radv_CmdDraw(
>   uint32_tfirstInstance)
>  {
>   RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
> -   radv_cmd_buffer_flush_state(cmd_buffer);
> +
> +   radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1),
> vertexCount);
>  
>   MAYBE_UNUSED unsigned cdw_max = 
> radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
>  
> @@ -2239,7 +2246,7 @@ void radv_CmdDrawIndexed(
>   uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - 
> cmd_buffer->state.index_offset) / index_size;
>   uint64_t index_va;
>  
> -   radv_cmd_buffer_flush_state(cmd_buffer);
> +   radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1),
> indexCount);
>   radv_emit_primitive_reset_index(cmd_buffer);
>  
>   MAYBE_UNUSED unsigned cdw_max = 
> radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
> @@ -2337,7 +2344,7 @@ radv_cmd_draw_indirect_count(VkCommandBuffer   
>  command
>   uint32_t   
>   stride)
>  {
>   RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
> -   

[Mesa-dev] [PATCH] radv: fixup IA_MULTI_VGT_PARAM handling.

[Dave Airlie]

From: Dave Airlie 

This ports the remains of the workarounds from radeonsi for
the non-TESS cases. It should provide equivalent workarounds
for hawaii and bonarie.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 23 +++-
 src/amd/vulkan/radv_pipeline.c   | 22 +++-
 src/amd/vulkan/radv_private.h| 12 +--
 src/amd/vulkan/si_cmd_buffer.c   | 78 +---
 4 files changed, 104 insertions(+), 31 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8f2e984..19d9ef8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1267,7 +1267,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
 }
 
 static void
-radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
+radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool 
instanced_or_indirect_draw, uint32_t count)
 {
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
struct radv_device *device = cmd_buffer->device;
@@ -1332,6 +1332,15 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer 
*cmd_buffer)
if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
radv_emit_scissor(cmd_buffer);
 
+   ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, 
instanced_or_indirect_draw, count);
+   if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
+   if (cmd_buffer->device->physical_device->rad_info.chip_class >= 
CIK)
+   radeon_set_context_reg_idx(cmd_buffer->cs, 
R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
+   else
+   radeon_set_context_reg(cmd_buffer->cs, 
R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
+   cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
+   }
+
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
uint32_t stages = 0;
 
@@ -1341,15 +1350,12 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer 
*cmd_buffer)
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
 
radeon_set_context_reg(cmd_buffer->cs, 
R_028B54_VGT_SHADER_STAGES_EN, stages);
-   ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
 
if (cmd_buffer->device->physical_device->rad_info.chip_class >= 
CIK) {
-   radeon_set_context_reg_idx(cmd_buffer->cs, 
R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
radeon_set_context_reg_idx(cmd_buffer->cs, 
R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
radeon_set_uconfig_reg_idx(cmd_buffer->cs, 
R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
} else {
radeon_set_config_reg(cmd_buffer->cs, 
R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
-   radeon_set_context_reg(cmd_buffer->cs, 
R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
radeon_set_context_reg(cmd_buffer->cs, 
R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
}
radeon_set_context_reg(cmd_buffer->cs, 
R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
@@ -2188,7 +2194,8 @@ void radv_CmdDraw(
uint32_tfirstInstance)
 {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
-   radv_cmd_buffer_flush_state(cmd_buffer);
+
+   radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), 
vertexCount);
 
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
 
@@ -2239,7 +2246,7 @@ void radv_CmdDrawIndexed(
uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - 
cmd_buffer->state.index_offset) / index_size;
uint64_t index_va;
 
-   radv_cmd_buffer_flush_state(cmd_buffer);
+   radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), 
indexCount);
radv_emit_primitive_reset_index(cmd_buffer);
 
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
@@ -2337,7 +2344,7 @@ radv_cmd_draw_indirect_count(VkCommandBuffer  
   command
  uint32_t
stride)
 {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
-   radv_cmd_buffer_flush_state(cmd_buffer);
+   radv_cmd_buffer_flush_state(cmd_buffer, true, 0);
 
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws,
   cmd_buffer->cs, 14);
@@ -2362,7 +2369,7 @@ radv_cmd_draw_indexed_indirect_count(
int index_size = cmd_buffer->state.index_type ? 4 : 2;
uint32_t index_max_size = 

Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

On Tue, Feb 14, 2017 at 11:39 AM, Kristian H. Kristensen
 wrote:
> Matt Turner  writes:
>> diff --git a/src/util/build_id.c b/src/util/build_id.c
>> new file mode 100644
>> index 000..a2e21b7
>> --- /dev/null
>> +++ b/src/util/build_id.c
>> @@ -0,0 +1,109 @@
>> +/*
>> + * Copyright © 2016 Intel Corporation
>
> I don't like it either, but we're in 2017 now.

Heh. I actually did write it in 2016.
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Re: [Mesa-dev] [PATCH v2 1/4] driconf: add allow_higher_compat_version option

[Edmondo Tommasina]

This series is
Reviewed-by: Edmondo Tommasina 

Thanks
edmondo

On Tue, Feb 14, 2017 at 4:18 PM, Samuel Pitoiset
 wrote:
> Mesa currently doesn't allow to create 3.1+ compatibility profiles
> mainly because various features are unimplemented and bugs can
> happen.
>
> However, some buggy apps request a compat profile without using
> any old features unimplemented in mesa, and they fail to start.
>
> This option should help some games to run but it's not enough
> for all (eg. Dying Ligth).
>
> v2: - s/force_compat_profile/allow_higher_compat_version
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/include/state_tracker/st_api.h  | 1 +
>  src/gallium/state_trackers/dri/dri_screen.c | 3 +++
>  src/mesa/drivers/dri/common/xmlpool/t_options.h | 5 +
>  src/mesa/drivers/dri/i965/brw_context.c | 3 +++
>  src/mesa/main/mtypes.h  | 7 +++
>  src/mesa/main/version.c | 6 --
>  src/mesa/state_tracker/st_extensions.c  | 2 ++
>  7 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/include/state_tracker/st_api.h 
> b/src/gallium/include/state_tracker/st_api.h
> index a2e37d2e48..1b9ef290b1 100644
> --- a/src/gallium/include/state_tracker/st_api.h
> +++ b/src/gallium/include/state_tracker/st_api.h
> @@ -245,6 +245,7 @@ struct st_config_options
> unsigned force_glsl_version;
> boolean force_s3tc_enable;
> boolean allow_glsl_extension_directive_midshader;
> +   boolean allow_higher_compat_version;
> boolean glsl_zero_init;
>  };
>
> diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
> b/src/gallium/state_trackers/dri/dri_screen.c
> index a950f5241d..1e278c3d1c 100644
> --- a/src/gallium/state_trackers/dri/dri_screen.c
> +++ b/src/gallium/state_trackers/dri/dri_screen.c
> @@ -70,6 +70,7 @@ const __DRIconfigOptionsExtension gallium_config_options = {
>   DRI_CONF_DISABLE_SHADER_BIT_ENCODING("false")
>   DRI_CONF_FORCE_GLSL_VERSION(0)
>   DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
> + DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
>DRI_CONF_SECTION_END
>
>DRI_CONF_SECTION_MISCELLANEOUS
> @@ -99,6 +100,8 @@ dri_fill_st_options(struct st_config_options *options,
>driQueryOptionb(optionCache, "force_s3tc_enable");
> options->allow_glsl_extension_directive_midshader =
>driQueryOptionb(optionCache, 
> "allow_glsl_extension_directive_midshader");
> +   options->allow_higher_compat_version =
> +  driQueryOptionb(optionCache, "allow_higher_compat_version");
> options->glsl_zero_init = driQueryOptionb(optionCache, "glsl_zero_init");
>  }
>
> diff --git a/src/mesa/drivers/dri/common/xmlpool/t_options.h 
> b/src/mesa/drivers/dri/common/xmlpool/t_options.h
> index a189bbedec..f200093177 100644
> --- a/src/mesa/drivers/dri/common/xmlpool/t_options.h
> +++ b/src/mesa/drivers/dri/common/xmlpool/t_options.h
> @@ -115,6 +115,11 @@ 
> DRI_CONF_OPT_BEGIN_B(allow_glsl_extension_directive_midshader, def) \
>  DRI_CONF_DESC(en,gettext("Allow GLSL #extension directives in the 
> middle of shaders")) \
>  DRI_CONF_OPT_END
>
> +#define DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(def) \
> +DRI_CONF_OPT_BEGIN_B(allow_higher_compat_version, def) \
> +DRI_CONF_DESC(en,gettext("Allow a higher compat profile (version 
> 3.1+) for apps that request it")) \
> +DRI_CONF_OPT_END
> +
>
>
>  /**
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 7240b1f445..c56a14e3d6 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -916,6 +916,9 @@ brw_process_driconf_options(struct brw_context *brw)
> ctx->Const.AllowGLSLExtensionDirectiveMidShader =
>driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
>
> +   ctx->Const.AllowHigherCompatVersion =
> +  driQueryOptionb(options, "allow_higher_compat_version");
> +
> ctx->Const.GLSLZeroInit = driQueryOptionb(options, "glsl_zero_init");
>
> brw->dual_color_blend_by_location =
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index a845a394c8..08bd929255 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -3501,6 +3501,13 @@ struct gl_constants
> GLboolean AllowGLSLExtensionDirectiveMidShader;
>
> /**
> +* Allow creating a higher compat profile (version 3.1+) for apps that
> +* request it. Be careful when adding that driconf option because some
> +* features are unimplemented and might not work correctly.
> +*/
> +   GLboolean AllowHigherCompatVersion;
> +
> +   /**
>  * Force uninitialized variables to default to zero.
>  */
> GLboolean GLSLZeroInit;
> diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
> index 85ec9de612..3d54d21a04 100644
> --- a/src/mesa/main/version.c
> +++ 

Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Kristian H. Kristensen]

Matt Turner  writes:

> Provides the ability to read the .note.gnu.build-id section of ELF
> binaries, which is inserted by the --build-id=... flag to ld.
> ---
>  configure.ac  |   2 +
>  src/util/Makefile.sources |   2 +
>  src/util/build_id.c   | 109 
> ++
>  src/util/build_id.h   |  56 
>  4 files changed, 169 insertions(+)
>  create mode 100644 src/util/build_id.c
>  create mode 100644 src/util/build_id.h
>
> diff --git a/configure.ac b/configure.ac
> index f001743..99c74f0 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -768,6 +768,8 @@ LIBS="$LIBS $DLOPEN_LIBS"
>  AC_CHECK_FUNCS([dladdr])
>  LIBS="$save_LIBS"
>  
> +AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES -DHAVE_DL_ITERATE_PHDR"])
> +
>  case "$host_os" in
>  darwin*)
>  ;;
> diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
> index a68a5fe..4c12e5f 100644
> --- a/src/util/Makefile.sources
> +++ b/src/util/Makefile.sources
> @@ -2,6 +2,8 @@ MESA_UTIL_FILES :=\
>   bitscan.c \
>   bitscan.h \
>   bitset.h \
> + build_id.c \
> + build_id.h \
>   crc32.c \
>   crc32.h \
>   debug.c \
> diff --git a/src/util/build_id.c b/src/util/build_id.c
> new file mode 100644
> index 000..a2e21b7
> --- /dev/null
> +++ b/src/util/build_id.c
> @@ -0,0 +1,109 @@
> +/*
> + * Copyright © 2016 Intel Corporation

I don't like it either, but we're in 2017 now.

Kristian

> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifdef HAVE_DL_ITERATE_PHDR
> +#include 
> +#include 
> +#include 
> +
> +#include "build_id.h"
> +
> +#define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
> +
> +struct note {
> +   ElfW(Nhdr) nhdr;
> +
> +   char name[4];
> +   uint8_t build_id[0];
> +};
> +
> +struct callback_data {
> +   const char *name;
> +   struct note *note;
> +};
> +
> +static int
> +build_id_find_nhdr_callback(struct dl_phdr_info *info, size_t size, void 
> *data_)
> +{
> +   struct callback_data *data = data_;
> +
> +   char *ptr = strstr(info->dlpi_name, data->name);
> +   if (ptr == NULL || ptr[strlen(data->name)] != '\0')
> +  return 0;
> +
> +   for (unsigned i = 0; i < info->dlpi_phnum; i++) {
> +  if (info->dlpi_phdr[i].p_type != PT_NOTE)
> + continue;
> +
> +  struct note *note = (void *)(info->dlpi_addr +
> +   info->dlpi_phdr[i].p_vaddr);
> +  ptrdiff_t len = info->dlpi_phdr[i].p_filesz;
> +
> +  while (len >= sizeof(struct note)) {
> + if (note->nhdr.n_type == NT_GNU_BUILD_ID &&
> +note->nhdr.n_descsz != 0 &&
> +note->nhdr.n_namesz == 4 &&
> +memcmp(note->name, "GNU", 4) == 0) {
> +data->note = note;
> +return 1;
> + }
> +
> + size_t offset = sizeof(ElfW(Nhdr)) +
> + ALIGN(note->nhdr.n_namesz, 4) +
> + ALIGN(note->nhdr.n_descsz, 4);
> + note = (struct note *)((char *)note + offset);
> + len -= offset;
> +  }
> +   }
> +
> +   return 0;
> +}
> +
> +const struct note *
> +build_id_find_nhdr(const char *name)
> +{
> +   struct callback_data data = {
> +  .name = name,
> +  .note = NULL,
> +   };
> +
> +   if (dl_iterate_phdr(build_id_find_nhdr_callback, )) {
> +  return data.note;
> +   } else {
> +  return NULL;
> +   }
> +}
> +
> +unsigned
> +build_id_length(const struct note *note)
> +{
> +   return note->nhdr.n_descsz;
> +}
> +
> +void
> +build_id_read(const struct note *note, unsigned char *build_id)
> +{
> +   memcpy(build_id, note->build_id, note->nhdr.n_descsz);
> +}
> +
> +#endif
> diff --git a/src/util/build_id.h b/src/util/build_id.h
> new file mode 100644
> index 000..0eaecf9
> --- /dev/null
> +++ b/src/util/build_id.h

Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Chad Versace]

On Tue 14 Feb 2017, Matt Turner wrote:
> Provides the ability to read the .note.gnu.build-id section of ELF
> binaries, which is inserted by the --build-id=... flag to ld.

Heh. Sunday night I wrote a prototype of this myself. I'm strongly in
favor of basing Vulkan unique id's on the ELF build-id instead of the
past and current approaches we've used.

Still reviewing the patch...

> ---
>  configure.ac  |   2 +
>  src/util/Makefile.sources |   2 +
>  src/util/build_id.c   | 109 
> ++
>  src/util/build_id.h   |  56 
>  4 files changed, 169 insertions(+)
>  create mode 100644 src/util/build_id.c
>  create mode 100644 src/util/build_id.h
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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Chad Versace]

On Tue 14 Feb 2017, Matt Turner wrote:
> On Tue, Feb 14, 2017 at 11:21 AM, Matt Turner  wrote:
> > On Tue, Feb 14, 2017 at 11:18 AM, Matt Turner  wrote:
> >> On Tue, Feb 14, 2017 at 10:59 AM, Jason Ekstrand  
> >> wrote:
> >>> I'm not sure how I feel about the silent fall-backs.  At least in the 
> >>> Vulkan
> >>> driver, we should fail to compile if we can't get build-id.  Otherwise,
> >>> you'll end up compiling a driver that will always fail device creation.
> >>
> >> That was really an attempt to preempt questions about Windows.
> >>
> >> I am happy to drop it.
> >
> > Think-o. No, it's necessary for systems that don't have
> > dl_iterate_phdr (Windows, AFAIK).
> 
> I promise I'll stop replying to myself after this...
> 
> I guess dropping the fallback and simply wrapping build_id.c in
> HAVE_DL_ITERATE_PHDR is sufficient? Windows will build an empty source
> file, which is fine because no code should ever attempt to use it on
> Windows; and there would be no chance of the Vulkan driver calling
> (non-existent) fallback code.

I'm in favor of dropping the fallback stubs.
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[Mesa-dev] [Bug 99692] [radv] Mostly broken on Hawaii PRO/CIK ASICs

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99692

--- Comment #15 from Jan Ziak <0xe2.0x9a.0...@gmail.com> ---
(In reply to Kai from comment #12)
> (In reply to Jan Ziak from comment #11)
> > Is LLVM-5.0-devel required? I am using LLVM-4.0.0_rc1 and even vulkaninfo is
> > terminating with an assertion error.
> 
> Not to my knowledge and not intentionally I would venture to say, otherwise
> proposed changes including different behaviour depending on whether you have
> LLVM < 4.0.0 or not wouldn't make too much sense. Or it could just be a
> broken assertion somewhere? My non-asserting build here works now.

llvm-git works without issues.

> In any case your issue looks like a different problem from what this bug
> was/is about (graphical corruption and VM faults with radv and CIK ASICS),
> please file a separate report for it.

It is true that it was a problem different from this bug.



Back to this bug:

Dota2 -vulkan (observer mode) is working without issues on my R9-390.

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[Mesa-dev] [Bug 99692] [radv] Mostly broken on Hawaii PRO/CIK ASICs

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99692

--- Comment #14 from Bas Nieuwenhuizen  ---
(In reply to Jan Ziak from comment #11)
> (In reply to Kai from comment #9)
> > The full stack I used was(Debian testing as a base) is:
> > GPU: Hawaii PRO [Radeon R9 290] (ChipID = 0x67b1)
> > Mesa: Git:master/956556b3c3 + attachment 127922 [details] [review] [review] 
> > (bug
> > 97988),  (see bug 99542)
> > and 
> > libdrm: Git:master/d4b8344363 (tag libdrm-2.4.75)
> > LLVM: SVN:trunk/r294982 (5.0 devel) +
> >  (bug 97988)
> 
> Is LLVM-5.0-devel required? I am using LLVM-4.0.0_rc1 and even vulkaninfo is
> terminating with an assertion error.

If we detect 4.0, we use a patch that got backported to the 4.0 branch after
rc1, so you might need to use rc2+ or a svn version.

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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

On Tue, Feb 14, 2017 at 11:21 AM, Matt Turner  wrote:
> On Tue, Feb 14, 2017 at 11:18 AM, Matt Turner  wrote:
>> On Tue, Feb 14, 2017 at 10:59 AM, Jason Ekstrand  
>> wrote:
>>> I'm not sure how I feel about the silent fall-backs.  At least in the Vulkan
>>> driver, we should fail to compile if we can't get build-id.  Otherwise,
>>> you'll end up compiling a driver that will always fail device creation.
>>
>> That was really an attempt to preempt questions about Windows.
>>
>> I am happy to drop it.
>
> Think-o. No, it's necessary for systems that don't have
> dl_iterate_phdr (Windows, AFAIK).

I promise I'll stop replying to myself after this...

I guess dropping the fallback and simply wrapping build_id.c in
HAVE_DL_ITERATE_PHDR is sufficient? Windows will build an empty source
file, which is fine because no code should ever attempt to use it on
Windows; and there would be no chance of the Vulkan driver calling
(non-existent) fallback code.
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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

On Tue, Feb 14, 2017 at 11:18 AM, Matt Turner  wrote:
> On Tue, Feb 14, 2017 at 10:59 AM, Jason Ekstrand  wrote:
>> I'm not sure how I feel about the silent fall-backs.  At least in the Vulkan
>> driver, we should fail to compile if we can't get build-id.  Otherwise,
>> you'll end up compiling a driver that will always fail device creation.
>
> That was really an attempt to preempt questions about Windows.
>
> I am happy to drop it.

Think-o. No, it's necessary for systems that don't have
dl_iterate_phdr (Windows, AFAIK).
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Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

On Tue, Feb 14, 2017 at 10:59 AM, Jason Ekstrand  wrote:
> I'm not sure how I feel about the silent fall-backs.  At least in the Vulkan
> driver, we should fail to compile if we can't get build-id.  Otherwise,
> you'll end up compiling a driver that will always fail device creation.

That was really an attempt to preempt questions about Windows.

I am happy to drop it.
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Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] i965/fs: emit MOV_INDIRECT with the source with the right register type

[Francisco Jerez]

Samuel Iglesias Gonsálvez  writes:

> This was hiding bugs as it retyped the source to destination's type.
>
> Signed-off-by: Samuel Iglesias Gonsálvez 
> Cc: "17.0" 

Reviewed-by: Francisco Jerez 

> ---
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 26ffbb169d2..65c75e63d27 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -428,7 +428,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
>brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
>struct brw_reg ind_src = brw_VxH_indirect(0, 0);
>  
> -  brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
> +  brw_inst *mov = brw_MOV(p, dst, retype(ind_src, reg.type));
>  
>if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
>!inst->get_next()->is_tail_sentinel() &&
> -- 
> 2.11.0
>
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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965/fs: fix indirect load DF uniforms on BSW/BXT

[Francisco Jerez]

Samuel Iglesias Gonsálvez  writes:

> Previously we were emitting two MOV_INDIRECT instructions by calculating
> source's indirect offsets for each 32-bit half of a DF source. However,
> this is not needed as we can just emit two 32-bit MOV INDIRECT without
> doing that calculation.
>

Maybe mention here the main motivation for fixing this and nominating it
for stable: The lowered BSW/BXT indirect move instructions had incorrect
source types, which luckily wasn't causing incorrect assembly to be
generated due to the bug fixed in the next patch, but would have
confused the remaining back-end IR infrastructure due to the mismatch
between the IR source types and the emitted machine code.

> Signed-off-by: Samuel Iglesias Gonsálvez 
> Cc: "17.0" 
> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 23 ++-
>  1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 991c20fad62..8975940e10b 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -3878,31 +3878,28 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
> nir_intrinsic_instr *instr
>   unsigned read_size = instr->const_index[1] -
>  (instr->num_components - 1) * type_sz(dest.type);
>  
> - fs_reg indirect_chv_high_32bit;
> - bool is_chv_bxt_64bit =
> -(devinfo->is_cherryview || devinfo->is_broxton) &&
> -type_sz(dest.type) == 8;
> - if (is_chv_bxt_64bit) {
> -indirect_chv_high_32bit = vgrf(glsl_type::uint_type);
> -/* Calculate indirect address to read high 32 bits */
> -bld.ADD(indirect_chv_high_32bit, indirect, brw_imm_ud(4));
> - }
> + bool supports_64bit_indirects =
> +!devinfo->is_cherryview && !devinfo->is_broxton;
>  
>   for (unsigned j = 0; j < instr->num_components; j++) {
> -if (!is_chv_bxt_64bit) {
> +if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
> bld.emit(SHADER_OPCODE_MOV_INDIRECT,
>  offset(dest, bld, j), offset(src, bld, j),
>  indirect, brw_imm_ud(read_size));
>  } else {
> +   /* We are going to read 64-bit data in two 32-bit MOV 
> INDIRECTS,
> +* each one reading half of the data.
> +*/
> +   read_size /= 2;

I don't think this is right, data for both halves is interleaved so the
read size will be roughly the same as for the 64 bit indirect move.

> bld.emit(SHADER_OPCODE_MOV_INDIRECT,
>  subscript(offset(dest, bld, j), 
> BRW_REGISTER_TYPE_UD, 0),
> -offset(src, bld, j),
> +subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, 
> 0),
>  indirect, brw_imm_ud(read_size));
>  
> bld.emit(SHADER_OPCODE_MOV_INDIRECT,
>  subscript(offset(dest, bld, j), 
> BRW_REGISTER_TYPE_UD, 1),
> -offset(src, bld, j),
> -indirect_chv_high_32bit, brw_imm_ud(read_size));
> +subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, 
> 1),
> +indirect, brw_imm_ud(read_size));

Given that this makes both emit statements nearly identical except for
the 0/1 indices passed to subscript(), wouldn't it make sense to remove
one of them and wrap it in a loop?

>  }
>   }
>}
> -- 
> 2.11.0
>
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[Mesa-dev] [Bug 99692] [radv] Mostly broken on Hawaii PRO/CIK ASICs

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99692

Dave Airlie  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #13 from Dave Airlie  ---
fixes pushed, thanks for testing.

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Re: [Mesa-dev] [PATCH] anv/entrypoints: Only generate entrypoints for supported features

[Emil Velikov]

On 14 February 2017 at 18:26, Jason Ekstrand  wrote:
> This changes the way anv_entrypoints_gen.py works from generating a
> table containing every single entrypoint in the XML to just the ones
> that we actually need.  There's no reason for us to burn entrypoint
> table space on a bunch of NV extensions we never plan to implement.

JFYI: Tapani mentioned that the conversion to XML 'magically' got
things working on Android-ia.
Might be worth checking if the latter requires (and/or uses ?) some
other extensions/entry points.

-Emil
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Re: [Mesa-dev] [PATCH 4/6] docs: add hyperlink to the releasing documentation

[Emil Velikov]

On 14 February 2017 at 18:06, Eric Engestrom  wrote:
> On Monday, 2017-02-13 13:42:21 +, Emil Velikov wrote:
>> From: Emil Velikov 
>>
>
> I just noticed xlibdriver.html and versions.html are also missing from
> contents.html, if you want to add them as well :)
>
Latter is intentionally out since it's one big release notes for Mesa
versions 1.0..6.3.2 which became separate html files.

For the former I'm leaning towards 'letting it rest in piece',
figuratively of course.

-Emil
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Re: [Mesa-dev] features.txt & EXT_debug_label extension

[Ian Romanick]

On 02/10/2017 02:56 AM, Eero Tamminen wrote:
> Hi,
> 
> On 09.02.2017 19:30, Ian Romanick wrote:
>> On 02/09/2017 05:19 PM, Eero Tamminen wrote:
>>> When checking GL errors for "Unturned" (Steam top-20 Unity3D based
>>> game), I noticed that it uses functions from extension unsupported by
>>> Mesa, and missing from "features.txt":
>>> https://www.khronos.org/registry/OpenGL/extensions/EXT/EXT_debug_label.txt
>>>
> 
> -
> New Procedures and Functions
> 
> void LabelObjectEXT(enum type, uint object, sizei length,
> const char *label);
> void GetObjectLabelEXT(enum type, uint object, sizei bufSize,
> sizei *length, char *label);
> -
> 
>>> Could it be added to "features.txt" file?
>>
>> I thought the functionality of that extension was folded into some other
>> ARB (or KHR) extension... GL_KHR_debug, maybe?
> 
> Yes, that has similar functionality, and Mesa already supports it:
> https://www.khronos.org/registry/OpenGL/extensions/KHR/KHR_debug.txt
> 
> Just with different function names:
> 
> void ObjectLabel(enum identifier, uint name, sizei length,
> const char *label);
> 
> void GetObjectLabel(enum identifier, uint name, sizei bufSize,
> sizei *length, char *label);
> 
> As fairly new & commonly used Unity3D game and Apitrace both support the
> EXT versions, I think it makes sense add aliases also for the EXT variants.

I checked both extensions, and they're not "just" aliases.  The EXT adds
a single function with an enum to select the kind of object.  The KHR
adds a function per kind of object.  It would be easy enough to add, but
it seems more valuable to suggest the developer use the more broadly
supported extension. :)

>> It's also not the sort of thing that an app should use in release mode.
> 
> That (free-to-play) game is still in early access phase.  Maybe it helps
> developer getting more useful feedback from more techical users. :-)
> 
> 
> - Eero
> 
>>> PS. Apitrace already outputs those debug labels in the replay output,
>>> but I didn't check whether its GUI could also make use of them.

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Re: [Mesa-dev] [PATCH v2 7/7] anv: Implement the Skylake stencil PMA optimization

[Nanley Chery]

On Tue, Feb 14, 2017 at 10:53:37AM -0800, Jason Ekstrand wrote:
> On Tue, Feb 14, 2017 at 10:35 AM, Nanley Chery 
> wrote:
> 
> > On Mon, Feb 13, 2017 at 08:45:47PM -0800, Jason Ekstrand wrote:
> > > On Mon, Feb 13, 2017 at 6:13 PM, Jason Ekstrand 
> > > wrote:
> > >
> > > > On Mon, Feb 13, 2017 at 5:00 PM, Nanley Chery 
> > > > wrote:
> > > >
> > > >> On Fri, Feb 10, 2017 at 11:02:21AM -0800, Jason Ekstrand wrote:
> > > >> > This improves the performance of Dota 2 on my Sky Lake Skull Canyon
> > > >> > machine by about 2-3%.
> > > >> >
> > > >>
> > > >> This patch looks good. Could we compare our setup and testing in the
> > > >> office? I can't reproduce these numbers.
> > > >>
> > > >
> > > > I'll have to do more runs.  At the moment, I'm not seeing a large boost
> > > > but I'll get a larger sample size and see if it's visible.
> > > >
> > >
> > > I did a bunch more runs.  It looks like it helps somewhere between 0 and
> > > 1%.  Not as much as I saw earlier, but it's definitely non-negative.
> > >
> >
> > Although I've confirmed that the fix is enabled in Dota 2, I'm also not
> > seeing any major changes on my SKL GT4. I get positive and negative
> > changes in FPS, but it's all < 1% and seemingly noise.
> >
> > With the commit message updated with your new findings, this patch is
> > Reviewed-by: Nanley Chery 
> >
> 
> Here's what I wrote:
> 
> Unfortunately, this doesn't substantially improve the performance of any
> known apps.  With Dota 2 on my Sky Lake gt4, it seems help by somewhere
> between 0% and 1% but there's enough noise that it's hard to get a clear
> picture.
> 

Looks good to me.

-Nanley

> 
> 
> > > --Jason
> > >
> > >
> > > > --Jason
> > > >
> > > >
> > > >> -Nanley
> > > >>
> > > >> > Reviewed-by: Lionel Landwerlin 
> > > >> > ---
> > > >> >  src/intel/vulkan/anv_private.h |   1 +
> > > >> >  src/intel/vulkan/gen8_cmd_buffer.c | 157
> > > >> -
> > > >> >  src/intel/vulkan/genX_pipeline.c   |   6 +-
> > > >> >  3 files changed, 158 insertions(+), 6 deletions(-)
> > > >> >
> > > >> > diff --git a/src/intel/vulkan/anv_private.h
> > > >> b/src/intel/vulkan/anv_private.h
> > > >> > index fa6032e..25c9c93 100644
> > > >> > --- a/src/intel/vulkan/anv_private.h
> > > >> > +++ b/src/intel/vulkan/anv_private.h
> > > >> > @@ -1482,6 +1482,7 @@ struct anv_pipeline {
> > > >> > bool writes_depth;
> > > >> > bool depth_test_enable;
> > > >> > bool writes_stencil;
> > > >> > +   bool
> >  stencil_test_enable;
> > > >> > bool depth_clamp_enable;
> > > >> > bool kill_pixel;
> > > >> >
> > > >> > diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
> > > >> b/src/intel/vulkan/gen8_cmd_buffer.c
> > > >> > index 0628f3a..59fd537 100644
> > > >> > --- a/src/intel/vulkan/gen8_cmd_buffer.c
> > > >> > +++ b/src/intel/vulkan/gen8_cmd_buffer.c
> > > >> > @@ -157,16 +157,39 @@ __emit_sf_state(struct anv_cmd_buffer
> > *cmd_buffer)
> > > >> >  void
> > > >> >  genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
> > > >> bool enable)
> > > >> >  {
> > > >> > -#if GEN_GEN == 8
> > > >> > if (cmd_buffer->state.pma_fix_enabled == enable)
> > > >> >return;
> > > >> >
> > > >> > +   cmd_buffer->state.pma_fix_enabled = enable;
> > > >> > +
> > > >> > +   /* According to the Broadwell PIPE_CONTROL documentation,
> > software
> > > >> should
> > > >> > +* emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush
> > bits
> > > >> set
> > > >> > +* prior to the LRI.  If stencil buffer writes are enabled,
> > then a
> > > >> Render
> > > >> > +* Cache Flush is also necessary.
> > > >> > +*
> > > >> > +* The Skylake docs say to use a depth stall rather than a
> > command
> > > >> > +* streamer stall.  However, the hardware seems to violently
> > > >> disagree.
> > > >> > +* A full command streamer stall seems to be needed in both
> > cases.
> > > >> > +*/
> > > >> > anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
> > > >> >pc.DepthCacheFlushEnable = true;
> > > >> >pc.CommandStreamerStallEnable = true;
> > > >> >pc.RenderTargetCacheFlushEnable = true;
> > > >> > }
> > > >> >
> > > >> > +#if GEN_GEN == 9
> > > >> > +
> > > >> > +   uint32_t cache_mode;
> > > >> > +   anv_pack_struct(_mode, GENX(CACHE_MODE_0),
> > > >> > +   .STCPMAOptimizationEnable = enable,
> > > >> > +   .STCPMAOptimizationEnableMask = true);
> > > >> > +   anv_batch_emit(_buffer->batch, GENX(MI_LOAD_REGISTER_IMM),
> > > >> lri) {
> > > >> > +  lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
> > > >> > +  lri.DataDWord   

Re: [Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 10:51 AM, Matt Turner  wrote:

> Provides the ability to read the .note.gnu.build-id section of ELF
> binaries, which is inserted by the --build-id=... flag to ld.
> ---
>  configure.ac  |   2 +
>  src/util/Makefile.sources |   2 +
>  src/util/build_id.c   | 109 ++
> 
>  src/util/build_id.h   |  56 
>  4 files changed, 169 insertions(+)
>  create mode 100644 src/util/build_id.c
>  create mode 100644 src/util/build_id.h
>
> diff --git a/configure.ac b/configure.ac
> index f001743..99c74f0 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -768,6 +768,8 @@ LIBS="$LIBS $DLOPEN_LIBS"
>  AC_CHECK_FUNCS([dladdr])
>  LIBS="$save_LIBS"
>
> +AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES
> -DHAVE_DL_ITERATE_PHDR"])
> +
>  case "$host_os" in
>  darwin*)
>  ;;
> diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
> index a68a5fe..4c12e5f 100644
> --- a/src/util/Makefile.sources
> +++ b/src/util/Makefile.sources
> @@ -2,6 +2,8 @@ MESA_UTIL_FILES :=  \
> bitscan.c \
> bitscan.h \
> bitset.h \
> +   build_id.c \
> +   build_id.h \
> crc32.c \
> crc32.h \
> debug.c \
> diff --git a/src/util/build_id.c b/src/util/build_id.c
> new file mode 100644
> index 000..a2e21b7
> --- /dev/null
> +++ b/src/util/build_id.c
> @@ -0,0 +1,109 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> next
> + * paragraph) shall be included in all copies or substantial portions of
> the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifdef HAVE_DL_ITERATE_PHDR
> +#include 
> +#include 
> +#include 
> +
> +#include "build_id.h"
> +
> +#define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
> +
> +struct note {
> +   ElfW(Nhdr) nhdr;
> +
> +   char name[4];
> +   uint8_t build_id[0];
> +};
> +
> +struct callback_data {
> +   const char *name;
> +   struct note *note;
> +};
> +
> +static int
> +build_id_find_nhdr_callback(struct dl_phdr_info *info, size_t size, void
> *data_)
> +{
> +   struct callback_data *data = data_;
> +
> +   char *ptr = strstr(info->dlpi_name, data->name);
> +   if (ptr == NULL || ptr[strlen(data->name)] != '\0')
> +  return 0;
> +
> +   for (unsigned i = 0; i < info->dlpi_phnum; i++) {
> +  if (info->dlpi_phdr[i].p_type != PT_NOTE)
> + continue;
> +
> +  struct note *note = (void *)(info->dlpi_addr +
> +   info->dlpi_phdr[i].p_vaddr);
> +  ptrdiff_t len = info->dlpi_phdr[i].p_filesz;
> +
> +  while (len >= sizeof(struct note)) {
> + if (note->nhdr.n_type == NT_GNU_BUILD_ID &&
> +note->nhdr.n_descsz != 0 &&
> +note->nhdr.n_namesz == 4 &&
> +memcmp(note->name, "GNU", 4) == 0) {
> +data->note = note;
> +return 1;
> + }
> +
> + size_t offset = sizeof(ElfW(Nhdr)) +
> + ALIGN(note->nhdr.n_namesz, 4) +
> + ALIGN(note->nhdr.n_descsz, 4);
> + note = (struct note *)((char *)note + offset);
> + len -= offset;
> +  }
> +   }
> +
> +   return 0;
> +}
> +
> +const struct note *
> +build_id_find_nhdr(const char *name)
> +{
> +   struct callback_data data = {
> +  .name = name,
> +  .note = NULL,
> +   };
> +
> +   if (dl_iterate_phdr(build_id_find_nhdr_callback, )) {
> +  return data.note;
> +   } else {
> +  return NULL;
> +   }
> +}
> +
> +unsigned
> +build_id_length(const struct note *note)
> +{
> +   return note->nhdr.n_descsz;
> +}
> +
> +void
> +build_id_read(const struct note *note, unsigned char *build_id)
> +{
> +   memcpy(build_id, note->build_id, note->nhdr.n_descsz);
> +}
> +
> +#endif
> diff --git a/src/util/build_id.h b/src/util/build_id.h
> new file mode 100644
> index 000..0eaecf9
> --- /dev/null
> +++ 

Re: [Mesa-dev] [PATCH v2 7/7] anv: Implement the Skylake stencil PMA optimization

[Jason Ekstrand]

On Tue, Feb 14, 2017 at 10:35 AM, Nanley Chery 
wrote:

> On Mon, Feb 13, 2017 at 08:45:47PM -0800, Jason Ekstrand wrote:
> > On Mon, Feb 13, 2017 at 6:13 PM, Jason Ekstrand 
> > wrote:
> >
> > > On Mon, Feb 13, 2017 at 5:00 PM, Nanley Chery 
> > > wrote:
> > >
> > >> On Fri, Feb 10, 2017 at 11:02:21AM -0800, Jason Ekstrand wrote:
> > >> > This improves the performance of Dota 2 on my Sky Lake Skull Canyon
> > >> > machine by about 2-3%.
> > >> >
> > >>
> > >> This patch looks good. Could we compare our setup and testing in the
> > >> office? I can't reproduce these numbers.
> > >>
> > >
> > > I'll have to do more runs.  At the moment, I'm not seeing a large boost
> > > but I'll get a larger sample size and see if it's visible.
> > >
> >
> > I did a bunch more runs.  It looks like it helps somewhere between 0 and
> > 1%.  Not as much as I saw earlier, but it's definitely non-negative.
> >
>
> Although I've confirmed that the fix is enabled in Dota 2, I'm also not
> seeing any major changes on my SKL GT4. I get positive and negative
> changes in FPS, but it's all < 1% and seemingly noise.
>
> With the commit message updated with your new findings, this patch is
> Reviewed-by: Nanley Chery 
>

Here's what I wrote:

Unfortunately, this doesn't substantially improve the performance of any
known apps.  With Dota 2 on my Sky Lake gt4, it seems help by somewhere
between 0% and 1% but there's enough noise that it's hard to get a clear
picture.



> > --Jason
> >
> >
> > > --Jason
> > >
> > >
> > >> -Nanley
> > >>
> > >> > Reviewed-by: Lionel Landwerlin 
> > >> > ---
> > >> >  src/intel/vulkan/anv_private.h |   1 +
> > >> >  src/intel/vulkan/gen8_cmd_buffer.c | 157
> > >> -
> > >> >  src/intel/vulkan/genX_pipeline.c   |   6 +-
> > >> >  3 files changed, 158 insertions(+), 6 deletions(-)
> > >> >
> > >> > diff --git a/src/intel/vulkan/anv_private.h
> > >> b/src/intel/vulkan/anv_private.h
> > >> > index fa6032e..25c9c93 100644
> > >> > --- a/src/intel/vulkan/anv_private.h
> > >> > +++ b/src/intel/vulkan/anv_private.h
> > >> > @@ -1482,6 +1482,7 @@ struct anv_pipeline {
> > >> > bool writes_depth;
> > >> > bool depth_test_enable;
> > >> > bool writes_stencil;
> > >> > +   bool
>  stencil_test_enable;
> > >> > bool depth_clamp_enable;
> > >> > bool kill_pixel;
> > >> >
> > >> > diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
> > >> b/src/intel/vulkan/gen8_cmd_buffer.c
> > >> > index 0628f3a..59fd537 100644
> > >> > --- a/src/intel/vulkan/gen8_cmd_buffer.c
> > >> > +++ b/src/intel/vulkan/gen8_cmd_buffer.c
> > >> > @@ -157,16 +157,39 @@ __emit_sf_state(struct anv_cmd_buffer
> *cmd_buffer)
> > >> >  void
> > >> >  genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
> > >> bool enable)
> > >> >  {
> > >> > -#if GEN_GEN == 8
> > >> > if (cmd_buffer->state.pma_fix_enabled == enable)
> > >> >return;
> > >> >
> > >> > +   cmd_buffer->state.pma_fix_enabled = enable;
> > >> > +
> > >> > +   /* According to the Broadwell PIPE_CONTROL documentation,
> software
> > >> should
> > >> > +* emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush
> bits
> > >> set
> > >> > +* prior to the LRI.  If stencil buffer writes are enabled,
> then a
> > >> Render
> > >> > +* Cache Flush is also necessary.
> > >> > +*
> > >> > +* The Skylake docs say to use a depth stall rather than a
> command
> > >> > +* streamer stall.  However, the hardware seems to violently
> > >> disagree.
> > >> > +* A full command streamer stall seems to be needed in both
> cases.
> > >> > +*/
> > >> > anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
> > >> >pc.DepthCacheFlushEnable = true;
> > >> >pc.CommandStreamerStallEnable = true;
> > >> >pc.RenderTargetCacheFlushEnable = true;
> > >> > }
> > >> >
> > >> > +#if GEN_GEN == 9
> > >> > +
> > >> > +   uint32_t cache_mode;
> > >> > +   anv_pack_struct(_mode, GENX(CACHE_MODE_0),
> > >> > +   .STCPMAOptimizationEnable = enable,
> > >> > +   .STCPMAOptimizationEnableMask = true);
> > >> > +   anv_batch_emit(_buffer->batch, GENX(MI_LOAD_REGISTER_IMM),
> > >> lri) {
> > >> > +  lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
> > >> > +  lri.DataDWord= cache_mode;
> > >> > +   }
> > >> > +
> > >> > +#elif GEN_GEN == 8
> > >> > +
> > >> > uint32_t cache_mode;
> > >> > anv_pack_struct(_mode, GENX(CACHE_MODE_1),
> > >> > .NPPMAFixEnable = enable,
> > >> > @@ -178,18 +201,20 @@ genX(cmd_buffer_enable_pma_fix)(struct
> > >> anv_cmd_buffer *cmd_buffer, bool 

Re: [Mesa-dev] GLSL IR & TGSI on-disk shader cache

[Matt Turner]

On Tue, Feb 7, 2017 at 3:31 PM, Timothy Arceri  wrote:
> On Tue, 2017-02-07 at 23:58 +0100, Matt Turner wrote:
>> On Tue, Feb 7, 2017 at 4:42 AM, Timothy Arceri > > wrote:
>> > This series adds support for a GLSL IR level and TGSI (OpenGL/st)
>> > level caches.
>> >
>> > There are a few small bug fixes and a little bit of restructuring
>> > to the GLSL IR patches to make things work for Gallium drivers vs
>> > just i965 previously, but nothing too major.
>> >
>> > The biggest change is patch 35 which changes the mesa cache
>> > directory to be more structured allowing us to not fallback to
>> > recompiles at draw time if we realise a cache item was created
>> > with an old version of Mesa. Patch 36 also cleans up old cache
>> > files so we shouldn't get into a possition were we are constantly
>> > evicting cache items because its never cleaned out.
>> >
>> > Even with the new directory structure I've still left in the
>> > code that adds the Mesa version string to cache items because
>> > users can do things like override the OpenGL version which will
>> > change the output (in future we might want to just add this as
>> > part of the sha1 input).
>> >
>> > This series does not include the patch that adds cache support
>> > to the radeonsi backend, the main reason for this is that llvm
>> > currently doesn't allow the version to be queried at runtime
>> > (as far as I'm aware) although it seems like other are interested
>> > in this feature [1] so I will follow up on that.
>> >
>> > The reason we don't just use the build time like radv is that we
>> > will want something consistent accross distros to enable
>> > distribution of precompiled shaders.
>>
>> I think I have a solution for this. I am traveling until next week,
>> but I will send it as soon as I can.
>
> Are you able to provide a hint as to what you are suggesting? I've just
> pinged the llvm about creating the api to query the version. Would be
> interested to know if your idea will make the unnecessary.

I just sent the code:

[PATCH 1/2] util: Add utility build-id code.
[PATCH 2/2] anv: Use build-id for pipeline cache UUID.
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Re: [Mesa-dev] [PATCH] anv/entrypoints: Only generate entrypoints for supported features

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

Thanks!

On 14/02/17 18:26, Jason Ekstrand wrote:

This changes the way anv_entrypoints_gen.py works from generating a
table containing every single entrypoint in the XML to just the ones
that we actually need.  There's no reason for us to burn entrypoint
table space on a bunch of NV extensions we never plan to implement.
---
  src/intel/vulkan/anv_entrypoints_gen.py | 44 ++---
  1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 0eb523d..93511ec 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -25,6 +25,20 @@
  import sys
  import xml.etree.ElementTree as ET
  
+max_api_version = 1.0

+
+supported_extensions = [
+   'VK_KHR_get_physical_device_properties2',
+   'VK_KHR_maintenance1',
+   'VK_KHR_sampler_mirror_clamp_to_edge',
+   'VK_KHR_shader_draw_parameters',
+   'VK_KHR_surface',
+   'VK_KHR_swapchain',
+   'VK_KHR_wayland_surface',
+   'VK_KHR_xcb_surface',
+   'VK_KHR_xlib_surface',
+]
+
  # We generate a static hash table for entry point lookup
  # (vkGetProcAddress). We use a linear congruential generator for our hash
  # function and a power-of-two size table. The prime numbers are determined
@@ -66,10 +80,32 @@ elif (sys.argv[1] == "code"):
  # Extract the entry points from the registry
  def get_entrypoints(doc, entrypoints_to_defines):
  entrypoints = []
-commands = doc.findall('./commands/command')
-for i, command in enumerate(commands):
+
+enabled_commands = set()
+for feature in doc.findall('./feature'):
+assert feature.attrib['api'] == 'vulkan'
+if float(feature.attrib['number']) > max_api_version:
+continue
+
+for command in feature.findall('./require/command'):
+enabled_commands.add(command.attrib['name'])
+
+for extension in doc.findall('.extensions/extension'):
+if extension.attrib['name'] not in supported_extensions:
+continue
+
+assert extension.attrib['supported'] == 'vulkan'
+for command in extension.findall('./require/command'):
+enabled_commands.add(command.attrib['name'])
+
+index = 0
+for command in doc.findall('./commands/command'):
  type = command.find('./proto/type').text
  fullname = command.find('./proto/name').text
+
+if fullname not in enabled_commands:
+continue
+
  shortname = fullname[2:]
  params = map(lambda p: "".join(p.itertext()), 
command.findall('./param'))
  params = ', '.join(params)
@@ -77,7 +113,9 @@ def get_entrypoints(doc, entrypoints_to_defines):
  guard = entrypoints_to_defines[fullname]
  else:
  guard = None
-entrypoints.append((type, shortname, params, i, hash(fullname), guard))
+entrypoints.append((type, shortname, params, index, hash(fullname), 
guard))
+index += 1
+
  return entrypoints
  
  # Maps entry points to extension defines



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[Mesa-dev] [PATCH 2/2] anv: Use build-id for pipeline cache UUID.

[Matt Turner]

The --build-id=... ld flag has been present since binutils-2.18,
released 28 Aug 2007.
---
 src/intel/vulkan/Makefile.am  |  1 +
 src/intel/vulkan/anv_device.c | 31 ---
 2 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index 95f276e..4197b0e 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -165,6 +165,7 @@ libvulkan_intel_la_LDFLAGS = \
-module \
-no-undefined \
-avoid-version \
+   -Wl,--build-id=sha1 \
$(BSYMBOLIC) \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 91ee67f..f09fd23 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -21,18 +21,17 @@
  * IN THE SOFTWARE.
  */
 
-#include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
 #include "anv_private.h"
 #include "util/strtod.h"
 #include "util/debug.h"
+#include "util/build_id.h"
 
 #include "genxml/gen7_pack.h"
 
@@ -55,30 +54,24 @@ compiler_perf_log(void *data, const char *fmt, ...)
 }
 
 static bool
-anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
+anv_device_get_cache_uuid(void *uuid)
 {
-   Dl_info info;
-   struct stat st;
-   if (!dladdr(ptr, ) || !info.dli_fname)
+   const struct note *note = build_id_find_nhdr("libvulkan_intel.so");
+   if (!note)
   return false;
 
-   if (stat(info.dli_fname, ))
+   unsigned len = build_id_length(note);
+   if (len < VK_UUID_SIZE)
   return false;
 
-   *timestamp = st.st_mtim.tv_sec;
-   return true;
-}
-
-static bool
-anv_device_get_cache_uuid(void *uuid)
-{
-   uint32_t timestamp;
-
-   memset(uuid, 0, VK_UUID_SIZE);
-   if (!anv_get_function_timestamp(anv_device_get_cache_uuid, ))
+   unsigned char *build_id = malloc(len);
+   if (!build_id)
   return false;
 
-   snprintf(uuid, VK_UUID_SIZE, "anv-%d", timestamp);
+   build_id_read(note, build_id);
+
+   memcpy(uuid, build_id, VK_UUID_SIZE);
+   free(build_id);
return true;
 }
 
-- 
2.10.2

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[Mesa-dev] [PATCH 1/2] util: Add utility build-id code.

[Matt Turner]

Provides the ability to read the .note.gnu.build-id section of ELF
binaries, which is inserted by the --build-id=... flag to ld.
---
 configure.ac  |   2 +
 src/util/Makefile.sources |   2 +
 src/util/build_id.c   | 109 ++
 src/util/build_id.h   |  56 
 4 files changed, 169 insertions(+)
 create mode 100644 src/util/build_id.c
 create mode 100644 src/util/build_id.h

diff --git a/configure.ac b/configure.ac
index f001743..99c74f0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -768,6 +768,8 @@ LIBS="$LIBS $DLOPEN_LIBS"
 AC_CHECK_FUNCS([dladdr])
 LIBS="$save_LIBS"
 
+AC_CHECK_FUNC([dl_iterate_phdr], [DEFINES="$DEFINES -DHAVE_DL_ITERATE_PHDR"])
+
 case "$host_os" in
 darwin*)
 ;;
diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
index a68a5fe..4c12e5f 100644
--- a/src/util/Makefile.sources
+++ b/src/util/Makefile.sources
@@ -2,6 +2,8 @@ MESA_UTIL_FILES :=  \
bitscan.c \
bitscan.h \
bitset.h \
+   build_id.c \
+   build_id.h \
crc32.c \
crc32.h \
debug.c \
diff --git a/src/util/build_id.c b/src/util/build_id.c
new file mode 100644
index 000..a2e21b7
--- /dev/null
+++ b/src/util/build_id.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_DL_ITERATE_PHDR
+#include 
+#include 
+#include 
+
+#include "build_id.h"
+
+#define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
+
+struct note {
+   ElfW(Nhdr) nhdr;
+
+   char name[4];
+   uint8_t build_id[0];
+};
+
+struct callback_data {
+   const char *name;
+   struct note *note;
+};
+
+static int
+build_id_find_nhdr_callback(struct dl_phdr_info *info, size_t size, void 
*data_)
+{
+   struct callback_data *data = data_;
+
+   char *ptr = strstr(info->dlpi_name, data->name);
+   if (ptr == NULL || ptr[strlen(data->name)] != '\0')
+  return 0;
+
+   for (unsigned i = 0; i < info->dlpi_phnum; i++) {
+  if (info->dlpi_phdr[i].p_type != PT_NOTE)
+ continue;
+
+  struct note *note = (void *)(info->dlpi_addr +
+   info->dlpi_phdr[i].p_vaddr);
+  ptrdiff_t len = info->dlpi_phdr[i].p_filesz;
+
+  while (len >= sizeof(struct note)) {
+ if (note->nhdr.n_type == NT_GNU_BUILD_ID &&
+note->nhdr.n_descsz != 0 &&
+note->nhdr.n_namesz == 4 &&
+memcmp(note->name, "GNU", 4) == 0) {
+data->note = note;
+return 1;
+ }
+
+ size_t offset = sizeof(ElfW(Nhdr)) +
+ ALIGN(note->nhdr.n_namesz, 4) +
+ ALIGN(note->nhdr.n_descsz, 4);
+ note = (struct note *)((char *)note + offset);
+ len -= offset;
+  }
+   }
+
+   return 0;
+}
+
+const struct note *
+build_id_find_nhdr(const char *name)
+{
+   struct callback_data data = {
+  .name = name,
+  .note = NULL,
+   };
+
+   if (dl_iterate_phdr(build_id_find_nhdr_callback, )) {
+  return data.note;
+   } else {
+  return NULL;
+   }
+}
+
+unsigned
+build_id_length(const struct note *note)
+{
+   return note->nhdr.n_descsz;
+}
+
+void
+build_id_read(const struct note *note, unsigned char *build_id)
+{
+   memcpy(build_id, note->build_id, note->nhdr.n_descsz);
+}
+
+#endif
diff --git a/src/util/build_id.h b/src/util/build_id.h
new file mode 100644
index 000..0eaecf9
--- /dev/null
+++ b/src/util/build_id.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the 

Re: [Mesa-dev] [PATCH] radeonsi: allow unaligned vertex buffer offsets and strides on CIK-VI

[Marek Olšák]

On Tue, Feb 14, 2017 at 7:24 PM, Matt Arsenault  wrote:
>
> On Feb 13, 2017, at 09:01, Marek Olšák  wrote:
>
> So that we can disable u_vbuf for GL core profiles.
>
> This is a v2 of the previous VI-only patch.
> It requires SH_MEM_CONFIG.ALIGNMENT_MODE = UNALIGNED on CIK-VI.
>
>
> Is this enabled? I wasn’t sure, so currently LLVM assumes no. You can start
> adding the +unaligned-buffer-access subtarget feature if it is.

Yes, it's enabled on amdgpu (CIK-VI), radeon compute-only (CIK). I
have a patch that will enable it for the radeon graphics queue (CIK).

It's only expected to affect buffer_load_format_{xyzw} instructions
for Mesa, as we get dword-aligned loads in all other cases. It seems
that +unaligned-buffer-access is unnecessary.

Marek
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Re: [Mesa-dev] [PATCH] anv: fix Get*MemoryRequirements for !LLC

[Nanley Chery]

On Tue, Feb 14, 2017 at 09:37:20AM -0800, Jason Ekstrand wrote:
> On Tue, Feb 14, 2017 at 9:35 AM, Connor Abbott  wrote:
> 
> > On Tue, Feb 14, 2017 at 12:33 PM, Jason Ekstrand 
> > wrote:
> > > On Tue, Feb 14, 2017 at 9:23 AM, Connor Abbott 
> > wrote:
> > >>
> > >> Even though we supported both coherent and non-coherent memory types, we
> > >> effectively forced apps to use the coherent types by accident. Found by
> > >> inspection, only compile tested.
> > >>
> > >> Signed-off-by: Connor Abbott 
> > >> ---
> > >> I sent this out a while ago, but it seems like it was lost.
> > >> ---
> > >>  src/intel/vulkan/anv_device.c | 14 --
> > >>  1 file changed, 8 insertions(+), 6 deletions(-)
> > >>
> > >> diff --git a/src/intel/vulkan/anv_device.c
> > b/src/intel/vulkan/anv_device.c
> > >> index 46b83a3..57d70b6 100644
> > >> --- a/src/intel/vulkan/anv_device.c
> > >> +++ b/src/intel/vulkan/anv_device.c
> > >> @@ -1554,11 +1554,12 @@ VkResult anv_InvalidateMappedMemoryRanges(
> > >>  }
> > >>
> > >>  void anv_GetBufferMemoryRequirements(
> > >> -VkDevicedevice,
> > >> +VkDevice_device,
> > >>  VkBuffer_buffer,
> > >>  VkMemoryRequirements*   pMemoryRequirements)
> > >>  {
> > >> ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
> > >> +   ANV_FROM_HANDLE(anv_device, device, _device);
> > >>
> > >> /* The Vulkan spec (git aaed022) says:
> > >>  *
> > >> @@ -1567,20 +1568,21 @@ void anv_GetBufferMemoryRequirements(
> > >>  *only if the memory type `i` in the
> > >> VkPhysicalDeviceMemoryProperties
> > >>  *structure for the physical device is supported.
> > >>  *
> > >> -* We support exactly one memory type.
> > >> +* We support exactly one memory type on LLC, two on non-LLC.
> > >>  */
> > >> -   pMemoryRequirements->memoryTypeBits = 1;
> > >> +   pMemoryRequirements->memoryTypeBits = device->info.has_llc ? 1 : 3;
> > >
> > >
> > > Is it two or three?  The comment and code don't match.
> >
> > It's a bitfield. See the comment above.
> 
> 
> Drp... Yeah, this looks fine.
> 
> Reviewed-by: Jason Ekstrand 
> 
> I'll run it through CI and push it.
> 
> 

Looks like this patch should fix this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=97579

> > >
> > >>
> > >>
> > >> pMemoryRequirements->size = buffer->size;
> > >> pMemoryRequirements->alignment = 16;
> > >>  }
> > >>
> > >>  void anv_GetImageMemoryRequirements(
> > >> -VkDevicedevice,
> > >> +VkDevice_device,
> > >>  VkImage _image,
> > >>  VkMemoryRequirements*   pMemoryRequirements)
> > >>  {
> > >> ANV_FROM_HANDLE(anv_image, image, _image);
> > >> +   ANV_FROM_HANDLE(anv_device, device, _device);
> > >>
> > >> /* The Vulkan spec (git aaed022) says:
> > >>  *
> > >> @@ -1589,9 +1591,9 @@ void anv_GetImageMemoryRequirements(
> > >>  *only if the memory type `i` in the
> > >> VkPhysicalDeviceMemoryProperties
> > >>  *structure for the physical device is supported.
> > >>  *
> > >> -* We support exactly one memory type.
> > >> +* We support exactly one memory type on LLC, two on non-LLC.
> > >>  */
> > >> -   pMemoryRequirements->memoryTypeBits = 1;
> > >> +   pMemoryRequirements->memoryTypeBits = device->info.has_llc ? 1 : 3;
> > >>
> > >> pMemoryRequirements->size = image->size;
> > >> pMemoryRequirements->alignment = image->alignment;
> > >> --
> > >> 2.9.3
> > >>
> > >> ___
> > >> mesa-dev mailing list
> > >> mesa-dev@lists.freedesktop.org
> > >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > >
> > >
> >

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Re: [Mesa-dev] [PATCH v2 7/7] anv: Implement the Skylake stencil PMA optimization

[Nanley Chery]

On Mon, Feb 13, 2017 at 08:45:47PM -0800, Jason Ekstrand wrote:
> On Mon, Feb 13, 2017 at 6:13 PM, Jason Ekstrand 
> wrote:
> 
> > On Mon, Feb 13, 2017 at 5:00 PM, Nanley Chery 
> > wrote:
> >
> >> On Fri, Feb 10, 2017 at 11:02:21AM -0800, Jason Ekstrand wrote:
> >> > This improves the performance of Dota 2 on my Sky Lake Skull Canyon
> >> > machine by about 2-3%.
> >> >
> >>
> >> This patch looks good. Could we compare our setup and testing in the
> >> office? I can't reproduce these numbers.
> >>
> >
> > I'll have to do more runs.  At the moment, I'm not seeing a large boost
> > but I'll get a larger sample size and see if it's visible.
> >
> 
> I did a bunch more runs.  It looks like it helps somewhere between 0 and
> 1%.  Not as much as I saw earlier, but it's definitely non-negative.
> 

Although I've confirmed that the fix is enabled in Dota 2, I'm also not
seeing any major changes on my SKL GT4. I get positive and negative
changes in FPS, but it's all < 1% and seemingly noise. 

With the commit message updated with your new findings, this patch is
Reviewed-by: Nanley Chery 


> --Jason
> 
> 
> > --Jason
> >
> >
> >> -Nanley
> >>
> >> > Reviewed-by: Lionel Landwerlin 
> >> > ---
> >> >  src/intel/vulkan/anv_private.h |   1 +
> >> >  src/intel/vulkan/gen8_cmd_buffer.c | 157
> >> -
> >> >  src/intel/vulkan/genX_pipeline.c   |   6 +-
> >> >  3 files changed, 158 insertions(+), 6 deletions(-)
> >> >
> >> > diff --git a/src/intel/vulkan/anv_private.h
> >> b/src/intel/vulkan/anv_private.h
> >> > index fa6032e..25c9c93 100644
> >> > --- a/src/intel/vulkan/anv_private.h
> >> > +++ b/src/intel/vulkan/anv_private.h
> >> > @@ -1482,6 +1482,7 @@ struct anv_pipeline {
> >> > bool writes_depth;
> >> > bool depth_test_enable;
> >> > bool writes_stencil;
> >> > +   bool stencil_test_enable;
> >> > bool depth_clamp_enable;
> >> > bool kill_pixel;
> >> >
> >> > diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
> >> b/src/intel/vulkan/gen8_cmd_buffer.c
> >> > index 0628f3a..59fd537 100644
> >> > --- a/src/intel/vulkan/gen8_cmd_buffer.c
> >> > +++ b/src/intel/vulkan/gen8_cmd_buffer.c
> >> > @@ -157,16 +157,39 @@ __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
> >> >  void
> >> >  genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
> >> bool enable)
> >> >  {
> >> > -#if GEN_GEN == 8
> >> > if (cmd_buffer->state.pma_fix_enabled == enable)
> >> >return;
> >> >
> >> > +   cmd_buffer->state.pma_fix_enabled = enable;
> >> > +
> >> > +   /* According to the Broadwell PIPE_CONTROL documentation, software
> >> should
> >> > +* emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits
> >> set
> >> > +* prior to the LRI.  If stencil buffer writes are enabled, then a
> >> Render
> >> > +* Cache Flush is also necessary.
> >> > +*
> >> > +* The Skylake docs say to use a depth stall rather than a command
> >> > +* streamer stall.  However, the hardware seems to violently
> >> disagree.
> >> > +* A full command streamer stall seems to be needed in both cases.
> >> > +*/
> >> > anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
> >> >pc.DepthCacheFlushEnable = true;
> >> >pc.CommandStreamerStallEnable = true;
> >> >pc.RenderTargetCacheFlushEnable = true;
> >> > }
> >> >
> >> > +#if GEN_GEN == 9
> >> > +
> >> > +   uint32_t cache_mode;
> >> > +   anv_pack_struct(_mode, GENX(CACHE_MODE_0),
> >> > +   .STCPMAOptimizationEnable = enable,
> >> > +   .STCPMAOptimizationEnableMask = true);
> >> > +   anv_batch_emit(_buffer->batch, GENX(MI_LOAD_REGISTER_IMM),
> >> lri) {
> >> > +  lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
> >> > +  lri.DataDWord= cache_mode;
> >> > +   }
> >> > +
> >> > +#elif GEN_GEN == 8
> >> > +
> >> > uint32_t cache_mode;
> >> > anv_pack_struct(_mode, GENX(CACHE_MODE_1),
> >> > .NPPMAFixEnable = enable,
> >> > @@ -178,18 +201,20 @@ genX(cmd_buffer_enable_pma_fix)(struct
> >> anv_cmd_buffer *cmd_buffer, bool enable)
> >> >lri.DataDWord= cache_mode;
> >> > }
> >> >
> >> > +#endif /* GEN_GEN == 8 */
> >> > +
> >> > /* After the LRI, a PIPE_CONTROL with both the Depth Stall and
> >> Depth Cache
> >> >  * Flush bits is often necessary.  We do it regardless because it's
> >> easier.
> >> >  * The render cache flush is also necessary if stencil writes are
> >> enabled.
> >> > +*
> >> > +* Again, the Skylake docs give a different set of flushes but the
> >> BDW
> >> > +* flushes seem to work just as well.
> 

[Mesa-dev] [Bug 99638] Mesa opengles Peppa Pig and openggles2 smurfs on Radeon PowerPC and PPC64

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99638

--- Comment #20 from Casey C  ---
If at all helpful, I'd be happy to donate and ship a G5 970MP (PCIe) to a dev

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