[Mesa-dev] [PATCH 1/2] r300: drop u_mm.h include.

2017-08-01 Thread Dave Airlie
From: Dave Airlie 

This is not used in any of these files.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r300/r300_emit.c| 1 -
 src/gallium/drivers/r300/r300_hyperz.c  | 1 -
 src/gallium/drivers/r300/r300_state.c   | 1 -
 src/gallium/drivers/r300/r300_texture.c | 1 -
 4 files changed, 4 deletions(-)

diff --git a/src/gallium/drivers/r300/r300_emit.c 
b/src/gallium/drivers/r300/r300_emit.c
index 63f12de..80c959b 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -25,7 +25,6 @@
 
 #include "util/u_format.h"
 #include "util/u_math.h"
-#include "util/u_mm.h"
 
 #include "r300_context.h"
 #include "r300_cb.h"
diff --git a/src/gallium/drivers/r300/r300_hyperz.c 
b/src/gallium/drivers/r300/r300_hyperz.c
index 0f021e9..d86819a 100644
--- a/src/gallium/drivers/r300/r300_hyperz.c
+++ b/src/gallium/drivers/r300/r300_hyperz.c
@@ -26,7 +26,6 @@
 #include "r300_fs.h"
 
 #include "util/u_format.h"
-#include "util/u_mm.h"
 
 /*
   HiZ rules - taken from various docs 
diff --git a/src/gallium/drivers/r300/r300_state.c 
b/src/gallium/drivers/r300/r300_state.c
index c2b9937..437df48 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -27,7 +27,6 @@
 #include "util/u_half.h"
 #include "util/u_helpers.h"
 #include "util/u_math.h"
-#include "util/u_mm.h"
 #include "util/u_memory.h"
 #include "util/u_pack_color.h"
 #include "util/u_transfer.h"
diff --git a/src/gallium/drivers/r300/r300_texture.c 
b/src/gallium/drivers/r300/r300_texture.c
index cdf9ccb..8873c54 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -34,7 +34,6 @@
 #include "util/u_format_s3tc.h"
 #include "util/u_math.h"
 #include "util/u_memory.h"
-#include "util/u_mm.h"
 
 #include "pipe/p_screen.h"
 
-- 
2.9.4

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[Mesa-dev] [PATCH 2/2] mesa/dri: drop unneeded mm.h include

2017-08-01 Thread Dave Airlie
From: Dave Airlie 

This isn't used in any of these drivers.

Signed-off-by: Dave Airlie 
---
 src/mesa/drivers/dri/i915/i830_texblend.c   | 1 -
 src/mesa/drivers/dri/i915/intel_context.h   | 1 -
 src/mesa/drivers/dri/r200/r200_context.h| 1 -
 src/mesa/drivers/dri/radeon/radeon_common_context.h | 1 -
 4 files changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_texblend.c 
b/src/mesa/drivers/dri/i915/i830_texblend.c
index c29b572..15d6d54 100644
--- a/src/mesa/drivers/dri/i915/i830_texblend.c
+++ b/src/mesa/drivers/dri/i915/i830_texblend.c
@@ -29,7 +29,6 @@
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/enums.h"
-#include "main/mm.h"
 
 #include "intel_screen.h"
 #include "intel_tex.h"
diff --git a/src/mesa/drivers/dri/i915/intel_context.h 
b/src/mesa/drivers/dri/i915/intel_context.h
index d0f3d36..c59436a 100644
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -32,7 +32,6 @@
 #include 
 #include 
 #include "main/mtypes.h"
-#include "main/mm.h"
 
 #include 
 #include 
diff --git a/src/mesa/drivers/dri/r200/r200_context.h 
b/src/mesa/drivers/dri/r200/r200_context.h
index 07eae23..550203d 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -56,7 +56,6 @@ struct r200_context;
 typedef struct r200_context r200ContextRec;
 typedef struct r200_context *r200ContextPtr;
 
-#include "main/mm.h"
 
 struct r200_vertex_program {
 struct gl_program mesa_program; /* Must be first */
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h 
b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index e551570..328b545 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -2,7 +2,6 @@
 #ifndef COMMON_CONTEXT_H
 #define COMMON_CONTEXT_H
 
-#include "main/mm.h"
 #include "math/m_vector.h"
 #include "tnl/t_context.h"
 #include "main/colormac.h"
-- 
2.9.4

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[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=101334

--- Comment #30 from John  ---
(In reply to Dave Airlie from comment #28)
> can you try the patch on master?
> 
> https://patchwork.freedesktop.org/series/27906/

The bevarior is the same for me as a day ago. Max Max hanged at the exact same
spot, nothing in dmesg or Xorg.0.log (and again I had to manually shutdown the
computer).

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[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=101334

--- Comment #29 from Marko  ---
(In reply to Dave Airlie from comment #28)
> can you try the patch on master?
> 
> https://patchwork.freedesktop.org/series/27906/

Thanks Dave, will try!

Marko

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Re: [Mesa-dev] [PATCH] gallivm: Fix build against LLVM SVN >= r302589

2017-08-01 Thread Michel Dänzer
On 02/08/17 01:57 PM, Keith Packard wrote:
> Michel Dänzer  writes:
> 
>> +#if HAVE_LLVM >= 0x0500
>> +  virtual void deregisterEHFrames() {
>> + mgr()->deregisterEHFrames();
>> +  }
>> +#elif HAVE_LLVM >= 0x0304
>> +  virtual void deregisterEHFrames(uint8_t *Addr, uint64_t LoadAddr, 
>> size_t Size) {
>> + mgr()->deregisterEHFrames(Addr, LoadAddr, Size);
>> +  }
>> +#endif
> 
> I've got llvm 5.0.0 and it doesn't have this API change. Should that
> be > instead of >=?

No. Is your LLVM 5.0 snapshot really SVN r302589 or newer?


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[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=101334

--- Comment #28 from Dave Airlie  ---

can you try the patch on master?

https://patchwork.freedesktop.org/series/27906/

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[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=101334

--- Comment #27 from John  ---
That does not seem much better in your case :/

Maybe I'll try a few emulators such as Dolphin and RPCS3 to see what happens.

It'd be great if we could get a dev back here :)

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[Mesa-dev] [Bug 101334] AMD SI cards: Some vulkan apps freeze the system

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=101334

--- Comment #26 from Marko  ---
Hi,

For the life of me can't find the commit I was using yesterday since I did a
fresh checkout and deleted the source before testing, but it was something like
early 2017-08-01 commits IIRC. 

DOOM and Dota2 still hang but kind of get a bit further than before. in Dota2 I
was actually able to click the "your client is out of date" before it froze.

In DOOM I was able to pass past loading screen and it froze just before
displaying main menu.

Regards,

Marko

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Re: [Mesa-dev] [PATCH] gallivm: Fix build against LLVM SVN >= r302589

2017-08-01 Thread Keith Packard
Michel Dänzer  writes:

> +#if HAVE_LLVM >= 0x0500
> +  virtual void deregisterEHFrames() {
> + mgr()->deregisterEHFrames();
> +  }
> +#elif HAVE_LLVM >= 0x0304
> +  virtual void deregisterEHFrames(uint8_t *Addr, uint64_t LoadAddr, 
> size_t Size) {
> + mgr()->deregisterEHFrames(Addr, LoadAddr, Size);
> +  }
> +#endif

I've got llvm 5.0.0 and it doesn't have this API change. Should that
be > instead of >=?

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[Mesa-dev] [PATCH 1/2] anv: Advertise support for two more sRGB formats

2017-08-01 Thread Jason Ekstrand
Unreal Engine 4 seems to really like VK_FORMAT_R8_SRGB for some reason.
We don't technically have the hardware format but we do have L8_SRGB.
It's easy enough to fake with that and a swizzle.  While we're at it, we
may as well support R8G8_SRGB using L8A8_SRGB.
---
 src/intel/vulkan/anv_formats.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index c656d7e..2309dfe 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -74,14 +74,16 @@ static const struct anv_format anv_formats[] = {
fmt(VK_FORMAT_R8_SSCALED,  ISL_FORMAT_R8_SSCALED),
fmt(VK_FORMAT_R8_UINT, ISL_FORMAT_R8_UINT),
fmt(VK_FORMAT_R8_SINT, ISL_FORMAT_R8_SINT),
-   fmt(VK_FORMAT_R8_SRGB, ISL_FORMAT_UNSUPPORTED),
+   swiz_fmt(VK_FORMAT_R8_SRGB,ISL_FORMAT_L8_UNORM_SRGB,
+  _ISL_SWIZZLE(RED, ZERO, ZERO, ONE)),
fmt(VK_FORMAT_R8G8_UNORM,  ISL_FORMAT_R8G8_UNORM),
fmt(VK_FORMAT_R8G8_SNORM,  ISL_FORMAT_R8G8_SNORM),
fmt(VK_FORMAT_R8G8_USCALED,ISL_FORMAT_R8G8_USCALED),
fmt(VK_FORMAT_R8G8_SSCALED,ISL_FORMAT_R8G8_SSCALED),
fmt(VK_FORMAT_R8G8_UINT,   ISL_FORMAT_R8G8_UINT),
fmt(VK_FORMAT_R8G8_SINT,   ISL_FORMAT_R8G8_SINT),
-   fmt(VK_FORMAT_R8G8_SRGB,   ISL_FORMAT_UNSUPPORTED), /* 
L8A8_UNORM_SRGB */
+   swiz_fmt(VK_FORMAT_R8G8_SRGB,  ISL_FORMAT_L8A8_UNORM_SRGB,
+  _ISL_SWIZZLE(RED, ALPHA, ZERO, ONE)),
fmt(VK_FORMAT_R8G8B8_UNORM,ISL_FORMAT_R8G8B8_UNORM),
fmt(VK_FORMAT_R8G8B8_SNORM,ISL_FORMAT_R8G8B8_SNORM),
fmt(VK_FORMAT_R8G8B8_USCALED,  ISL_FORMAT_R8G8B8_USCALED),
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/2] spirv: Fix SpvImageFormatR16ui

2017-08-01 Thread Jason Ekstrand
Cc: "17.1 17.2" 
---
 src/compiler/spirv/spirv_to_nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 4b9c121..7b34dad 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -721,7 +721,7 @@ translate_image_format(SpvImageFormat format)
case SpvImageFormatRg32ui:   return 0x823C; /* GL_RG32UI */
case SpvImageFormatRg16ui:   return 0x823A; /* GL_RG16UI */
case SpvImageFormatRg8ui:return 0x8238; /* GL_RG8UI */
-   case SpvImageFormatR16ui:return 0x823A; /* GL_RG16UI */
+   case SpvImageFormatR16ui:return 0x8234; /* GL_R16UI */
case SpvImageFormatR8ui: return 0x8232; /* GL_R8UI */
default:
   assert(!"Invalid image format");
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [Mesa-dev RESEND 26/26] mesa: add KHR_no_error support to glPolygonMode()

2017-08-01 Thread Timothy Arceri

\o/ 9-26:

Reviewed-by: Timothy Arceri 

Thanks for doing all this :) Please try to knock off a few more piglit 
tests here and there when time permits, it would be a shame if dev's 
tried to start turning this stuff on only to run into strange errors.

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[Mesa-dev] [PATCH] i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.

2017-08-01 Thread Kenneth Graunke
The cacheline alignment restriction is on the base address; the pitch
can be anything.

Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):

intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 
64 == 0' failed.

Cc: mesa-sta...@lists.freedesktop.org
---
 src/mesa/drivers/dri/i965/intel_blit.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index eca87368047..b1db7aa2293 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -187,7 +187,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
* The offsets we get from ISL in the tiled case are already aligned.
* In the linear case, we need to do some of our own aligning.
*/
-  assert(mt->surf.row_pitch % 64 == 0);
   uint32_t delta = *base_address_offset & 63;
   assert(delta % mt->cpp == 0);
   *base_address_offset -= delta;
-- 
2.13.4

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[Mesa-dev] [PATCH] build: Don't bail on OSError in git_sha1_gen.py

2017-08-01 Thread Tobias Klausmann
When building sandboxed, we may encounter additional errors. Ignore the errors,
as we are in a constrained environment.

This can be observed when building latest git with OBS.

Signed-off-by: Tobias Klausmann 
---
 bin/git_sha1_gen.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/bin/git_sha1_gen.py b/bin/git_sha1_gen.py
index 6d13db1e16..fe30084a4f 100755
--- a/bin/git_sha1_gen.py
+++ b/bin/git_sha1_gen.py
@@ -16,5 +16,8 @@ try:
 except subprocess.CalledProcessError as e:
 # don't print anything if git fails
 pass
+except OSError as eos:
+# don't fail on inaccessible files when sandboxed
+pass
 else:
 sys.stdout.write('#define MESA_GIT_SHA1 "git-%s"\n' % git_sha1.rstrip())
-- 
2.13.3

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Re: [Mesa-dev] [PATCH] glsl: look up for transform feedback varyings after linking

2017-08-01 Thread Timothy Arceri

On 06/07/17 19:12, Juan A. Suarez Romero wrote:

Check if shaders have transform feedback varyings also after the
post-link step.

This fixes:
KHR-GL45.enhanced_layouts.xfb_vertex_streams
piglit/spec/arb_enhanced_layouts/gs-stream-location-aliasing
---
  src/compiler/glsl/glsl_to_nir.cpp | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 2153004..fad08ec 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -171,6 +171,9 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
shader->info.label = ralloc_strdup(shader, shader_prog->Label);


Can you add a couple of comments:

   /* Check for transform feedback varyings specified via the API */

 shader->info.has_transform_feedback_varyings =
shader_prog->TransformFeedback.NumVarying > 0;


  /* Check for transform feedback varyings specified in Shader */

+   if (shader_prog->last_vert_prog)
+  shader->info.has_transform_feedback_varyings |=
+ shader_prog->last_vert_prog->sh.LinkedTransformFeedback->NumVarying > 
0;
  
 return shader;

  }



Otherwise:

Reviewed-by: Timothy Arceri 
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[Mesa-dev] [Bug 102010] libvulkan_radeon crashes if loaded on Intel hardware

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102010

--- Comment #1 from Thiago Macieira  ---
Also submitted at libvulkan itself:
https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/issues/1978

I don't know what is at fault: whether it's libvulkan for loading the wrong
driver, or the driver for failing to properly bail out, or both for there not
being a mechanism to bail out in the first place.

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[Mesa-dev] [Bug 102010] libvulkan_radeon crashes if loaded on Intel hardware

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102010

Bug ID: 102010
   Summary: libvulkan_radeon crashes if loaded on Intel hardware
   Product: Mesa
   Version: 17.1
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: thi...@kde.org
QA Contact: mesa-dev@lists.freedesktop.org

When I run vulkaninfo, it crashes:

===
VULKAN INFO
===

Vulkan API Version: 1.0.41

INFO: [loader] Code 0 : Found manifest file
/etc/vulkan/explicit_layer.d/VkLayer_core_validation.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/etc/vulkan/explicit_layer.d/VkLayer_object_tracker.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/etc/vulkan/explicit_layer.d/VkLayer_parameter_validation.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/etc/vulkan/explicit_layer.d/VkLayer_swapchain.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/etc/vulkan/explicit_layer.d/VkLayer_threading.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/etc/vulkan/explicit_layer.d/VkLayer_unique_objects.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/usr/share/vulkan/explicit_layer.d/VkLayer_core_validation.json, version
"1.0.0"
INFO: [loader] Code 0 : Found manifest file
/usr/share/vulkan/explicit_layer.d/VkLayer_object_tracker.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/usr/share/vulkan/explicit_layer.d/VkLayer_parameter_validation.json, version
"1.0.0"
INFO: [loader] Code 0 : Found manifest file
/usr/share/vulkan/explicit_layer.d/VkLayer_swapchain.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/usr/share/vulkan/explicit_layer.d/VkLayer_threading.json, version "1.0.0"
INFO: [loader] Code 0 : Found manifest file
/usr/share/vulkan/explicit_layer.d/VkLayer_unique_objects.json, version "1.0.0"
INFO: [loader] Code 0 : Found ICD manifest file
/usr/share/vulkan/icd.d/intel_icd.x86_64.json, version "1.0.0"
INFO: [loader] Code 0 : Found ICD manifest file
/usr/share/vulkan/icd.d/radeon_icd.x86_64.json, version "1.0.0"

Program received signal SIGSEGV, Segmentation fault.

The backtrace points to libvulkan loading the Radeon driver:

(gdb) bt
#0  0x0001f436 in ?? ()
#1  0x7fffede683f2 in radv_lookup_entrypoint (name=) at
radv_entrypoints.c:833
#2  0x7797f3e9 in loader_scanned_icd_add (api_version=4194307, 
filename=0x7fffd0a0 "/usr/lib64/libvulkan_radeon.so",
icd_tramp_list=0x557c2bb0, inst=0x557c2b70)
at
/usr/src/debug/Vulkan-LoaderAndValidationLayers-1.0.41/loader/loader.c:1565
#3  loader_icd_scan (inst=inst@entry=0x557c2b70,
icd_tramp_list=icd_tramp_list@entry=0x557c2bb0)
at
/usr/src/debug/Vulkan-LoaderAndValidationLayers-1.0.41/loader/loader.c:3177
#4  0x7798506b in vkCreateInstance (pCreateInfo=0x7fffd660,
pAllocator=0x0, pInstance=0x7fffd6b0)
at
/usr/src/debug/Vulkan-LoaderAndValidationLayers-1.0.41/loader/trampoline.c:329
#5  0x58c2 in AppCreateInstance (inst=0x7fffd6b0)
at
/usr/src/debug/Vulkan-LoaderAndValidationLayers-1.0.41/demos/vulkaninfo.c:667
#6  main (argc=, argv=)
at
/usr/src/debug/Vulkan-LoaderAndValidationLayers-1.0.41/demos/vulkaninfo.c:1454

My system has an Intel GPU:

$ lspci -s 0:2
00:02.0 VGA compatible controller: Intel Corporation Iris Graphics 540 (rev 0a)

The Intel driver is installed:

$ ls -l /usr/lib64/libvulkan*
-rwxr-xr-x 1 root root 2625088 jul 24 04:26 /usr/lib64/libvulkan_intel.so
-rwxr-xr-x 1 root root 1655912 jul 24 04:26 /usr/lib64/libvulkan_radeon.so
lrwxrwxrwx 1 root root  19 mai 27 22:52 /usr/lib64/libvulkan.so.1 ->
libvulkan.so.1.0.41
-rwxr-xr-x 1 root root  239600 mai 27 22:52 /usr/lib64/libvulkan.so.1.0.41

Both files drivers are installed due to a dependency in package management, but
clearly the Radeon one should not be used. The driver should validate that it
is in the correct HW and bail out if not.

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[Mesa-dev] [PATCH] vulkan/wsi: handle UINT64_MAX timeout correctly.

2017-08-01 Thread Dave Airlie
From: Dave Airlie 

The spec says
"If timeout is UINT64_MAX, the function will not return until an image is 
acquired from the presentation engine."

Now I know UINT64_MAX is probably heat death of the universe,
but this changes the code to avoid calculating things in that
case and uses the pthread_cond_wait interface instead.

(just noticed in passing).
Signed-off-by: Dave Airlie 
---
 src/vulkan/wsi/wsi_common_queue.h | 37 ++---
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_queue.h 
b/src/vulkan/wsi/wsi_common_queue.h
index 6d489cb..21b2cb0 100644
--- a/src/vulkan/wsi/wsi_common_queue.h
+++ b/src/vulkan/wsi/wsi_common_queue.h
@@ -113,23 +113,30 @@ wsi_queue_pull(struct wsi_queue *queue, uint32_t *index, 
uint64_t timeout)
 
pthread_mutex_lock(&queue->mutex);
 
-   struct timespec now;
-   clock_gettime(CLOCK_MONOTONIC, &now);
-
-   uint32_t abs_nsec = now.tv_nsec + timeout % NSEC_PER_SEC;
-   uint64_t abs_sec = now.tv_sec + (abs_nsec / NSEC_PER_SEC) +
-  (timeout / NSEC_PER_SEC);
-   abs_nsec %= NSEC_PER_SEC;
-
-   /* Avoid roll-over in tv_sec on 32-bit systems if the user provided timeout
-* is UINT64_MAX
-*/
-   struct timespec abstime;
-   abstime.tv_nsec = abs_nsec;
-   abstime.tv_sec = MIN2(abs_sec, INT_TYPE_MAX(abstime.tv_sec));
+   struct timespec abstime = {0};
+   bool block = false;
+   if (timeout != UINT64_MAX) {
+  struct timespec now;
+  clock_gettime(CLOCK_MONOTONIC, &now);
+
+  uint32_t abs_nsec = now.tv_nsec + timeout % NSEC_PER_SEC;
+  uint64_t abs_sec = now.tv_sec + (abs_nsec / NSEC_PER_SEC) +
+ (timeout / NSEC_PER_SEC);
+  abs_nsec %= NSEC_PER_SEC;
+
+  /* Avoid roll-over in tv_sec on 32-bit systems if the user provided 
timeout
+   * is UINT64_MAX
+   */
+  abstime.tv_nsec = abs_nsec;
+  abstime.tv_sec = MIN2(abs_sec, INT_TYPE_MAX(abstime.tv_sec));
+   } else
+  block = true;
 
while (u_vector_length(&queue->vector) == 0) {
-  ret = pthread_cond_timedwait(&queue->cond, &queue->mutex, &abstime);
+  if (block)
+ ret = pthread_cond_wait(&queue->cond, &queue->mutex);
+  else
+ ret = pthread_cond_timedwait(&queue->cond, &queue->mutex, &abstime);
   if (ret == 0) {
  continue;
   } else if (ret == ETIMEDOUT) {
-- 
2.9.4

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[Mesa-dev] [PATCH 1/2] gallium: add CAPs to support HW atomic counters.

2017-08-01 Thread Dave Airlie
From: Dave Airlie 

This looks like an evergreen specific feature, but with atomic
counters AMD have hw specific counters they use instead of operating
on buffers directly. These are separate to the buffer atomics,
so require different limits and code paths.

I've left the CAP for atomic type extensible in case someone
else has a variant on this sort of thing (freedreno maybe?)
and needs to change it.

This adds all the CAPs required to add support for those atomic
counters, along with a related CAP for limiting the number of
output resources.

I'd like to land this and the st patch then I can start to
upstream the evergreen support for these and other GL4.x features.

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/gallivm/lp_bld_limits.h|  2 ++
 src/gallium/auxiliary/tgsi/tgsi_exec.h   |  2 ++
 src/gallium/docs/source/screen.rst   | 15 +--
 src/gallium/drivers/etnaviv/etnaviv_screen.c |  4 
 src/gallium/drivers/freedreno/freedreno_screen.c |  4 
 src/gallium/drivers/i915/i915_screen.c   |  2 ++
 src/gallium/drivers/llvmpipe/lp_screen.c |  2 ++
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   |  4 
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   |  4 
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   |  4 
 src/gallium/drivers/r300/r300_screen.c   |  4 
 src/gallium/drivers/r600/r600_pipe.c |  4 
 src/gallium/drivers/radeonsi/si_pipe.c   |  4 
 src/gallium/drivers/softpipe/sp_screen.c |  2 ++
 src/gallium/drivers/svga/svga_screen.c   |  8 
 src/gallium/drivers/swr/swr_screen.cpp   |  2 ++
 src/gallium/drivers/vc4/vc4_screen.c |  4 
 src/gallium/drivers/virgl/virgl_screen.c |  4 
 src/gallium/include/pipe/p_defines.h |  9 +
 19 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h 
b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
index 354e2a4..f37e53e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
@@ -136,6 +136,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
   return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
   return 32;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 9d7e65f..9d37087 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -528,6 +528,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
   return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   return PIPE_MAX_SHADER_BUFFERS;
diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index ee7accb..56de928 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -398,7 +398,16 @@ The integer capabilities:
   supported.
 * ``PIPE_CAP_NIR_SAMPLERS_AS_DEREF``: Whether NIR tex instructions should
   reference texture and sampler as NIR derefs instead of by indices.
-
+* ``PIPE_CAP_ATOMIC_COUNTER_MODE``: How hw implements atomic counters. If
+  set to PIPE_CAP_ATOMIC_COUNTER_MODE_USE_BUFFERS, atomics are implemented
+  on top of buffers. If set to PIPE_ATOMIC_COUNTER_MODE_HW_COUNTERS, counters
+  are a separate limited hw resource (AMD evergreen) with limits on how many
+  counters can be used across shader stages. If this is set to the latter,
+  PIPE_SHADER_CAP_MAX_ATOMIC_COUNTERS,
+  PIPE_SHADER_CAP_MAX_ATOMIC_COUNTER_BUFFERS should have valid values.
+* ``PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES``: Limit on combined shader
+  output resources (images + buffers + fragment outputs). If 0 the state
+  tracker works it out.
 
 .. _pipe_capf:
 
@@ -501,7 +510,9 @@ to be 0.
 * ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers
   TGSI pass is skipped. This might reduce code size and register pressure if
   the underlying driver has a real backend compiler.
-
+* ``PIPE_SHADER_CAP_MAX_ATOMIC_COUNTERS``: If atomic counters are separate,
+  how many HW counters are available for this stage.
+* ``PIPE_SHADER_CAP_MAX_ATOMIC_COUNTER_BUFFERS``: If atomic counters are 
separate, how many atomic counter buffers are available for this stage.
 
 .. _pipe_compute_cap:
 
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 0e3d5d8..83fd495 100644
--- a/src/gallium/dr

[Mesa-dev] [PATCH 2/2] mesa/st: add support for hw atomics

2017-08-01 Thread Dave Airlie
From: Dave Airlie 

This adds support for hw atomics to the state tracker,
it just sets the limits using the new CAPs, and sets
the maximums etc for it.

Signed-off-by: Dave Airlie 
---
 src/mesa/state_tracker/st_extensions.c | 50 +++---
 1 file changed, 40 insertions(+), 10 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 74193cc..49c3f82 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -78,6 +78,8 @@ void st_init_limits(struct pipe_screen *screen,
int supported_irs;
unsigned sh;
boolean can_ubo = TRUE;
+   uint32_t atomic_counter_mode = screen->get_param(screen, 
PIPE_CAP_ATOMIC_COUNTER_MODE);
+   uint32_t temp;
 
c->MaxTextureLevels
   = _min(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
@@ -242,11 +244,19 @@ void st_init_limits(struct pipe_screen *screen,
   c->MaxUniformBlockSize / 4 *
   pc->MaxUniformBlocks);
 
-  pc->MaxAtomicCounters = MAX_ATOMIC_COUNTERS;
-  pc->MaxAtomicBuffers = screen->get_shader_param(
-screen, sh, PIPE_SHADER_CAP_MAX_SHADER_BUFFERS) / 2;
-  pc->MaxShaderStorageBlocks = pc->MaxAtomicBuffers;
-
+  if (atomic_counter_mode == PIPE_ATOMIC_COUNTER_MODE_HW_COUNTERS) {
+ /*
+  * for separate atomic counters get the actual hw limits
+  * per stage on atomic counters and buffers
+  */
+ pc->MaxAtomicCounters = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS);
+ pc->MaxAtomicBuffers = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS);
+ pc->MaxShaderStorageBlocks = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_SHADER_BUFFERS);
+  } else {
+ pc->MaxAtomicCounters = MAX_ATOMIC_COUNTERS;
+ pc->MaxAtomicBuffers = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_SHADER_BUFFERS) / 2;
+ pc->MaxShaderStorageBlocks = pc->MaxAtomicBuffers;
+  }
   pc->MaxImageUniforms = screen->get_shader_param(
 screen, sh, PIPE_SHADER_CAP_MAX_SHADER_IMAGES);
 
@@ -406,14 +416,26 @@ void st_init_limits(struct pipe_screen *screen,
   screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
 
c->MaxAtomicBufferBindings =
- c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
-   c->MaxCombinedAtomicBuffers =
+  c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
+
+   if (atomic_counter_mode == PIPE_ATOMIC_COUNTER_MODE_HW_COUNTERS) {
+  /* for separate atomic buffers - there atomic buffer size will be
+ limitied */
+  c->MaxAtomicBufferSize = 
c->Program[MESA_SHADER_FRAGMENT].MaxAtomicCounters * ATOMIC_COUNTER_SIZE;
+  /* on all HW with separate atomic (evergreen) the following
+ lines are true. not sure it's worth adding CAPs for this at this
+ stage. */
+  c->MaxCombinedAtomicCounters = 
c->Program[MESA_SHADER_FRAGMENT].MaxAtomicCounters;
+  c->MaxCombinedAtomicBuffers = 
c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
+   } else {
+  c->MaxCombinedAtomicBuffers =
  c->Program[MESA_SHADER_VERTEX].MaxAtomicBuffers +
  c->Program[MESA_SHADER_TESS_CTRL].MaxAtomicBuffers +
  c->Program[MESA_SHADER_TESS_EVAL].MaxAtomicBuffers +
  c->Program[MESA_SHADER_GEOMETRY].MaxAtomicBuffers +
  c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
-   assert(c->MaxCombinedAtomicBuffers <= MAX_COMBINED_ATOMIC_BUFFERS);
+  assert(c->MaxCombinedAtomicBuffers <= MAX_COMBINED_ATOMIC_BUFFERS);
+   }
 
if (c->MaxCombinedAtomicBuffers > 0) {
   extensions->ARB_shader_atomic_counters = GL_TRUE;
@@ -424,8 +446,11 @@ void st_init_limits(struct pipe_screen *screen,
c->ShaderStorageBufferOffsetAlignment =
   screen->get_param(screen, PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT);
if (c->ShaderStorageBufferOffsetAlignment) {
-  c->MaxCombinedShaderStorageBlocks = c->MaxShaderStorageBufferBindings =
- c->MaxCombinedAtomicBuffers;
+
+  /* for hw atomic counters leaves these at default for now */
+  if (atomic_counter_mode == PIPE_ATOMIC_COUNTER_MODE_USE_BUFFERS)
+ c->MaxCombinedShaderStorageBlocks = c->MaxShaderStorageBufferBindings 
=
+c->MaxCombinedAtomicBuffers;
   c->MaxCombinedShaderOutputResources +=
  c->MaxCombinedShaderStorageBlocks;
   c->MaxShaderStorageBlockSize = 1 << 27;
@@ -466,6 +491,11 @@ void st_init_limits(struct pipe_screen *screen,
 
c->AllowMappedBuffersDuringExecution =
   screen->get_param(screen, 
PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION);
+
+   /* limit the max combined shader output resources to a driver limit */
+   temp = screen->get_param(screen, 
PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES);
+   if (temp > 0 && c->MaxCombinedShaderOutputReso

[Mesa-dev] [PATCH 1/5] intel/isl: Set MOCS based on usage for surface states

2017-08-01 Thread Jason Ekstrand
This makes ISL now ignore the MOCS data provided by the caller and just
set it based on surface usage.
---
 src/intel/isl/isl_emit_depth_stencil.c | 12 
 src/intel/isl/isl_genX_mocs.h  | 53 ++
 src/intel/isl/isl_surface_state.c  |  9 +++---
 3 files changed, 65 insertions(+), 9 deletions(-)
 create mode 100644 src/intel/isl/isl_genX_mocs.h

diff --git a/src/intel/isl/isl_emit_depth_stencil.c 
b/src/intel/isl/isl_emit_depth_stencil.c
index 0d541fd..212ed88 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -23,6 +23,9 @@
 
 #include 
 
+#include "isl_priv.h"
+#include "isl_genX_mocs.h"
+
 #define __gen_address_type uint64_t
 #define __gen_user_data void
 
@@ -35,8 +38,6 @@ __gen_combine_address(void *data, void *loc, uint64_t addr, 
uint32_t delta)
 #include "genxml/gen_macros.h"
 #include "genxml/genX_pack.h"
 
-#include "isl_priv.h"
-
 #define __PASTE2(x, y) x ## y
 #define __PASTE(x, y) __PASTE2(x, y)
 #define isl_genX(x) __PASTE(isl_, genX(x))
@@ -96,7 +97,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device 
*dev, void *batch,
 #endif
   db.SurfaceBaseAddress = info->depth_address;
 #if GEN_GEN >= 6
-  db.DepthBufferMOCS = info->mocs;
+  db.DepthBufferMOCS = get_mocs_for_usage(ISL_SURF_USAGE_DEPTH_BIT);
 #endif
 
 #if GEN_GEN <= 6
@@ -140,7 +141,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device 
*dev, void *batch,
 #endif
   sb.SurfaceBaseAddress = info->stencil_address;
 #if GEN_GEN >= 6
-  sb.StencilBufferMOCS = info->mocs;
+  sb.StencilBufferMOCS = get_mocs_for_usage(ISL_SURF_USAGE_STENCIL_BIT);
 #endif
   sb.SurfacePitch = info->stencil_surf->row_pitch - 1;
 #if GEN_GEN >= 8
@@ -163,7 +164,8 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device 
*dev, void *batch,
   db.HierarchicalDepthBufferEnable = true;
 
   hiz.SurfaceBaseAddress = info->hiz_address;
-  hiz.HierarchicalDepthBufferMOCS = info->mocs;
+  hiz.HierarchicalDepthBufferMOCS =
+ get_mocs_for_usage(ISL_SURF_USAGE_HIZ_BIT);
   hiz.SurfacePitch = info->hiz_surf->row_pitch - 1;
 #if GEN_GEN >= 8
   /* From the SKL PRM Vol2a:
diff --git a/src/intel/isl/isl_genX_mocs.h b/src/intel/isl/isl_genX_mocs.h
new file mode 100644
index 000..158ebec
--- /dev/null
+++ b/src/intel/isl/isl_genX_mocs.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files (the "Software"),
+ *  to deal in the Software without restriction, including without limitation
+ *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ *  Software is furnished to do so, subject to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the next
+ *  paragraph) shall be included in all copies or substantial portions of the
+ *  Software.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS
+ *  IN THE SOFTWARE.
+ */
+
+#include 
+
+#include "isl_priv.h"
+
+#include "genxml/gen_macros.h"
+
+#if GEN_GEN >= 6
+static uint32_t
+get_mocs_for_usage(isl_surf_usage_flags_t usage)
+{
+#if GEN_GEN == 6
+   return 0; /* PTE */
+#elif GEN_GEN == 7
+   return 1; /* Cache in L3$, LLC and eLLC use PTE */
+#elif GEN_GEN == 8
+   if (usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+  return 0x18; /* LLC and eLLC use PTE */
+   else
+  return 0x78; /* LLC and eLLC are forced to WB */
+#elif GEN_GEN >= 9
+   /* We have to shift by one because of a reserved bit in the MOCS field */
+   if (usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+  return I915_MOCS_PTE << 1;
+   else
+  return I915_MOCS_CACHED << 1;
+#else
+#  error "Unknown hardware generation"
+#endif
+}
+#endif
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index e8bdb65..66b5add 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -23,6 +23,9 @@
 
 #include 
 
+#include "isl_priv.h"
+#include "isl_genX_mocs.h"
+
 #define __gen_address_type uint64_t
 #define __gen_user_data void
 
@@ -35,8 +38,6 @@ __gen_combine_address(void *data, void *loc, uint64_t addr, 
uint32_t delta)
 #include "genxml/gen_macros.h"
 #include "genxml/genX_pack.h"
 
-#include "isl_priv.h"
-
 #define __PASTE2(x, y) x ## y
 #define __PASTE(x, y) __PASTE2(x, y)
 #define isl_genX(x) __PASTE(isl_, genX(x)

[Mesa-dev] [PATCH 4/5] anv: Stop passing MOCS information into ISL

2017-08-01 Thread Jason Ekstrand
As of a couple of commits ago, ISL is ignoring it.
---
 src/intel/vulkan/anv_device.c  |  1 -
 src/intel/vulkan/anv_image.c   | 12 
 src/intel/vulkan/anv_private.h |  2 --
 src/intel/vulkan/genX_cmd_buffer.c | 13 -
 src/intel/vulkan/genX_state.c  |  3 ---
 5 files changed, 8 insertions(+), 23 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 70b5cd1..3be8c84 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1967,7 +1967,6 @@ anv_fill_buffer_surface_state(struct anv_device *device, 
struct anv_state state,
 {
isl_buffer_fill_state(&device->isl_dev, state.map,
  .address = offset,
- .mocs = device->default_mocs,
  .size = range,
  .format = format,
  .stride = stride);
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 4f0a818..29c3d54 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -774,8 +774,7 @@ anv_CreateImageView(VkDevice _device,
   .view = &view,
   .clear_color = clear_color,
   .aux_surf = &image->aux_surface.isl,
-  .aux_usage = iview->optimal_sampler_aux_usage,
-  .mocs = device->default_mocs);
+  .aux_usage = iview->optimal_sampler_aux_usage);
 
   isl_surf_fill_state(&device->isl_dev,
   iview->general_sampler_surface_state.map,
@@ -783,8 +782,7 @@ anv_CreateImageView(VkDevice _device,
   .view = &view,
   .clear_color = clear_color,
   .aux_surf = &image->aux_surface.isl,
-  .aux_usage = iview->general_sampler_aux_usage,
-  .mocs = device->default_mocs);
+  .aux_usage = iview->general_sampler_aux_usage);
 
   anv_state_flush(device, iview->optimal_sampler_surface_state);
   anv_state_flush(device, iview->general_sampler_surface_state);
@@ -806,8 +804,7 @@ anv_CreateImageView(VkDevice _device,
   .surf = &surface->isl,
   .view = &view,
   .aux_surf = &image->aux_surface.isl,
-  .aux_usage = image->aux_usage,
-  .mocs = device->default_mocs);
+  .aux_usage = image->aux_usage);
 
   if (isl_has_matching_typed_storage_image_format(&device->info,
   format.isl_format)) {
@@ -823,8 +820,7 @@ anv_CreateImageView(VkDevice _device,
  .surf = &surface->isl,
  .view = &view,
  .aux_surf = &image->aux_surface.isl,
- .aux_usage = image->aux_usage,
- .mocs = device->default_mocs);
+ .aux_usage = image->aux_usage);
   } else {
  anv_fill_buffer_surface_state(device, iview->storage_surface_state,
ISL_FORMAT_RAW,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 818f699..b7150a9 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -754,8 +754,6 @@ struct anv_device {
 
 struct anv_scratch_pool scratch_pool;
 
-uint32_tdefault_mocs;
-
 pthread_mutex_t mutex;
 pthread_cond_t  queue_submit;
 boollost;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 280efcc..a23ab41 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -782,8 +782,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
},
   .aux_surf = &image->aux_surface.isl,
   .aux_usage = image->aux_usage == ISL_AUX_USAGE_NONE ?
-   ISL_AUX_USAGE_CCS_D : image->aux_usage,
-  .mocs = cmd_buffer->device->default_mocs);
+   ISL_AUX_USAGE_CCS_D : image->aux_usage);
   add_image_relocs(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
image->aux_usage == ISL_AUX_USAGE_CCS_E ?
ISL_AUX_USAGE_CCS_E : ISL_AUX_USAGE_CCS_D,
@@ -934,8 +933,7 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer 
*cmd_buffer,
 .view = &view,
 .aux_surf = &iview->image->aux_surface.isl,
 .aux_usage = state->attachments[i].aux_u

[Mesa-dev] [PATCH 2/5] intel/blorp: Delete the MOCS plumbing

2017-08-01 Thread Jason Ekstrand
---
 src/intel/blorp/blorp.h   |  6 --
 src/intel/blorp/blorp_genX_exec.h | 37 +++
 src/intel/vulkan/anv_blorp.c  |  3 ---
 src/mesa/drivers/dri/i965/brw_blorp.c | 15 --
 4 files changed, 24 insertions(+), 37 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index d19920e..345e4f6 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -45,12 +45,6 @@ struct blorp_context {
 
const struct brw_compiler *compiler;
 
-   struct {
-  uint32_t tex;
-  uint32_t rb;
-  uint32_t vb;
-   } mocs;
-
bool (*lookup_shader)(struct blorp_context *blorp,
  const void *key, uint32_t key_size,
  uint32_t *kernel_out, void *prog_data_out);
diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 9353416..ff17f21 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -28,6 +28,7 @@
 #include "common/gen_device_info.h"
 #include "common/gen_sample_positions.h"
 #include "genxml/gen_macros.h"
+#include "i915_drm.h"
 
 /**
  * This file provides the blorp pipeline setup and execution functionality.
@@ -257,6 +258,25 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
blorp_flush_range(batch, data, *size);
 }
 
+#if GEN_GEN >= 6
+static uint32_t
+get_vb_mocs()
+{
+#if GEN_GEN == 6
+   return 0; /* PTE */
+#elif GEN_GEN == 7
+   return 1; /* Cache in L3$, LLC and eLLC use PTE */
+#elif GEN_GEN == 8
+   return 0x78; /* LLC and eLLC are forced to WB */
+#elif GEN_GEN >= 9
+   /* We have to shift by one because of a reserved bit in the MOCS field */
+   return I915_MOCS_CACHED << 1;
+#else
+#  error "Unknown hardware generation"
+#endif
+}
+#endif
+
 static void
 blorp_emit_vertex_buffers(struct blorp_batch *batch,
   const struct blorp_params *params)
@@ -269,7 +289,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
vb[0].VertexBufferIndex = 0;
vb[0].BufferPitch = 3 * sizeof(float);
 #if GEN_GEN >= 6
-   vb[0].VertexBufferMOCS = batch->blorp->mocs.vb;
+   vb[0].VertexBufferMOCS = get_vb_mocs();
 #endif
 #if GEN_GEN >= 7
vb[0].AddressModifyEnable = true;
@@ -290,7 +310,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
vb[1].VertexBufferIndex = 1;
vb[1].BufferPitch = 0;
 #if GEN_GEN >= 6
-   vb[1].VertexBufferMOCS = batch->blorp->mocs.vb;
+   vb[1].VertexBufferMOCS = get_vb_mocs();
 #endif
 #if GEN_GEN >= 7
vb[1].AddressModifyEnable = true;
@@ -1235,13 +1255,10 @@ blorp_emit_surface_state(struct blorp_batch *batch,
  write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
}
 
-   const uint32_t mocs =
-  is_render_target ? batch->blorp->mocs.rb : batch->blorp->mocs.tex;
-
isl_surf_fill_state(batch->blorp->isl_dev, state,
.surf = &surf, .view = &surface->view,
.aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
-   .mocs = mocs, .clear_color = surface->clear_color,
+   .clear_color = surface->clear_color,
.write_disables = write_disable_mask);
 
blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
@@ -1363,13 +1380,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch 
*batch,
if (dw == NULL)
   return;
 
-   struct isl_depth_stencil_hiz_emit_info info = {
-#if GEN_GEN >= 7
-  .mocs = 1, /* GEN7_MOCS_L3 */
-#else
-  .mocs = 0,
-#endif
-   };
+   struct isl_depth_stencil_hiz_emit_info info = { 0, };
 
if (params->depth.enabled) {
   info.view = ¶ms->depth.view;
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 860e50a..4f7ae63 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -92,9 +92,6 @@ anv_device_init_blorp(struct anv_device *device)
anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
blorp_init(&device->blorp, device, &device->isl_dev);
device->blorp.compiler = device->instance->physicalDevice.compiler;
-   device->blorp.mocs.tex = device->default_mocs;
-   device->blorp.mocs.rb = device->default_mocs;
-   device->blorp.mocs.vb = device->default_mocs;
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
switch (device->info.gen) {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index b2987ca..f15f467 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -82,15 +82,9 @@ brw_blorp_init(struct brw_context *brw)
   brw->blorp.exec = gen5_blorp_exec;
   break;
case 6:
-  brw->blorp.mocs.tex = 0;
-  brw->blorp.mocs.rb = 0;
-  brw->blorp.mocs.vb = 0;
   brw->blorp.exec = gen6_blorp_exec;
   break;
case 7:
-  brw->blorp.mocs.tex = GEN7_MOCS_L3;
-  brw->blorp.mocs.rb = GEN7_MOCS_L3

[Mesa-dev] [PATCH 5/5] intel/isl: Get rid of the mocs fields in fill/emit_info

2017-08-01 Thread Jason Ekstrand
They are now unused.
---
 src/intel/isl/isl.h | 22 --
 1 file changed, 22 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index dafe952..e392f72 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1254,13 +1254,6 @@ struct isl_surf_fill_state_info {
uint64_t address;
 
/**
-* The Memory Object Control state for the filled surface state.
-*
-* The exact format of this value depends on hardware generation.
-*/
-   uint32_t mocs;
-
-   /**
 * The auxilary surface or NULL if no auxilary surface is to be used.
 */
const struct isl_surf *aux_surf;
@@ -1295,13 +1288,6 @@ struct isl_buffer_fill_state_info {
uint64_t size;
 
/**
-* The Memory Object Control state for the filled surface state.
-*
-* The exact format of this value depends on hardware generation.
-*/
-   uint32_t mocs;
-
-   /**
 * The format to use in the surface state
 *
 * This may differ from the format of the actual isl_surf but have the
@@ -1347,14 +1333,6 @@ struct isl_depth_stencil_hiz_emit_info {
uint64_t stencil_address;
 
/**
-* The Memory Object Control state for depth and stencil buffers
-*
-* Both depth and stencil will get the same MOCS value.  The exact format
-* of this value depends on hardware generation.
-*/
-   uint32_t mocs;
-
-   /**
 * The HiZ surface or NULL if HiZ is disabled.
 */
const struct isl_surf *hiz_surf;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 3/5] i965: Stop passing MOCS information into ISL

2017-08-01 Thread Jason Ekstrand
As of a couple of commits ago, ISL is ignoring it.
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 26 
 1 file changed, 4 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a0ca6dd..4d87eca 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -60,20 +60,6 @@ enum {
INTEL_AUX_BUFFER_DISABLED = 1 << 1,
 };
 
-uint32_t tex_mocs[] = {
-   [7] = GEN7_MOCS_L3,
-   [8] = BDW_MOCS_WB,
-   [9] = SKL_MOCS_WB,
-   [10] = CNL_MOCS_WB,
-};
-
-uint32_t rb_mocs[] = {
-   [7] = GEN7_MOCS_L3,
-   [8] = BDW_MOCS_PTE,
-   [9] = SKL_MOCS_PTE,
-   [10] = CNL_MOCS_PTE,
-};
-
 static void
 get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
  GLenum target, struct isl_view *view,
@@ -132,7 +118,7 @@ brw_emit_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLenum target, struct isl_view view,
enum isl_aux_usage aux_usage,
-   uint32_t mocs, uint32_t *surf_offset, int surf_index,
+   uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
 {
uint32_t tile_x = mt->level[0].level_x;
@@ -183,7 +169,7 @@ brw_emit_surface_state(struct brw_context *brw,
.address = mt->bo->offset64 + offset,
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
-   .mocs = mocs, .clear_color = clear_color,
+   .clear_color = clear_color,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
 
brw_emit_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset,
@@ -244,7 +230,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 
uint32_t offset;
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
-  rb_mocs[brw->gen],
   &offset, surf_index,
   I915_GEM_DOMAIN_RENDER,
   I915_GEM_DOMAIN_RENDER);
@@ -589,7 +574,6 @@ brw_update_texture_surface(struct gl_context *ctx,
  aux_usage = ISL_AUX_USAGE_NONE;
 
   brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
- tex_mocs[brw->gen],
  surf_offset, surf_index,
  I915_GEM_DOMAIN_SAMPLER, 0);
}
@@ -614,8 +598,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
  .address = (bo ? bo->offset64 : 0) + buffer_offset,
  .size = buffer_size,
  .format = surface_format,
- .stride = pitch,
- .mocs = tex_mocs[brw->gen]);
+ .stride = pitch);
 
if (bo) {
   brw_emit_reloc(&brw->batch, *out_offset + brw->isl_dev.ss.addr_offset,
@@ -1163,7 +1146,6 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
aux_usage = ISL_AUX_USAGE_NONE;
 
 brw_emit_surface_state(brw, irb->mt, target, view, aux_usage,
-   tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
 
@@ -1652,7 +1634,7 @@ update_image_surface(struct brw_context *brw,
view.base_array_layer,
view.array_len));
 brw_emit_surface_state(brw, mt, mt->target, view,
-   ISL_AUX_USAGE_NONE, tex_mocs[brw->gen],
+   ISL_AUX_USAGE_NONE,
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER,
access == GL_READ_ONLY ? 0 :
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 0/5] intel/isl: Set MOCS based on view usage

2017-08-01 Thread Jason Ekstrand
This little series changes things around so that, instead of passing MOCS
values into ISL, ISL knows how to set them itself.  This allows us to
centralize some of the decisions about how MOCS gets set for surfaces and
hopefully, if we ever do anything crazy in the future, we can share it
between GL and Vulkan.  Unfortunately, surfaces are not the only places
where MOCS is used.  It also shows up in vertex buffers, index buffers, and
streamout buffers.  However those are always set to the platform equivalent
of I915_MOCS_CACHED (and that's not all that liable to change) so they're
not particularly interesting.

If people like this approach, I'd like to Cc it to stable for 17.2 because
it has the side-effect of making Vulkan MOCS a bit more sane.

Jason Ekstrand (5):
  intel/isl: Set MOCS based on usage for surface states
  intel/blorp: Delete the MOCS plumbing
  i965: Stop passing MOCS information into ISL
  anv: Stop passing MOCS information into ISL
  intel/isl: Get rid of the mocs fields in fill/emit_info

 src/intel/blorp/blorp.h  |  6 ---
 src/intel/blorp/blorp_genX_exec.h| 37 +++--
 src/intel/isl/isl.h  | 22 --
 src/intel/isl/isl_emit_depth_stencil.c   | 12 +++---
 src/intel/isl/isl_genX_mocs.h| 53 
 src/intel/isl/isl_surface_state.c|  9 ++--
 src/intel/vulkan/anv_blorp.c |  3 --
 src/intel/vulkan/anv_device.c|  1 -
 src/intel/vulkan/anv_image.c | 12 ++
 src/intel/vulkan/anv_private.h   |  2 -
 src/intel/vulkan/genX_cmd_buffer.c   | 13 ++
 src/intel/vulkan/genX_state.c|  3 --
 src/mesa/drivers/dri/i965/brw_blorp.c| 15 ---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 26 ++--
 14 files changed, 101 insertions(+), 113 deletions(-)
 create mode 100644 src/intel/isl/isl_genX_mocs.h

-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 2/5] anv: Add MAX_API_VERSION to anv_extensions.py

2017-08-01 Thread Lionel Landwerlin

On 01/08/17 23:32, Jason Ekstrand wrote:
On Tue, Aug 1, 2017 at 2:07 PM, Lionel Landwerlin 
mailto:lionel.g.landwer...@intel.com>> 
wrote:


On 01/08/17 19:54, Jason Ekstrand wrote:

The VkVersion class is probably overkill but it makes it
really easy to
compare versions in a way that's safe without the caller
having to think
about patch vs. no patch.
---
  src/intel/vulkan/anv_entrypoints_gen.py |  4 +--
  src/intel/vulkan/anv_extensions.py  | 43
+
  2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
b/src/intel/vulkan/anv_entrypoints_gen.py
index 9177a94..f5c527e 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -32,8 +32,6 @@ from mako.template import Template
from anv_extensions import *
  -MAX_API_VERSION = 1.0
-
  # We generate a static hash table for entry point lookup
  # (vkGetProcAddress). We use a linear congruential generator
for our hash
  # function and a power-of-two size table. The prime numbers
are determined
@@ -262,7 +260,7 @@ def get_entrypoints(doc,
entrypoints_to_defines):
  enabled_commands = set()
  for feature in doc.findall('./feature'):
  assert feature.attrib['api'] == 'vulkan'
-if float(feature.attrib['number']) > MAX_API_VERSION:
+if VkVersion(feature.attrib['number']) > MAX_API_VERSION:
  continue
for command in feature.findall('./require/command'):
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 0d243c6..7307cac 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -25,10 +25,14 @@ COPYRIGHT = """\
  """
import argparse
+import copy
+import re
  import xml.etree.cElementTree as et
from mako.template import Template
  +MAX_API_VERSION = '1.0.54'
+
  class Extension:
  def __init__(self, name, ext_version, enable):
self.name  = name
@@ -64,6 +68,45 @@ EXTENSIONS = [
  Extension('VK_KHX_multiview',1, True),
  ]
  +class VkVersion:
+def __init__(self, string):
+split = string.split('.')
+self.major = int(split[0])
+self.minor = int(split[1])
+if len(split) > 2:
+assert len(split) == 3
+self.patch = int(split[2])
+else:
+self.patch = None
+
+# Sanity check.  The range bits are required by the
definition of the
+# VK_MAKE_VERSION macro
+assert self.major < 1024 and self.minor < 1024
+assert self.patch is None or self.patch < 4096
+assert(str(self) == string)
+
+def __str__(self):
+ver_list = [str(self.major), str(self.minor)]
+if self.patch is not None:
+ver_list.append(str(self.patch))
+return '.'.join(ver_list)
+
+def __int_ver(self):
+# This is just an expansion of VK_VERSION
+patch = self.patch if self.patch is not None else 0
+return (self.major << 22) | (self.minor << 12) | patch
+
+def __cmp__(self, other):
+# If only one of them has a patch version, "ignore"
it by making
+# other's patch version match self.
+if (self.patch is None) != (other.patch is None):
+other = copy.copy(other)
+other.patch = self.patch
+
+return self.__int_ver().__cmp__(other.__int_ver())
+
+MAX_API_VERSION = VkVersion(MAX_API_VERSION)


Why not just MAX_API_VERSION = VkVersion('1.0.54') ?


Because I wanted the obvious declaration MAX_API_VERSION to go as high 
up in the file as possible for readability.  VkVersion is an 
annoyingly complicated class and I didn't want it cluttering the top 
of the file.  The end result is this little bit of uglyness.  I'm not 
sure if it was worth it.


--Jason


Alright, I thought maybe I was missing something :

Reviewed-by: Lionel Landwerlin 


+
  def _init_exts_from_xml(xml):
  """ Walk the Vulkan XML and fill out extra extension
information. """






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_

Re: [Mesa-dev] [PATCH 2/2] anv: Advertise VK_KHR_relaxed_block_layout

2017-08-01 Thread Lionel Landwerlin

On 01/08/17 23:33, Jason Ekstrand wrote:
On Tue, Aug 1, 2017 at 2:03 PM, Lionel Landwerlin 
mailto:lionel.g.landwer...@intel.com>> 
wrote:


Since this is available from 1.0.57, do we need to bump the
supported API version first?


I don't think it really matters


Rb then :)


On 01/08/17 17:02, Jason Ekstrand wrote:

There is literally no work for us to do here.  It already just
works in
our driver.
---
  src/intel/vulkan/anv_device.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c
b/src/intel/vulkan/anv_device.c
index f69ebfc..b171c2b 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -477,6 +477,10 @@ static const VkExtensionProperties
device_extensions[] = {
.specVersion = 1,
 },
 {
+  .extensionName =
VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME,
+  .specVersion = 1,
+   },
+   {
.extensionName =
VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
.specVersion = 1,
 },






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[Mesa-dev] [RFC] intel: Common MOCS metadata straw-man

2017-08-01 Thread Jason Ekstrand
This is more of a straw-man patch than something I intend to land today.
The idea is to come up with some central way of representing MOCS that
we can use from either GL or Vulkan.  I have no idea if this is how we
want to represent MOCS or not.  There are many alternative approaches:

 1) Having a selection function that takes a devinfo and a fiew pieces
of data and returns a mocs value based on some sort of weights.

 2) Using a finitely enumerated set of values (the kernel already has
such an enum) and simply map them onto something "sensible" for
older hardware generations

 3) ...

I have no idea whether or not this approach of having a table full of
metadata is useful or not.  With the table, one could implement (1)
above by just walking the table.  However, this is way more complex than
needed for mesa today.  I'll be sending out some ISL patches shortly
which take a completely different approach.  Thoughs?

Cc: Ben Widawsky 
Cc: Francisco Jerez 
Cc: Kenneth Graunke 
---
 src/intel/common/gen_mocs.c | 115 
 src/intel/common/gen_mocs.h |  71 +++
 2 files changed, 186 insertions(+)
 create mode 100644 src/intel/common/gen_mocs.c
 create mode 100644 src/intel/common/gen_mocs.h

diff --git a/src/intel/common/gen_mocs.c b/src/intel/common/gen_mocs.c
new file mode 100644
index 000..544deec
--- /dev/null
+++ b/src/intel/common/gen_mocs.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "gen_mocs.h"
+
+/* Get rid of some prefixes */
+#define CC_UC  GEN_MOCS_CC_UC
+#define CC_WB  GEN_MOCS_CC_WB
+#define CC_WT  GEN_MOCS_CC_WT
+#define CC_PTE GEN_MOCS_CC_PTE
+
+static const struct gen_mocs_info snb_mocs[] = {
+   { .mocs = 0x0,.l3 = CC_PTE,  .llc = CC_PTE, .ellc = CC_UC  },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info ivb_mocs[] = {
+   { .mocs = 0x1,.l3 = CC_WB,   .llc = CC_PTE, .ellc = CC_UC  },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info byt_mocs[] = {
+   { .mocs = 0x1,.l3 = CC_WB,   .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info hsw_mocs[] = {
+   { .mocs = 0x1,.l3 = CC_WB,   .llc = CC_PTE, .ellc = CC_PTE },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info bdw_mocs[] = {
+   { .mocs = 0x78,   .l3 = CC_WB,   .llc = CC_WB,  .ellc = CC_WB  },
+   { .mocs = 0x58,   .l3 = CC_WB,   .llc = CC_WT,  .ellc = CC_WT  },
+   { .mocs = 0x18,   .l3 = CC_WB,   .llc = CC_PTE, .ellc = CC_PTE },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info chv_mocs[] = {
+   { .mocs = 0x78,   .l3 = CC_WB,   .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = 0x18,   .l3 = CC_UC,   .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info skl_mocs[] = {
+   { .mocs = 0,  .l3 = CC_UC,   .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = 1,  .l3 = CC_PTE,  .llc = CC_PTE, .ellc = CC_PTE },
+   { .mocs = 3,  .l3 = CC_WB,   .llc = CC_WB,  .ellc = CC_WB  },
+   { .mocs = MOCS_INVALID }
+};
+
+static const struct gen_mocs_info bxt_mocs[] = {
+   { .mocs = 0,  .l3 = CC_UC,   .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = 1,  .l3 = CC_PTE,  .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = 3,  .l3 = CC_WB,   .llc = CC_UC,  .ellc = CC_UC  },
+   { .mocs = MOCS_INVALID }
+};
+
+/* Sky Lake and Cannon Lake tables are the same today */
+static const struct gen_mocs_info *cnl_mocs = skl_mocs;
+
+const struct gen_mocs_info *
+gen_get_mocs_table(const struct gen_device_info *devinfo)
+{
+   switch (devinfo->gen) {
+   case 6:
+  return snb_mocs;
+
+   case 7:
+  if (devinfo->is_baytrail)
+ return byt_mocs;
+  else if (devinfo->is_haswell)
+ return hsw_mocs;
+  else
+ return ivb_

Re: [Mesa-dev] [PATCH 2/2] anv: Advertise VK_KHR_relaxed_block_layout

2017-08-01 Thread Jason Ekstrand
On Tue, Aug 1, 2017 at 2:03 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> Since this is available from 1.0.57, do we need to bump the supported API
> version first?
>

I don't think it really matters


> On 01/08/17 17:02, Jason Ekstrand wrote:
>
>> There is literally no work for us to do here.  It already just works in
>> our driver.
>> ---
>>   src/intel/vulkan/anv_device.c | 4 
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.
>> c
>> index f69ebfc..b171c2b 100644
>> --- a/src/intel/vulkan/anv_device.c
>> +++ b/src/intel/vulkan/anv_device.c
>> @@ -477,6 +477,10 @@ static const VkExtensionProperties
>> device_extensions[] = {
>> .specVersion = 1,
>>  },
>>  {
>> +  .extensionName = VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME,
>> +  .specVersion = 1,
>> +   },
>> +   {
>> .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO
>> _EDGE_EXTENSION_NAME,
>> .specVersion = 1,
>>  },
>>
>
>
>
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Re: [Mesa-dev] [PATCH 2/5] anv: Add MAX_API_VERSION to anv_extensions.py

2017-08-01 Thread Jason Ekstrand
On Tue, Aug 1, 2017 at 2:07 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 01/08/17 19:54, Jason Ekstrand wrote:
>
>> The VkVersion class is probably overkill but it makes it really easy to
>> compare versions in a way that's safe without the caller having to think
>> about patch vs. no patch.
>> ---
>>   src/intel/vulkan/anv_entrypoints_gen.py |  4 +--
>>   src/intel/vulkan/anv_extensions.py  | 43
>> +
>>   2 files changed, 44 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
>> b/src/intel/vulkan/anv_entrypoints_gen.py
>> index 9177a94..f5c527e 100644
>> --- a/src/intel/vulkan/anv_entrypoints_gen.py
>> +++ b/src/intel/vulkan/anv_entrypoints_gen.py
>> @@ -32,8 +32,6 @@ from mako.template import Template
>> from anv_extensions import *
>>   -MAX_API_VERSION = 1.0
>> -
>>   # We generate a static hash table for entry point lookup
>>   # (vkGetProcAddress). We use a linear congruential generator for our
>> hash
>>   # function and a power-of-two size table. The prime numbers are
>> determined
>> @@ -262,7 +260,7 @@ def get_entrypoints(doc, entrypoints_to_defines):
>>   enabled_commands = set()
>>   for feature in doc.findall('./feature'):
>>   assert feature.attrib['api'] == 'vulkan'
>> -if float(feature.attrib['number']) > MAX_API_VERSION:
>> +if VkVersion(feature.attrib['number']) > MAX_API_VERSION:
>>   continue
>> for command in feature.findall('./require/command'):
>> diff --git a/src/intel/vulkan/anv_extensions.py
>> b/src/intel/vulkan/anv_extensions.py
>> index 0d243c6..7307cac 100644
>> --- a/src/intel/vulkan/anv_extensions.py
>> +++ b/src/intel/vulkan/anv_extensions.py
>> @@ -25,10 +25,14 @@ COPYRIGHT = """\
>>   """
>> import argparse
>> +import copy
>> +import re
>>   import xml.etree.cElementTree as et
>> from mako.template import Template
>>   +MAX_API_VERSION = '1.0.54'
>> +
>>   class Extension:
>>   def __init__(self, name, ext_version, enable):
>>   self.name = name
>> @@ -64,6 +68,45 @@ EXTENSIONS = [
>>   Extension('VK_KHX_multiview', 1, True),
>>   ]
>>   +class VkVersion:
>> +def __init__(self, string):
>> +split = string.split('.')
>> +self.major = int(split[0])
>> +self.minor = int(split[1])
>> +if len(split) > 2:
>> +assert len(split) == 3
>> +self.patch = int(split[2])
>> +else:
>> +self.patch = None
>> +
>> +# Sanity check.  The range bits are required by the definition
>> of the
>> +# VK_MAKE_VERSION macro
>> +assert self.major < 1024 and self.minor < 1024
>> +assert self.patch is None or self.patch < 4096
>> +assert(str(self) == string)
>> +
>> +def __str__(self):
>> +ver_list = [str(self.major), str(self.minor)]
>> +if self.patch is not None:
>> +ver_list.append(str(self.patch))
>> +return '.'.join(ver_list)
>> +
>> +def __int_ver(self):
>> +# This is just an expansion of VK_VERSION
>> +patch = self.patch if self.patch is not None else 0
>> +return (self.major << 22) | (self.minor << 12) | patch
>> +
>> +def __cmp__(self, other):
>> +# If only one of them has a patch version, "ignore" it by making
>> +# other's patch version match self.
>> +if (self.patch is None) != (other.patch is None):
>> +other = copy.copy(other)
>> +other.patch = self.patch
>> +
>> +return self.__int_ver().__cmp__(other.__int_ver())
>> +
>> +MAX_API_VERSION = VkVersion(MAX_API_VERSION)
>>
>
> Why not just MAX_API_VERSION = VkVersion('1.0.54') ?
>

Because I wanted the obvious declaration MAX_API_VERSION to go as high up
in the file as possible for readability.  VkVersion is an annoyingly
complicated class and I didn't want it cluttering the top of the file.  The
end result is this little bit of uglyness.  I'm not sure if it was worth it.

--Jason


> +
>>   def _init_exts_from_xml(xml):
>>   """ Walk the Vulkan XML and fill out extra extension information.
>> """
>>
>>
>
>
>
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[Mesa-dev] [Bug 97852] Unreal Engine corrupted preview viewport

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=97852

--- Comment #10 from Markus  ---
Any news on this?

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[Mesa-dev] [Bug 102003] Mesa demos doesn't compile due to gles1

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102003

Mike Lothian  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #3 from Mike Lothian  ---
The commit 3db05ed1d10738d0c2f14cb692d5d618c5872dcd fixed it

Thanks

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Re: [Mesa-dev] [PATCH 6/6] egl/x11: use dri2_create_image_khr for swrast

2017-08-01 Thread Gurchetan Singh
Thanks for the reviews!  I rebased patch number #4, and added
platform_wayland support and squashed this patch to form patch #5.  Note it
seems platform_drm already has the correct path for swrast,
since gbm_dri_screen_extensions already has the lookup extension and the
dri2_drm_display_vtbl is used regardless whether the driver is hardware or
swrast.

On Tue, Aug 1, 2017 at 8:55 AM, Emil Velikov 
wrote:

> On 28 July 2017 at 04:48, Gurchetan Singh 
> wrote:
> > This will allow the swrast driver to use eglCreateImageKHR,
> > provided the target is EGL_GL_TEXTURE_2D_KHR or
> > EGL_GL_RENDERBUFFER_KHR.  Note we still have to implement the
> > create from render buffer path.
> Thanks for the re-spin Gurchetan!
>
> Implementing the renderbuffer path would be great. None of the gallium
> drivers currently support it ;-)
>
> A couple of small suggestions:
>  - 5/6 effectively enables the extensions, thus it should be the last
> in the series
>  - the drm and wayland platforms could use a patch similar to this,
> otherwise they'll advertise the extensions but the API will always
> fail
> Feel free to squash with this patch, keep separate or simply force
> disable the extensions on said platforms.
>
> With that the series is
> Reviewed-by: Emil Velikov 
>
> -Emil
>
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[Mesa-dev] [PATCH 5/5] egl/dri2: add image extension such it's usable by swrast driver

2017-08-01 Thread Gurchetan Singh
Otherwise, this extension is not visible to the EGL users who
use the swrast driver.

This will allow the swrast driver to use eglCreateImageKHR,
provided the target is EGL_GL_TEXTURE_2D_KHR or
EGL_GL_RENDERBUFFER_KHR.  Note we still have to implement the
create from render buffer path.

v2: add it to optional_core_extensions instead of swrast_core_extensions,
so it's not a requirement (Emil)
v3: Merge egl/dri2 changes together, also add support for
platform_wayland (Emil)
---
 src/egl/drivers/dri2/egl_dri2.c | 1 +
 src/egl/drivers/dri2/platform_wayland.c | 3 ++-
 src/egl/drivers/dri2/platform_x11.c | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index a197e0456f..31a984fab9 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -435,6 +435,7 @@ static const struct dri2_extension_match 
optional_core_extensions[] = {
{ __DRI2_FENCE, 1, offsetof(struct dri2_egl_display, fence) },
{ __DRI2_RENDERER_QUERY, 1, offsetof(struct dri2_egl_display, 
rendererQuery) },
{ __DRI2_INTEROP, 1, offsetof(struct dri2_egl_display, interop) },
+   { __DRI_IMAGE, 1, offsetof(struct dri2_egl_display, image) },
{ NULL, 0, 0 }
 };
 
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 73966b7c50..a11eaedefd 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1883,7 +1883,7 @@ static const struct dri2_egl_display_vtbl 
dri2_wl_swrast_display_vtbl = {
.create_pixmap_surface = dri2_wl_create_pixmap_surface,
.create_pbuffer_surface = dri2_fallback_create_pbuffer_surface,
.destroy_surface = dri2_wl_destroy_surface,
-   .create_image = dri2_fallback_create_image_khr,
+   .create_image = dri2_create_image_khr,
.swap_buffers = dri2_wl_swrast_swap_buffers,
.swap_buffers_with_damage = dri2_fallback_swap_buffers_with_damage,
.swap_buffers_region = dri2_fallback_swap_buffers_region,
@@ -1906,6 +1906,7 @@ static const __DRIswrastLoaderExtension 
swrast_loader_extension = {
 
 static const __DRIextension *swrast_loader_extensions[] = {
&swrast_loader_extension.base,
+   &image_lookup_extension.base,
NULL,
 };
 
diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index 35c62a4975..07ef610f0d 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1126,7 +1126,7 @@ static const struct dri2_egl_display_vtbl 
dri2_x11_swrast_display_vtbl = {
.create_pixmap_surface = dri2_x11_create_pixmap_surface,
.create_pbuffer_surface = dri2_x11_create_pbuffer_surface,
.destroy_surface = dri2_x11_destroy_surface,
-   .create_image = dri2_fallback_create_image_khr,
+   .create_image = dri2_create_image_khr,
.swap_interval = dri2_fallback_swap_interval,
.swap_buffers = dri2_x11_swap_buffers,
.set_damage_region = dri2_fallback_set_damage_region,
@@ -1171,6 +1171,7 @@ static const __DRIswrastLoaderExtension 
swrast_loader_extension = {
 
 static const __DRIextension *swrast_loader_extensions[] = {
&swrast_loader_extension.base,
+   &image_lookup_extension.base,
NULL,
 };
 
-- 
2.14.0.rc1.383.gd1ce394fe2-goog

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[Mesa-dev] [PATCH 4/5] st/dri: add drisw image extension

2017-08-01 Thread Gurchetan Singh
Since the revelant functions have been moved to dri_helpers,
drisw.c can make use of the extension. Note we have version 6
of the extension, since we want to support createImageFromTexture.

v2: Rebase to master
---
 src/gallium/state_trackers/dri/drisw.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/gallium/state_trackers/dri/drisw.c 
b/src/gallium/state_trackers/dri/drisw.c
index dc3415e3b4..db5159e45c 100644
--- a/src/gallium/state_trackers/dri/drisw.c
+++ b/src/gallium/state_trackers/dri/drisw.c
@@ -362,6 +362,14 @@ drisw_update_tex_buffer(struct dri_drawable *drawable,
pipe_transfer_unmap(pipe, transfer);
 }
 
+static __DRIimageExtension driSWImageExtension = {
+.base = { __DRI_IMAGE, 6 },
+
+.createImageFromRenderbuffer  = dri2_create_image_from_renderbuffer,
+.createImageFromTexture = dri2_create_from_texture,
+.destroyImage = dri2_destroy_image,
+};
+
 /*
  * Backend function for init_screen.
  */
@@ -372,6 +380,7 @@ static const __DRIextension *drisw_screen_extensions[] = {
&dri2ConfigQueryExtension.base,
&dri2FenceExtension.base,
&dri2NoErrorExtension.base,
+   &driSWImageExtension.base,
NULL
 };
 
@@ -412,6 +421,8 @@ drisw_init_screen(__DRIscreen * sPriv)
if (!configs)
   goto fail;
 
+   screen->lookup_egl_image = dri2_lookup_egl_image;
+
return configs;
 fail:
dri_destroy_screen_helper(screen);
-- 
2.14.0.rc1.383.gd1ce394fe2-goog

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Re: [Mesa-dev] [PATCH] radeon/ac: use ds_swizzle for derivs on si/cik.

2017-08-01 Thread Marek Olšák
Tested on SI.

Acked-by: Marek Olšák 

Marek

On Tue, Aug 1, 2017 at 6:14 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This looks like it's supported since llvm 3.9 at least,
> so switch over radeonsi and radv to using it, -pro also
> uses this. We can now drop creating lds for these operations
> as the ds_swizzle operation doesn't actually write to lds at all.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/common/ac_llvm_build.c   | 57 
> +++-
>  src/amd/common/ac_llvm_build.h   |  1 -
>  src/amd/common/ac_nir_to_llvm.c  |  9 +
>  src/gallium/drivers/radeonsi/si_shader.c | 16 +
>  4 files changed, 44 insertions(+), 39 deletions(-)
>
> diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
> index 9b939c1..a38aad6 100644
> --- a/src/amd/common/ac_llvm_build.c
> +++ b/src/amd/common/ac_llvm_build.c
> @@ -796,21 +796,21 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
>   bool has_ds_bpermute,
>   uint32_t mask,
>   int idx,
> - LLVMValueRef lds,
>   LLVMValueRef val)
>  {
> -   LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, args[2];
> +   LLVMValueRef tl, trbl, args[2];
> LLVMValueRef result;
>
> -   thread_id = ac_get_thread_id(ctx);
> +   if (has_ds_bpermute) {
> +   LLVMValueRef thread_id, tl_tid, trbl_tid;
> +   thread_id = ac_get_thread_id(ctx);
>
> -   tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
> - LLVMConstInt(ctx->i32, mask, false), "");
> +   tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
> + LLVMConstInt(ctx->i32, mask, false), 
> "");
>
> -   trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
> -   LLVMConstInt(ctx->i32, idx, false), "");
> +   trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
> +   LLVMConstInt(ctx->i32, idx, false), 
> "");
>
> -   if (has_ds_bpermute) {
> args[0] = LLVMBuildMul(ctx->builder, tl_tid,
>LLVMConstInt(ctx->i32, 4, false), "");
> args[1] = val;
> @@ -828,15 +828,42 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
>   AC_FUNC_ATTR_READNONE |
>   AC_FUNC_ATTR_CONVERGENT);
> } else {
> -   LLVMValueRef store_ptr, load_ptr0, load_ptr1;
> +   uint32_t masks[2];
> +
> +   switch (mask) {
> +   case AC_TID_MASK_TOP_LEFT:
> +   masks[0] = 0x8000;
> +   if (idx == 1)
> +   masks[1] = 0x8055;
> +   else
> +   masks[1] = 0x80aa;
> +
> +   break;
> +   case AC_TID_MASK_TOP:
> +   masks[0] = 0x8044;
> +   masks[1] = 0x80ee;
> +   break;
> +   case AC_TID_MASK_LEFT:
> +   masks[0] = 0x80a0;
> +   masks[1] = 0x80f5;
> +   break;
> +   }
>
> -   store_ptr = ac_build_gep0(ctx, lds, thread_id);
> -   load_ptr0 = ac_build_gep0(ctx, lds, tl_tid);
> -   load_ptr1 = ac_build_gep0(ctx, lds, trbl_tid);
> +   args[0] = val;
> +   args[1] = LLVMConstInt(ctx->i32, masks[0], false);
>
> -   LLVMBuildStore(ctx->builder, val, store_ptr);
> -   tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
> -   trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
> +   tl = ac_build_intrinsic(ctx,
> +   "llvm.amdgcn.ds.swizzle", ctx->i32,
> +   args, 2,
> +   AC_FUNC_ATTR_READNONE |
> +   AC_FUNC_ATTR_CONVERGENT);
> +
> +   args[1] = LLVMConstInt(ctx->i32, masks[1], false);
> +   trbl = ac_build_intrinsic(ctx,
> +   "llvm.amdgcn.ds.swizzle", ctx->i32,
> +   args, 2,
> +   AC_FUNC_ATTR_READNONE |
> +   AC_FUNC_ATTR_CONVERGENT);
> }
>
> tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
> diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
> index 09fd585..ee27d3c 100644
> --- a/src/amd/common/ac_llvm_build.h
> +++ b/src/amd/common/ac_llvm_build.h
> @@ -174,7 +174,6 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
>   bool has_ds_bpermute,
>   uint32_t mask,
>   int idx,
> - LLVMValueRef lds,
>   LLVMValueRef val);
>
>  #define AC_SENDMSG_GS 2
> diff --git a/s

Re: [Mesa-dev] [PATCH 1/5] anv: Make some bits of anv_extensions module-private

2017-08-01 Thread Lionel Landwerlin

Patches 1, 3, 4 & 5 are:

Reviewed-by: Lionel Landwerlin 

On 01/08/17 19:54, Jason Ekstrand wrote:

This way we can use "from anv_extensions import *" in the entrypoint
generator without worrying too much about pollution
---
  src/intel/vulkan/anv_entrypoints_gen.py | 4 ++--
  src/intel/vulkan/anv_extensions.py  | 8 
  2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 0c6e310..9177a94 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -30,7 +30,7 @@ import xml.etree.cElementTree as et
  
  from mako.template import Template
  
-import anv_extensions

+from anv_extensions import *
  
  MAX_API_VERSION = 1.0
  
@@ -268,7 +268,7 @@ def get_entrypoints(doc, entrypoints_to_defines):

  for command in feature.findall('./require/command'):
  enabled_commands.add(command.attrib['name'])
  
-supported = set(ext.name for ext in anv_extensions.EXTENSIONS)

+supported = set(ext.name for ext in EXTENSIONS)
  for extension in doc.findall('.extensions/extension'):
  if extension.attrib['name'] not in supported:
  continue
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 005a514..0d243c6 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -64,7 +64,7 @@ EXTENSIONS = [
  Extension('VK_KHX_multiview', 1, True),
  ]
  
-def init_exts_from_xml(xml):

+def _init_exts_from_xml(xml):
  """ Walk the Vulkan XML and fill out extra extension information. """
  
  xml = et.parse(xml)

@@ -84,7 +84,7 @@ def init_exts_from_xml(xml):
  for ext in EXTENSIONS:
  assert ext.type == 'instance' or ext.type == 'device'
  
-TEMPLATE = Template(COPYRIGHT + """

+_TEMPLATE = Template(COPYRIGHT + """
  #include "anv_private.h"
  
  #include "vk_util.h"

@@ -172,7 +172,7 @@ if __name__ == '__main__':
  parser.add_argument('--xml', help='Vulkan API XML file.', required=True)
  args = parser.parse_args()
  
-init_exts_from_xml(args.xml)

+_init_exts_from_xml(args.xml)
  
  template_env = {

  'instance_extensions': [e for e in EXTENSIONS if e.type == 
'instance'],
@@ -180,4 +180,4 @@ if __name__ == '__main__':
  }
  
  with open(args.out, 'w') as f:

-f.write(TEMPLATE.render(**template_env))
+f.write(_TEMPLATE.render(**template_env))



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Re: [Mesa-dev] [PATCH 2/5] anv: Add MAX_API_VERSION to anv_extensions.py

2017-08-01 Thread Lionel Landwerlin

On 01/08/17 19:54, Jason Ekstrand wrote:

The VkVersion class is probably overkill but it makes it really easy to
compare versions in a way that's safe without the caller having to think
about patch vs. no patch.
---
  src/intel/vulkan/anv_entrypoints_gen.py |  4 +--
  src/intel/vulkan/anv_extensions.py  | 43 +
  2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 9177a94..f5c527e 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -32,8 +32,6 @@ from mako.template import Template
  
  from anv_extensions import *
  
-MAX_API_VERSION = 1.0

-
  # We generate a static hash table for entry point lookup
  # (vkGetProcAddress). We use a linear congruential generator for our hash
  # function and a power-of-two size table. The prime numbers are determined
@@ -262,7 +260,7 @@ def get_entrypoints(doc, entrypoints_to_defines):
  enabled_commands = set()
  for feature in doc.findall('./feature'):
  assert feature.attrib['api'] == 'vulkan'
-if float(feature.attrib['number']) > MAX_API_VERSION:
+if VkVersion(feature.attrib['number']) > MAX_API_VERSION:
  continue
  
  for command in feature.findall('./require/command'):

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 0d243c6..7307cac 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -25,10 +25,14 @@ COPYRIGHT = """\
  """
  
  import argparse

+import copy
+import re
  import xml.etree.cElementTree as et
  
  from mako.template import Template
  
+MAX_API_VERSION = '1.0.54'

+
  class Extension:
  def __init__(self, name, ext_version, enable):
  self.name = name
@@ -64,6 +68,45 @@ EXTENSIONS = [
  Extension('VK_KHX_multiview', 1, True),
  ]
  
+class VkVersion:

+def __init__(self, string):
+split = string.split('.')
+self.major = int(split[0])
+self.minor = int(split[1])
+if len(split) > 2:
+assert len(split) == 3
+self.patch = int(split[2])
+else:
+self.patch = None
+
+# Sanity check.  The range bits are required by the definition of the
+# VK_MAKE_VERSION macro
+assert self.major < 1024 and self.minor < 1024
+assert self.patch is None or self.patch < 4096
+assert(str(self) == string)
+
+def __str__(self):
+ver_list = [str(self.major), str(self.minor)]
+if self.patch is not None:
+ver_list.append(str(self.patch))
+return '.'.join(ver_list)
+
+def __int_ver(self):
+# This is just an expansion of VK_VERSION
+patch = self.patch if self.patch is not None else 0
+return (self.major << 22) | (self.minor << 12) | patch
+
+def __cmp__(self, other):
+# If only one of them has a patch version, "ignore" it by making
+# other's patch version match self.
+if (self.patch is None) != (other.patch is None):
+other = copy.copy(other)
+other.patch = self.patch
+
+return self.__int_ver().__cmp__(other.__int_ver())
+
+MAX_API_VERSION = VkVersion(MAX_API_VERSION)


Why not just MAX_API_VERSION = VkVersion('1.0.54') ?


+
  def _init_exts_from_xml(xml):
  """ Walk the Vulkan XML and fill out extra extension information. """
  



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Re: [Mesa-dev] [PATCH 2/2] anv: Advertise VK_KHR_relaxed_block_layout

2017-08-01 Thread Lionel Landwerlin
Since this is available from 1.0.57, do we need to bump the supported 
API version first?


On 01/08/17 17:02, Jason Ekstrand wrote:

There is literally no work for us to do here.  It already just works in
our driver.
---
  src/intel/vulkan/anv_device.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index f69ebfc..b171c2b 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -477,6 +477,10 @@ static const VkExtensionProperties device_extensions[] = {
.specVersion = 1,
 },
 {
+  .extensionName = VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME,
+  .specVersion = 1,
+   },
+   {
.extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
.specVersion = 1,
 },



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Re: [Mesa-dev] [PATCH] ac/nir: Add float cast before shadow comparator clamp.

2017-08-01 Thread Marek Olšák
Reviewed-by: Marek Olšák 

Marek

On Tue, Aug 1, 2017 at 12:27 PM, Bas Nieuwenhuizen
 wrote:
> LLVM complained about passing an i32 to a float clamp.
>
> Signed-off-by: Bas Nieuwenhuizen 
> Fixes: 0f9e32519bb "ac/nir: clamp shadow texture comparison value on VI"
> ---
>  src/amd/common/ac_nir_to_llvm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 530b5817af3..0ad5475e9cb 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -4492,7 +4492,8 @@ static void visit_tex(struct ac_nir_context *ctx, 
> nir_tex_instr *instr)
>
> /* Pack depth comparison value */
> if (instr->is_shadow && comparator) {
> -   LLVMValueRef z = llvm_extract_elem(&ctx->ac, comparator, 0);
> +   LLVMValueRef z = to_float(&ctx->ac,
> + llvm_extract_elem(&ctx->ac, 
> comparator, 0));
>
> /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
>  * so the depth comparison value isn't clamped for Z16 and
> --
> 2.13.3
>
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Re: [Mesa-dev] [PATCH] glsl: look up for transform feedback varyings after linking

2017-08-01 Thread Marek Olšák
Reviewed-by: Marek Olšák 

Marek

On Thu, Jul 6, 2017 at 11:12 AM, Juan A. Suarez Romero
 wrote:
> Check if shaders have transform feedback varyings also after the
> post-link step.
>
> This fixes:
> KHR-GL45.enhanced_layouts.xfb_vertex_streams
> piglit/spec/arb_enhanced_layouts/gs-stream-location-aliasing
> ---
>  src/compiler/glsl/glsl_to_nir.cpp | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
> b/src/compiler/glsl/glsl_to_nir.cpp
> index 2153004..fad08ec 100644
> --- a/src/compiler/glsl/glsl_to_nir.cpp
> +++ b/src/compiler/glsl/glsl_to_nir.cpp
> @@ -171,6 +171,9 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
>shader->info.label = ralloc_strdup(shader, shader_prog->Label);
> shader->info.has_transform_feedback_varyings =
>shader_prog->TransformFeedback.NumVarying > 0;
> +   if (shader_prog->last_vert_prog)
> +  shader->info.has_transform_feedback_varyings |=
> + shader_prog->last_vert_prog->sh.LinkedTransformFeedback->NumVarying 
> > 0;
>
> return shader;
>  }
> --
> 2.9.4
>
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Re: [Mesa-dev] [PATCH 13/13] radeonsi: enable ARB_transform_feedback_overflow_query

2017-08-01 Thread Marek Olšák
I commented on patches 9 and 11. Other than that, the series is:

Reviewed-by: Marek Olšák 

Marek

On Thu, Jul 27, 2017 at 9:14 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> ---
>  docs/features.txt  | 2 +-
>  docs/relnotes/17.3.0.html  | 2 +-
>  src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 1f628e1..6c0c697 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -303,7 +303,7 @@ Khronos, ARB, and OES extensions that are not part of any 
> OpenGL or OpenGL ES ve
>GL_ARB_sparse_texture2not started
>GL_ARB_sparse_texture_clamp   not started
>GL_ARB_texture_filter_minmax  not started
> -  GL_ARB_transform_feedback_overflow_query  DONE (i965/gen6+)
> +  GL_ARB_transform_feedback_overflow_query  DONE 
> (i965/gen6+,radeonsi)
>GL_KHR_blend_equation_advanced_coherent   DONE (i965/gen9+)
>GL_KHR_no_error   started (Timothy 
> Arceri)
>GL_KHR_texture_compression_astc_hdr   DONE (i965/bxt)
> diff --git a/docs/relnotes/17.3.0.html b/docs/relnotes/17.3.0.html
> index 335e405..f86d1a3 100644
> --- a/docs/relnotes/17.3.0.html
> +++ b/docs/relnotes/17.3.0.html
> @@ -44,7 +44,7 @@ Note: some of the new features are only available with 
> certain drivers.
>  
>
>  
> -TBD
> +GL_ARB_transform_feedback_overflow_query on radeonsi
>  
>
>  Bug fixes
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 458b218..1f890dc 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -511,6 +511,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_BINDLESS_TEXTURE:
> case PIPE_CAP_QUERY_TIMESTAMP:
> case PIPE_CAP_QUERY_TIME_ELAPSED:
> +   case PIPE_CAP_QUERY_SO_OVERFLOW_ANY:
> return 1;
>
> case PIPE_CAP_INT64:
> @@ -598,7 +599,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_UMA:
> case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
> case PIPE_CAP_POST_DEPTH_COVERAGE:
> -   case PIPE_CAP_QUERY_SO_OVERFLOW_ANY:
> return 0;
>
> case PIPE_CAP_QUERY_BUFFER_OBJECT:
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH 11/13] radeonsi: fix streamout overflow predication on VI+

2017-08-01 Thread Marek Olšák
On Thu, Jul 27, 2017 at 9:14 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> There is a firmware regression that causes failures. Work around it by
> using the compute shader for query_buffer_objects to summarize the query
> results.
> ---
>  src/amd/common/r600d_common.h   |  1 +
>  src/gallium/drivers/radeon/r600_query.c | 88 
> ++---
>  src/gallium/drivers/radeon/r600_query.h |  4 ++
>  3 files changed, 75 insertions(+), 18 deletions(-)
>
> diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h
> index 3374475..bf3fe24 100644
> --- a/src/amd/common/r600d_common.h
> +++ b/src/amd/common/r600d_common.h
> @@ -117,6 +117,7 @@
>  #define PREDICATION_OP_CLEAR 0x0
>  #define PREDICATION_OP_ZPASS 0x1
>  #define PREDICATION_OP_PRIMCOUNT 0x2
> +#define PREDICATION_OP_DX12 0x3

sid.h contains:

#define PREDICATION_OP_BOOL64 0x3

We should use the same name in both places. I'll leave the choice of
the name up to you.

Marek
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Re: [Mesa-dev] [PATCH 09/13] gallium/radeon: implement basic parts of PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE

2017-08-01 Thread Marek Olšák
Hi Nicolai,

Can you add R600_MAX_STREAM = 4 to make the code more readable?

Thanks,
Marek

On Thu, Jul 27, 2017 at 9:14 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> ---
>  src/gallium/drivers/radeon/r600_query.c | 96 
> -
>  1 file changed, 71 insertions(+), 25 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_query.c 
> b/src/gallium/drivers/radeon/r600_query.c
> index 9f33bac..4c727d6 100644
> --- a/src/gallium/drivers/radeon/r600_query.c
> +++ b/src/gallium/drivers/radeon/r600_query.c
> @@ -648,6 +648,12 @@ static struct pipe_query *r600_query_hw_create(struct 
> r600_common_screen *rscree
> query->num_cs_dw_end = 6;
> query->stream = index;
> break;
> +   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
> +   /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
> +   query->result_size = 32 * 4;
> +   query->num_cs_dw_begin = 6 * 4;
> +   query->num_cs_dw_end = 6 * 4;
> +   break;
> case PIPE_QUERY_PIPELINE_STATISTICS:
> /* 11 values on EG, 8 on R600. */
> query->result_size = (rscreen->chip_class >= EVERGREEN ? 11 : 
> 8) * 16;
> @@ -696,9 +702,9 @@ static void r600_update_occlusion_query_state(struct 
> r600_common_context *rctx,
> }
>  }
>
> -static unsigned event_type_for_stream(struct r600_query_hw *query)
> +static unsigned event_type_for_stream(unsigned stream)
>  {
> -   switch (query->stream) {
> +   switch (stream) {
> default:
> case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
> case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
> @@ -707,6 +713,15 @@ static unsigned event_type_for_stream(struct 
> r600_query_hw *query)
> }
>  }
>
> +static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
> + unsigned stream)
> +{
> +   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
> +   radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | 
> EVENT_INDEX(3));
> +   radeon_emit(cs, va);
> +   radeon_emit(cs, va >> 32);
> +}
> +
>  static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
> struct r600_query_hw *query,
> struct r600_resource *buffer,
> @@ -726,10 +741,11 @@ static void r600_query_hw_do_emit_start(struct 
> r600_common_context *ctx,
> case PIPE_QUERY_PRIMITIVES_GENERATED:
> case PIPE_QUERY_SO_STATISTICS:
> case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
> -   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
> -   radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | 
> EVENT_INDEX(3));
> -   radeon_emit(cs, va);
> -   radeon_emit(cs, va >> 32);
> +   emit_sample_streamout(cs, va, query->stream);
> +   break;
> +   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
> +   for (unsigned stream = 0; stream < 4; ++stream)
> +   emit_sample_streamout(cs, va + 32 * stream, stream);
> break;
> case PIPE_QUERY_TIME_ELAPSED:
> if (ctx->chip_class >= SI) {
> @@ -821,11 +837,13 @@ static void r600_query_hw_do_emit_stop(struct 
> r600_common_context *ctx,
> case PIPE_QUERY_PRIMITIVES_GENERATED:
> case PIPE_QUERY_SO_STATISTICS:
> case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
> -   va += query->result_size/2;
> -   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
> -   radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | 
> EVENT_INDEX(3));
> -   radeon_emit(cs, va);
> -   radeon_emit(cs, va >> 32);
> +   va += 16;
> +   emit_sample_streamout(cs, va, query->stream);
> +   break;
> +   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
> +   va += 16;
> +   for (unsigned stream = 0; stream < 4; ++stream)
> +   emit_sample_streamout(cs, va + 32 * stream, stream);
> break;
> case PIPE_QUERY_TIME_ELAPSED:
> va += 8;
> @@ -885,10 +903,29 @@ static void r600_query_hw_emit_stop(struct 
> r600_common_context *ctx,
> r600_update_prims_generated_query_state(ctx, query->b.type, -1);
>  }
>
> +static void emit_set_predicate(struct r600_common_context *ctx,
> +  struct r600_resource *buf, uint64_t va,
> +  uint32_t op)
> +{
> +   struct radeon_winsys_cs *cs = ctx->gfx.cs;
> +
> +   if (ctx->chip_class >= GFX9) {
> +   radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
> +   radeon_emit(cs, op);
> +   radeon_emit(cs, va);
> +   radeon_emit(cs, va >> 32);
> +   } else {
> +   radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
> +  

Re: [Mesa-dev] [PATCH] swr: Add arch flags to support Cray and PGI compilers

2017-08-01 Thread Rowley, Timothy O

On Jul 31, 2017, at 3:51 PM, Chuck Atkins 
mailto:chuck.atk...@kitware.com>> wrote:

Hi Tim,

If the Cray flags are for wrapper scripts, why do we need specific flags for 
that instead of using the underlying compiler flags?

Sort answer: It's the "Cray" way of doing things.

Long answer: The target-cpu flag sometimes just controlls the -march flags (or 
equiv) but it can also add other low level flags.  By using the target-cpu flag 
with the cray compiler wrappers, you ensure that you're using whatever flags 
for a given architecture are appropriate for the underlying compiler, even if 
you don't have that compiler knowledge specified encoded anywhere in your 
configure.  For instance, when using another compiler backend that ./configure 
isn't explicitly checking for (pathscale, actual cray compiler, etc.), then the 
build will continue to work because -target-cpu gets translated by the wrpper 
to whatever is appropriate.  You'll also get a default set of flags loaded 
anyways based on your module environment.  Specifying target-cpu replaces those 
default flags whereas adding -xCORE-AVX512 would just append to them, maybe 
overriding the default flags, maybe not, depending on how the module 
environment is set up.  It's one of the many quirks and oddities of the Cray 
Programming Environment.

Thanks for explanation.

Reviewed-by: Tim Rowley 
mailto:timothy.o.row...@intel.com>>


I’m guessing you intend this for the 17.2 branch as well?

Nope.  I've no pressing customer need for it so keeping it in master but out of 
stable is fine with me.


--
Chuck Atkins
Staff R&D Engineer, Scientific Computing
Kitware, Inc.

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Re: [Mesa-dev] [PATCH v2 6/6] radeonsi: try to re-use previously deleted bindless descriptor slots

2017-08-01 Thread Marek Olšák
Hi Samuel,

Can you move this slot allocator into a util module? It seems generic
enough that it could be reused for "handle" and "ID" allocations.

Some additional notes:
- a bit array of uin32_t would be better. bool is too large (1 byte).
- "free" is the inverse of "used", so the "used" array is redundant.

Thanks,
Marek

On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
 wrote:
> Currently, when the array is full it is resized but it can grow
> over and over because we don't try to re-use descriptor slots.
>
> The idea is to maintain two simple lists which keep track of
> which slots is used and which ones have been deleted. When the
> array is resized, previously deleted slots can be marked as
> free because we are going to upload a new fresh buffer.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 85 
> +++
>  src/gallium/drivers/radeonsi/si_pipe.h|  2 +
>  2 files changed, 75 insertions(+), 12 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 543a19ba1e..95f0479be7 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -2299,11 +2299,72 @@ static void si_init_bindless_descriptors(struct 
> si_context *sctx,
>  * considered to be a valid handle.
>  */
> sctx->num_bindless_descriptors = 1;
> +
> +   /* Allocate two simple arrays for re-using previously deleted slots. 
> */
> +   sctx->bindless_used_slots = CALLOC(num_elements, sizeof(bool));
> +   sctx->bindless_free_slots = CALLOC(num_elements, sizeof(bool));
>  }
>
>  static inline void si_release_bindless_descriptors(struct si_context *sctx)
>  {
> si_release_descriptors(&sctx->bindless_descriptors);
> +   FREE(sctx->bindless_used_slots);
> +   FREE(sctx->bindless_free_slots);
> +}
> +
> +static unsigned si_get_next_free_bindless_slot(struct si_context *sctx)
> +{
> +   struct si_descriptors *desc = &sctx->bindless_descriptors;
> +   unsigned i;
> +
> +   for (i = 1; i < desc->num_elements; i++) {
> +   if (!sctx->bindless_used_slots[i]) {
> +   /* Lock this descriptor slot. */
> +   sctx->bindless_used_slots[i] = true;
> +   return i;
> +   }
> +   }
> +
> +   /* No available descriptor slots. */
> +   return 0;
> +}
> +
> +static void si_resize_bindless_descriptor(struct si_context *sctx)
> +{
> +   struct si_descriptors *desc = &sctx->bindless_descriptors;
> +   unsigned slot_size = desc->element_dw_size * 4;
> +   unsigned old_num_elements = desc->num_elements;
> +   unsigned new_num_elements = old_num_elements * 2;
> +   unsigned i;
> +
> +   /* All previously deleted slots can now be re-used because we are 
> going
> +* to upload a new buffer.
> +*/
> +   for (i = 1; i < old_num_elements; i++) {
> +   if (sctx->bindless_free_slots[i]) {
> +   /* Unlock this descriptor slot. */
> +   sctx->bindless_used_slots[i] = false;
> +   }
> +   sctx->bindless_free_slots[i] = false;
> +   }
> +
> +   /* Resize the array of descriptors. */
> +   desc->list = REALLOC(desc->list, desc->num_elements * slot_size,
> +new_num_elements * slot_size);
> +   desc->num_elements = new_num_elements;
> +   desc->num_active_slots = new_num_elements;
> +
> +   /* Resize the two simple arrays and mark all slots as free. */
> +   sctx->bindless_used_slots = REALLOC(sctx->bindless_used_slots,
> +   old_num_elements,
> +   new_num_elements);
> +   sctx->bindless_free_slots = REALLOC(sctx->bindless_free_slots,
> +   old_num_elements,
> +   new_num_elements);
> +   for (i = old_num_elements; i < new_num_elements; i++) {
> +   sctx->bindless_used_slots[i] = false;
> +   sctx->bindless_free_slots[i] = false;
> +   }
>  }
>
>  static unsigned
> @@ -2315,19 +2376,16 @@ si_create_bindless_descriptor(struct si_context 
> *sctx, uint32_t *desc_list,
> unsigned desc_slot, desc_slot_offset;
> bool resized = false;
>
> -   /* Reserve a new slot for this bindless descriptor. */
> -   desc_slot = sctx->num_bindless_descriptors++;
> -
> -   if (desc_slot >= desc->num_elements) {
> -   /* The array of bindless descriptors is full, resize it. */
> -   unsigned slot_size = desc->element_dw_size * 4;
> -   unsigned new_num_elements = desc->num_elements * 2;
> -
> -   desc->list = REALLOC(desc->list, desc->num_elements * 
> slot_size,
> -new_

[Mesa-dev] [PATCH v2 17/17] swr/rast: fix core / knights split of AVX512 intrinsics

2017-08-01 Thread Tim Rowley
Move AVX512BW specific intrinics to be Core-only.

Move some AVX512F intrinsics back to common implementation file.
---
 .../drivers/swr/rasterizer/common/simdlib.hpp  |  2 +
 .../swr/rasterizer/common/simdlib_512_avx512.inl   | 53 +
 .../rasterizer/common/simdlib_512_avx512_core.inl  | 54 ++
 .../common/simdlib_512_avx512_knights.inl  | 15 --
 4 files changed, 69 insertions(+), 55 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp 
b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
index 22d7da4..500cf8a 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
@@ -214,6 +214,8 @@ struct SIMDBase : Traits::IsaImpl
 using Vec4  = typename Traits::Vec4;
 using Mask  = typename Traits::Mask;
 
+static const size_t VECTOR_BYTES = sizeof(Float);
+
 // Populates a SIMD Vec4 from a non-simd vector. So p = xyzw becomes  
  .
 static SIMDINLINE
 void vec4_load1_ps(Vec4& r, const float *p)
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
index 1dbfff8..95e4c31 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
@@ -158,6 +158,11 @@ private:
 return _mm512_maskz_set1_epi32(m, -1);
 }
 
+static SIMDINLINE Integer vmask(__mmask8 m)
+{
+return _mm512_maskz_set1_epi64(m, -1LL);
+}
+
 public:
 //---
 // Single precision floating point arithmetic operations
@@ -187,8 +192,8 @@ static SIMDINLINE Float SIMDCALL floor_ps(Float a) { return 
round_ps 0xff) ? 0xff : (a + b) 
(uint8) 
+//SIMD_IWRAPPER_2(add_epi8);  // return a + b (int8)
+//SIMD_IWRAPPER_2(adds_epu8); // return ((a + b) > 0xff) ? 0xff : (a + b) 
(uint8) 
 SIMD_IWRAPPER_2(max_epi32); // return (a > b) ? a : b (int32)
 SIMD_IWRAPPER_2(max_epu32); // return (a > b) ? a : b (uint32)
 SIMD_IWRAPPER_2(min_epi32); // return (a < b) ? a : b (int32)
@@ -202,7 +207,7 @@ SIMD_IWRAPPER_2(mul_epi32); // return a * b (int32)
 SIMD_IWRAPPER_2(mullo_epi32);
 SIMD_IWRAPPER_2(sub_epi32); // return a - b (int32)
 SIMD_IWRAPPER_2(sub_epi64); // return a - b (int64)
-SIMD_IWRAPPER_2(subs_epu8); // return (b > a) ? 0 : (a - b) (uint8)
+//SIMD_IWRAPPER_2(subs_epu8); // return (b > a) ? 0 : (a - b) (uint8)
 
 //---
 // Logical operations
@@ -276,7 +281,7 @@ static SIMDINLINE Float SIMDCALL cvtepi32_ps(Integer a) // 
return (float)a(i
 return _mm512_cvtepi32_ps(a);
 }
 
-SIMD_IWRAPPER_1_8(cvtepu8_epi16); // return (int16)a(uint8 --> int16)
+//SIMD_IWRAPPER_1_8(cvtepu8_epi16); // return (int16)a(uint8 --> int16)
 SIMD_IWRAPPER_1_4(cvtepu8_epi32); // return (int32)a(uint8 --> int32)
 SIMD_IWRAPPER_1_8(cvtepu16_epi32);// return (int32)a(uint16 --> int32)
 SIMD_IWRAPPER_1_4(cvtepu16_epi64);// return (int64)a(uint16 --> int64)
@@ -317,20 +322,6 @@ static SIMDINLINE Float SIMDCALL cmpge_ps(Float a, Float 
b) { return cmp_ps(a, b); }
 
 template
-static SIMDINLINE Integer SIMDCALL cmp_epi8(Integer a, Integer b)
-{
-// Legacy vector mask generator
-__mmask64 result = _mm512_cmp_epi8_mask(a, b, static_cast(CmpTypeT));
-return vmask(result);
-}
-template
-static SIMDINLINE Integer SIMDCALL cmp_epi16(Integer a, Integer b)
-{
-// Legacy vector mask generator
-__mmask32 result = _mm512_cmp_epi16_mask(a, b, static_cast(CmpTypeT));
-return vmask(result);
-}
-template
 static SIMDINLINE Integer SIMDCALL cmp_epi32(Integer a, Integer b)
 {
 // Legacy vector mask generator
@@ -345,12 +336,12 @@ static SIMDINLINE Integer SIMDCALL cmp_epi64(Integer a, 
Integer b)
 return vmask(result);
 }
 
-SIMD_IWRAPPER_2_CMP(cmpeq_epi8,  cmp_epi8);// return a 
== b (int8)
-SIMD_IWRAPPER_2_CMP(cmpeq_epi16, cmp_epi16);   // return a 
== b (int16)
+//SIMD_IWRAPPER_2_CMP(cmpeq_epi8,  cmp_epi8);// return 
a == b (int8)
+//SIMD_IWRAPPER_2_CMP(cmpeq_epi16, cmp_epi16);   // return 
a == b (int16)
 SIMD_IWRAPPER_2_CMP(cmpeq_epi32, cmp_epi32);   // return a 
== b (int32)
 SIMD_IWRAPPER_2_CMP(cmpeq_epi64, cmp_epi64);   // return a 
== b (int64)
-SIMD_IWRAPPER_2_CMP(cmpgt_epi8,  cmp_epi8);// return a 
> b (int8)
-SIMD_IWRAPPER_2_CMP(cmpgt_epi16, cmp_epi16);   // return a 
> b (int16)
+//SIMD_IWRAPPER_2_CMP(cmpgt_epi8,  cmp_epi8);// return 
a > b (int8)
+//SIMD_IWRAPPER_2_CMP(cmpgt_epi16, cmp_epi16);   // return 
a > b (int16)
 SIMD_IWRAPPER_2_CMP(cmpgt_epi32, cmp_epi32);   // return a 
> b (int32)
 SIMD_IWRAPPER_2_CMP(cmpgt_epi64, cmp_epi64);   // return a 
> b (int64)
 SIMD_IWRAPPER_2_CMP(cmplt_epi32, cmp_epi32);   // return a 
< b (int32)
@@ -458,7 +449,7 @@ SIMD_IWRAPP

[Mesa-dev] [PATCH v2 14/17] swr/rast: gen_knobs template code style

2017-08-01 Thread Tim Rowley
---
 src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
index e6fe165..a950643 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
@@ -203,8 +203,8 @@ GlobalKnobs g_GlobalKnobs;
 //
 GlobalKnobs::GlobalKnobs()
 {
-% for knob in knobs:
-InitKnob(${knob[0]});
+% for knob in knobs :
+InitKnob(${ knob[0] });
 % endfor
 }
 
-- 
2.7.4

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[Mesa-dev] [PATCH v2 16/17] swr/rast: simplify knob default value setup

2017-08-01 Thread Tim Rowley
---
 .../drivers/swr/rasterizer/codegen/templates/gen_knobs.h| 13 -
 src/gallium/drivers/swr/rasterizer/core/knobs_init.h| 12 +++-
 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h
index b02870b..d81f7d0 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h
@@ -67,12 +67,6 @@ public:
 return Value();
 }
 
-protected:
-Knob(T const &defaultValue) :
-m_Value(expandEnvironmentVariables(defaultValue))
-{
-}
-
 private:
 T m_Value;
 };
@@ -83,10 +77,10 @@ private:
 
 {   \\
 
-Knob_##_name() : Knob<_type>(_default) { }  \\
-
 static const char* Name() { return "KNOB_" #_name; }\\
 
+static _type DefaultValue() { return (_default); }  \\
+
 } _name;
 
 #define GET_KNOB(_name) g_GlobalKnobs._name.Value()
@@ -117,8 +111,9 @@ struct GlobalKnobs
 % endif
 
 % endfor
-GlobalKnobs();
+
 std::string ToString(const char* optPerLinePrefix="");
+GlobalKnobs();
 };
 extern GlobalKnobs g_GlobalKnobs;
 
diff --git a/src/gallium/drivers/swr/rasterizer/core/knobs_init.h 
b/src/gallium/drivers/swr/rasterizer/core/knobs_init.h
index ba2df22..12c2a30 100644
--- a/src/gallium/drivers/swr/rasterizer/core/knobs_init.h
+++ b/src/gallium/drivers/swr/rasterizer/core/knobs_init.h
@@ -91,16 +91,18 @@ static inline void ConvertEnvToKnob(const char* pOverride, 
std::string& knobValu
 template 
 static inline void InitKnob(T& knob)
 {
-
-// TODO, read registry first
-
-// Second, read environment variables
+// Read environment variables
 const char* pOverride = getenv(knob.Name());
 
 if (pOverride)
 {
-auto knobValue = knob.Value();
+auto knobValue = knob.DefaultValue();
 ConvertEnvToKnob(pOverride, knobValue);
 knob.Value(knobValue);
 }
+else
+{
+// Set default value
+knob.Value(knob.DefaultValue());
+}
 }
-- 
2.7.4

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[Mesa-dev] [PATCH v2 15/17] swr/rast: split gen_knobs templates into .h/.cpp

2017-08-01 Thread Tim Rowley
Switch to a 1:1 mapping template:generated for future maintenance.
---
 src/gallium/drivers/swr/Makefile.am|   3 +-
 src/gallium/drivers/swr/SConscript |   2 +-
 .../drivers/swr/rasterizer/codegen/gen_knobs.py|  14 +-
 .../swr/rasterizer/codegen/templates/gen_knobs.cpp | 108 --
 .../swr/rasterizer/codegen/templates/gen_knobs.h   | 157 +
 5 files changed, 166 insertions(+), 118 deletions(-)
 create mode 100644 
src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h

diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 73fe904..b20f128 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -115,7 +115,7 @@ rasterizer/codegen/gen_knobs.cpp: 
rasterizer/codegen/gen_knobs.py rasterizer/cod
--output rasterizer/codegen/gen_knobs.cpp \
--gen_cpp
 
-rasterizer/codegen/gen_knobs.h: rasterizer/codegen/gen_knobs.py 
rasterizer/codegen/knob_defs.py rasterizer/codegen/templates/gen_knobs.cpp 
rasterizer/codegen/gen_common.py
+rasterizer/codegen/gen_knobs.h: rasterizer/codegen/gen_knobs.py 
rasterizer/codegen/knob_defs.py rasterizer/codegen/templates/gen_knobs.h 
rasterizer/codegen/gen_common.py
$(MKDIR_GEN)
$(PYTHON_GEN) \
$(srcdir)/rasterizer/codegen/gen_knobs.py \
@@ -347,5 +347,6 @@ EXTRA_DIST = \
rasterizer/codegen/templates/gen_builder.hpp \
rasterizer/codegen/templates/gen_header_init.hpp \
rasterizer/codegen/templates/gen_knobs.cpp \
+   rasterizer/codegen/templates/gen_knobs.h \
rasterizer/codegen/templates/gen_llvm.hpp \
rasterizer/codegen/templates/gen_rasterizer.cpp
diff --git a/src/gallium/drivers/swr/SConscript 
b/src/gallium/drivers/swr/SConscript
index c578d7a..b394cbc 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -54,7 +54,7 @@ env.CodeGenerate(
 command = python_cmd + ' $SCRIPT --output $TARGET --gen_h'
 )
 Depends('rasterizer/codegen/gen_knobs.h',
-swrroot + 'rasterizer/codegen/templates/gen_knobs.cpp')
+swrroot + 'rasterizer/codegen/templates/gen_knobs.h')
 
 env.CodeGenerate(
 target = 'rasterizer/jitter/gen_state_llvm.h',
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.py 
b/src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.py
index 2c271c7..33f62a2 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.py
+++ b/src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.py
@@ -37,27 +37,25 @@ def main(args=sys.argv[1:]):
 args = parser.parse_args()
 
 cur_dir = os.path.dirname(os.path.abspath(__file__))
-template_file = os.path.join(cur_dir, 'templates', 'gen_knobs.cpp')
+template_cpp = os.path.join(cur_dir, 'templates', 'gen_knobs.cpp')
+template_h = os.path.join(cur_dir, 'templates', 'gen_knobs.h')
 
 if args.gen_h:
 MakoTemplateWriter.to_file(
-template_file,
+template_h,
 args.output,
 cmdline=sys.argv,
 filename='gen_knobs',
-knobs=knob_defs.KNOBS,
-includes=['core/knobs_init.h', 'common/os.h', 'sstream', 
'iomanip'],
-gen_header=True)
+knobs=knob_defs.KNOBS)
 
 if args.gen_cpp:
 MakoTemplateWriter.to_file(
-template_file,
+template_cpp,
 args.output,
 cmdline=sys.argv,
 filename='gen_knobs',
 knobs=knob_defs.KNOBS,
-includes=['core/knobs_init.h', 'common/os.h', 'sstream', 
'iomanip'],
-gen_header=False)
+includes=['core/knobs_init.h', 'common/os.h', 'sstream', 
'iomanip'])
 
 return 0
 
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
index a950643..2f4c47a 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
@@ -20,11 +20,7 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
-% if gen_header:
-* @file ${filename}.h
-% else:
 * @file ${filename}.cpp
-% endif 
 *
 * @brief Dynamic Knobs for Core.
 *
@@ -35,105 +31,6 @@
 *
 **/
 <% calc_max_knob_len(knobs) %>
-%if gen_header:
-#pragma once
-#include 
-
-struct KnobBase
-{
-private:
-// Update the input string.
-static void autoExpandEnvironmentVariables(std::string &text);
-
-protected:
-// Leave input alone and return new string.
-static std::string expandEnvironmentVariables(std::string const &input)
-{
-std::string text = input;
-autoExpandEnvironmentVariables(text);
-return text;
-}
-
-template 
-static T expandEnvironmentVariables(T const &input)

[Mesa-dev] [PATCH v2 06/17] swr/rast: stop using MSFT types in platform independent code

2017-08-01 Thread Tim Rowley
---
 src/gallium/drivers/swr/rasterizer/common/os.h |  6 --
 src/gallium/drivers/swr/rasterizer/core/api.cpp|  2 +-
 src/gallium/drivers/swr/rasterizer/core/api.h  |  4 ++--
 src/gallium/drivers/swr/rasterizer/core/binner.cpp |  4 ++--
 src/gallium/drivers/swr/rasterizer/core/blend.h|  2 +-
 src/gallium/drivers/swr/rasterizer/core/clip.h |  8 
 src/gallium/drivers/swr/rasterizer/core/fifo.hpp   |  2 +-
 src/gallium/drivers/swr/rasterizer/core/format_traits.h|  4 ++--
 src/gallium/drivers/swr/rasterizer/core/pa.h   |  2 +-
 src/gallium/drivers/swr/rasterizer/core/threads.cpp|  4 ++--
 src/gallium/drivers/swr/rasterizer/core/tilemgr.h  | 12 ++--
 src/gallium/drivers/swr/rasterizer/core/utils.h| 10 ++
 src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp|  2 +-
 src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp |  4 ++--
 14 files changed, 35 insertions(+), 31 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index dc90fca..4ed6b88 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -220,12 +220,6 @@ void *AlignedMalloc(unsigned int size, unsigned int 
alignment)
 return ret;
 }
 
-inline
-unsigned char _bittest(const LONG *a, LONG b)
-{
-return ((*(unsigned *)(a) & (1 << b)) != 0);
-}
-
 static inline
 void AlignedFree(void* p)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 855d133..8dc9ac2 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -189,7 +189,7 @@ void QueueWork(SWR_CONTEXT *pContext)
 
 if (IsDraw)
 {
-InterlockedIncrement((volatile LONG*)&pContext->drawsOutstandingFE);
+InterlockedIncrement((volatile long*)&pContext->drawsOutstandingFE);
 }
 
 _ReadWriteBarrier();
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.h 
b/src/gallium/drivers/swr/rasterizer/core/api.h
index 236e0fc..a394205 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.h
+++ b/src/gallium/drivers/swr/rasterizer/core/api.h
@@ -697,8 +697,8 @@ SWR_FUNC(void, SwrStoreHotTileToSurface,
 SWR_FUNC(void, SwrStoreHotTileClear,
  SWR_SURFACE_STATE *pDstSurface,
  SWR_RENDERTARGET_ATTACHMENT renderTargetIndex,
- UINT x,
- UINT y,
+ uint32_t x,
+ uint32_t y,
  uint32_t renderTargetArrayIndex,
  const float* pClearColor);
 
diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp 
b/src/gallium/drivers/swr/rasterizer/core/binner.cpp
index de6691b..c1f0f07 100644
--- a/src/gallium/drivers/swr/rasterizer/core/binner.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/binner.cpp
@@ -64,7 +64,7 @@ INLINE void ProcessAttributes(
 static_assert(NumVertsT::value > 0 && NumVertsT::value <= 3, "Invalid 
value for NumVertsT");
 const SWR_BACKEND_STATE& backendState = pDC->pState->state.backendState;
 // Conservative Rasterization requires degenerate tris to have constant 
attribute interpolation
-LONG constantInterpMask = IsDegenerate::value ? 0x : 
backendState.constantInterpolationMask;
+uint32_t constantInterpMask = IsDegenerate::value ? 0x : 
backendState.constantInterpolationMask;
 const uint32_t provokingVertex = 
pDC->pState->state.frontendState.topologyProvokingVertex;
 const PRIMITIVE_TOPOLOGY topo = pDC->pState->state.topology;
 
@@ -93,7 +93,7 @@ INLINE void ProcessAttributes(
 
 if (HasConstantInterpT::value || IsDegenerate::value)
 {
-if (_bittest(&constantInterpMask, i))
+if (CheckBit(constantInterpMask, i))
 {
 uint32_t vid;
 uint32_t adjustedTriIndex;
diff --git a/src/gallium/drivers/swr/rasterizer/core/blend.h 
b/src/gallium/drivers/swr/rasterizer/core/blend.h
index 1b98e44..c89c476 100644
--- a/src/gallium/drivers/swr/rasterizer/core/blend.h
+++ b/src/gallium/drivers/swr/rasterizer/core/blend.h
@@ -278,7 +278,7 @@ INLINE void Clamp(simdvector &src)
 }
 
 template
-void Blend(const SWR_BLEND_STATE *pBlendState, const 
SWR_RENDER_TARGET_BLEND_STATE *pState, simdvector &src, simdvector& src1, BYTE 
*pDst, simdvector &result)
+void Blend(const SWR_BLEND_STATE *pBlendState, const 
SWR_RENDER_TARGET_BLEND_STATE *pState, simdvector &src, simdvector& src1, 
uint8_t *pDst, simdvector &result)
 {
 // load render target
 simdvector dst;
diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index bf16792..ca6596e 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -464,7 +464,7 @@ public:
 // input/output vertex store for clipper
  

[Mesa-dev] [PATCH v2 08/17] swr/rast: rename frontend pVertexStore

2017-08-01 Thread Tim Rowley
Rename to reflect global nature.
---
 src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index f9eda83..e51f967 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -1332,7 +1332,7 @@ static void TessellationStages(
 TSDestroyCtx(tsCtx);
 }
 
-THREAD PA_STATE::SIMDVERTEX *pVertexStore = nullptr;
+THREAD PA_STATE::SIMDVERTEX *gpVertexStore = nullptr;
 THREAD uint32_t gVertexStoreSize = 0;
 
 //
@@ -1459,19 +1459,22 @@ void ProcessDraw(
 // grow the vertex store for the PA as necessary
 if (gVertexStoreSize < vertexStoreSize)
 {
-if (pVertexStore != nullptr)
+if (gpVertexStore != nullptr)
 {
-AlignedFree(pVertexStore);
+AlignedFree(gpVertexStore);
+gpVertexStore = nullptr;
 }
 
-pVertexStore = reinterpret_cast(AlignedMalloc(vertexStoreSize, 64));
+SWR_ASSERT(gpVertexStore == nullptr);
+
+gpVertexStore = reinterpret_cast(AlignedMalloc(vertexStoreSize, 64));
 gVertexStoreSize = vertexStoreSize;
 
-SWR_ASSERT(pVertexStore != nullptr);
+SWR_ASSERT(gpVertexStore != nullptr);
 }
 
 // choose primitive assembler
-PA_FACTORY paFactory(pDC, state.topology, 
work.numVerts, pVertexStore, numVerts, state.frontendState.vsVertexSize);
+PA_FACTORY paFactory(pDC, state.topology, 
work.numVerts, gpVertexStore, numVerts, state.frontendState.vsVertexSize);
 PA_STATE& pa = paFactory.GetPA();
 
 #if USE_SIMD16_FRONTEND
-- 
2.7.4

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[Mesa-dev] [PATCH v2 13/17] swr/rast: switch gen_knobs.cpp license

2017-08-01 Thread Tim Rowley
Unintentionally added with an apache2 license; relicense to match
the rest of the tree.
---
 .../swr/rasterizer/codegen/templates/gen_knobs.cpp | 29 +-
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
index 06b93bd..e6fe165 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.cpp
@@ -1,19 +1,24 @@
 /**
+* Copyright (C) 2015-2017 Intel Corporation.   All Rights Reserved.
 *
-* Copyright 2015-2017
-* Intel Corporation
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
 *
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
+* The above copyright notice and this permission notice (including the next
+* paragraph) shall be included in all copies or substantial portions of the
+* Software.
 *
-* http ://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+* IN THE SOFTWARE.
 *
 % if gen_header:
 * @file ${filename}.h
-- 
2.7.4

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[Mesa-dev] [PATCH v2 12/17] swr/rast: fix scons gen_knobs.h dependency

2017-08-01 Thread Tim Rowley
Copy/paste error was duplicating a gen_knobs.cpp rule.
---
 src/gallium/drivers/swr/SConscript | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/SConscript 
b/src/gallium/drivers/swr/SConscript
index a32807d..c578d7a 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -53,7 +53,7 @@ env.CodeGenerate(
 source = '',
 command = python_cmd + ' $SCRIPT --output $TARGET --gen_h'
 )
-Depends('rasterizer/codegen/gen_knobs.cpp',
+Depends('rasterizer/codegen/gen_knobs.h',
 swrroot + 'rasterizer/codegen/templates/gen_knobs.cpp')
 
 env.CodeGenerate(
-- 
2.7.4

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[Mesa-dev] [PATCH v2 09/17] swr/rast: vmask() implementations for KNL

2017-08-01 Thread Tim Rowley
---
 .../swr/rasterizer/common/simdlib_512_avx512_knights.inl   | 14 ++
 1 file changed, 14 insertions(+)

diff --git 
a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_knights.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_knights.inl
index 17001be..2ee7639 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_knights.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_knights.inl
@@ -132,6 +132,20 @@
 }
 #define SIMD_IWRAPPER_2I(op) SIMD_IWRAPPER_2I_(op, op)
 
+private:
+static SIMDINLINE Integer vmask(__mmask8 m)
+{
+return _mm512_mask_set1_epi64(_mm512_setzero_si512(), m, -1LL);
+}
+static SIMDINLINE Integer vmask(__mmask32 m)
+{
+return _mm512_mask_set1_epi16(_mm512_setzero_si512(), m, -1);
+}
+static SIMDINLINE Integer vmask(__mmask64 m)
+{
+return _mm512_mask_set1_epi8(_mm512_setzero_si512(), m, -1);
+}
+
 public:
 SIMD_WRAPPERI_2_(and_ps, and_epi32);  // return a & b   (float 
treated as int)
 SIMD_WRAPPERI_2_(andnot_ps, andnot_epi32);// return (~a) & b(float 
treated as int)
-- 
2.7.4

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[Mesa-dev] [PATCH v2 03/17] swr/rast: fix USE_SIMD16_FRONTEND issues

2017-08-01 Thread Tim Rowley
Fix problems found when enabling USE_SIMD16_FRONTEND, mostly related to
vMask / movemask_ps(pd).
---
 .../drivers/swr/rasterizer/common/simd16intrin.h| 14 ++
 .../drivers/swr/rasterizer/common/simdintrin.h  | 21 +
 .../swr/rasterizer/common/simdlib_128_avx.inl   | 15 +++
 .../swr/rasterizer/common/simdlib_256_avx.inl   | 10 ++
 .../swr/rasterizer/common/simdlib_512_avx512.inl|  4 ++--
 .../common/simdlib_512_avx512_knights.inl   | 21 -
 .../swr/rasterizer/common/simdlib_512_emu.inl   | 12 +---
 src/gallium/drivers/swr/rasterizer/core/backend.cpp |  2 +-
 .../drivers/swr/rasterizer/core/backend_impl.h  |  8 
 .../drivers/swr/rasterizer/core/backend_sample.cpp  |  2 +-
 .../swr/rasterizer/core/backend_singlesample.cpp|  2 +-
 src/gallium/drivers/swr/rasterizer/core/clip.h  |  6 +++---
 .../drivers/swr/rasterizer/core/frontend.cpp|  2 +-
 src/gallium/drivers/swr/rasterizer/core/pa.h|  4 +++-
 14 files changed, 49 insertions(+), 74 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simd16intrin.h 
b/src/gallium/drivers/swr/rasterizer/common/simd16intrin.h
index a160ca2..019b26d 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simd16intrin.h
+++ b/src/gallium/drivers/swr/rasterizer/common/simd16intrin.h
@@ -159,20 +159,10 @@ typedef SIMD512 SIMD16;
 #define _simd16_packus_epi32SIMD16::packus_epi32
 #define _simd16_packs_epi32 SIMD16::packs_epi32
 #define _simd16_cmplt_ps_mask   
SIMD16::cmp_ps_mask
+#define _simd16_cmpeq_ps_mask   
SIMD16::cmp_ps_mask
 #define _simd16_int2mask(mask)  simd16mask(mask)
 #define _simd16_mask2int(mask)  int(mask)
-
-// convert bitmask to vector mask
-SIMDINLINE simd16scalar vMask16(int32_t mask)
-{
-simd16scalari temp = _simd16_set1_epi32(mask);
-
-simd16scalari bits = _simd16_set_epi32(0x8000, 0x4000, 0x2000, 0x1000, 
0x0800, 0x0400, 0x0200, 0x0100, 0x0080, 0x0040, 0x0020, 0x0010, 0x0008, 0x0004, 
0x0002, 0x0001);
-
-simd16scalari result = _simd16_cmplt_epi32(_simd16_setzero_si(), 
_simd16_and_si(temp, bits));
-
-return _simd16_castsi_ps(result);
-}
+#define _simd16_vmask_psSIMD16::vmask_ps
 
 #endif//ENABLE_AVX512_SIMD16
 
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdintrin.h 
b/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
index f95c109..f4b9e10 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
+++ b/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
@@ -181,6 +181,7 @@ typedef SIMD256 SIMD;
 #define _simd_storeu2_siSIMD::storeu2_si
 
 #define _simd_blendv_epi32  SIMD::blendv_epi32
+#define _simd_vmask_ps  SIMD::vmask_ps
 
 template SIMDINLINE
 SIMD128::Integer _simd_blend4_epi32(SIMD128::Integer a, SIMD128::Integer b)
@@ -188,26 +189,6 @@ SIMD128::Integer _simd_blend4_epi32(SIMD128::Integer a, 
SIMD128::Integer b)
 return SIMD128::castps_si(SIMD128::blend_ps(SIMD128::castsi_ps(a), 
SIMD128::castsi_ps(b)));
 }
 
-// convert bitmask to vector mask
-SIMDINLINE
-SIMD256::Float vMask(int32_t mask)
-{
-SIMD256::Integer vec = SIMD256::set1_epi32(mask);
-const SIMD256::Integer bit = SIMD256::set_epi32(0x80, 0x40, 0x20, 0x10, 
0x08, 0x04, 0x02, 0x01);
-vec = SIMD256::and_si(vec, bit);
-vec = SIMD256::cmplt_epi32(SIMD256::setzero_si(), vec);
-return SIMD256::castsi_ps(vec);
-}
-
-SIMDINLINE
-SIMD256::Integer vMaski(int32_t mask)
-{
-SIMD256::Integer vec = SIMD256::set1_epi32(mask);
-const SIMD256::Integer bit = SIMD256::set_epi32(0x80, 0x40, 0x20, 0x10, 
0x08, 0x04, 0x02, 0x01);
-vec = SIMD256::and_si(vec, bit);
-return SIMD256::cmplt_epi32(SIMD256::setzero_si(), vec);
-}
-
 SIMDINLINE
 void _simd_mov(simdscalar &r, unsigned int rlane, simdscalar& s, unsigned int 
slane)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
index 5bcedf3..7232791 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
@@ -519,6 +519,11 @@ static SIMDINLINE Float SIMDCALL set_ps(float in3, float 
in2, float in1, float i
 return _mm_set_ps(in3, in2, in1, in0);
 }
 
+static SIMDINLINE Integer SIMDCALL set_epi32(int in3, int in2, int in1, int 
in0)
+{
+return _mm_set_epi32(in3, in2, in1, in0);
+}
+
 template 
 static SIMDINLINE float SIMDCALL extract_ps(Float a)
 {
@@ -526,6 +531,16 @@ static SIMDINLINE float SIMDCALL extract_ps(Float a)
 return *reinterpret_cast(&tmp);
 }
 
+static SIMDINLINE Float SIMDCALL vmask_ps(int32_t mask)
+{
+Integer vec = set1_epi32(mask);
+const Integer bit = set_epi32(
+0x08, 0x04, 0x02, 0x01);
+vec 

[Mesa-dev] [PATCH v2 07/17] swr/rast: fix movemask_ps / movemask_pd on AVX512

2017-08-01 Thread Tim Rowley
---
 src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
index 1001417..1dbfff8 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
@@ -554,15 +554,20 @@ static SIMDINLINE uint64_t SIMDCALL movemask_epi8(Integer 
a)
 
 static SIMDINLINE uint32_t SIMDCALL movemask_pd(Double a)
 {
-__mmask8 m = _mm512_test_epi64_mask(castpd_si(a), set1_epi32(-1));
+__mmask8 m = _mm512_test_epi64_mask(castpd_si(a), 
set1_epi64(0x8000LL));
 return static_cast(m);
 }
 static SIMDINLINE uint32_t SIMDCALL movemask_ps(Float a)
 {
-__mmask16 m = _mm512_test_epi32_mask(castps_si(a), set1_epi32(-1));
+__mmask16 m = _mm512_test_epi32_mask(castps_si(a), set1_epi32(0x800));
 return static_cast(m);
 }
 
+static SIMDINLINE Integer SIMDCALL set1_epi64(long long i) // return i (all 
elements are same value)
+{
+return _mm512_set1_epi64(i);
+}
+
 static SIMDINLINE Integer SIMDCALL set1_epi32(int i) // return i (all elements 
are same value)
 {
 return _mm512_set1_epi32(i);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 10/17] swr/rast: SIMD16 shaders - widen fetch and vertex shaders

2017-08-01 Thread Tim Rowley
Work in progress, disabled by default.
---
 .../drivers/swr/rasterizer/core/frontend.cpp   |  33 
 src/gallium/drivers/swr/rasterizer/core/knobs.h|   1 +
 src/gallium/drivers/swr/rasterizer/core/state.h|  10 ++
 .../drivers/swr/rasterizer/jitter/JitManager.cpp   |  16 ++
 .../drivers/swr/rasterizer/jitter/JitManager.h |   8 +
 .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 175 -
 6 files changed, 238 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index e51f967..daea088 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -1478,13 +1478,22 @@ void ProcessDraw(
 PA_STATE& pa = paFactory.GetPA();
 
 #if USE_SIMD16_FRONTEND
+#if USE_SIMD16_SHADERS
+simd16vertexvin;
+#else
 simdvertex  vin_lo;
 simdvertex  vin_hi;
+#endif
 SWR_VS_CONTEXT  vsContext_lo;
 SWR_VS_CONTEXT  vsContext_hi;
 
+#if USE_SIMD16_SHADERS
+vsContext_lo.pVin = reinterpret_cast(&vin);
+vsContext_hi.pVin = reinterpret_cast(&vin);
+#else
 vsContext_lo.pVin = &vin_lo;
 vsContext_hi.pVin = &vin_hi;
+#endif
 vsContext_lo.AlternateOffset = 0;
 vsContext_hi.AlternateOffset = 1;
 
@@ -1565,17 +1574,31 @@ void ProcessDraw(
 {
 // 1. Execute FS/VS for a single SIMD.
 AR_BEGIN(FEFetchShader, pDC->drawId);
+#if USE_SIMD16_SHADERS
+state.pfnFetchFunc(fetchInfo_lo, vin);
+#else
 state.pfnFetchFunc(fetchInfo_lo, vin_lo);
 
 if ((i + KNOB_SIMD_WIDTH) < endVertex)  // 1/2 of 
KNOB_SIMD16_WIDTH
 {
 state.pfnFetchFunc(fetchInfo_hi, vin_hi);
 }
+#endif
 AR_END(FEFetchShader, 0);
 
 // forward fetch generated vertex IDs to the vertex shader
+#if USE_SIMD16_SHADERS
+#if 0
+vsContext_lo.VertexID = _simd16_extract(fetchInfo_lo.VertexID, 
0);
+vsContext_hi.VertexID = _simd16_extract(fetchInfo_lo.VertexID, 
1);
+#else
+vsContext_lo.VertexID = fetchInfo_lo.VertexID;
+vsContext_hi.VertexID = fetchInfo_lo.VertexID2;
+#endif
+#else
 vsContext_lo.VertexID = fetchInfo_lo.VertexID;
 vsContext_hi.VertexID = fetchInfo_hi.VertexID;
+#endif
 
 // Setup active mask for vertex shader.
 vsContext_lo.mask = GenerateMask(endVertex - i);
@@ -1584,8 +1607,18 @@ void ProcessDraw(
 // forward cut mask to the PA
 if (IsIndexedT::value)
 {
+#if USE_SIMD16_SHADERS
+#if 0
+*pvCutIndices_lo = 
_simd_movemask_ps(_simd_castsi_ps(_simd16_extract(fetchInfo_lo.CutMask, 0)));
+*pvCutIndices_hi = 
_simd_movemask_ps(_simd_castsi_ps(_simd16_extract(fetchInfo_lo.CutMask, 1)));
+#else
+*pvCutIndices_lo = 
_simd_movemask_ps(_simd_castsi_ps(fetchInfo_lo.CutMask));
+*pvCutIndices_hi = 
_simd_movemask_ps(_simd_castsi_ps(fetchInfo_lo.CutMask2));
+#endif
+#else
 *pvCutIndices_lo = 
_simd_movemask_ps(_simd_castsi_ps(fetchInfo_lo.CutMask));
 *pvCutIndices_hi = 
_simd_movemask_ps(_simd_castsi_ps(fetchInfo_hi.CutMask));
+#endif
 }
 
 UPDATE_STAT_FE(IaVertices, GetNumInvocations(i, endVertex));
diff --git a/src/gallium/drivers/swr/rasterizer/core/knobs.h 
b/src/gallium/drivers/swr/rasterizer/core/knobs.h
index 10bd4a5..fe0a044 100644
--- a/src/gallium/drivers/swr/rasterizer/core/knobs.h
+++ b/src/gallium/drivers/swr/rasterizer/core/knobs.h
@@ -41,6 +41,7 @@
 #define ENABLE_AVX512_SIMD161
 #define USE_8x2_TILE_BACKEND1
 #define USE_SIMD16_FRONTEND 1
+#define USE_SIMD16_SHADERS  0   // requires USE_SIMD16_FRONTEND
 
 ///
 // Architecture validation
diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h 
b/src/gallium/drivers/swr/rasterizer/core/state.h
index 7af3f82..9e63955 100644
--- a/src/gallium/drivers/swr/rasterizer/core/state.h
+++ b/src/gallium/drivers/swr/rasterizer/core/state.h
@@ -577,6 +577,12 @@ struct SWR_FETCH_CONTEXT
 uint32_t StartInstance; // IN: start instance
 simdscalari VertexID;   // OUT: vector of vertex IDs
 simdscalari CutMask;// OUT: vector mask of indices 
which have the cut index value
+#if USE_SIMD16_SHADERS
+//simd16scalari VertexID; // OUT: vector of vertex IDs
+//simd16scalari CutMask;  // OUT: vector mask of 
indices which have the cut index value
+simdscalari VertexID2;  // OUT: vector of vertex IDs
+simdscalari CutMask2; 

[Mesa-dev] [PATCH v2 00/17] swr: update rasterizer

2017-08-01 Thread Tim Rowley
Highlights include enabling the simd16 frontend and code cleanups.

v2: split previous gen_knobs patch into five chunks: scons fix,
  relicense to match rest of tree, code style, template split,
  simplification of default value setup

Tim Rowley (17):
  swr/rast: threadID via portable std::this_thread::get_id()
  swr/rast: simdlib better seperation of core vs. knights avx512
  swr/rast: fix USE_SIMD16_FRONTEND issues
  swr/rast: disable AVX512 optimization of SSE / AVX code
  swr/rast: enable USE_SIMD16_FRONTEND by default
  swr/rast: stop using MSFT types in platform independent code
  swr/rast: fix movemask_ps / movemask_pd on AVX512
  swr/rast: rename frontend pVertexStore
  swr/rast: vmask() implementations for KNL
  swr/rast: SIMD16 shaders - widen fetch and vertex shaders
  swr/rast: fixes for 32-bit builds
  swr/rast: fix scons gen_knobs.h dependency
  swr/rast: switch gen_knobs.cpp license
  swr/rast: gen_knobs template code style
  swr/rast: split gen_knobs templates into .h/.cpp
  swr/rast: simplify knob default value setup
  swr/rast: fix core / knights split of AVX512 intrinsics

 src/gallium/drivers/swr/Makefile.am|   5 +-
 src/gallium/drivers/swr/Makefile.sources   |   8 +
 src/gallium/drivers/swr/SConscript |   4 +-
 .../drivers/swr/rasterizer/codegen/gen_knobs.py|  14 +-
 .../codegen/templates/gen_ar_eventhandlerfile.hpp  |  20 +-
 .../swr/rasterizer/codegen/templates/gen_knobs.cpp | 141 ++---
 .../swr/rasterizer/codegen/templates/gen_knobs.h   | 152 +++
 src/gallium/drivers/swr/rasterizer/common/os.h |   6 -
 .../drivers/swr/rasterizer/common/simd16intrin.h   |  14 +-
 .../drivers/swr/rasterizer/common/simdintrin.h |  35 +---
 .../drivers/swr/rasterizer/common/simdlib.hpp  |  37 +++-
 .../swr/rasterizer/common/simdlib_128_avx.inl  |  15 ++
 .../swr/rasterizer/common/simdlib_128_avx512.inl   | 108 +++---
 .../rasterizer/common/simdlib_128_avx512_core.inl  | 193 ++
 .../common/simdlib_128_avx512_knights.inl  |  35 
 .../swr/rasterizer/common/simdlib_256_avx.inl  | 140 +++--
 .../swr/rasterizer/common/simdlib_256_avx2.inl |  32 +--
 .../swr/rasterizer/common/simdlib_256_avx512.inl   | 128 +++-
 .../rasterizer/common/simdlib_256_avx512_core.inl  | 127 
 .../common/simdlib_256_avx512_knights.inl  |  35 
 .../swr/rasterizer/common/simdlib_512_avx512.inl   | 137 +
 .../rasterizer/common/simdlib_512_avx512_core.inl  | 217 +
 .../common/simdlib_512_avx512_knights.inl  | 161 +++
 .../common/simdlib_512_avx512_masks_core.inl   |  27 +++
 .../common/simdlib_512_avx512_masks_knights.inl|  27 +++
 .../swr/rasterizer/common/simdlib_512_emu.inl  | 155 +++
 .../swr/rasterizer/common/simdlib_types.hpp|  78 
 src/gallium/drivers/swr/rasterizer/core/api.cpp|   2 +-
 src/gallium/drivers/swr/rasterizer/core/api.h  |   4 +-
 .../drivers/swr/rasterizer/core/backend.cpp|   2 +-
 .../drivers/swr/rasterizer/core/backend_impl.h |  20 +-
 .../drivers/swr/rasterizer/core/backend_sample.cpp |   2 +-
 .../swr/rasterizer/core/backend_singlesample.cpp   |   2 +-
 src/gallium/drivers/swr/rasterizer/core/binner.cpp |  40 ++--
 src/gallium/drivers/swr/rasterizer/core/binner.h   |   4 +-
 src/gallium/drivers/swr/rasterizer/core/blend.h|   2 +-
 src/gallium/drivers/swr/rasterizer/core/clip.cpp   |  12 +-
 src/gallium/drivers/swr/rasterizer/core/clip.h |  80 
 src/gallium/drivers/swr/rasterizer/core/context.h  |   8 +-
 .../drivers/swr/rasterizer/core/depthstencil.h |  12 +-
 src/gallium/drivers/swr/rasterizer/core/fifo.hpp   |   2 +-
 .../swr/rasterizer/core/format_conversion.h|  18 +-
 .../drivers/swr/rasterizer/core/format_traits.h|   4 +-
 .../drivers/swr/rasterizer/core/format_types.h |  71 ---
 .../drivers/swr/rasterizer/core/frontend.cpp   |  54 -
 src/gallium/drivers/swr/rasterizer/core/frontend.h |  12 +-
 src/gallium/drivers/swr/rasterizer/core/knobs.h|   3 +-
 .../drivers/swr/rasterizer/core/knobs_init.h   |  12 +-
 src/gallium/drivers/swr/rasterizer/core/pa.h   |   6 +-
 src/gallium/drivers/swr/rasterizer/core/state.h|  12 +-
 .../drivers/swr/rasterizer/core/threads.cpp|   4 +-
 src/gallium/drivers/swr/rasterizer/core/tilemgr.h  |  12 +-
 src/gallium/drivers/swr/rasterizer/core/utils.h|  10 +
 .../drivers/swr/rasterizer/jitter/JitManager.cpp   |  16 ++
 .../drivers/swr/rasterizer/jitter/JitManager.h |   8 +
 .../drivers/swr/rasterizer/jitter/blend_jit.cpp|   2 +-
 .../drivers/swr/rasterizer/jitter/builder_misc.cpp |   4 +-
 .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 175 -
 58 files changed, 1826 insertions(+), 840 deletions(-)
 create mode 100644 
src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h
 create mode 100644 
src/galli

[Mesa-dev] [PATCH v2 05/17] swr/rast: enable USE_SIMD16_FRONTEND by default

2017-08-01 Thread Tim Rowley
---
 src/gallium/drivers/swr/rasterizer/core/knobs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/knobs.h 
b/src/gallium/drivers/swr/rasterizer/core/knobs.h
index 7ad6fe3..10bd4a5 100644
--- a/src/gallium/drivers/swr/rasterizer/core/knobs.h
+++ b/src/gallium/drivers/swr/rasterizer/core/knobs.h
@@ -40,7 +40,7 @@
 
 #define ENABLE_AVX512_SIMD161
 #define USE_8x2_TILE_BACKEND1
-#define USE_SIMD16_FRONTEND 0
+#define USE_SIMD16_FRONTEND 1
 
 ///
 // Architecture validation
-- 
2.7.4

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[Mesa-dev] [PATCH v2 02/17] swr/rast: simdlib better seperation of core vs. knights avx512

2017-08-01 Thread Tim Rowley
---
 src/gallium/drivers/swr/Makefile.am|   2 +-
 src/gallium/drivers/swr/Makefile.sources   |   8 +
 .../drivers/swr/rasterizer/common/simdlib.hpp  |  21 ++-
 .../swr/rasterizer/common/simdlib_128_avx512.inl   | 108 +++-
 .../rasterizer/common/simdlib_128_avx512_core.inl  | 193 +
 .../common/simdlib_128_avx512_knights.inl  |  35 
 .../swr/rasterizer/common/simdlib_256_avx512.inl   | 128 +++---
 .../rasterizer/common/simdlib_256_avx512_core.inl  | 127 ++
 .../common/simdlib_256_avx512_knights.inl  |  35 
 .../swr/rasterizer/common/simdlib_512_avx512.inl   |  79 +++--
 .../rasterizer/common/simdlib_512_avx512_core.inl  | 181 +++
 .../common/simdlib_512_avx512_knights.inl  | 183 +++
 .../common/simdlib_512_avx512_masks_core.inl   |  27 +++
 .../common/simdlib_512_avx512_masks_knights.inl|  27 +++
 .../swr/rasterizer/common/simdlib_types.hpp|   2 +-
 15 files changed, 911 insertions(+), 245 deletions(-)
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx512_core.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx512_knights.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_256_avx512_core.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_256_avx512_knights.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_core.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_knights.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_masks_core.inl
 create mode 100644 
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512_masks_knights.inl

diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 05fc3b3..73fe904 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -285,7 +285,7 @@ lib_LTLIBRARIES += libswrKNL.la
 libswrKNL_la_CXXFLAGS = \
$(PTHREAD_CFLAGS) \
$(SWR_KNL_CXXFLAGS) \
-   -DKNOB_ARCH=KNOB_ARCH_AVX512 -DAVX512F_STRICT \
+   -DKNOB_ARCH=KNOB_ARCH_AVX512 -DSIMD_ARCH_KNIGHTS \
$(COMMON_CXXFLAGS)
 
 libswrKNL_la_SOURCES = \
diff --git a/src/gallium/drivers/swr/Makefile.sources 
b/src/gallium/drivers/swr/Makefile.sources
index 3c1118b..53f8bf0 100644
--- a/src/gallium/drivers/swr/Makefile.sources
+++ b/src/gallium/drivers/swr/Makefile.sources
@@ -69,11 +69,19 @@ COMMON_CXX_SOURCES := \
rasterizer/common/simdlib_128_avx.inl \
rasterizer/common/simdlib_128_avx2.inl \
rasterizer/common/simdlib_128_avx512.inl \
+   rasterizer/common/simdlib_128_avx512_core.inl \
+   rasterizer/common/simdlib_128_avx512_knights.inl \
rasterizer/common/simdlib_256_avx.inl \
rasterizer/common/simdlib_256_avx2.inl \
rasterizer/common/simdlib_256_avx512.inl \
+   rasterizer/common/simdlib_256_avx512_core.inl \
+   rasterizer/common/simdlib_256_avx512_knights.inl \
rasterizer/common/simdlib_512_avx512.inl \
+   rasterizer/common/simdlib_512_avx512_core.inl \
+   rasterizer/common/simdlib_512_avx512_knights.inl \
rasterizer/common/simdlib_512_avx512_masks.inl \
+   rasterizer/common/simdlib_512_avx512_masks_core.inl \
+   rasterizer/common/simdlib_512_avx512_masks_knights.inl \
rasterizer/common/simdlib_512_emu.inl \
rasterizer/common/simdlib_512_emu_masks.inl \
rasterizer/common/simdlib_interface.hpp \
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp 
b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
index fb11132..0c79cdd 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
@@ -55,6 +55,11 @@ namespace SIMDImpl
 {
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_128_avx512.inl"
+#if defined(SIMD_ARCH_KNIGHTS)
+#include "simdlib_128_avx512_knights.inl"
+#else // optimize for core
+#include "simdlib_128_avx512_core.inl"
+#endif // defined(SIMD_ARCH_KNIGHTS)
 #undef __SIMD_LIB_AVX512_HPP__
 }; // struct AVX2Impl
 #endif // #if SIMD_ARCH >= SIMD_ARCH_AVX512
@@ -105,6 +110,11 @@ namespace SIMDImpl
 {
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_256_avx512.inl"
+#if defined(SIMD_ARCH_KNIGHTS)
+#include "simdlib_256_avx512_knights.inl"
+#else // optimize for core
+#include "simdlib_256_avx512_core.inl"
+#endif // defined(SIMD_ARCH_KNIGHTS)
 #undef __SIMD_LIB_AVX512_HPP__
 }; // struct AVX2Impl
 #endif // #if SIMD_ARCH >= SIMD_ARCH_AVX512
@@ -150,13 +160,20 @@ namespace SIMDImpl
 
 
 #if SIMD_ARCH >= SIMD_ARCH_AVX512
-struct AVX512Impl
+struct AVX512Impl : AVXImplBase
 {
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_512_avx512.inl"
 #include "simdlib_512_avx512_masks.inl"
+#if defined(

[Mesa-dev] [PATCH v2 01/17] swr/rast: threadID via portable std::this_thread::get_id()

2017-08-01 Thread Tim Rowley
Replace use of Win32 GetCurrentThreadId() with portable
std::this_thread::get_id().
---
 .../codegen/templates/gen_ar_eventhandlerfile.hpp| 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git 
a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
index 9017e8d..0ca9a78 100644
--- 
a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
+++ 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
@@ -36,6 +36,7 @@
 #include "${event_header}"
 #include 
 #include 
+#include 
 
 namespace ArchRast
 {
@@ -56,21 +57,22 @@ namespace ArchRast
 std::stringstream outDir;
 outDir << KNOB_DEBUG_OUTPUT_DIR << pBaseName << "_" << pid << 
std::ends;
 CreateDirectory(outDir.str().c_str(), NULL);
-
-char buf[255];
+
 // There could be multiple threads creating thread pools. We
 // want to make sure they are uniquly identified by adding in
 // the creator's thread id into the filename.
-sprintf(buf, "%s\\ar_event%d_%d.bin", outDir.str().c_str(), 
GetCurrentThreadId(), id);
-mFilename = std::string(buf);
+std::stringstream fstr;
+fstr << outDir.str().c_str() << "\\ar_event" << 
std::this_thread::get_id();
+fstr << "_" << id << ".bin" << std::ends;
+mFilename = fstr.str();
 #else
-char buf[255];
 // There could be multiple threads creating thread pools. We
 // want to make sure they are uniquly identified by adding in
-// the creator's thread (process) id into the filename.
-// Assumes a 1:1 thread:LWP mapping as in linux.
-sprintf(buf, "%s/ar_event%d_%d.bin", "/tmp", 
GetCurrentProcessId(), id);
-mFilename = std::string(buf);
+// the creator's thread id into the filename.
+std::stringstream fstr;
+fstr << "/tmp/ar_event" << std::this_thread::get_id();
+fstr << "_" << id << ".bin" << std::ends;
+mFilename = fstr.str();
 #endif
 }
 
-- 
2.7.4

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[Mesa-dev] [PATCH v2 04/17] swr/rast: disable AVX512 optimization of SSE / AVX code

2017-08-01 Thread Tim Rowley
Disable an optimization which implemented sse/avx operations on avx512
using avx512 intrinsics (to avoid switching between lane widths).

Compile with SIMD_OPT_128_AVX512 / SIMD_OPT_256_AVX512 defined to enable
these optimizations.
---
 src/gallium/drivers/swr/rasterizer/common/simdlib.hpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp 
b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
index 0c79cdd..a4b5854 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
@@ -53,6 +53,7 @@ namespace SIMDImpl
 #if SIMD_ARCH >= SIMD_ARCH_AVX512
 struct AVX512Impl : AVX2Impl
 {
+#if defined(SIMD_OPT_128_AVX512)
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_128_avx512.inl"
 #if defined(SIMD_ARCH_KNIGHTS)
@@ -61,6 +62,7 @@ namespace SIMDImpl
 #include "simdlib_128_avx512_core.inl"
 #endif // defined(SIMD_ARCH_KNIGHTS)
 #undef __SIMD_LIB_AVX512_HPP__
+#endif // SIMD_OPT_128_AVX512
 }; // struct AVX2Impl
 #endif // #if SIMD_ARCH >= SIMD_ARCH_AVX512
 
@@ -108,6 +110,7 @@ namespace SIMDImpl
 #if SIMD_ARCH >= SIMD_ARCH_AVX512
 struct AVX512Impl : AVX2Impl
 {
+#if defined(SIMD_OPT_256_AVX512)
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_256_avx512.inl"
 #if defined(SIMD_ARCH_KNIGHTS)
@@ -116,6 +119,7 @@ namespace SIMDImpl
 #include "simdlib_256_avx512_core.inl"
 #endif // defined(SIMD_ARCH_KNIGHTS)
 #undef __SIMD_LIB_AVX512_HPP__
+#endif // SIMD_OPT_256_AVX512
 }; // struct AVX2Impl
 #endif // #if SIMD_ARCH >= SIMD_ARCH_AVX512
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v2 5/6] radeonsi: use slot indexes for bindless handles

2017-08-01 Thread Marek Olšák
There is an issue independent of this patch:

si_update_all_resident_texture_descriptors only updates resident
descriptors. Non-resident descriptors aren't updated, and
si_make_texture_handle_resident doesn't update them either. I think it
should be fixed in si_make_texture_handle_resident. Same for images.
It should be a separate patch.

This patch is:

Reviewed-by: Marek Olšák 

Marek

On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
 wrote:
> Using VRAM address as bindless handles is not a good idea because
> we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize
> because it has no information about the pointer.
>
> Instead, use slots indexes like the existing descriptors. Note
> that we use fixed 16-dword slots for both samplers and images.
> This doesn't really matter because no real apps use image handles.
>
> This improves performance with DOW3 by +7%.
>
> v2: - inline si_release_bindless_descriptors()
> - fix overwriting sampler and image slots
> - use fixed 16-dword slots for images
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 345 
> +++---
>  src/gallium/drivers/radeonsi/si_pipe.c|  12 -
>  src/gallium/drivers/radeonsi/si_pipe.h|  23 +-
>  src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c |  35 ++-
>  4 files changed, 195 insertions(+), 220 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 06a171ff9e..543a19ba1e 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -1852,16 +1852,20 @@ static void si_rebind_buffer(struct pipe_context 
> *ctx, struct pipe_resource *buf
>
> /* Bindless texture handles */
> if (rbuffer->texture_handle_allocated) {
> +   struct si_descriptors *descs = &sctx->bindless_descriptors;
> +
> util_dynarray_foreach(&sctx->resident_tex_handles,
>   struct si_texture_handle *, tex_handle) 
> {
> struct pipe_sampler_view *view = (*tex_handle)->view;
> -   struct si_bindless_descriptor *desc = 
> (*tex_handle)->desc;
> +   unsigned desc_slot = (*tex_handle)->desc_slot;
>
> if (view->texture == buf) {
> si_set_buf_desc_address(rbuffer,
> view->u.buf.offset,
> -   &desc->desc_list[4]);
> -   desc->dirty = true;
> +   descs->list +
> +   desc_slot * 16 + 4);
> +
> +   (*tex_handle)->desc_dirty = true;
> sctx->bindless_descriptors_dirty = true;
>
> radeon_add_to_buffer_list_check_mem(
> @@ -1874,10 +1878,12 @@ static void si_rebind_buffer(struct pipe_context 
> *ctx, struct pipe_resource *buf
>
> /* Bindless image handles */
> if (rbuffer->image_handle_allocated) {
> +   struct si_descriptors *descs = &sctx->bindless_descriptors;
> +
> util_dynarray_foreach(&sctx->resident_img_handles,
>   struct si_image_handle *, img_handle) {
> struct pipe_image_view *view = &(*img_handle)->view;
> -   struct si_bindless_descriptor *desc = 
> (*img_handle)->desc;
> +   unsigned desc_slot = (*img_handle)->desc_slot;
>
> if (view->resource == buf) {
> if (view->access & PIPE_IMAGE_ACCESS_WRITE)
> @@ -1885,8 +1891,10 @@ static void si_rebind_buffer(struct pipe_context *ctx, 
> struct pipe_resource *buf
>
> si_set_buf_desc_address(rbuffer,
> view->u.buf.offset,
> -   &desc->desc_list[4]);
> -   desc->dirty = true;
> +   descs->list +
> +   desc_slot * 16 + 4);
> +
> +   (*img_handle)->desc_dirty = true;
> sctx->bindless_descriptors_dirty = true;
>
> radeon_add_to_buffer_list_check_mem(
> @@ -1918,11 +1926,19 @@ static void si_invalidate_buffer(struct pipe_context 
> *ctx, struct pipe_resource
>  }
>
>  static void si_upload_bindless_descriptor(struct si_context *sctx,
> - struct si_bindless_descriptor *desc)
> + unsigned desc_slot,
> + unsigned num_dw

[Mesa-dev] [PATCH 3/5] anv: Use python to generate ICD json files

2017-08-01 Thread Jason Ekstrand
This is more lines of code but the python is far easier to read than the
sed expressions we were using before.  Also, this allows us to pull the
API version from anv_entrypoints.py so it never gets out-of-sync.
---
 src/intel/Makefile.vulkan.am   | 16 ++---
 src/intel/vulkan/anv_icd.py| 47 ++
 src/intel/vulkan/dev_icd.json.in   |  7 --
 src/intel/vulkan/intel_icd.json.in |  7 --
 4 files changed, 54 insertions(+), 23 deletions(-)
 create mode 100644 src/intel/vulkan/anv_icd.py
 delete mode 100644 src/intel/vulkan/dev_icd.json.in
 delete mode 100644 src/intel/vulkan/intel_icd.json.in

diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index f91fdc6..de5c09f 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -50,15 +50,13 @@ EXTRA_DIST += \
vulkan/intel_icd.json.in \
vulkan/TODO
 
-vulkan/dev_icd.json : vulkan/dev_icd.json.in
-   $(AM_V_GEN) $(SED) \
-   -e "s#@build_libdir@#${abs_top_builddir}/${LIB_DIR}#" \
-   < $(srcdir)/vulkan/dev_icd.json.in > $@
-
-vulkan/intel_icd.@host_cpu@.json : vulkan/intel_icd.json.in
-   $(AM_V_GEN) $(SED) \
-   -e "s#@install_libdir@#${libdir}#" \
-   < $(srcdir)/vulkan/intel_icd.json.in > $@
+vulkan/dev_icd.json : vulkan/anv_extensions.py vulkan/anv_icd.py
+   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
+   --lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@
+
+vulkan/intel_icd.@host_cpu@.json : vulkan/anv_extensions.py vulkan/anv_icd.py
+   $(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
+   --lib-path="${libdir}" --out $@
 
 if HAVE_INTEL_VULKAN
 
diff --git a/src/intel/vulkan/anv_icd.py b/src/intel/vulkan/anv_icd.py
new file mode 100644
index 000..4ed01fa
--- /dev/null
+++ b/src/intel/vulkan/anv_icd.py
@@ -0,0 +1,47 @@
+# Copyright 2017 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sub license, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice (including the
+# next paragraph) shall be included in all copies or substantial portions
+# of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+# IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+# ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+import json
+import os.path
+
+from anv_extensions import *
+
+if __name__ == '__main__':
+parser = argparse.ArgumentParser()
+parser.add_argument('--out', help='Output jsono file.', required=True)
+parser.add_argument('--lib-path', help='Path to libvulkan_intel.so')
+args = parser.parse_args()
+
+path = 'libvulkan_intel.so'
+if args.lib_path:
+path = os.path.join(args.lib_path, path)
+
+json_data = {
+'file_format_version': '1.0.0',
+'ICD': {
+'library_path': path,
+'api_version': str(MAX_API_VERSION),
+},
+}
+
+with open(args.out, 'w') as f:
+json.dump(json_data, f, indent = 4)
diff --git a/src/intel/vulkan/dev_icd.json.in b/src/intel/vulkan/dev_icd.json.in
deleted file mode 100644
index 84ac3d4..000
--- a/src/intel/vulkan/dev_icd.json.in
+++ /dev/null
@@ -1,7 +0,0 @@
-{
-"file_format_version": "1.0.0",
-"ICD": {
-"library_path": "@build_libdir@/libvulkan_intel.so",
-"api_version": "1.0.54"
-}
-}
diff --git a/src/intel/vulkan/intel_icd.json.in 
b/src/intel/vulkan/intel_icd.json.in
deleted file mode 100644
index 61db4bf..000
--- a/src/intel/vulkan/intel_icd.json.in
+++ /dev/null
@@ -1,7 +0,0 @@
-{
-"file_format_version": "1.0.0",
-"ICD": {
-"library_path": "@install_libdir@/libvulkan_intel.so",
-"api_version": "1.0.54"
-}
-}
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 4/5] anv: Pull the API version from anv_extensions.py

2017-08-01 Thread Jason Ekstrand
This way everything stays in sync and we only have the one version
number.
---
 src/intel/vulkan/anv_device.c  |  2 +-
 src/intel/vulkan/anv_extensions.py | 11 +++
 src/intel/vulkan/anv_private.h |  1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 70b5cd1..793e519 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -794,7 +794,7 @@ void anv_GetPhysicalDeviceProperties(
};
 
*pProperties = (VkPhysicalDeviceProperties) {
-  .apiVersion = VK_MAKE_VERSION(1, 0, 54),
+  .apiVersion = anv_physical_device_api_version(pdevice),
   .driverVersion = vk_get_driver_version(),
   .vendorID = 0x8086,
   .deviceID = pdevice->chipset_id,
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 7307cac..f4bfcf1 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -91,6 +91,10 @@ class VkVersion:
 ver_list.append(str(self.patch))
 return '.'.join(ver_list)
 
+def c_vk_version(self):
+ver_list = [str(self.major), str(self.minor), str(self.patch)]
+return 'VK_MAKE_VERSION(' + ', '.join(ver_list) + ')'
+
 def __int_ver(self):
 # This is just an expansion of VK_VERSION
 patch = self.patch if self.patch is not None else 0
@@ -173,6 +177,12 @@ VkResult anv_EnumerateInstanceExtensionProperties(
 return vk_outarray_status(&out);
 }
 
+uint32_t
+anv_physical_device_api_version(struct anv_physical_device *dev)
+{
+return ${MAX_API_VERSION.c_vk_version()};
+}
+
 bool
 anv_physical_device_extension_supported(struct anv_physical_device *device,
 const char *name)
@@ -218,6 +228,7 @@ if __name__ == '__main__':
 _init_exts_from_xml(args.xml)
 
 template_env = {
+'MAX_API_VERSION': MAX_API_VERSION,
 'instance_extensions': [e for e in EXTENSIONS if e.type == 'instance'],
 'device_extensions': [e for e in EXTENSIONS if e.type == 'device'],
 }
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 818f699..c364491 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -685,6 +685,7 @@ VkResult anv_init_wsi(struct anv_physical_device 
*physical_device);
 void anv_finish_wsi(struct anv_physical_device *physical_device);
 
 bool anv_instance_extension_supported(const char *name);
+uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
  const char *name);
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 5/5] anv: Bump the advertised version to 1.0.57

2017-08-01 Thread Jason Ekstrand
---
 src/intel/vulkan/anv_extensions.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index f4bfcf1..49254c1 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -31,7 +31,7 @@ import xml.etree.cElementTree as et
 
 from mako.template import Template
 
-MAX_API_VERSION = '1.0.54'
+MAX_API_VERSION = '1.0.57'
 
 class Extension:
 def __init__(self, name, ext_version, enable):
-- 
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[Mesa-dev] [PATCH 2/5] anv: Add MAX_API_VERSION to anv_extensions.py

2017-08-01 Thread Jason Ekstrand
The VkVersion class is probably overkill but it makes it really easy to
compare versions in a way that's safe without the caller having to think
about patch vs. no patch.
---
 src/intel/vulkan/anv_entrypoints_gen.py |  4 +--
 src/intel/vulkan/anv_extensions.py  | 43 +
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 9177a94..f5c527e 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -32,8 +32,6 @@ from mako.template import Template
 
 from anv_extensions import *
 
-MAX_API_VERSION = 1.0
-
 # We generate a static hash table for entry point lookup
 # (vkGetProcAddress). We use a linear congruential generator for our hash
 # function and a power-of-two size table. The prime numbers are determined
@@ -262,7 +260,7 @@ def get_entrypoints(doc, entrypoints_to_defines):
 enabled_commands = set()
 for feature in doc.findall('./feature'):
 assert feature.attrib['api'] == 'vulkan'
-if float(feature.attrib['number']) > MAX_API_VERSION:
+if VkVersion(feature.attrib['number']) > MAX_API_VERSION:
 continue
 
 for command in feature.findall('./require/command'):
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 0d243c6..7307cac 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -25,10 +25,14 @@ COPYRIGHT = """\
 """
 
 import argparse
+import copy
+import re
 import xml.etree.cElementTree as et
 
 from mako.template import Template
 
+MAX_API_VERSION = '1.0.54'
+
 class Extension:
 def __init__(self, name, ext_version, enable):
 self.name = name
@@ -64,6 +68,45 @@ EXTENSIONS = [
 Extension('VK_KHX_multiview', 1, True),
 ]
 
+class VkVersion:
+def __init__(self, string):
+split = string.split('.')
+self.major = int(split[0])
+self.minor = int(split[1])
+if len(split) > 2:
+assert len(split) == 3
+self.patch = int(split[2])
+else:
+self.patch = None
+
+# Sanity check.  The range bits are required by the definition of the
+# VK_MAKE_VERSION macro
+assert self.major < 1024 and self.minor < 1024
+assert self.patch is None or self.patch < 4096
+assert(str(self) == string)
+
+def __str__(self):
+ver_list = [str(self.major), str(self.minor)]
+if self.patch is not None:
+ver_list.append(str(self.patch))
+return '.'.join(ver_list)
+
+def __int_ver(self):
+# This is just an expansion of VK_VERSION
+patch = self.patch if self.patch is not None else 0
+return (self.major << 22) | (self.minor << 12) | patch
+
+def __cmp__(self, other):
+# If only one of them has a patch version, "ignore" it by making
+# other's patch version match self.
+if (self.patch is None) != (other.patch is None):
+other = copy.copy(other)
+other.patch = self.patch
+
+return self.__int_ver().__cmp__(other.__int_ver())
+
+MAX_API_VERSION = VkVersion(MAX_API_VERSION)
+
 def _init_exts_from_xml(xml):
 """ Walk the Vulkan XML and fill out extra extension information. """
 
-- 
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[Mesa-dev] [PATCH 1/5] anv: Make some bits of anv_extensions module-private

2017-08-01 Thread Jason Ekstrand
This way we can use "from anv_extensions import *" in the entrypoint
generator without worrying too much about pollution
---
 src/intel/vulkan/anv_entrypoints_gen.py | 4 ++--
 src/intel/vulkan/anv_extensions.py  | 8 
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 0c6e310..9177a94 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -30,7 +30,7 @@ import xml.etree.cElementTree as et
 
 from mako.template import Template
 
-import anv_extensions
+from anv_extensions import *
 
 MAX_API_VERSION = 1.0
 
@@ -268,7 +268,7 @@ def get_entrypoints(doc, entrypoints_to_defines):
 for command in feature.findall('./require/command'):
 enabled_commands.add(command.attrib['name'])
 
-supported = set(ext.name for ext in anv_extensions.EXTENSIONS)
+supported = set(ext.name for ext in EXTENSIONS)
 for extension in doc.findall('.extensions/extension'):
 if extension.attrib['name'] not in supported:
 continue
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 005a514..0d243c6 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -64,7 +64,7 @@ EXTENSIONS = [
 Extension('VK_KHX_multiview', 1, True),
 ]
 
-def init_exts_from_xml(xml):
+def _init_exts_from_xml(xml):
 """ Walk the Vulkan XML and fill out extra extension information. """
 
 xml = et.parse(xml)
@@ -84,7 +84,7 @@ def init_exts_from_xml(xml):
 for ext in EXTENSIONS:
 assert ext.type == 'instance' or ext.type == 'device'
 
-TEMPLATE = Template(COPYRIGHT + """
+_TEMPLATE = Template(COPYRIGHT + """
 #include "anv_private.h"
 
 #include "vk_util.h"
@@ -172,7 +172,7 @@ if __name__ == '__main__':
 parser.add_argument('--xml', help='Vulkan API XML file.', required=True)
 args = parser.parse_args()
 
-init_exts_from_xml(args.xml)
+_init_exts_from_xml(args.xml)
 
 template_env = {
 'instance_extensions': [e for e in EXTENSIONS if e.type == 'instance'],
@@ -180,4 +180,4 @@ if __name__ == '__main__':
 }
 
 with open(args.out, 'w') as f:
-f.write(TEMPLATE.render(**template_env))
+f.write(_TEMPLATE.render(**template_env))
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH mesa 4/4] egl/drm: clamp image to buffer size in swrast_{get_image, put_image2}

2017-08-01 Thread Eric Engestrom
I have pushed 1-3.

DanielS, do we want this one too?

Emil, I just realized that 2 and 3 depend on 1, but 1 isn't nominated
for stable. I'll let you decide whether to pull all 3 in 17.2 or not.


On Wednesday, 2017-07-19 15:05:32 +0100, Eric Engestrom wrote:
> From: Mun Gwan-gyeong 
> 
> It adds limits of the height and the width on the copy region.
> 
> Cc: Daniel Stone 
> Signed-off-by: Mun Gwan-gyeong 
> 
> [Eric: compare coordinates instead of bytes (Suggested by DanielS)]
> Signed-off-by: Eric Engestrom 
> ---
>  src/egl/drivers/dri2/platform_drm.c | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/src/egl/drivers/dri2/platform_drm.c 
> b/src/egl/drivers/dri2/platform_drm.c
> index a952aa5456..b3c2563c2e 100644
> --- a/src/egl/drivers/dri2/platform_drm.c
> +++ b/src/egl/drivers/dri2/platform_drm.c
> @@ -530,6 +530,12 @@ swrast_put_image2(__DRIdrawable *driDrawable,
> int x_bytes, width_bytes;
> char *src, *dst;
>  
> +   if (height > dri2_surf->base.Height - y)
> +  height = dri2_surf->base.Height - y;
> +
> +   if (width > dri2_surf->base.Width - x)
> +  width = dri2_surf->base.Width  - x;
> +
> if (op != __DRI_SWRAST_IMAGE_OP_DRAW &&
> op != __DRI_SWRAST_IMAGE_OP_SWAP)
>return;
> @@ -579,6 +585,12 @@ swrast_get_image(__DRIdrawable *driDrawable,
> int x_bytes, width_bytes;
> char *src, *dst;
>  
> +   if (height > dri2_surf->base.Height - y)
> +  height = dri2_surf->base.Height - y;
> +
> +   if (width > dri2_surf->base.Width - x)
> +  width = dri2_surf->base.Width  - x;
> +
> if (get_swrast_front_bo(dri2_surf) < 0)
>return;
>  
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [PATCH] gles: Restore some lost typedefs

2017-08-01 Thread Eric Engestrom
On Monday, 2017-07-17 11:00:26 -0700, Scott D Phillips wrote:
> Eric Engestrom  writes:
> 
> > On Friday, 2017-06-30 15:06:36 -0700, Ian Romanick wrote:
> >> Has this been reported to upstream (i.e., Khronos)?  I don't mind fixing
> >> these in our tree, but they really should get fixed at the source too.
> >
> > I can't see any mention of this on neither the old Bugzilla (both
> > private and public) nor in the GitLab or the GitHub issues.
> >
> > Scott, would you care to raise a bug? [1] if you have Khronos access,
> > or [2] otherwise.
> 
> I have filed an issue and pull request for this in the Khronos repo:
> 
> https://github.com/KhronosGroup/OpenGL-Registry/pull/76
> 
> https://github.com/KhronosGroup/OpenGL-Registry/issues/77

Since the fix hasn't been merged yet, I'm merging this patch with a big
warning that it should be reverted when updating to the fixed upstream
header.

Cheers,
  Eric
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[Mesa-dev] [Bug 102003] Mesa demos doesn't compile due to gles1

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102003

Eric Engestrom  changed:

   What|Removed |Added

 Blocks||101191


Referenced Bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=101191
[Bug 101191] [NVC3] Vsync stops working after mode changes in nouveau DDX
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[Mesa-dev] [Bug 102003] Mesa demos doesn't compile due to gles1

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102003

Eric Engestrom  changed:

   What|Removed |Added

 Blocks|101191  |101911


Referenced Bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=101191
[Bug 101191] [NVC3] Vsync stops working after mode changes in nouveau DDX
https://bugs.freedesktop.org/show_bug.cgi?id=101911
[Bug 101911] [TRACKER] Mesa 17.2 release tracker
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Re: [Mesa-dev] [PATCH 12/13] swr/rast: split gen_knobs template into .cpp and .h files

2017-08-01 Thread Rowley, Timothy O

On Jul 31, 2017, at 3:18 PM, Emil Velikov 
mailto:emil.l.veli...@gmail.com>> wrote:

Hi Tim,

What's the goal behind the split. Please add a couple of words in the
commit message.

Will do.


On 31 July 2017 at 20:40, Tim Rowley 
mailto:timothy.o.row...@intel.com>> wrote:
---
src/gallium/drivers/swr/Makefile.am|   3 +-
src/gallium/drivers/swr/SConscript |   4 +-
.../drivers/swr/rasterizer/codegen/gen_knobs.py|  14 +-
.../swr/rasterizer/codegen/templates/gen_knobs.cpp | 112 +---
.../swr/rasterizer/codegen/templates/gen_knobs.h   | 147 +
.../drivers/swr/rasterizer/core/knobs_init.h   |  12 +-
6 files changed, 166 insertions(+), 126 deletions(-)
create mode 100644 
src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h

diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 73fe904..b20f128 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -115,7 +115,7 @@ rasterizer/codegen/gen_knobs.cpp: 
rasterizer/codegen/gen_knobs.py rasterizer/cod
   --output rasterizer/codegen/gen_knobs.cpp \
   --gen_cpp

-rasterizer/codegen/gen_knobs.h: rasterizer/codegen/gen_knobs.py 
rasterizer/codegen/knob_defs.py rasterizer/codegen/templates/gen_knobs.cpp 
rasterizer/codegen/gen_common.py
+rasterizer/codegen/gen_knobs.h: rasterizer/codegen/gen_knobs.py 
rasterizer/codegen/knob_defs.py rasterizer/codegen/templates/gen_knobs.h 
rasterizer/codegen/gen_common.py
   $(MKDIR_GEN)
   $(PYTHON_GEN) \
   $(srcdir)/rasterizer/codegen/gen_knobs.py \
@@ -347,5 +347,6 @@ EXTRA_DIST = \
   rasterizer/codegen/templates/gen_builder.hpp \
   rasterizer/codegen/templates/gen_header_init.hpp \
   rasterizer/codegen/templates/gen_knobs.cpp \
+   rasterizer/codegen/templates/gen_knobs.h \
   rasterizer/codegen/templates/gen_llvm.hpp \
   rasterizer/codegen/templates/gen_rasterizer.cpp
diff --git a/src/gallium/drivers/swr/SConscript 
b/src/gallium/drivers/swr/SConscript
index a32807d..b394cbc 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -53,8 +53,8 @@ env.CodeGenerate(
source = '',
command = python_cmd + ' $SCRIPT --output $TARGET --gen_h'
)
-Depends('rasterizer/codegen/gen_knobs.cpp',
Seems like this should have been gen_knobs.h in the first place - oops :-)

Yep, noticed that bug when updating the rule - I’ve pulled the fix into a 
separate commit.


-swrroot + 'rasterizer/codegen/templates/gen_knobs.cpp')
+Depends('rasterizer/codegen/gen_knobs.h',
+swrroot + 'rasterizer/codegen/templates/gen_knobs.h')


The build bits are
Reviewed-by: Emil Velikov 
mailto:emil.veli...@collabora.com>>

--- /dev/null
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_knobs.h
@@ -0,0 +1,147 @@
+/**
+*
+* Copyright 2015-2017
+* Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http 
://www.apache.org/licenses/LICENSE-2.0
+*
I'm not a lawyer so I'm not sure if having Apache licensed code is
fine with rest of Mesa.

Considering that rest of SWR (barring the original gen_knobs.cpp where
this is comes from) uses MIT X11/Expat I'd stay consistent and
re-license this/these files.
If possible, of course.

Adding files with another license was unintentional - I’ve added a relicense 
commit prior to the split.



--- a/src/gallium/drivers/swr/rasterizer/core/knobs_init.h
+++ b/src/gallium/drivers/swr/rasterizer/core/knobs_init.h
@@ -91,16 +91,18 @@ static inline void ConvertEnvToKnob(const char* pOverride, 
std::string& knobValu
template 
static inline void InitKnob(T& knob)
{
-
-// TODO, read registry first
-
-// Second, read environment variables
+// Read environment variables
const char* pOverride = getenv(knob.Name());

if (pOverride)
{
-auto knobValue = knob.Value();
+auto knobValue = knob.DefaultValue();
ConvertEnvToKnob(pOverride, knobValue);
knob.Value(knobValue);
}
+else
+{
+// Set default value
+knob.Value(knob.DefaultValue());
This and the underlying code seems to have changed a bit.

Would be nice to keep "dummy split" and functionality changes as
separate patches.
Then again: it's not my code, so please don't read too much into my suggestion.

I’ve unwoven this commit into five commits for the upcoming v2 of the patchset:

commit 566ea1983277bf62f07ea02571854009b667081f
Author: Tim Rowley 
mailto:timothy.o.row...@intel.com>>
Date:   Mon Jul 31 17:22:54 2017 -0500

swr/rast: simplify knob default value setup

commit f83d47cd01d987600b59106828bb75c672ea610c
Author: Tim Rowley 
mailto:timothy.o.row...

Re: [Mesa-dev] [PATCH v2 4/6] radeonsi: add si_emit_graphics_shader_pointers() helper

2017-08-01 Thread Marek Olšák
On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
 wrote:
> To share common code between rw buffers and bindless descriptors.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 57 
> +++
>  1 file changed, 31 insertions(+), 26 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 91204f0102..06a171ff9e 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -2162,6 +2162,35 @@ static void si_emit_shader_pointer(struct si_context 
> *sctx,
> radeon_emit(cs, va >> 32);
>  }
>
> +static void si_emit_graphics_shader_pointers(struct si_context *sctx,
> +struct si_descriptors *descs)
> +{
> +   si_emit_shader_pointer(sctx, descs,
> +  R_00B030_SPI_SHADER_USER_DATA_PS_0);
> +   si_emit_shader_pointer(sctx, descs,
> +  R_00B130_SPI_SHADER_USER_DATA_VS_0);
> +
> +   if (sctx->b.chip_class >= GFX9) {
> +   /* GFX9 merged LS-HS and ES-GS.
> +* Set RW_BUFFERS in the special registers, so that
> +* it's preloaded into s[0:1] instead of s[8:9].
> +*/
> +   si_emit_shader_pointer(sctx, descs,
> +  
> R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS);
> +   si_emit_shader_pointer(sctx, descs,
> +  
> R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS);

This GFX9 code is not reusable. SPI_SHADER_USER_DATA_ADDR_LO & HI
refer to exactly 2 SGPRs and there are no other user SGPRs around
that. This is how SGPRs are loaded for GFX9 HS and GS stages:

s0 = SPI_SHADER_USER_DATA_ADDR_LO_GS/HS
s1 = SPI_SHADER_USER_DATA_ADDR_HI_GS/HS
s2 = hw-specific system values
s3 = hw-specific system values
s4 = hw-specific system values
s5 = hw-specific system values
s6 = (SPI_SHADER_PGM_LO+HI_GS/HS << 8)
s7 = (SPI_SHADER_PGM_LO+HI_GS/HS << 8) >> 32
s8 = SPI_SHADER_USER_DATA_ES/LS_0
...
s39 = SPI_SHADER_USER_DATA_ES/LS_31

That should explain the layout for SI_SHADER_MERGED_VERTEX_*. I admit
it wasn't properly documented.

Marek
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[Mesa-dev] [Bug 102003] Mesa demos doesn't compile due to gles1

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102003

--- Comment #2 from Eric Engestrom  ---
This is an issue with the upstream headers, which has been reported [1] and a
fix suggested [2].
We will pull the update headers once Khronos merges the fix.
In the mean time, this patch [3] should fix the issue.

[1] https://github.com/KhronosGroup/OpenGL-Registry/issues/77
[2] https://github.com/KhronosGroup/OpenGL-Registry/pull/76
[3] https://lists.freedesktop.org/archives/mesa-dev/2017-June/161647.html

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Re: [Mesa-dev] [PATCH v2 2/6] radeonsi: make some si_descriptors fields 32-bit

2017-08-01 Thread Marek Olšák
Reviewed-by: Marek Olšák 

Marek

On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
 wrote:
> The number of bindless descriptors is dynamic and we definitely
> have to support more than 256 slots.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_state.h | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.h 
> b/src/gallium/drivers/radeonsi/si_state.h
> index ec28abaf9a..c1fb5beef0 100644
> --- a/src/gallium/drivers/radeonsi/si_state.h
> +++ b/src/gallium/drivers/radeonsi/si_state.h
> @@ -235,7 +235,7 @@ struct si_descriptors {
> /* The size of one descriptor. */
> ubyte element_dw_size;
> /* The maximum number of descriptors. */
> -   ubyte num_elements;
> +   uint32_t num_elements;
>
> /* Offset in CE RAM */
> uint16_t ce_offset;
> @@ -244,16 +244,16 @@ struct si_descriptors {
>  * range, direct uploads to memory will be used instead. This 
> basically
>  * governs switching between onchip (CE) and offchip (upload) modes.
>  */
> -   ubyte first_ce_slot;
> -   ubyte num_ce_slots;
> +   uint32_t first_ce_slot;
> +   uint32_t num_ce_slots;
>
> /* Slots that are used by currently-bound shaders.
>  * With CE: It determines which slots are dumped to L2.
>  *  It doesn't skip uploads to CE RAM.
>  * Without CE: It determines which slots are uploaded.
>  */
> -   ubyte first_active_slot;
> -   ubyte num_active_slots;
> +   uint32_t first_active_slot;
> +   uint32_t num_active_slots;
>
> /* Whether CE is used to upload this descriptor array. */
> bool uses_ce;
> --
> 2.13.3
>
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Re: [Mesa-dev] [PATCH v2 3/6] radeonsi: only initialize dirty_mask when CE is used

2017-08-01 Thread Marek Olšák
Reviewed-by: Marek Olšák 

Marek

On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
 wrote:
> Looks like it's useless to initialize that field when CE is
> unused. This will also allow to declare more than 64 elements
> for the array of bindless descriptors.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 18b070ba3a..91204f0102 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -120,19 +120,20 @@ static void si_init_descriptors(struct si_context *sctx,
> unsigned num_ce_slots,
> unsigned *ce_offset)
>  {
> -   assert(num_elements <= sizeof(desc->dirty_mask)*8);
> -
> desc->list = CALLOC(num_elements, element_dw_size * 4);
> desc->element_dw_size = element_dw_size;
> desc->num_elements = num_elements;
> desc->first_ce_slot = sctx->ce_ib ? first_ce_slot : 0;
> desc->num_ce_slots = sctx->ce_ib ? num_ce_slots : 0;
> -   desc->dirty_mask = u_bit_consecutive64(0, num_elements);
> +   desc->dirty_mask = 0;
> desc->shader_userdata_offset = shader_userdata_index * 4;
>
> if (desc->num_ce_slots) {
> +   assert(num_elements <= sizeof(desc->dirty_mask)*8);
> +
> desc->uses_ce = true;
> desc->ce_offset = *ce_offset;
> +   desc->dirty_mask = u_bit_consecutive64(0, num_elements);
>
> *ce_offset += element_dw_size * desc->num_ce_slots * 4;
> }
> --
> 2.13.3
>
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Re: [Mesa-dev] [PATCH 1/2] anv: Add a new centralized extensions file

2017-08-01 Thread Lionel Landwerlin

Both patches are :

Reviewed-by: Lionel Landwerlin 

On 14/07/17 07:14, Jason Ekstrand wrote:

This will allow us to keep everything in one place when it comes to
declaring what extensions are supported.
---
  src/intel/Makefile.vulkan.am|  3 +-
  src/intel/vulkan/anv_entrypoints_gen.py | 27 +++---
  src/intel/vulkan/anv_extensions.py  | 63 +
  3 files changed, 69 insertions(+), 24 deletions(-)
  create mode 100644 src/intel/vulkan/anv_extensions.py

diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 6550f68..d6e11f8 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -24,7 +24,8 @@
  # out and we'll fail at `make dist'
  vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
  
-vulkan/anv_entrypoints.c: vulkan/anv_entrypoints_gen.py $(vulkan_api_xml)

+vulkan/anv_entrypoints.c: vulkan/anv_entrypoints_gen.py \
+ vulkan/anv_extensions.py $(vulkan_api_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_entrypoints_gen.py \
--xml $(vulkan_api_xml) --outdir $(builddir)/vulkan
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index e59c494..0c6e310 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -30,29 +30,9 @@ import xml.etree.cElementTree as et
  
  from mako.template import Template
  
-MAX_API_VERSION = 1.0

+import anv_extensions
  
-SUPPORTED_EXTENSIONS = [

-'VK_KHR_dedicated_allocation',
-'VK_KHR_descriptor_update_template',
-'VK_KHR_external_memory',
-'VK_KHR_external_memory_capabilities',
-'VK_KHR_external_memory_fd',
-'VK_KHR_get_memory_requirements2',
-'VK_KHR_get_physical_device_properties2',
-'VK_KHR_get_surface_capabilities2',
-'VK_KHR_incremental_present',
-'VK_KHR_maintenance1',
-'VK_KHR_push_descriptor',
-'VK_KHR_sampler_mirror_clamp_to_edge',
-'VK_KHR_shader_draw_parameters',
-'VK_KHR_surface',
-'VK_KHR_swapchain',
-'VK_KHR_wayland_surface',
-'VK_KHR_xcb_surface',
-'VK_KHR_xlib_surface',
-'VK_KHX_multiview',
-]
+MAX_API_VERSION = 1.0
  
  # We generate a static hash table for entry point lookup

  # (vkGetProcAddress). We use a linear congruential generator for our hash
@@ -288,8 +268,9 @@ def get_entrypoints(doc, entrypoints_to_defines):
  for command in feature.findall('./require/command'):
  enabled_commands.add(command.attrib['name'])
  
+supported = set(ext.name for ext in anv_extensions.EXTENSIONS)

  for extension in doc.findall('.extensions/extension'):
-if extension.attrib['name'] not in SUPPORTED_EXTENSIONS:
+if extension.attrib['name'] not in supported:
  continue
  
  assert extension.attrib['supported'] == 'vulkan'

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
new file mode 100644
index 000..79d6bb2
--- /dev/null
+++ b/src/intel/vulkan/anv_extensions.py
@@ -0,0 +1,63 @@
+COPYRIGHT = """\
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+"""
+
+import argparse
+import xml.etree.cElementTree as et
+
+from mako.template import Template
+
+class Extension:
+def __init__(self, name, ext_version, enable):
+self.name = name
+self.ext_version = int(ext_version)
+if enable is True:
+self.enable = 'true';
+elif enable is False:
+self.enable = 'false';
+else:
+self.enable = enable;
+
+EXTENSIONS = [
+Extension('VK_KHR_dedicated_allocation',  1, True),
+Extension('VK_KHR_descriptor_update_template',1, True),
+Extension('VK_KHR_external_memory',   1, True),
+Extension('VK_KHR_external_memory_capabilit

Re: [Mesa-dev] [PATCH] Convert git_sha1_gen script to Python.

2017-08-01 Thread Rob Herring
On Tue, Aug 1, 2017 at 8:38 AM, Jose Fonseca  wrote:
> Python is the scripting language we've been using for scripts that need
> to run across all supported platforms.
>
> Shell is *not* a portable language for scripts.
> ---

[...]

> diff --git a/src/mesa/Android.libmesa_git_sha1.mk 
> b/src/mesa/Android.libmesa_git_sha1.mk
> index 7d64b1c809..f66f88484b 100644
> --- a/src/mesa/Android.libmesa_git_sha1.mk
> +++ b/src/mesa/Android.libmesa_git_sha1.mk
> @@ -46,7 +46,7 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, 
> git_sha1.h)
>  $(intermediates)/git_sha1.h: $(wildcard $(MESA_TOP)/.git/logs/HEAD)
> @mkdir -p $(dir $@)
> @echo "GIT-SHA1: $(PRIVATE_MODULE) <= git"
> -   $(hide) sh $(MESA_TOP)/bin/git_sha1_gen.sh > $@
> +   $(hide) python $(MESA_TOP)/bin/git_sha1_gen.py > $@

s/python/$(MESA_PYTHON2)/

Rob
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Re: [Mesa-dev] [PATCH 11/13] swr/rast: fixes for 32-bit builds

2017-08-01 Thread Rowley, Timothy O

> On Jul 31, 2017, at 3:56 PM, Emil Velikov  wrote:
> 
> Hi Tim,
> 
> Some of the inline functions seem unused.
> Very quick search showed the following:
> 
> InterpolateComponent
> _simd128_abs_ps
> _simd_abs_ps

The intent of simdlib is a general purpose vector library, so some 
functions/methods are in there for completeness sake so that when a developer 
is using it in the future they’re not surprised by obvious holes in the api.

> Might be worth cleaning things up, first?

I’ve been experimenting with —print-gc-sections to see if I can prune used code 
from the tree, but real unused functions seem to get lost in the inline 
functions/methods defined in headers which the linker is reaping as expected.

> -Emil

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Re: [Mesa-dev] [PATCH mesa 1/3] egl: deduplicate swap interval clamping logic

2017-08-01 Thread Tapani Pälli

lgtm
Reviewed-by: Tapani Pälli 

On 08/01/2017 03:55 PM, Eric Engestrom wrote:

Signed-off-by: Eric Engestrom 
Reviewed-by: Daniel Stone 
---
  src/egl/drivers/dri2/platform_wayland.c | 14 +-
  src/egl/drivers/dri2/platform_x11.c |  9 +
  src/egl/main/eglapi.c   | 12 +++-
  src/egl/main/eglsurface.c   | 19 +--
  4 files changed, 14 insertions(+), 40 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index ff35507d25..02db473c8c 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -63,10 +63,6 @@ enum wl_drm_format_flags {
 HAS_RGB565 = 4,
  };
  
-static EGLBoolean

-dri2_wl_swap_interval(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf,
-  EGLint interval);
-
  static int
  roundtrip(struct dri2_egl_display *dri2_dpy)
  {
@@ -230,8 +226,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay 
*disp,
 goto cleanup_surf;
  }
  
-   dri2_wl_swap_interval(drv, disp, &dri2_surf->base,

- dri2_dpy->default_swap_interval);
+   dri2_surf->base.SwapInterval = dri2_dpy->default_swap_interval;
  
 return &dri2_surf->base;
  
@@ -1150,13 +1145,6 @@ dri2_wl_swap_interval(_EGLDriver *drv,

 _EGLSurface *surf,
 EGLint interval)
  {
-   if (interval > surf->Config->MaxSwapInterval)
-  interval = surf->Config->MaxSwapInterval;
-   else if (interval < surf->Config->MinSwapInterval)
-  interval = surf->Config->MinSwapInterval;
-
-   surf->SwapInterval = interval;
-
 return EGL_TRUE;
  }
  
diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/platform_x11.c

index b01f739010..35c62a4975 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -956,16 +956,9 @@ dri2_x11_swap_interval(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *surf,
 struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
 struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
  
-   if (interval > surf->Config->MaxSwapInterval)

-  interval = surf->Config->MaxSwapInterval;
-   else if (interval < surf->Config->MinSwapInterval)
-  interval = surf->Config->MinSwapInterval;
-
-   if (interval != surf->SwapInterval && dri2_dpy->swap_available)
+   if (dri2_dpy->swap_available)
xcb_dri2_swap_interval(dri2_dpy->conn, dri2_surf->drawable, interval);
  
-   surf->SwapInterval = interval;

-
 return EGL_TRUE;
  }
  
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c

index 000368a46a..c5e3955c48 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1201,7 +1201,17 @@ eglSwapInterval(EGLDisplay dpy, EGLint interval)
 if (_eglGetSurfaceHandle(surf) == EGL_NO_SURFACE)
RETURN_EGL_ERROR(disp, EGL_BAD_SURFACE, EGL_FALSE);
  
-   ret = drv->API.SwapInterval(drv, disp, surf, interval);

+   interval = CLAMP(interval,
+surf->Config->MinSwapInterval,
+surf->Config->MaxSwapInterval);
+
+   if (surf->SwapInterval != interval)
+  ret = drv->API.SwapInterval(drv, disp, surf, interval);
+   else
+  ret = EGL_TRUE;
+
+   if (ret)
+  surf->SwapInterval = interval;
  
 RETURN_EGL_EVAL(disp, ret);

  }
diff --git a/src/egl/main/eglsurface.c b/src/egl/main/eglsurface.c
index f6e41f10d7..3bd14a8cd0 100644
--- a/src/egl/main/eglsurface.c
+++ b/src/egl/main/eglsurface.c
@@ -45,22 +45,6 @@
  #include "eglsurface.h"
  
  
-static void

-_eglClampSwapInterval(_EGLSurface *surf, EGLint interval)
-{
-   EGLint bound = surf->Config->MaxSwapInterval;
-   if (interval >= bound) {
-  interval = bound;
-   }
-   else {
-  bound = surf->Config->MinSwapInterval;
-  if (interval < bound)
- interval = bound;
-   }
-   surf->SwapInterval = interval;
-}
-
-
  /**
   * Parse the list of surface attributes and return the proper error code.
   */
@@ -319,7 +303,7 @@ _eglInitSurface(_EGLSurface *surf, _EGLDisplay *dpy, EGLint 
type,
 surf->BufferAgeRead = EGL_FALSE;
  
 /* the default swap interval is 1 */

-   _eglClampSwapInterval(surf, 1);
+   surf->SwapInterval = 1;
  
 err = _eglParseSurfaceAttribList(surf, attrib_list);

 if (err != EGL_SUCCESS)
@@ -565,6 +549,5 @@ EGLBoolean
  _eglSwapInterval(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf,
   EGLint interval)
  {
-   _eglClampSwapInterval(surf, interval);
 return EGL_TRUE;
  }



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[Mesa-dev] [PATCH 2/2] anv: Advertise VK_KHR_relaxed_block_layout

2017-08-01 Thread Jason Ekstrand
There is literally no work for us to do here.  It already just works in
our driver.
---
 src/intel/vulkan/anv_device.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index f69ebfc..b171c2b 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -477,6 +477,10 @@ static const VkExtensionProperties device_extensions[] = {
   .specVersion = 1,
},
{
+  .extensionName = VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME,
+  .specVersion = 1,
+   },
+   {
   .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
   .specVersion = 1,
},
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH v2 1/6] radeonsi: declare new user SGPR indices for bindless samplers/images

2017-08-01 Thread Marek Olšák
These stages should declare it too. They don't invoke
declare_default_desc_pointers:

SI_SHADER_MERGED_VERTEX_TESSCTRL
SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY

These functions should also pass the pointer:
- si_set_ls_return_value_for_tcs
- si_set_es_return_value_for_gs


Marek

On Wed, Jul 26, 2017 at 4:21 PM, Samuel Pitoiset
 wrote:
> A new pair of user SGPR is needed for loading the bindless
> descriptors from shaders. Because the descriptors are global for
> all stages, there is no need to add separate indices for GFX9.
>
> v2: - fix declaring new bindless parameter
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/radeonsi/si_shader.c  | 5 +
>  src/gallium/drivers/radeonsi/si_shader.h  | 4 +++-
>  src/gallium/drivers/radeonsi/si_shader_internal.h | 1 +
>  3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index a5baf71b0d..6885aeda82 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -4079,6 +4079,8 @@ static void declare_default_desc_pointers(struct 
> si_shader_context *ctx,
>  {
> params[ctx->param_rw_buffers = (*num_params)++] =
> si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS);
> +   params[ctx->param_bindless_samplers_and_images = (*num_params)++] =
> +   si_const_array(ctx->v8i32, 0);
> declare_per_stage_desc_pointers(ctx, params, num_params, true);
>  }
>
> @@ -6709,6 +6711,7 @@ static void si_build_tcs_epilog_function(struct 
> si_shader_context *ctx,
> params[num_params++] = ctx->i64;
> params[num_params++] = ctx->i64;
> params[num_params++] = ctx->i64;
> +   params[num_params++] = ctx->i64;
> params[num_params++] = ctx->i32;
> params[num_params++] = ctx->i32;
> params[num_params++] = ctx->i32;
> @@ -6722,6 +6725,7 @@ static void si_build_tcs_epilog_function(struct 
> si_shader_context *ctx,
> params[num_params++] = ctx->i64;
> params[num_params++] = ctx->i64;
> params[num_params++] = ctx->i64;
> +   params[num_params++] = ctx->i64;
> params[ctx->param_tcs_offchip_layout = num_params++] = 
> ctx->i32;
> params[num_params++] = ctx->i32;
> params[num_params++] = ctx->i32;
> @@ -7070,6 +7074,7 @@ static void si_build_ps_epilog_function(struct 
> si_shader_context *ctx,
>
> /* Declare input SGPRs. */
> params[ctx->param_rw_buffers = num_params++] = ctx->i64;
> +   params[ctx->param_bindless_samplers_and_images = num_params++] = 
> ctx->i64;
> params[ctx->param_const_and_shader_buffers = num_params++] = ctx->i64;
> params[ctx->param_samplers_and_images = num_params++] = ctx->i64;
> assert(num_params == SI_PARAM_ALPHA_REF);
> diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
> b/src/gallium/drivers/radeonsi/si_shader.h
> index a10067d025..4ff588695a 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.h
> +++ b/src/gallium/drivers/radeonsi/si_shader.h
> @@ -157,6 +157,8 @@ enum {
>  */
> SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
> SI_SGPR_RW_BUFFERS_HI,
> +   SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES,
> +   SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES_HI,
> SI_SGPR_CONST_AND_SHADER_BUFFERS,
> SI_SGPR_CONST_AND_SHADER_BUFFERS_HI,
> SI_SGPR_SAMPLERS_AND_IMAGES,
> @@ -217,7 +219,7 @@ enum {
>
>  /* LLVM function parameter indices */
>  enum {
> -   SI_NUM_RESOURCE_PARAMS = 3,
> +   SI_NUM_RESOURCE_PARAMS = 4,
>
> /* PS only parameters */
> SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
> diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h 
> b/src/gallium/drivers/radeonsi/si_shader_internal.h
> index 6e86e0b56d..205b8b92fc 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_internal.h
> +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
> @@ -117,6 +117,7 @@ struct si_shader_context {
> int param_rw_buffers;
> int param_const_and_shader_buffers;
> int param_samplers_and_images;
> +   int param_bindless_samplers_and_images;
> /* Common inputs for merged shaders. */
> int param_merged_wave_info;
> int param_merged_scratch_offset;
> --
> 2.13.3
>
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Re: [Mesa-dev] [PATCH 6/6] egl/x11: use dri2_create_image_khr for swrast

2017-08-01 Thread Emil Velikov
On 28 July 2017 at 04:48, Gurchetan Singh  wrote:
> This will allow the swrast driver to use eglCreateImageKHR,
> provided the target is EGL_GL_TEXTURE_2D_KHR or
> EGL_GL_RENDERBUFFER_KHR.  Note we still have to implement the
> create from render buffer path.
Thanks for the re-spin Gurchetan!

Implementing the renderbuffer path would be great. None of the gallium
drivers currently support it ;-)

A couple of small suggestions:
 - 5/6 effectively enables the extensions, thus it should be the last
in the series
 - the drm and wayland platforms could use a patch similar to this,
otherwise they'll advertise the extensions but the API will always
fail
Feel free to squash with this patch, keep separate or simply force
disable the extensions on said platforms.

With that the series is
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 2/2] anv: Autogenerate extension query and lookup

2017-08-01 Thread Jason Ekstrand
Nanley or Lionel, could I get a second set of eyes on this?  I don't want
to push with just Emil's review as this is a significant change to how we
do extensions.

--Jason

On Fri, Jul 14, 2017 at 7:17 AM, Emil Velikov 
wrote:

> On 14 July 2017 at 07:14, Jason Ekstrand  wrote:
> > As time goes on, extension advertising is going to get more complex.
> > Today, we either implement an extension or we don't.  However, in the
> > future, whether or not we advertise an extension will depend on kernel
> > or hardware features.  This commit introduces a python codegen framework
> > that generates the anv_EnumerateFooExtensionProperties functions as well
> > as a pair of anv_foo_extension_supported functions for querying for the
> > support of a given extension string.  Each extension has an "enable"
> > predicate that is any valid C expression.  For device extensions, the
> > physical device is available as "device" so the expression could be
> > something such as "device->has_kernel_feature".  For instance
> > extensions, the only option is VK_USE_PLATFORM defines.
> >
> > This mechanism also means that we have a single one-line-per-entry table
> > for all extension declarations instead of the two tables we had in
> > anv_device.c and the one we had in anv_entrypoints_gen.py.  The Python
> > code is smart and uses the XML to determine whether an extension is an
> > instance extension or device extension.
> > ---
> >  src/intel/Android.vulkan.mk|   8 ++
> >  src/intel/Makefile.sources |   3 +-
> >  src/intel/Makefile.vulkan.am   |   5 ++
> >  src/intel/vulkan/anv_device.c  | 149 +-
> ---
> >  src/intel/vulkan/anv_extensions.py | 118 +
> >  src/intel/vulkan/anv_private.h |   4 +
> >  6 files changed, 141 insertions(+), 146 deletions(-)
> >
> > diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
> > index 398f2e7..f93d71f 100644
> > --- a/src/intel/Android.vulkan.mk
> > +++ b/src/intel/Android.vulkan.mk
> > @@ -25,6 +25,8 @@ include $(LOCAL_PATH)/Makefile.sources
> >
> >  VK_ENTRYPOINTS_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/vulkan/anv_
> entrypoints_gen.py
> >
> > +VK_EXTENSIONS_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/vulkan/anv_
> extensions.py
> > +
> >  VULKAN_COMMON_INCLUDES := \
> > $(MESA_TOP)/src/mapi \
> > $(MESA_TOP)/src/gallium/auxiliary \
> > @@ -213,6 +215,12 @@ $(intermediates)/vulkan/anv_entrypoints.c:
> > --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
> > --outdir $(dir $@)
> >
> Add the following line otherwise the file won't be in the binary.
>
> LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.c
>
> With the above nit
> Reviewed-by: Emil Velikov 
>
> -Emil
>
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Re: [Mesa-dev] [PATCH] docs: Add Vulkan to features.txt

2017-08-01 Thread Jason Ekstrand
On Tue, Aug 1, 2017 at 4:29 AM, Bas Nieuwenhuizen 
wrote:

> On Tue, Aug 1, 2017 at 1:27 AM, Jordan Justen 
> wrote:
> > On 2017-07-31 16:08:51, Bas Nieuwenhuizen wrote:
> >> On Tue, Aug 1, 2017 at 12:32 AM, Jordan Justen
> >> > +Vulkan 1.0 -- all DONE: anv
> >>
> >> So while we don't have conformance, we have at several times had local
> >> conformance suite runs pass all tests, so I think we can write up radv
> >> as all done here too?
> >
> > Ok, I can add radv here if you recommend it.
> >
> >> > +
> >> > +Khronos and EXT extensions that are not part of any Vulkan version:
> >> > +  VK_EXT_acquire_xlib_display   not started
> >> > +  VK_EXT_blend_operation_advanced   not started
> >> > +  VK_EXT_debug_marker   not started
> >>
> >> Do we even want to implement this as driver, or let this be for the
> layers?
> >
> > I just used grep to find the extensions. If the consensus is to drop
> > this, I can do that.
>
> So the question here is do we want to have a generic list of supported
> features or more like a TODO list. if its the former, adding it would
> be ok, if its the latter I'd think adding this (and the win32 exts are
> for mesa also unlikely) extension to the list would be kind of
> misleading.
>

That's a very good question.  Here's what I see in GL and I think it's
probably reasonable:

 1) There is a section for each OpenGL version 3.0 and above with what
extensions are required by that version.  We only have Vulkan 1.0 today but
I'm sure new versions are coming.

 2) Theree is a section for all KHR, ARB, and OES extensions not yet tied
to any particular OpenGL version

 3) The only EXTs listed are those which got promoted directly to core
without going through ARB first.  There are not many of these but they
happen.  Mesa supports piles of EXTs which are not in features.txt.

I think we should follow a similar pattern.  I really don't want this to
come back and bite us.  Lists of features have this nasty tendency to turn
into ToDo lists.


> >
> >> > +  VK_KHX_multiview  DONE (anv)
>

I'd be a fan of not listing KHX extensions in features.txt.  They're
experimental and guaranteed just to go away at some point.


> >> I started this one for radv too, not sure if we put those in if one
> >> driver already has them though.
> >
> > Based on GL, I don't think we have a way to indicate that it is
> > started for another driver after one has completed it. Do you have a
> > recommendation?
>
> If GL doesn't do it, lets leave it alone for vulkan.
>
> >
> > Side note: Looking at the header of the file, it looks like I should
> > use 'in progress' rather than 'started'.
> >
> >> btw, no vendor extensions?
> >
> > Looking at the 'Khronos, ARB, and OES extensions that are not part of
> > any OpenGL or OpenGL ES version' section, it doesn't seem to include
> > vendor extensions. I did see a few 'NV' extensions in other sections
> > of the file, but I think in those cases they were rolled into the core
> > versions.
> >
> > Should we add another section for extensions that at least 1 driver
> > has implemented or started to implement?
>
> I think that would be nice as some of the AMD/NV exts seem to be
> implementable cross-vendor. Not a blocker though for adding this.
> >
> > -Jordan
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Re: [Mesa-dev] [PATCH] glsl: look up for transform feedback varyings after linking

2017-08-01 Thread Juan A. Suarez Romero
On Thu, 2017-07-06 at 11:12 +0200, Juan A. Suarez Romero wrote:
> Check if shaders have transform feedback varyings also after the
> post-link step.
> 
> This fixes:
> KHR-GL45.enhanced_layouts.xfb_vertex_streams
> piglit/spec/arb_enhanced_layouts/gs-stream-location-aliasing
> ---
>  src/compiler/glsl/glsl_to_nir.cpp | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/compiler/glsl/glsl_to_nir.cpp
> b/src/compiler/glsl/glsl_to_nir.cpp
> index 2153004..fad08ec 100644
> --- a/src/compiler/glsl/glsl_to_nir.cpp
> +++ b/src/compiler/glsl/glsl_to_nir.cpp
> @@ -171,6 +171,9 @@ glsl_to_nir(const struct gl_shader_program
> *shader_prog,
>shader->info.label = ralloc_strdup(shader, shader_prog-
> >Label);
> shader->info.has_transform_feedback_varyings =
>shader_prog->TransformFeedback.NumVarying > 0;
> +   if (shader_prog->last_vert_prog)
> +  shader->info.has_transform_feedback_varyings |=
> + shader_prog->last_vert_prog->sh.LinkedTransformFeedback-
> >NumVarying > 0;
>  
> return shader;
>  }

Gently asking for a review.


J.A.

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[Mesa-dev] Thou shalt not use shell scripts on Windows (Was: Mesa (master): build systems: uniformize git_sha1.h generation)

2017-08-01 Thread Jose Fonseca
Sorry for being late to the party  - I was on PTO when this review went out.  
Only now I was trying to diagnose why some of our builds were broken for very 
long time, and tracked down to this.


Let me start stating what I think it should be obvious for everybody: using a 
shell script on Windows is a awful awful idea.  It's not admissible.  That's 
the whole reason we use SCons instead of autotools and stuff.


The only reason this didn't break things completely for us is that Git for 
windows often bundles sh.exe and some times it's left in the Path.  But that's 
a coincidence, which in fact creates problems of its own.


If you truly want to uniformize  git_sha1.h generation then one must use cross 
platform scripting language as Python.  Like all other scripts we have!


Honestly, I don't know how this pass through peer review unchallenged...  It 
should have been stopped before it ever reached master.


Jose



From: mesa-dev  on behalf of Brian Paul 

Sent: Saturday, July 1, 2017 00:19
To: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] Mesa (master): build systems: uniformize git_sha1.h 
generation

Hi Eric,

Shouldn't the new script file be put in the bin/ directory with the
other helper scripts?

-Brian

On 06/29/2017 09:52 AM, Eric Engeström wrote:
> Module: Mesa
> Branch: master
> Commit: 3fd425aed764fb771f2f49ddb6b30b389a114504
> URL:
> https://urldefense.proofpoint.com/v2/url?u=http-3A__cgit.freedesktop.org_mesa_mesa_commit_-3Fid-3D3fd425aed764fb771f2f49ddb6b30b389a114504&d=DwIGaQ&c=uilaK90D4TOVoH58JNXRgQ&r=Ie7_encNUsqxbSRbqbNgofw0ITcfE8JKfaUjIQhncGA&m=C2QHFlT8FYNq-A29CoLU1hnnK3jQhP0A-EpQrqbU_GQ&s=ZjxcahOcytLNOgFBZuod2dWN2xvP8Ph32iP3dluOunQ&e=
>
> Author: Eric Engestrom 
> Date:   Tue Jun 27 12:08:41 2017 +0100
>
> build systems: uniformize git_sha1.h generation
>
> Signed-off-by: Eric Engestrom 
> Reviewed-by: Matt Turner 
> Reviewed-by: Emil Velikov 
>
> ---
>
>   git_sha1_gen.sh  | 12 
>   src/Makefile.am  | 13 +
>   src/SConscript   | 28 
>   src/mesa/Android.libmesa_git_sha1.mk |  7 +--
>   4 files changed, 22 insertions(+), 38 deletions(-)
>
> diff --git a/git_sha1_gen.sh b/git_sha1_gen.sh
> new file mode 100755
> index 00..20ab8df8ea
> --- /dev/null
> +++ b/git_sha1_gen.sh
> @@ -0,0 +1,12 @@
> +#!/bin/sh
> +
> +# run git from the sources directory
> +cd "$(dirname "$0")"
> +
> +# don't print anything if git fails
> +if ! git_sha1=$(git --git-dir=.git rev-parse --short=10 HEAD 2>/dev/null)
> +then
> +  exit
> +fi
> +
> +printf '#define MESA_GIT_SHA1 "git-%s"\n' "$git_sha1"
> diff --git a/src/Makefile.am b/src/Makefile.am
> index df912c442a..d8a2ee59fc 100644
> --- a/src/Makefile.am
> +++ b/src/Makefile.am
> @@ -21,18 +21,7 @@
>
>   .PHONY: git_sha1.h.tmp
>   git_sha1.h.tmp:
> - @# Don't assume that $(top_srcdir)/.git is a directory. It may be
> - @# a gitlink file if $(top_srcdir) is a submodule checkout or a linked
> - @# worktree.
> - @# If we are building from a release tarball copy the bundled header.
> - @touch git_sha1.h.tmp
> - @if test -e $(top_srcdir)/.git; then \
> - if which git > /dev/null; then \
> - printf '#define MESA_GIT_SHA1 "git-%s"\n' \
> - `git --git-dir=$(top_srcdir)/.git rev-parse --short=10 
> HEAD` \
> - > git_sha1.h.tmp ; \
> - fi \
> - fi
> + @sh $(top_srcdir)/git_sha1_gen.sh > $@
>
>   git_sha1.h: git_sha1.h.tmp
>@echo "updating git_sha1.h"
> diff --git a/src/SConscript b/src/SConscript
> index d861af8e4d..5e1171b524 100644
> --- a/src/SConscript
> +++ b/src/SConscript
> @@ -22,27 +22,15 @@ def write_git_sha1_h_file(filename):
>   to retrieve the git hashid and write the header file.  An empty file
>   will be created if anything goes wrong."""
>
> -args = [ 'git', 'rev-parse', '--short=10', 'HEAD' ]
> -try:
> -(commit, foo) = subprocess.Popen(args, 
> stdout=subprocess.PIPE).communicate()
> -except:
> -print "Warning: exception in write_git_sha1_h_file()"
> -# git log command didn't work
> -if not os.path.exists(filename):
> -dirname = os.path.dirname(filename)
> -if dirname and not os.path.exists(dirname):
> -os.makedirs(dirname)
> -# create an empty file if none already exists
> -f = open(filename, "w")
> -f.close()
> -return
> -
> -# note that commit[:-1] removes the trailing newline character
> -commit = '#define MESA_GIT_SHA1 "git-%s"\n' % commit[:-1]
>   tempfile = "git_sha1.h.tmp"
> -f = open(tempfile, "w")
> -f.write(commit)
> -f.close()
> +with open(tempfile, "w") as f:
> +args = [ 'sh', Dir('#').abspath + '/git_sha1_gen.sh' ]
> +try:
> +subprocess.Popen(args, stdout=f)
> + 

Re: [Mesa-dev] [PATCH] i965: skip varyings without slot

2017-08-01 Thread Juan A. Suarez Romero
On Mon, 2017-07-10 at 12:18 +0200, Juan A. Suarez Romero wrote:
> On Thu, 2017-06-29 at 14:43 +1000, Timothy Arceri wrote:
> > On 27/06/17 21:20, Juan A. Suarez Romero wrote:
> > > On Tue, 2017-06-27 at 09:29 +1000, Timothy Arceri wrote:
> > > > On 16/06/17 18:12, Juan A. Suarez Romero wrote:
> > > > 
> > > > > Commit 00620782c9 (i965: use nir_shader_gather_info() over
> > > > > do_set_program_inouts()) changed how we compute the outputs
> > > > > written.
> > > > > 
> > > > > In the previous version it was using the IR declared outputs,
> > > > > while in
> > > > > the new one it uses NIR to parse the instructions that write
> > > > > outputs.
> > > > > 
> > > > > Thus, if the shader has declared some output that is not
> > > > > written later
> > > > > in the code, like this:
> > > > > 
> > > > > ~~~
> > > > > struct S {
> > > > >   vec4 a;
> > > > >   vec4 b;
> > > > >   vec4 c;
> > > > > };
> > > > > 
> > > > > layout (xfb_offset = sizeof_type) out S s;
> > > > > 
> > > > > void main()
> > > > > {
> > > > > 
> > > > >   s.a = vec4(1.0, 0.0, 0.0, 1.0);
> > > > >   s.c = vec4(0.0, 1.0, 0.0, 1.0);
> > > > > }
> > > > > ~~~
> > > > > 
> > > > > The former version computing 3 outputs written (s.a, s.b and
> > > > > s.c), while
> > > > > the new version only counts 2 (s.a and s.c).
> > > > > 
> > > > > This means that with the new version, then could be varyings
> > > > > in the VUE
> > > > > map that do not have an slot assigned (s.b), that must be
> > > > > skipped.
> > > > > 
> > > > > This fixes KHR-GL45.enhanced_layouts.xfb_capture_struct.
> > > > > ---
> > > > >src/mesa/drivers/dri/i965/genX_state_upload.c | 5 +++--
> > > > >1 file changed, 3 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> > > > > b/src/mesa/drivers/dri/i965/genX_state_upload.c
> > > > > index a5ad2ca..573f0e3 100644
> > > > > --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> > > > > +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> > > > > @@ -3102,9 +3102,10 @@
> > > > > genX(upload_3dstate_so_decl_list)(struct brw_context *brw,
> > > > >  const unsigned stream_id = output->StreamId;
> > > > >  assert(stream_id < MAX_VERTEX_STREAMS);
> > > > >
> > > > > -  buffer_mask[stream_id] |= 1 << buffer;
> > > > > +  if (vue_map->varying_to_slot[varying] == -1)
> > > > > +   continue;
> > > > >
> > > > > -  assert(vue_map->varying_to_slot[varying] >= 0);
> > > > > +  buffer_mask[stream_id] |= 1 << buffer;
> > > > >
> > > > 
> > > > My feeling is we should try to avoid adding it to the VUE map
> > > > in the
> > > > first place rather than trying to work around it.
> > > > 
> > > 
> > > It isn't in the VUE map. That's the reason to skip it.
> > > 
> > > Maybe you mean not adding it in the linked_xfb_info?
> > 
> > oh, right. I had it the wrong way around in my head.
> > 
> > I think the problem is we setup xfb in the glsl linker but then run
> > all 
> > the NIR optimisation before calling nir_shader_gather_info().
> > 
> > However I'm not sure removing the assert is the best idea, as it
> > could 
> > result in real issues being hidden.
> > 
> 
> Not sure, could be. I've run piglit and CTS tests looking up for
> regressions, but found nothing.
> 
> > Ideally we would run the NIR opts before we do the final linking in
> > GLSL 
> > IR. I've outlined how this can be done in past emails (which I
> > can't 
> > seem to find), but its a lot of work. Nicolai's spirv might make
> > is 
> > easier to do, but there will still be things like a nir varying
> > packing 
> > pass required which I believe will be outside of what Nicolai needs
> > for 
> > his changes.
> > 
> > For now I believe this issue only impacts debug builds so I'm not
> > sure 
> > removing the assert and silently skipping is a good idea.
> > 
> > I'll let others comment further.
> > 
> 
> 
> Any other feedback on this is welcomed.
> 
> 

Any other opinion on this?


J.A.

> 
> > > 
> > >   J.A.
> > > 
> > > 
> > > 
> > > > Is it not possible to do that instead?
> > > > 
> > > > 
> > > > >  /* Mesa doesn't store entries for gl_SkipComponents
> > > > > in the Outputs[]
> > > > >   * array.  Instead, it simply increments DstOffset
> > > > > for the following
> > > > 
> > > > 
> > 
> > 
> 
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Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence for Android OS v4.2

2017-08-01 Thread Rafael Antognolli
On Mon, Jul 31, 2017 at 09:58:24AM -0700, Marathe, Yogesh wrote:
> Rafael,  Tomasz,
> 
> > -Original Message-
> > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
> > Of Rafael Antognolli
> > Sent: Tuesday, July 25, 2017 9:39 PM
> > To: Wu, Zhongmin 
> > Cc: Gao, Shuo ; Liu, Zhiquan ;
> > Daniel Stone ; emil.l.veli...@gmail.com; Eric
> > Engestrom ; Marathe, Yogesh
> > ; tf...@chromium.org; Kondapally, Kalyan
> > ; mesa-dev@lists.freedesktop.org; Varad
> > Gautam 
> > Subject: Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence
> > for Android OS v4.2
> > 
> > On Tue, Jul 25, 2017 at 10:07:23AM +0800, Zhongmin Wu wrote:
> > > Before we queued the buffer with a invalid fence (-1), it will make
> > > some benchmarks failed to test such as flatland.
> > >
> > > Now we get the out fence during the flushing buffer and then pass it
> > > to SurfaceFlinger in eglSwapbuffer function.
> > >
> > > v2: a) Also implement the fence in cancelBuffer.
> > > b) The last sync fence is stored in drawable object
> > >rather than brw context.
> > > c) format clear.
> > >
> > > v3: a) Save the last fence fd in DRI Context object.
> > > b) Return the last fence if the batch buffer is empty and
> > >nothing to be flushed when _intel_batchbuffer_flush_fence
> > > c) Add the new interface in vbtl to set the retrieve fence
> > >
> > > v3.1 a) close fd in the new vbtl interface on none Android platform
> > >
> > > v4: a) The last fence is saved in brw context.
> > > b) The retrieve fd is for all the platform but not just Android
> > > c) Add a uniform dri2 interface to initialize the surface.
> > >
> > > v4.1: a) make some changes of variable name.
> > >   b) the patch is breaked into two patches.
> > >
> > > v4.2: a) Add a deinit interface for surface to clear the out fence
> > 
> > Hi Zhongmin,
> > 
> > The patch is indeed looking better. I agree with Tomasz, it would be good to
> > have a way for the platform to inform whether it is interested in fences or 
> > not.
> > What about some flag that you pass to dri2_surf_init? (I'm not sure that's 
> > the
> > best place, though).
> > 
> 
> I would like to take it forward from here for remaining review comments, 
> Zhongmin agrees.
> 
> I added 'enable_out_fence' bool to dri2_surf_init() as a parameter and all 
> platforms except
> android pass this as false. Based on  'enable_out_fence'  stored with surface,
> 'dri2_surf_get/update_fence_fd()' has a check before it calls 
> create_fence_fd(). Is this the
> right expectation here?

Sounds good to me, although I would need to see the patch. Also please make
sure that the dri2 fence extension is supported, assuming you are trying to
enable this.

> Please let me know if 'enable_out_fence' can be changed for a better name. 
> I've already
> implemented other review other comments Rafael mentioned and will include them
> in v4.3 along with this.

I also don't have any better name in mind.

Thanks,
Rafael

> > Please see other comments below.
> > 
> > > Change-Id: Ided54d2e193cde73a6f0feb36ac1c0056e4958f2
> > > Signed-off-by: Zhongmin Wu 
> > > ---
> > >  src/egl/drivers/dri2/egl_dri2.c |   51 
> > > +++
> > >  src/egl/drivers/dri2/egl_dri2.h |8 +
> > >  src/egl/drivers/dri2/platform_android.c |   12 ---
> > >  src/egl/drivers/dri2/platform_drm.c |3 +-
> > >  src/egl/drivers/dri2/platform_surfaceless.c |3 +-
> > >  src/egl/drivers/dri2/platform_wayland.c |3 +-
> > >  src/egl/drivers/dri2/platform_x11.c |3 +-
> > >  src/egl/drivers/dri2/platform_x11_dri3.c|3 +-
> > >  8 files changed, 77 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/src/egl/drivers/dri2/egl_dri2.c
> > > b/src/egl/drivers/dri2/egl_dri2.c index 020a0bc..ffd3a8a 100644
> > > --- a/src/egl/drivers/dri2/egl_dri2.c
> > > +++ b/src/egl/drivers/dri2/egl_dri2.c
> > > @@ -1307,6 +1307,32 @@ dri2_destroy_context(_EGLDriver *drv,
> > _EGLDisplay *disp, _EGLContext *ctx)
> > > return EGL_TRUE;
> > >  }
> > >
> > > +EGLBoolean
> > > +dri2_surf_init(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
> > > +_EGLConfig *conf, const EGLint *attrib_list) {
> > > +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> > > +   dri2_surf->out_fence_fd = -1;
> > > +   return _eglInitSurface(surf, dpy, type, conf, attrib_list); }
> > > +
> > > +static void
> > > +dri2_surface_set_out_fence( _EGLSurface *surf, int fence_fd) {
> > > +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> > > +   if (dri2_surf->out_fence_fd >=0)
> > > +  close(dri2_surf->out_fence_fd);
> > > +
> > > +   dri2_surf->out_fence_fd = fence_fd; }
> > > +
> > > +void
> > > +dri2_surf_deinit(_EGLSurface *surf)
> > > +{
> > > +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> > > +   dri2_surface_set_out_fence(surf, -1); }
> > > +
> > >  static EGLBoolean
> > >  dr

[Mesa-dev] [Bug 102003] Mesa demos doesn't compile due to gles1

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102003

Mike Lothian  changed:

   What|Removed |Added

 CC||m...@fireburn.co.uk

--- Comment #1 from Mike Lothian  ---
I should add this was from a fresh clone and running autogen.sh

I'm running Mesa from master and gles1 is enabled

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[Mesa-dev] [Bug 102003] Mesa demos doesn't compile due to gles1

2017-08-01 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=102003

Bug ID: 102003
   Summary: Mesa demos doesn't compile due to gles1
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Demos
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: m...@fireburn.co.uk
QA Contact: mesa-dev@lists.freedesktop.org

Looks like some primitives are no longer defined for GLES1 

Making all in opengles1
make[3]: Entering directory '/home/fireburn/Demos/src/egl/opengles1'
  CC   clear.o
  CC   drawtex.o
  CC   eglfbdev.o
  CC   es1_info.o
  CC   gears.o
  CC   msaa.o
  CC   pbuffer.o
  CC   render_tex.o
  CC   texture_from_pixmap.o
  CC   torus.o
gears.c: In function ‘draw_gear’:
gears.c:205:7: error: unknown type name ‘GLushort’; did you mean ‘ushort’?
   GLushort indices[7];
   ^~~~
   ushort
torus.c: In function ‘make_cpal_texture’:
torus.c:224:10: error: unknown type name ‘GLushort’; did you mean ‘ushort’?
  GLushort *pal = (GLushort *) palette;
  ^~~~
  ushort
torus.c:224:27: error: ‘GLushort’ undeclared (first use in this function); did
you mean ‘ushort’?
  GLushort *pal = (GLushort *) palette;
   ^~~~
   ushort
torus.c:224:27: note: each undeclared identifier is reported only once for each
function it appears in
torus.c:224:37: error: expected expression before ‘)’ token
  GLushort *pal = (GLushort *) palette;
 ^
torus.c:234:20: error: ‘pal’ undeclared (first use in this function); did you
mean ‘fmal’?
  GLushort *pal = (GLushort *) palette;
^~~
fmal
torus.c:234:37: error: expected expression before ‘)’ token
  GLushort *pal = (GLushort *) palette;
 ^
torus.c:244:37: error: expected expression before ‘)’ token
  GLushort *pal = (GLushort *) palette;
 ^
make[3]: *** [Makefile:563: gears.o] Error 1
make[3]: *** Waiting for unfinished jobs
clear.c:40:45: error: unknown type name ‘GLclampf’; did you mean ‘GLclampx’?
 typedef void (GL_APIENTRY *type_ClearColor)(GLclampf red, GLclampf green,
GLclampf blue, GLclampf alpha);
 ^~~~
 GLclampx
clear.c:40:59: error: unknown type name ‘GLclampf’; did you mean ‘GLclampx’?
 typedef void (GL_APIENTRY *type_ClearColor)(GLclampf red, GLclampf green,
GLclampf blue, GLclampf alpha);
   ^~~~
   GLclampx
clear.c:40:75: error: unknown type name ‘GLclampf’; did you mean ‘GLclampx’?
 typedef void (GL_APIENTRY *type_ClearColor)(GLclampf red, GLclampf green,
GLclampf blue, GLclampf alpha);
  
^~~~
  
GLclampx
clear.c:40:90: error: unknown type name ‘GLclampf’; did you mean ‘GLclampx’?
 typedef void (GL_APIENTRY *type_ClearColor)(GLclampf red, GLclampf green,
GLclampf blue, GLclampf alpha);
   
  ^~~~
   
  GLclampx
make[3]: *** [Makefile:563: torus.o] Error 1
clear.c:43:8: error: unknown type name ‘type_ClearColor’
 static type_ClearColor fn_ClearColor;
^~~
clear.c: In function ‘init’:
clear.c:73:21: error: ‘type_ClearColor’ undeclared (first use in this
function); did you mean ‘fn_ClearColor’?
fn_ClearColor = (type_ClearColor) get_proc("glClearColor");
 ^~~
 fn_ClearColor
clear.c:73:21: note: each undeclared identifier is reported only once for each
function it appears in
clear.c:73:38: error: expected ‘;’ before ‘get_proc’
fn_ClearColor = (type_ClearColor) get_proc("glClearColor");
  ^~~~
clear.c:76:4: error: called object ‘fn_ClearColor’ is not a function or
function pointer
fn_ClearColor(1.0, 0.4, 0.4, 0.0);
^
clear.c:43:24: note: declared here
 static type_ClearColor fn_ClearColor;
^
make[3]: *** [Makefile:563: clear.o] Error 1
eglfbdev.c: In function ‘egl_init_for_fbdev’:
eglfbdev.c:201:28: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
egl_dpy = eglGetDisplay((EGLNativeDisplayType) fd);
^
make[3]: Leaving directory '/home/fireburn/Demos/src/egl/opengles1'
make[2]: *** [Makefile:419: all-recursive] Error 1
make[2]: Leaving directory '

Re: [Mesa-dev] [PATCH 1/3] glsl: recognize GLSL 4.60

2017-08-01 Thread Samuel Pitoiset



On 08/01/2017 04:47 PM, Ilia Mirkin wrote:
Can be done in another patch, but you should go through all the relevant 
extension checks and update the with something that also considers the 
features enabled for 460. Should be fairly mechanical.


Yeah, will do in a separate patch.



On Aug 1, 2017 5:26 AM, "Samuel Pitoiset" > wrote:


Signed-off-by: Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>>
---
  src/compiler/glsl/glsl_parser_extras.cpp | 4 ++--
  src/compiler/glsl/glsl_parser_extras.h   | 2 +-
  src/compiler/glsl/standalone.cpp | 2 ++
  3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
b/src/compiler/glsl/glsl_parser_extras.cpp
index 68af6baafa..8f1651d494 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -54,9 +54,9 @@ glsl_compute_version_string(void *mem_ctx, bool
is_es, unsigned version)


  static const unsigned known_desktop_glsl_versions[] =
-   { 110, 120, 130, 140, 150, 330, 400, 410, 420, 430, 440, 450 };
+   { 110, 120, 130, 140, 150, 330, 400, 410, 420, 430, 440, 450, 460 };
  static const unsigned known_desktop_gl_versions[] =
-   {  20,  21,  30,  31,  32,  33,  40,  41,  42,  43,  44,  45 };
+   {  20,  21,  30,  31,  32,  33,  40,  41,  42,  43,  44,  45, 46 };


  _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct gl_context
*_ctx,
diff --git a/src/compiler/glsl/glsl_parser_extras.h
b/src/compiler/glsl/glsl_parser_extras.h
index be6c8dce6b..fb35813087 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -354,7 +354,7 @@ struct _mesa_glsl_parse_state {
unsigned ver;
uint8_t gl_ver;
bool es;
-   } supported_versions[16];
+   } supported_versions[17];

 bool es_shader;
 bool compat_shader;
diff --git a/src/compiler/glsl/standalone.cpp
b/src/compiler/glsl/standalone.cpp
index 52554bb92a..8e5bc352fc 100644
--- a/src/compiler/glsl/standalone.cpp
+++ b/src/compiler/glsl/standalone.cpp
@@ -253,6 +253,7 @@ initialize_context(struct gl_context *ctx,
gl_api api)
 case 430:
 case 440:
 case 450:
+   case 460:
ctx->Const.MaxClipPlanes = 8;
ctx->Const.MaxDrawBuffers = 8;
ctx->Const.MinProgramTexelOffset = -8;
@@ -418,6 +419,7 @@ standalone_compile_shader(const struct
standalone_options *_options,
 case 430:
 case 440:
 case 450:
+   case 460:
glsl_es = false;
break;
 default:
--
2.13.3

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Re: [Mesa-dev] [PATCH] Convert git_sha1_gen script to Python.

2017-08-01 Thread Emil Velikov
On 1 August 2017 at 15:37, Jose Fonseca  wrote:
> On 01/08/17 15:32, Emil Velikov wrote:
>>
>> On 1 August 2017 at 14:38, Jose Fonseca  wrote:
>>>
>>> Python is the scripting language we've been using for scripts that need
>>> to run across all supported platforms.
>>>
>>> Shell is *not* a portable language for scripts.
>>
>>
>> Guessing that you've hit some issues on Windows?
>
>
> Yep.  While it's possible to find  sh implementations on Windows all suffer
> from many issues.  It's better to stay away from them.
>
Ack. I was fortunate enough in my very limited experience.


>>> --- /dev/null
>>> +++ b/bin/git_sha1_gen.py
>>> @@ -0,0 +1,20 @@
>>> +#!/usr/bin/env python
>>
>> Script is already invoked manually via $python.
>> Please drop the execute bit alongside the shbang line.
>
>
> The shell script was also invoked by `sh` and still had the shbang line.
>
My bad - we should have invoked the script directly.

> I don't see the harm of the shbang line.  By the contrary, it's convenient.
>
On the python topic - I've seen it fuel some discussions... amongst others:
Python tends to be a symlink it to python2 or python3 depending on distro.

Anyway - as-is script works like a charm here.
R-b still stands, regardless of the shbang suggestion.

-Emil
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Re: [Mesa-dev] [PATCH mesa 1/3] egl: deduplicate swap interval clamping logic

2017-08-01 Thread Emil Velikov
On 1 August 2017 at 13:55, Eric Engestrom  wrote:
> Signed-off-by: Eric Engestrom 
> Reviewed-by: Daniel Stone 
If we only had implementation swap_interval implementation across the
board, we could have simplified things ever further.

Regardless, nice cleanup. For the lot
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 1/3] glsl: recognize GLSL 4.60

2017-08-01 Thread Ilia Mirkin
Can be done in another patch, but you should go through all the relevant
extension checks and update the with something that also considers the
features enabled for 460. Should be fairly mechanical.

On Aug 1, 2017 5:26 AM, "Samuel Pitoiset"  wrote:

> Signed-off-by: Samuel Pitoiset 
> ---
>  src/compiler/glsl/glsl_parser_extras.cpp | 4 ++--
>  src/compiler/glsl/glsl_parser_extras.h   | 2 +-
>  src/compiler/glsl/standalone.cpp | 2 ++
>  3 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
> b/src/compiler/glsl/glsl_parser_extras.cpp
> index 68af6baafa..8f1651d494 100644
> --- a/src/compiler/glsl/glsl_parser_extras.cpp
> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
> @@ -54,9 +54,9 @@ glsl_compute_version_string(void *mem_ctx, bool is_es,
> unsigned version)
>
>
>  static const unsigned known_desktop_glsl_versions[] =
> -   { 110, 120, 130, 140, 150, 330, 400, 410, 420, 430, 440, 450 };
> +   { 110, 120, 130, 140, 150, 330, 400, 410, 420, 430, 440, 450, 460 };
>  static const unsigned known_desktop_gl_versions[] =
> -   {  20,  21,  30,  31,  32,  33,  40,  41,  42,  43,  44,  45 };
> +   {  20,  21,  30,  31,  32,  33,  40,  41,  42,  43,  44,  45, 46 };
>
>
>  _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct gl_context *_ctx,
> diff --git a/src/compiler/glsl/glsl_parser_extras.h
> b/src/compiler/glsl/glsl_parser_extras.h
> index be6c8dce6b..fb35813087 100644
> --- a/src/compiler/glsl/glsl_parser_extras.h
> +++ b/src/compiler/glsl/glsl_parser_extras.h
> @@ -354,7 +354,7 @@ struct _mesa_glsl_parse_state {
>unsigned ver;
>uint8_t gl_ver;
>bool es;
> -   } supported_versions[16];
> +   } supported_versions[17];
>
> bool es_shader;
> bool compat_shader;
> diff --git a/src/compiler/glsl/standalone.cpp b/src/compiler/glsl/
> standalone.cpp
> index 52554bb92a..8e5bc352fc 100644
> --- a/src/compiler/glsl/standalone.cpp
> +++ b/src/compiler/glsl/standalone.cpp
> @@ -253,6 +253,7 @@ initialize_context(struct gl_context *ctx, gl_api api)
> case 430:
> case 440:
> case 450:
> +   case 460:
>ctx->Const.MaxClipPlanes = 8;
>ctx->Const.MaxDrawBuffers = 8;
>ctx->Const.MinProgramTexelOffset = -8;
> @@ -418,6 +419,7 @@ standalone_compile_shader(const struct
> standalone_options *_options,
> case 430:
> case 440:
> case 450:
> +   case 460:
>glsl_es = false;
>break;
> default:
> --
> 2.13.3
>
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Re: [Mesa-dev] [PATCH] Convert git_sha1_gen script to Python.

2017-08-01 Thread Jose Fonseca

On 01/08/17 15:32, Emil Velikov wrote:

On 1 August 2017 at 14:38, Jose Fonseca  wrote:

Python is the scripting language we've been using for scripts that need
to run across all supported platforms.

Shell is *not* a portable language for scripts.


Guessing that you've hit some issues on Windows?


Yep.  While it's possible to find  sh implementations on Windows all 
suffer from many issues.  It's better to stay away from them.



All the other platforms should be fine, afaict.





---
  Makefile.am  |  2 +-
  bin/git_sha1_gen.py  | 20 
  bin/git_sha1_gen.sh  | 12 
  src/Makefile.am  |  2 +-
  src/SConscript   |  3 ++-
  src/mesa/Android.libmesa_git_sha1.mk |  2 +-
  6 files changed, 25 insertions(+), 16 deletions(-)
  create mode 100755 bin/git_sha1_gen.py
  delete mode 100755 bin/git_sha1_gen.sh

diff --git a/Makefile.am b/Makefile.am
index cf52c834aa..538c38ddeb 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -53,7 +53,7 @@ EXTRA_DIST = \
 common.py \
 docs \
 doxygen \
-   bin/git_sha1_gen.sh \
+   bin/git_sha1_gen.py \
 scons \
 SConstruct

diff --git a/bin/git_sha1_gen.py b/bin/git_sha1_gen.py
new file mode 100755
index 00..6d13db1e16
--- /dev/null
+++ b/bin/git_sha1_gen.py
@@ -0,0 +1,20 @@
+#!/usr/bin/env python

Script is already invoked manually via $python.
Please drop the execute bit alongside the shbang line.


The shell script was also invoked by `sh` and still had the shbang line.

I don't see the harm of the shbang line.  By the contrary, it's convenient.




+
+import os.path
+import subprocess
+import sys
+
+git_dir = os.path.join(os.path.dirname(sys.argv[0]), '..', '.git')
+try:
+git_sha1 = subprocess.check_output([
+'git',
+'--git-dir=' + git_dir,
+'rev-parse',
+'--short=10',
+'HEAD',
+], stderr=open(os.devnull, 'w'))
+except subprocess.CalledProcessError as e:
+# don't print anything if git fails
+pass
+else:
+sys.stdout.write('#define MESA_GIT_SHA1 "git-%s"\n' % git_sha1.rstrip())
diff --git a/bin/git_sha1_gen.sh b/bin/git_sha1_gen.sh
deleted file mode 100755
index 898e590758..00
--- a/bin/git_sha1_gen.sh
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/sh
-
-# run git from the sources directory
-cd "$(dirname "$0")"
-
-# don't print anything if git fails
-if ! git_sha1=$(git --git-dir=../.git rev-parse --short=10 HEAD 2>/dev/null)
-then
-  exit
-fi
-
-printf '#define MESA_GIT_SHA1 "git-%s"\n' "$git_sha1"
diff --git a/src/Makefile.am b/src/Makefile.am
index 5aee6b0141..8d7483fc75 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -21,7 +21,7 @@

  .PHONY: git_sha1.h.tmp
  git_sha1.h.tmp:
-   @sh $(top_srcdir)/bin/git_sha1_gen.sh > $@
+   @python $(top_srcdir)/bin/git_sha1_gen.py > $@


Swap "python" with $(PYTHON2) ...


--- a/src/mesa/Android.libmesa_git_sha1.mk
+++ b/src/mesa/Android.libmesa_git_sha1.mk
@@ -46,7 +46,7 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, 
git_sha1.h)
  $(intermediates)/git_sha1.h: $(wildcard $(MESA_TOP)/.git/logs/HEAD)
 @mkdir -p $(dir $@)
 @echo "GIT-SHA1: $(PRIVATE_MODULE) <= git"
-   $(hide) sh $(MESA_TOP)/bin/git_sha1_gen.sh > $@
+   $(hide) python $(MESA_TOP)/bin/git_sha1_gen.py > $@

... and $(MESA_PYTHON2)


OK. I'll fix these.

Jose



With the above
Reviewed-by: Emil Velikov 

Thanks
Emil



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Re: [Mesa-dev] [PATCH] Convert git_sha1_gen script to Python.

2017-08-01 Thread Emil Velikov
On 1 August 2017 at 14:38, Jose Fonseca  wrote:
> Python is the scripting language we've been using for scripts that need
> to run across all supported platforms.
>
> Shell is *not* a portable language for scripts.

Guessing that you've hit some issues on Windows?
All the other platforms should be fine, afaict.

> ---
>  Makefile.am  |  2 +-
>  bin/git_sha1_gen.py  | 20 
>  bin/git_sha1_gen.sh  | 12 
>  src/Makefile.am  |  2 +-
>  src/SConscript   |  3 ++-
>  src/mesa/Android.libmesa_git_sha1.mk |  2 +-
>  6 files changed, 25 insertions(+), 16 deletions(-)
>  create mode 100755 bin/git_sha1_gen.py
>  delete mode 100755 bin/git_sha1_gen.sh
>
> diff --git a/Makefile.am b/Makefile.am
> index cf52c834aa..538c38ddeb 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -53,7 +53,7 @@ EXTRA_DIST = \
> common.py \
> docs \
> doxygen \
> -   bin/git_sha1_gen.sh \
> +   bin/git_sha1_gen.py \
> scons \
> SConstruct
>
> diff --git a/bin/git_sha1_gen.py b/bin/git_sha1_gen.py
> new file mode 100755
> index 00..6d13db1e16
> --- /dev/null
> +++ b/bin/git_sha1_gen.py
> @@ -0,0 +1,20 @@
> +#!/usr/bin/env python
Script is already invoked manually via $python.
Please drop the execute bit alongside the shbang line.

> +
> +import os.path
> +import subprocess
> +import sys
> +
> +git_dir = os.path.join(os.path.dirname(sys.argv[0]), '..', '.git')
> +try:
> +git_sha1 = subprocess.check_output([
> +'git',
> +'--git-dir=' + git_dir,
> +'rev-parse',
> +'--short=10',
> +'HEAD',
> +], stderr=open(os.devnull, 'w'))
> +except subprocess.CalledProcessError as e:
> +# don't print anything if git fails
> +pass
> +else:
> +sys.stdout.write('#define MESA_GIT_SHA1 "git-%s"\n' % git_sha1.rstrip())
> diff --git a/bin/git_sha1_gen.sh b/bin/git_sha1_gen.sh
> deleted file mode 100755
> index 898e590758..00
> --- a/bin/git_sha1_gen.sh
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#!/bin/sh
> -
> -# run git from the sources directory
> -cd "$(dirname "$0")"
> -
> -# don't print anything if git fails
> -if ! git_sha1=$(git --git-dir=../.git rev-parse --short=10 HEAD 2>/dev/null)
> -then
> -  exit
> -fi
> -
> -printf '#define MESA_GIT_SHA1 "git-%s"\n' "$git_sha1"
> diff --git a/src/Makefile.am b/src/Makefile.am
> index 5aee6b0141..8d7483fc75 100644
> --- a/src/Makefile.am
> +++ b/src/Makefile.am
> @@ -21,7 +21,7 @@
>
>  .PHONY: git_sha1.h.tmp
>  git_sha1.h.tmp:
> -   @sh $(top_srcdir)/bin/git_sha1_gen.sh > $@
> +   @python $(top_srcdir)/bin/git_sha1_gen.py > $@
>
Swap "python" with $(PYTHON2) ...

> --- a/src/mesa/Android.libmesa_git_sha1.mk
> +++ b/src/mesa/Android.libmesa_git_sha1.mk
> @@ -46,7 +46,7 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, 
> git_sha1.h)
>  $(intermediates)/git_sha1.h: $(wildcard $(MESA_TOP)/.git/logs/HEAD)
> @mkdir -p $(dir $@)
> @echo "GIT-SHA1: $(PRIVATE_MODULE) <= git"
> -   $(hide) sh $(MESA_TOP)/bin/git_sha1_gen.sh > $@
> +   $(hide) python $(MESA_TOP)/bin/git_sha1_gen.py > $@
... and $(MESA_PYTHON2)

With the above
Reviewed-by: Emil Velikov 

Thanks
Emil
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