[Mesa-dev] [PATCH] glsl/linker: outputs in the same location must share interpolation

[Iago Toral Quiroga]

From ARB_enhanced_layouts:

"[...]when location aliasing, the aliases sharing the location
 must have the same underlying numerical type (floating-point or
 integer) and the same auxiliary storage and
 interpolation qualification.[...]"

Add code to the linker to validate that aliased locations do
have the same interpolation.

Fixes:
KHR-GL45.enhanced_layouts.varying_location_aliasing_with_mixed_interpolation
---
 src/compiler/glsl/link_varyings.cpp | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index 69c92bf53b..c888635e82 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -459,6 +459,41 @@ cross_validate_outputs_to_inputs(struct gl_context *ctx,
 
  while (idx < slot_limit) {
 unsigned i = var->data.location_frac;
+
+/* If there are other outputs assigned to the same location
+ * they must have the same interpolation
+ */
+unsigned comp = 0;
+while (comp < i) {
+   ir_variable *tmp = explicit_locations[idx][comp];
+   if (tmp && tmp->data.interpolation != var->data.interpolation) {
+  linker_error(prog,
+   "%s shader has multiple outputs at explicit "
+   "location %u with different interpolation "
+   "settings\n",
+   _mesa_shader_stage_to_string(producer->Stage),
+   idx);
+  return;
+   }
+   comp++;
+}
+
+comp = last_comp + 1;
+while (comp < 4) {
+   ir_variable *tmp = explicit_locations[idx][comp];
+   if (tmp && tmp->data.interpolation != var->data.interpolation) {
+  linker_error(prog,
+   "%s shader has multiple outputs at explicit "
+   "location %u with different interpolation "
+   "settings\n",
+   _mesa_shader_stage_to_string(producer->Stage),
+   idx);
+  return;
+   }
+   comp++;
+}
+
+/* Component aliasing is not allowed */
 while (i < last_comp) {
if (explicit_locations[idx][i] != NULL) {
   linker_error(prog,
-- 
2.11.0

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Re: [Mesa-dev] [PATCH] i965/sbe: fix active components for SSO programs with over 16 inputs

[Kenneth Graunke]

On Friday, October 13, 2017 2:10:15 AM PDT Iago Toral Quiroga wrote:
> When we have up to 16 FS inputs, the SF unit will reorder our inputs
> to be consecutive, however, when we have more than 16 we need to
> to read our inputs from the URB exactly as they have been
> output from the previous stage. This means that for SSO we have to
> consider if we have URB padding due to unused input locations.
> 
> Specifically, this affects gen9 active components programming, since
> for things to work in scenarios with over 16 inputs that have padded
> regions we need to ensure that we program active components for the
> padded regions too. If we don't do this the hardware won't read
> the URB properly for inputs located after padded regions.
> 
> Found empirically.
> 
> Fixes (these also require a patch in CTS):
> KHR-GL45.enhanced_layouts.varying_locations
> KHR-GL45.enhanced_layouts.varying_array_locations
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 10 ++
>  1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index ecf5a9ae68..2137de9597 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -3452,15 +3452,9 @@ genX(upload_sbe)(struct brw_context *brw)
>  
>  #if GEN_GEN >= 9
>/* prepare the active component dwords */
> -  int input_index = 0;
> -  for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
> - if (!(fp->info.inputs_read & BITFIELD64_BIT(attr)))
> -continue;
> -
> - assert(input_index < 32);
> -
> +  const int num_inputs = urb_entry_read_length * 2;
> +  for (int input_index = 0; input_index < num_inputs; input_index++) {
>   sbe.AttributeActiveComponentFormat[input_index] = 
> ACTIVE_COMPONENT_XYZW;
> - ++input_index;
>}
>  #endif
> }
> 

Wow, good find!  Thanks!

Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH 1/4] i965: Make intel_miptree_prepare_texture() take level/layer arguments.

[Kenneth Graunke]

This effectively exports intel_miptree_prepare_texture_slices() as
intel_miptree_prepare_texture().  The hope is to avoid resolves for
when using texture views that access a subset of the levels/layers.

For now, we pass the same arguments to separate the mechanical change
from the one that actually modifies our behavior.
---
 src/mesa/drivers/dri/i965/brw_draw.c  |  2 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 30 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 ++
 3 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 2721c722693..f9a8264f27f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -403,6 +403,8 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
  intel_disable_rb_aux_buffer(brw, tex_obj->mt, "for sampling");
 
   intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
+0, INTEL_REMAINING_LEVELS,
+0, INTEL_REMAINING_LAYERS,
 disable_aux);
 
   brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b57290e8238..61b0a2dd49c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2617,13 +2617,13 @@ isl_formats_are_fast_clear_compatible(enum isl_format 
a, enum isl_format b)
return isl_format_srgb_to_linear(a) == isl_format_srgb_to_linear(b);
 }
 
-static void
-intel_miptree_prepare_texture_slices(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- enum isl_format view_format,
- uint32_t start_level, uint32_t num_levels,
- uint32_t start_layer, uint32_t num_layers,
- bool disable_aux)
+void
+intel_miptree_prepare_texture(struct brw_context *brw,
+  struct intel_mipmap_tree *mt,
+  enum isl_format view_format,
+  uint32_t start_level, uint32_t num_levels,
+  uint32_t start_layer, uint32_t num_layers,
+  bool disable_aux)
 {
enum isl_aux_usage aux_usage = disable_aux ? ISL_AUX_USAGE_NONE :
   intel_miptree_texture_aux_usage(brw, mt, view_format);
@@ -2641,18 +2641,6 @@ intel_miptree_prepare_texture_slices(struct brw_context 
*brw,
 aux_usage, clear_supported);
 }
 
-void
-intel_miptree_prepare_texture(struct brw_context *brw,
-  struct intel_mipmap_tree *mt,
-  enum isl_format view_format,
-  bool disable_aux)
-{
-   intel_miptree_prepare_texture_slices(brw, mt, view_format,
-0, INTEL_REMAINING_LEVELS,
-0, INTEL_REMAINING_LAYERS,
-disable_aux);
-}
-
 void
 intel_miptree_prepare_image(struct brw_context *brw,
 struct intel_mipmap_tree *mt)
@@ -2673,8 +2661,8 @@ intel_miptree_prepare_fb_fetch(struct brw_context *brw,
 */
assert(brw->screen->devinfo.gen < 9);
 
-   intel_miptree_prepare_texture_slices(brw, mt, mt->surf.format, level, 1,
-start_layer, num_layers, false);
+   intel_miptree_prepare_texture(brw, mt, mt->surf.format, level, 1,
+ start_layer, num_layers, false);
 }
 
 enum isl_aux_usage
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 48b07e4df6d..6dd097ac6d0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -640,6 +640,8 @@ void
 intel_miptree_prepare_texture(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
   enum isl_format view_format,
+  uint32_t start_level, uint32_t num_levels,
+  uint32_t start_layer, uint32_t num_layers,
   bool disable_aux);
 void
 intel_miptree_prepare_image(struct brw_context *brw,
-- 
2.14.2

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[Mesa-dev] [PATCH 2/4] i965: Only resolve texture levels/layers that are accessed.

[Kenneth Graunke]

This should avoid unnecessary resolves when working with texture views.
---
 src/mesa/drivers/dri/i965/brw_draw.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index f9a8264f27f..53d973f3761 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -399,12 +399,26 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
   enum isl_format view_format =
  translate_tex_format(brw, tex_obj->_Format, sampler->sRGBDecode);
 
+  unsigned min_level, min_layer, num_levels, num_layers;
+  if (tex_obj->base.Immutable) {
+ min_level  = tex_obj->base.MinLevel;
+ num_levels = MIN2(tex_obj->base.NumLevels, tex_obj->_MaxLevel + 1);
+ min_layer  = tex_obj->base.MinLayer;
+ num_layers = tex_obj->base.Target != GL_TEXTURE_3D ?
+  tex_obj->base.NumLayers : INTEL_REMAINING_LAYERS;
+  } else {
+ min_level  = tex_obj->base.BaseLevel;
+ num_levels = tex_obj->_MaxLevel - tex_obj->base.BaseLevel + 1;
+ min_layer  = 0;
+ num_layers = INTEL_REMAINING_LAYERS;
+  }
+
   const bool disable_aux =
  intel_disable_rb_aux_buffer(brw, tex_obj->mt, "for sampling");
 
   intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
-0, INTEL_REMAINING_LEVELS,
-0, INTEL_REMAINING_LAYERS,
+min_level, num_levels,
+min_layer, num_layers,
 disable_aux);
 
   brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
-- 
2.14.2

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[Mesa-dev] [PATCH 4/4] i965: Don't disable aux buffers for non-overlapping miplevels.

[Kenneth Graunke]

Meta's GenerateMipmap implementation binds the same image for both
sampling and rendering - but it samples from one miplevel while
rendering the next.  This is a false self-dependency, and there's
no need to disable auxiliary buffers in this case.  In fact, we really
want to leave it enabled so the new miplevels gain color compression.

Thankfully, the texture object's _MaxLevel is always one shy of the
miplevel being rendered.  So we can simply check if irb->mt_level is
overlaps with the texture's defined levels.  If not, there's no self-
dependency and we can leave the auxiliary buffers enabled.

Fixes a performance regression in GFXBench4 Car Chase, which apparently
calls glGenerateMipmap() on every frame.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103247
---
 src/mesa/drivers/dri/i965/brw_draw.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 51e2a26ca2f..a4c042f3f4f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -344,6 +344,7 @@ brw_merge_inputs(struct brw_context *brw,
 static bool
 intel_disable_rb_aux_buffer(struct brw_context *brw,
 struct intel_mipmap_tree *tex_mt,
+unsigned min_level, unsigned num_levels,
 const char *usage)
 {
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
@@ -358,7 +359,9 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
   const struct intel_renderbuffer *irb =
  intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
-  if (irb && irb->mt->bo == tex_mt->bo) {
+  if (irb && irb->mt->bo == tex_mt->bo &&
+  irb->mt_level >= min_level &&
+  irb->mt_level < min_level + num_levels) {
  found = brw->draw_aux_buffer_disabled[i] = true;
   }
}
@@ -414,7 +417,8 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
   }
 
   const bool disable_aux =
- intel_disable_rb_aux_buffer(brw, tex_obj->mt, "for sampling");
+ intel_disable_rb_aux_buffer(brw, tex_obj->mt, min_level, num_levels,
+ "for sampling");
 
   intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
 min_level, num_levels,
@@ -440,7 +444,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
 tex_obj = intel_texture_object(u->TexObj);
 
 if (tex_obj && tex_obj->mt) {
-   intel_disable_rb_aux_buffer(brw, tex_obj->mt,
+   intel_disable_rb_aux_buffer(brw, tex_obj->mt, 0, ~0,
"as a shader image");
 
intel_miptree_prepare_image(brw, tex_obj->mt);
-- 
2.14.2

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[Mesa-dev] [PATCH 3/4] i965: Remove the intel_miptree_prepare_fb_fetch wrapper.

[Kenneth Graunke]

Now that intel_miptree_prepare_texture takes levels and layers, there's
not much use in this anymore.
---
 src/mesa/drivers/dri/i965/brw_draw.c  |  6 --
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 --
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 +
 3 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 53d973f3761..51e2a26ca2f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -478,8 +478,10 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw)
 intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
  if (irb) {
-intel_miptree_prepare_fb_fetch(brw, irb->mt, irb->mt_level,
-   irb->mt_layer, irb->layer_count);
+intel_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format,
+  irb->mt_level, 1,
+  irb->mt_layer, irb->layer_count,
+  false);
  }
   }
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 61b0a2dd49c..56105ef8af3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2651,20 +2651,6 @@ intel_miptree_prepare_image(struct brw_context *brw,
 ISL_AUX_USAGE_NONE, false);
 }
 
-void
-intel_miptree_prepare_fb_fetch(struct brw_context *brw,
-   struct intel_mipmap_tree *mt, uint32_t level,
-   uint32_t start_layer, uint32_t num_layers)
-{
-   /* This is only used for non-coherent framebuffer fetch, so we don't
-* need to worry about CCS_E and can simply pass 'false' below.
-*/
-   assert(brw->screen->devinfo.gen < 9);
-
-   intel_miptree_prepare_texture(brw, mt, mt->surf.format, level, 1,
- start_layer, num_layers, false);
-}
-
 enum isl_aux_usage
 intel_miptree_render_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6dd097ac6d0..c24b5a35f85 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -646,10 +646,7 @@ intel_miptree_prepare_texture(struct brw_context *brw,
 void
 intel_miptree_prepare_image(struct brw_context *brw,
 struct intel_mipmap_tree *mt);
-void
-intel_miptree_prepare_fb_fetch(struct brw_context *brw,
-   struct intel_mipmap_tree *mt, uint32_t level,
-   uint32_t start_layer, uint32_t num_layers);
+
 enum isl_aux_usage
 intel_miptree_render_aux_usage(struct brw_context *brw,
struct intel_mipmap_tree *mt,
-- 
2.14.2

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[Mesa-dev] [PATCH v2 29/32] disk_cache: Fix issue reading GLSL metadata

[Jordan Justen]

This would cause the read of the metadata content to fail, which would
prevent the linking from being skipped.

Seen on Rocket League with i965 shader cache.

Cc: Timothy Arceri 
Signed-off-by: Jordan Justen 
---
 src/util/disk_cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
index e38cacb259..fde6e2e097 100644
--- a/src/util/disk_cache.c
+++ b/src/util/disk_cache.c
@@ -1110,7 +1110,7 @@ disk_cache_get(struct disk_cache *cache, const cache_key 
key, size_t *size)
* TODO: pass the metadata back to the caller and do some basic
* validation.
*/
-  cache_item_md_size += sizeof(cache_key);
+  cache_item_md_size += num_keys * sizeof(cache_key);
   ret = lseek(fd, num_keys * sizeof(cache_key), SEEK_CUR);
   if (ret == -1)
  goto fail;
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 28/32] glsl/shader_cache: Save fs (BlendSupport) metadata

[Jordan Justen]

Fixes many GL 4.5 CTS blend tests, such as:

* GL45-CTS.blend_equation_advanced.extension_directive_enable
* GL45-CTS.blend_equation_advanced.extension_directive_warn
* GL45-CTS.blend_equation_advanced.blend_all.GL_MULTIPLY_KHR_all_qualifier
* GL45-CTS.blend_equation_advanced.blend_specific.GL_COLORBURN_KHR

v2:
 * Directly save the BlendSupport field to avoid potentially including
   a pointer in the future in the structure is updated. (tarceri)

Cc: Timothy Arceri 
Signed-off-by: Jordan Justen 
---
 src/compiler/glsl/shader_cache.cpp | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/compiler/glsl/shader_cache.cpp 
b/src/compiler/glsl/shader_cache.cpp
index f43bd6b17e..e848af0b76 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -1061,6 +1061,9 @@ write_shader_metadata(struct blob *metadata, 
gl_linked_shader *shader)
sizeof(struct gl_bindless_image) - ptr_size);
}
 
+   blob_write_bytes(metadata, >sh.fs.BlendSupport,
+sizeof(glprog->sh.fs.BlendSupport));
+
write_shader_parameters(metadata, glprog->Parameters);
 
assert((glprog->serialized_nir == NULL) ==
@@ -1122,6 +1125,9 @@ read_shader_metadata(struct blob_reader *metadata,
   }
}
 
+   blob_copy_bytes(metadata, (uint8_t *) >sh.fs.BlendSupport,
+   sizeof(glprog->sh.fs.BlendSupport));
+
glprog->Parameters = _mesa_new_parameter_list();
read_shader_parameters(metadata, glprog->Parameters);
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 24/32] i965: add support for cached shaders with xfb qualifiers

[Jordan Justen]

From: Timothy Arceri 

For now this disables the shader cache when transform feedback is
enabled via the GL API as we don't currently allow for it when
generating the sha for the shader.
---
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 0a612d7811..d89df846d5 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -290,6 +290,14 @@ brw_disk_cache_upload_program(struct brw_context *brw, 
gl_shader_stage stage)
if (prog == NULL)
   return false;
 
+   /* FIXME: For now we don't read from the cache if transform feedback is
+* enabled via the API. However the shader cache does support transform
+* feedback when enabled via in shader xfb qualifiers.
+*/
+   if (prog->sh.LinkedTransformFeedback &&
+   prog->sh.LinkedTransformFeedback->api_enabled)
+  return false;
+
if (prog->sh.data->LinkStatus != linking_skipped)
   goto FAIL;
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 04/32] compiler/types: Support [de]serializing void types

[Jordan Justen]

From: Jason Ekstrand 

---
 src/compiler/glsl_types.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index a7fc7ff7f6..704b63c5cf 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -2149,6 +2149,8 @@ encode_type_to_blob(struct blob *blob, const glsl_type 
*type)
   }
   return;
case GLSL_TYPE_VOID:
+  encoding = (type->base_type << 24);
+  break;
case GLSL_TYPE_ERROR:
default:
   assert(!"Cannot encode type!");
@@ -2230,6 +2232,7 @@ decode_type_from_blob(struct blob_reader *blob)
   return t;
}
case GLSL_TYPE_VOID:
+  return glsl_type::void_type;
case GLSL_TYPE_ERROR:
default:
   assert(!"Cannot decode type!");
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 23/32] mesa/glsl: add api_enabled flag to gl_transform_feedback_info

[Jordan Justen]

From: Timothy Arceri 

This will be used to disable the shader cache when xfb is enabled
via the api as we don't currently allow for it when generating the
sha for the shader.
---
 src/compiler/glsl/link_varyings.cpp | 5 -
 src/mesa/main/mtypes.h  | 3 +++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index 29842ecacd..823d6899d7 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -1089,9 +1089,12 @@ store_tfeedback_info(struct gl_context *ctx, struct 
gl_shader_program *prog,
 * however some drivers expect to receive the list of transform feedback
 * declarations in order so sort it now for convenience.
 */
-   if (has_xfb_qualifiers)
+   if (has_xfb_qualifiers) {
   qsort(tfeedback_decls, num_tfeedback_decls, sizeof(*tfeedback_decls),
 cmp_xfb_offset);
+   } else {
+  xfb_prog->sh.LinkedTransformFeedback->api_enabled = true;
+   }
 
xfb_prog->sh.LinkedTransformFeedback->Varyings =
   rzalloc_array(xfb_prog, struct gl_transform_feedback_varying_info,
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index a5a1398698..d94ed22b65 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1779,6 +1779,9 @@ struct gl_transform_feedback_buffer
 /** Post-link transform feedback info. */
 struct gl_transform_feedback_info
 {
+   /* Was xfb enabled via the api or in shader layout qualifiers */
+   bool api_enabled;
+
unsigned NumOutputs;
 
/* Bitmask of active buffer indices. */
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 31/32] i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false

[Jordan Justen]

Double negative FTW!

For now, the shader cache is disabled by default on i965 to allow us
to verify its stability.

In other words, to enable the shader cache on i965, set
MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then
the shader cache will be disabled.

We use the build-id of i965_dri.so for the timestamp, and the pci
device id for the device name.

v2:
 * Simplify code by forcing link to include build id sha. (Matt)

Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_context.c|  2 ++
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 39 ++
 src/mesa/drivers/dri/i965/brw_state.h  |  1 +
 3 files changed, 42 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 6a88d8bb48..1fdaf02022 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1018,6 +1018,8 @@ brwCreateContext(gl_api api,
  brw->dri_config_options_sha1);
brw->ctx.Const.dri_config_options_sha1 = brw->dri_config_options_sha1;
 
+   brw_disk_cache_init(brw);
+
return true;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 790fad6925..582c2cfbc7 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -26,6 +26,8 @@
 #include "compiler/glsl/shader_cache.h"
 #include "compiler/nir/nir_serialize.h"
 #include "main/mtypes.h"
+#include "util/build_id.h"
+#include "util/debug.h"
 #include "util/disk_cache.h"
 #include "util/macros.h"
 #include "util/mesa-sha1.h"
@@ -496,3 +498,40 @@ brw_disk_cache_write_compute_program(struct brw_context 
*brw)
  MESA_SHADER_COMPUTE);
}
 }
+
+void
+brw_disk_cache_init(struct brw_context *brw)
+{
+#ifdef ENABLE_SHADER_CACHE
+   if (env_var_as_boolean("MESA_GLSL_CACHE_DISABLE", true))
+  return;
+
+   char *renderer = NULL;
+   int len = asprintf(, "i965_%04x", brw->screen->deviceID);
+   if (len < 0) {
+  renderer = strdup("i965");
+   }
+   if (renderer == NULL)
+   return;
+
+   const struct build_id_note *note =
+  build_id_find_nhdr_for_addr(brw_disk_cache_init);
+   assert(note);
+   int id_size = build_id_length(note);
+   char *timestamp = malloc(2 * id_size + 1);
+
+   const uint8_t *data = build_id_data(note);
+   int i;
+   for (i = 0; i < id_size; i++)
+  snprintf([2 * i], 3, "%02x", data[i]);
+
+   if (timestamp == NULL) {
+  free(renderer);
+  return;
+   }
+
+   brw->ctx.Cache = disk_cache_create(renderer, timestamp, 0);
+   free(renderer);
+   free(timestamp);
+#endif
+}
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c98b7facd5..927e77920e 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,6 +132,7 @@ void gen8_write_pma_stall_bits(struct brw_context *brw,
uint32_t pma_stall_bits);
 
 /* brw_disk_cache.c */
+void brw_disk_cache_init(struct brw_context *brw);
 bool brw_disk_cache_upload_program(struct brw_context *brw,
gl_shader_stage stage);
 void brw_disk_cache_write_compute_program(struct brw_context *brw);
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 26/32] i965: Don't link when the program was found in the disk cache

[Jordan Justen]

Signed-off-by: Jordan Justen 
Cc: Timothy Arceri 
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 2d10325e4a..b5b84dec63 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -225,6 +225,9 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
unsigned int stage;
struct shader_info *infos[MESA_SHADER_STAGES] = { 0, };
 
+   if (shProg->data->LinkStatus == linking_skipped)
+  return GL_TRUE;
+
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
   struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
   if (!shader)
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 32/32] disk_cache: Add support for MESA_GLSL_CACHE_TIMESTAMP in debug builds

[Jordan Justen]

The MESA_GLSL_CACHE_TIMESTAMP environment variable can be set to
override the driver timestamp. Usually the driver will specify a hash
of their driver build so the cache items become invalid with each
driver build.

We don't guarantee a stable serialized shader cache format, so
changing the timestamp for each build is required for safety.

Nevertheless, during debug, making small changes to the driver may be
known to be safe. The driver developer can use this variable to keep
the timestamp consistent. When debugging issues on an application for
which the shader cache greatly lowers the startup time, this can save
the developer significant time.

Signed-off-by: Jordan Justen 
---
 src/util/disk_cache.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
index fde6e2e097..54f48a8ba5 100644
--- a/src/util/disk_cache.c
+++ b/src/util/disk_cache.c
@@ -208,6 +208,18 @@ disk_cache_create(const char *gpu_name, const char 
*timestamp,
if (env_var_as_boolean("MESA_GLSL_CACHE_DISABLE", false))
   goto fail;
 
+#ifdef DEBUG
+   /* For debug builds, MESA_GLSL_CACHE_TIMESTAMP can be set to override the
+* driver specified timestamp. This will allow small changes to be made to
+* the driver without invalidating the cache. Given that this is normally
+* unsafe, it is only allowed for debug builds.
+*/
+   const char *timestamp_override = getenv("MESA_GLSL_CACHE_TIMESTAMP");
+   if (timestamp_override) {
+  timestamp = timestamp_override;
+   }
+#endif
+
/* Determine path for cache based on the first defined name as follows:
 *
 *   $MESA_GLSL_CACHE_DIR
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 22/32] i965: Add shader cache support for compute

[Jordan Justen]

v2:
 * Use MAYBE_UNUSED. (Matt)

Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_cs.c   | 24 ---
 src/mesa/drivers/dri/i965/brw_cs.h   |  3 +++
 src/mesa/drivers/dri/i965/brw_disk_cache.c   | 36 +++-
 src/mesa/drivers/dri/i965/brw_state.h|  3 ++-
 src/mesa/drivers/dri/i965/brw_state_upload.c |  3 ++-
 5 files changed, 57 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
b/src/mesa/drivers/dri/i965/brw_cs.c
index be7680def7..a319f14ff3 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -153,7 +153,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
 }
 
 
-static void
+void
 brw_cs_populate_key(struct brw_context *brw, struct brw_cs_prog_key *key)
 {
struct gl_context *ctx = >ctx;
@@ -191,14 +191,20 @@ brw_upload_cs_prog(struct brw_context *brw)
 
brw_cs_populate_key(brw, );
 
-   if (!brw_search_cache(>cache, BRW_CACHE_CS_PROG,
- , sizeof(key),
- >cs.base.prog_offset,
- >cs.base.prog_data)) {
-  bool success = brw_codegen_cs_prog(brw, cp, );
-  (void) success;
-  assert(success);
-   }
+   if (brw_search_cache(>cache, BRW_CACHE_CS_PROG,
+, sizeof(key),
+>cs.base.prog_offset,
+>cs.base.prog_data))
+  return;
+
+   if (brw_disk_cache_upload_program(brw, MESA_SHADER_COMPUTE))
+  return;
+
+   cp = (struct brw_program *) brw->programs[MESA_SHADER_COMPUTE];
+   cp->id = key.program_string_id;
+
+   MAYBE_UNUSED bool success = brw_codegen_cs_prog(brw, cp, );
+   assert(success);
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_cs.h 
b/src/mesa/drivers/dri/i965/brw_cs.h
index 890a0c8a80..60eb19c359 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.h
+++ b/src/mesa/drivers/dri/i965/brw_cs.h
@@ -32,6 +32,9 @@ extern "C" {
 void
 brw_upload_cs_prog(struct brw_context *brw);
 
+void
+brw_cs_populate_key(struct brw_context *brw, struct brw_cs_prog_key *key);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 4481189eca..0a612d7811 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -31,6 +31,7 @@
 
 #include "brw_context.h"
 #include "brw_program.h"
+#include "brw_cs.h"
 #include "brw_gs.h"
 #include "brw_state.h"
 #include "brw_vs.h"
@@ -129,6 +130,7 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
struct brw_tes_prog_key tes_key;
struct brw_gs_prog_key gs_key;
struct brw_vs_prog_key vs_key;
+   struct brw_cs_prog_key cs_key;
 
switch (stage) {
case MESA_SHADER_VERTEX:
@@ -159,6 +161,11 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
   wm_key.program_string_id = 0;
   gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
   break;
+   case MESA_SHADER_COMPUTE:
+  brw_cs_populate_key(brw, _key);
+  cs_key.program_string_id = 0;
+  gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
+  break;
default:
   unreachable("Unsupported stage!");
}
@@ -229,6 +236,11 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
   SET_UPLOAD_PRAMS(wm, FS, wp)
   break;
}
+   case MESA_SHADER_COMPUTE: {
+  struct brw_program *cp = (struct brw_program *) prog;
+  SET_UPLOAD_PRAMS(cs, CS, cp)
+  break;
+   }
default:
   unreachable("Unsupported stage!");
}
@@ -357,7 +369,7 @@ write_program_data(struct brw_context *brw, struct 
gl_program *prog,
 }
 
 void
-brw_disk_cache_write_program(struct brw_context *brw)
+brw_disk_cache_write_render_programs(struct brw_context *brw)
 {
struct disk_cache *cache = brw->ctx.Cache;
if (cache == NULL)
@@ -429,3 +441,25 @@ brw_disk_cache_write_program(struct brw_context *brw)
  MESA_SHADER_FRAGMENT);
}
 }
+
+void
+brw_disk_cache_write_compute_program(struct brw_context *brw)
+{
+   struct disk_cache *cache = brw->ctx.Cache;
+   if (cache == NULL)
+  return;
+
+   struct gl_program *prog =
+  brw->ctx._Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+   if (prog && !prog->program_written_to_cache) {
+  struct brw_cs_prog_key cs_key;
+  brw_cs_populate_key(brw, _key);
+  cs_key.program_string_id = 0;
+
+  write_program_data(brw, prog, _key, brw->cs.base.prog_data,
+ brw->cs.base.prog_data->program_size,
+ sizeof(struct brw_cs_prog_data),
+ brw->cs.base.prog_offset, cache,
+ MESA_SHADER_COMPUTE);
+   }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6f2e0501b4..c98b7facd5 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h

[Mesa-dev] [PATCH v2 03/32] nir/intrinsics: Set the correct num_indices for load_output

[Jordan Justen]

From: Jason Ekstrand 

Cc: mesa-sta...@lists.freedesktop.org
---
 src/compiler/nir/nir_intrinsics.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_intrinsics.h 
b/src/compiler/nir/nir_intrinsics.h
index 0de7080bfa..cefd18be90 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -434,7 +434,7 @@ INTRINSIC(load_interpolated_input, 2, ARR(2, 1), true, 0, 0,
 /* src[] = { buffer_index, offset }. No const_index */
 LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { offset }. const_index[] = { base, component } */
-LOAD(output, 1, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
+LOAD(output, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { vertex, offset }. const_index[] = { base, component } */
 LOAD(per_vertex_output, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { offset }. const_index[] = { base } */
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 20/32] i965: add shader cache support for geometry shaders

[Jordan Justen]

From: Timothy Arceri 

v2:
 * Use MAYBE_UNUSED. (Matt)

[jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 25 +
 src/mesa/drivers/dri/i965/brw_gs.c | 22 ++
 2 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 6fe39a7997..a16053f4bb 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -30,6 +30,7 @@
 #include "util/mesa-sha1.h"
 
 #include "brw_context.h"
+#include "brw_gs.h"
 #include "brw_state.h"
 #include "brw_vs.h"
 #include "brw_wm.h"
@@ -123,6 +124,7 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
unsigned char binary_sha1[20];
 
struct brw_wm_prog_key wm_key;
+   struct brw_gs_prog_key gs_key;
struct brw_vs_prog_key vs_key;
 
switch (stage) {
@@ -134,6 +136,11 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
   vs_key.program_string_id = 0;
   gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
   break;
+   case MESA_SHADER_GEOMETRY:
+  brw_gs_populate_key(brw, _key);
+  gs_key.program_string_id = 0;
+  gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
+  break;
case MESA_SHADER_FRAGMENT:
   brw_wm_populate_key(brw, _key);
   wm_key.program_string_id = 0;
@@ -189,6 +196,11 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
   SET_UPLOAD_PRAMS(vs, VS, vp)
   break;
}
+   case MESA_SHADER_GEOMETRY: {
+  struct brw_program *gp = (struct brw_program *) prog;
+  SET_UPLOAD_PRAMS(gs, GS, gp)
+  break;
+   }
case MESA_SHADER_FRAGMENT: {
   struct brw_program *wp = (struct brw_program *) prog;
   SET_UPLOAD_PRAMS(wm, FS, wp)
@@ -342,6 +354,19 @@ brw_disk_cache_write_program(struct brw_context *brw)
  MESA_SHADER_VERTEX);
}
 
+   prog = brw->ctx._Shader->CurrentProgram[MESA_SHADER_GEOMETRY];
+   if (prog && !prog->program_written_to_cache) {
+  struct brw_gs_prog_key gs_key;
+  brw_gs_populate_key(brw, _key);
+  gs_key.program_string_id = 0;
+
+  write_program_data(brw, prog, _key, brw->gs.base.prog_data,
+ brw->gs.base.prog_data->program_size,
+ sizeof(struct brw_gs_prog_data),
+ brw->gs.base.prog_offset, cache,
+ MESA_SHADER_GEOMETRY);
+   }
+
prog = brw->ctx._Shader->CurrentProgram[MESA_SHADER_FRAGMENT];
if (prog && !prog->program_written_to_cache) {
   struct brw_wm_prog_key wm_key;
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index 007629cbbb..d9860ebf33 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -194,14 +194,20 @@ brw_upload_gs_prog(struct brw_context *brw)
 
brw_gs_populate_key(brw, );
 
-   if (!brw_search_cache(>cache, BRW_CACHE_GS_PROG,
- , sizeof(key),
- _state->prog_offset,
- >gs.base.prog_data)) {
-  bool success = brw_codegen_gs_prog(brw, gp, );
-  assert(success);
-  (void)success;
-   }
+   if (brw_search_cache(>cache, BRW_CACHE_GS_PROG,
+, sizeof(key),
+_state->prog_offset,
+>gs.base.prog_data))
+  return;
+
+   if (brw_disk_cache_upload_program(brw, MESA_SHADER_GEOMETRY))
+  return;
+
+   gp = (struct brw_program *) brw->programs[MESA_SHADER_GEOMETRY];
+   gp->id = key.program_string_id;
+
+   MAYBE_UNUSED bool success = brw_codegen_gs_prog(brw, gp, );
+   assert(success);
 }
 
 bool
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 30/32] dri drivers: Always add the sha1 build-id

[Jordan Justen]

Cc: Dylan Baker 
Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/Makefile.am | 1 +
 src/mesa/drivers/dri/meson.build | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/Makefile.am b/src/mesa/drivers/dri/Makefile.am
index 95c637d0cd..5cb2127501 100644
--- a/src/mesa/drivers/dri/Makefile.am
+++ b/src/mesa/drivers/dri/Makefile.am
@@ -57,6 +57,7 @@ mesa_dri_drivers_la_LDFLAGS = \
-module \
-no-undefined \
-avoid-version \
+   -Wl,--build-id=sha1 \
$(BSYMBOLIC) \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
diff --git a/src/mesa/drivers/dri/meson.build b/src/mesa/drivers/dri/meson.build
index 36079324d4..98ed28d04c 100644
--- a/src/mesa/drivers/dri/meson.build
+++ b/src/mesa/drivers/dri/meson.build
@@ -41,7 +41,7 @@ if dri_drivers != []
  libmesa_util, libnir, libmesa_classic],
 dependencies : [dep_selinux, dep_libdrm, dep_expat, dep_m, dep_thread,
 dep_dl],
-link_args : [ld_args_bsymbolic, ld_args_gc_sections],
+link_args : ['-Wl,--build-id=sha1', ld_args_bsymbolic, 
ld_args_gc_sections],
   )
 
   pkg.generate(
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 06/32] nir: Zero local_size const struct for valgrind & nir_serialize

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/compiler/nir/nir_lower_system_values.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_lower_system_values.c 
b/src/compiler/nir/nir_lower_system_values.c
index ba20d3083f..39b1a260bd 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -58,6 +58,7 @@ convert_block(nir_block *block, nir_builder *b)
   */
 
  nir_const_value local_size;
+ memset(_size, 0, sizeof(local_size));
  local_size.u32[0] = b->shader->info.cs.local_size[0];
  local_size.u32[1] = b->shader->info.cs.local_size[1];
  local_size.u32[2] = b->shader->info.cs.local_size[2];
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 21/32] i965: add shader cache support for tess stages

[Jordan Justen]

From: Timothy Arceri 

v2:
 * Use MAYBE_UNUSED. (Matt)

[jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 49 ++
 src/mesa/drivers/dri/i965/brw_tcs.c| 23 +-
 src/mesa/drivers/dri/i965/brw_tes.c| 22 +-
 3 files changed, 78 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index a16053f4bb..4481189eca 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -30,6 +30,7 @@
 #include "util/mesa-sha1.h"
 
 #include "brw_context.h"
+#include "brw_program.h"
 #include "brw_gs.h"
 #include "brw_state.h"
 #include "brw_vs.h"
@@ -124,6 +125,8 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
unsigned char binary_sha1[20];
 
struct brw_wm_prog_key wm_key;
+   struct brw_tcs_prog_key tcs_key;
+   struct brw_tes_prog_key tes_key;
struct brw_gs_prog_key gs_key;
struct brw_vs_prog_key vs_key;
 
@@ -136,6 +139,16 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
   vs_key.program_string_id = 0;
   gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
   break;
+   case MESA_SHADER_TESS_CTRL:
+  brw_tcs_populate_key(brw, _key);
+  tcs_key.program_string_id = 0;
+  gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
+  break;
+   case MESA_SHADER_TESS_EVAL:
+  brw_tes_populate_key(brw, _key);
+  tes_key.program_string_id = 0;
+  gen_shader_sha1(brw, prog, stage, _key, binary_sha1);
+  break;
case MESA_SHADER_GEOMETRY:
   brw_gs_populate_key(brw, _key);
   gs_key.program_string_id = 0;
@@ -196,6 +209,16 @@ read_and_upload(struct brw_context *brw, struct disk_cache 
*cache,
   SET_UPLOAD_PRAMS(vs, VS, vp)
   break;
}
+   case MESA_SHADER_TESS_CTRL: {
+  struct brw_program *tcp = (struct brw_program *) prog;
+  SET_UPLOAD_PRAMS(tcs, TCS, tcp)
+  break;
+   }
+   case MESA_SHADER_TESS_EVAL: {
+  struct brw_program *tep = (struct brw_program *) prog;
+  SET_UPLOAD_PRAMS(tes, TES, tep)
+  break;
+   }
case MESA_SHADER_GEOMETRY: {
   struct brw_program *gp = (struct brw_program *) prog;
   SET_UPLOAD_PRAMS(gs, GS, gp)
@@ -354,6 +377,32 @@ brw_disk_cache_write_program(struct brw_context *brw)
  MESA_SHADER_VERTEX);
}
 
+   prog = brw->ctx._Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
+   if (prog && !prog->program_written_to_cache) {
+  struct brw_tcs_prog_key tcs_key;
+  brw_tcs_populate_key(brw, _key);
+  tcs_key.program_string_id = 0;
+
+  write_program_data(brw, prog, _key, brw->tcs.base.prog_data,
+ brw->tcs.base.prog_data->program_size,
+ sizeof(struct brw_tcs_prog_data),
+ brw->tcs.base.prog_offset, cache,
+ MESA_SHADER_TESS_CTRL);
+   }
+
+   prog = brw->ctx._Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
+   if (prog && !prog->program_written_to_cache) {
+  struct brw_tes_prog_key tes_key;
+  brw_tes_populate_key(brw, _key);
+  tes_key.program_string_id = 0;
+
+  write_program_data(brw, prog, _key, brw->tes.base.prog_data,
+ brw->tes.base.prog_data->program_size,
+ sizeof(struct brw_tes_prog_data),
+ brw->tes.base.prog_offset, cache,
+ MESA_SHADER_TESS_EVAL);
+   }
+
prog = brw->ctx._Shader->CurrentProgram[MESA_SHADER_GEOMETRY];
if (prog && !prog->program_written_to_cache) {
   struct brw_gs_prog_key gs_key;
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c 
b/src/mesa/drivers/dri/i965/brw_tcs.c
index 6c9cb153d3..3ee6a59d41 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -339,14 +339,21 @@ brw_upload_tcs_prog(struct brw_context *brw)
 
brw_tcs_populate_key(brw, );
 
-   if (!brw_search_cache(>cache, BRW_CACHE_TCS_PROG,
- , sizeof(key),
- _state->prog_offset,
- >tcs.base.prog_data)) {
-  bool success = brw_codegen_tcs_prog(brw, tcp, tep, );
-  assert(success);
-  (void)success;
-   }
+   if (brw_search_cache(>cache, BRW_CACHE_TCS_PROG,
+, sizeof(key),
+_state->prog_offset,
+>tcs.base.prog_data))
+  return;
+
+   if (brw_disk_cache_upload_program(brw, MESA_SHADER_TESS_CTRL))
+  return;
+
+   tcp = (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
+   if (tcp)
+  tcp->id = key.program_string_id;
+
+   MAYBE_UNUSED bool success = brw_codegen_tcs_prog(brw, tcp, tep, );
+   assert(success);
 }
 
 
diff --git 

[Mesa-dev] [PATCH v2 12/32] nir: Add hooks for testing serialization

[Jordan Justen]

From: Jason Ekstrand 

---
 src/compiler/nir/nir.h   | 17 +
 src/compiler/nir/nir_serialize.c | 19 +++
 2 files changed, 36 insertions(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index dd833cf183..87c725625d 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2312,6 +2312,8 @@ nir_variable *nir_variable_clone(const nir_variable *c, 
nir_shader *shader);
 nir_deref *nir_deref_clone(const nir_deref *deref, void *mem_ctx);
 nir_deref_var *nir_deref_var_clone(const nir_deref_var *deref, void *mem_ctx);
 
+nir_shader *nir_shader_serialize_deserialize(void *mem_ctx, nir_shader *s);
+
 #ifdef DEBUG
 void nir_validate_shader(nir_shader *shader);
 void nir_metadata_set_validation_flag(nir_shader *shader);
@@ -2327,6 +2329,16 @@ should_clone_nir(void)
return should_clone;
 }
 
+static inline bool
+should_serialize_deserialize_nir(void)
+{
+   static int test_serialize = -1;
+   if (test_serialize < 0)
+  test_serialize = env_var_as_boolean("NIR_TEST_SERIALIZE", false);
+
+   return test_serialize;
+}
+
 static inline bool
 should_print_nir(void)
 {
@@ -2341,6 +2353,7 @@ static inline void nir_validate_shader(nir_shader 
*shader) { (void) shader; }
 static inline void nir_metadata_set_validation_flag(nir_shader *shader) { 
(void) shader; }
 static inline void nir_metadata_check_validation_flag(nir_shader *shader) { 
(void) shader; }
 static inline bool should_clone_nir(void) { return false; }
+static inline bool should_serialize_deserialize_nir(void) { return false; }
 static inline bool should_print_nir(void) { return false; }
 #endif /* DEBUG */
 
@@ -2352,6 +2365,10 @@ static inline bool should_print_nir(void) { return 
false; }
   ralloc_free(nir);  \
   nir = clone;   \
} \
+   if (should_serialize_deserialize_nir()) { \
+  void *mem_ctx = ralloc_parent(nir);\
+  nir = nir_shader_serialize_deserialize(mem_ctx, nir);  \
+   } \
 } while (0)
 
 #define NIR_PASS(progress, nir, pass, ...) _PASS(nir,\
diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c
index fb6232446b..eb82fa65ac 100644
--- a/src/compiler/nir/nir_serialize.c
+++ b/src/compiler/nir/nir_serialize.c
@@ -1199,3 +1199,22 @@ nir_deserialize(void *mem_ctx,
 
return ctx.nir;
 }
+
+nir_shader *
+nir_shader_serialize_deserialize(void *mem_ctx, nir_shader *s)
+{
+   const struct nir_shader_compiler_options *options = s->options;
+
+   struct blob writer;
+   blob_init();
+   nir_serialize(, s);
+   ralloc_free(s);
+
+   struct blob_reader reader;
+   blob_reader_init(, writer.data, writer.size);
+   nir_shader *ns = nir_deserialize(mem_ctx, options, );
+
+   blob_finish();
+
+   return ns;
+}
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 11/32] nir: add serialization and deserialization

[Jordan Justen]

From: Connor Abbott 

v2 (Jason Ekstrand):
 - Various whitespace cleanups
 - Add helpers for reading/writing objects
 - Rework derefs
 - [de]serialize nir_shader::num_*
 - Fix uses of blob_reserve_bytes
 - Use a bitfield struct for packing tex_instr data

v3:
 - Zero nir_variable struct on deserialization. (Jordan)
 - Allow nir_serialize.h to be included in C++. (Jordan)
 - Handle NULL info.name. (Jason)
 - Set info.name to NULL when name is NULL. (Jordan)
---
 src/compiler/Makefile.sources|2 +
 src/compiler/nir/meson.build |2 +
 src/compiler/nir/nir_serialize.c | 1201 ++
 src/compiler/nir/nir_serialize.h |   43 ++
 4 files changed, 1248 insertions(+)
 create mode 100644 src/compiler/nir/nir_serialize.c
 create mode 100644 src/compiler/nir/nir_serialize.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 2724a41286..f4d4c17855 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -276,6 +276,8 @@ NIR_FILES = \
nir/nir_search.c \
nir/nir_search.h \
nir/nir_search_helpers.h \
+   nir/nir_serialize.c \
+   nir/nir_serialize.h \
nir/nir_split_var_copies.c \
nir/nir_sweep.c \
nir/nir_to_lcssa.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 144cf01d2c..b4c733dcae 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -164,6 +164,8 @@ files_libnir = files(
   'nir_search.c',
   'nir_search.h',
   'nir_search_helpers.h',
+  'nir_serialize.c',
+  'nir_serialize.h',
   'nir_split_var_copies.c',
   'nir_sweep.c',
   'nir_to_lcssa.c',
diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c
new file mode 100644
index 00..fb6232446b
--- /dev/null
+++ b/src/compiler/nir/nir_serialize.c
@@ -0,0 +1,1201 @@
+/*
+ * Copyright © 2017 Connor Abbott
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir_serialize.h"
+#include "nir_control_flow.h"
+#include "util/u_dynarray.h"
+
+typedef struct {
+   size_t blob_offset;
+   nir_ssa_def *src;
+   nir_block *block;
+} write_phi_fixup;
+
+typedef struct {
+   const nir_shader *nir;
+
+   struct blob *blob;
+
+   /* maps pointer to index */
+   struct hash_table *remap_table;
+
+   /* the next index to assign to a NIR in-memory object */
+   uintptr_t next_idx;
+
+   /* Array of write_phi_fixup structs representing phi sources that need to
+* be resolved in the second pass.
+*/
+   struct util_dynarray phi_fixups;
+} write_ctx;
+
+typedef struct {
+   nir_shader *nir;
+
+   struct blob_reader *blob;
+
+   /* the next index to assign to a NIR in-memory object */
+   uintptr_t next_idx;
+
+   /* The length of the index -> object table */
+   uintptr_t idx_table_len;
+
+   /* map from index to deserialized pointer */
+   void **idx_table;
+
+   /* List of phi sources. */
+   struct list_head phi_srcs;
+
+} read_ctx;
+
+static void
+write_add_object(write_ctx *ctx, const void *obj)
+{
+   uintptr_t index = ctx->next_idx++;
+   _mesa_hash_table_insert(ctx->remap_table, obj, (void *) index);
+}
+
+static uintptr_t
+write_lookup_object(write_ctx *ctx, const void *obj)
+{
+   struct hash_entry *entry = _mesa_hash_table_search(ctx->remap_table, obj);
+   assert(entry);
+   return (uintptr_t) entry->data;
+}
+
+static void
+write_object(write_ctx *ctx, const void *obj)
+{
+   blob_write_intptr(ctx->blob, write_lookup_object(ctx, obj));
+}
+
+static void
+read_add_object(read_ctx *ctx, void *obj)
+{
+   assert(ctx->next_idx < ctx->idx_table_len);
+   ctx->idx_table[ctx->next_idx++] = obj;
+}
+
+static void *
+read_lookup_object(read_ctx *ctx, uintptr_t idx)
+{
+   assert(idx < ctx->idx_table_len);
+   return ctx->idx_table[idx];
+}
+
+static void *
+read_object(read_ctx *ctx)
+{
+   return read_lookup_object(ctx, 

[Mesa-dev] [PATCH v2 27/32] i965: Initialize sha1 hash of dri config options

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_context.c | 4 
 src/mesa/drivers/dri/i965/brw_context.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 609d815064..6a88d8bb48 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1014,6 +1014,10 @@ brwCreateContext(gl_api api,
vbo_use_buffer_objects(ctx);
vbo_always_unmap_buffers(ctx);
 
+   driComputeOptionsSha1(>screen->optionCache,
+ brw->dri_config_options_sha1);
+   brw->ctx.Const.dri_config_options_sha1 = brw->dri_config_options_sha1;
+
return true;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 679b848c50..f2bba2cfc1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1211,6 +1211,7 @@ struct brw_context
bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS];
 
__DRIcontext *driContext;
+   unsigned char dri_config_options_sha1[20];
struct intel_screen *screen;
 };
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 25/32] i965: add cache fallback support using serialized nir

[Jordan Justen]

If the i965 gen program cannot be loaded from the cache, then we
fallback to using a serialized nir program.

This is based on "i965: add cache fallback support" by Timothy Arceri
. Tim's version was written to fallback
to compiling from source, and therefore had to be much more complex.
After Connor and Jason implemented nir serialization, I was able to
rewrite and greatly simplify this patch.

Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index d89df846d5..790fad6925 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -24,6 +24,7 @@
 #include "compiler/blob.h"
 #include "compiler/glsl/ir_uniform.h"
 #include "compiler/glsl/shader_cache.h"
+#include "compiler/nir/nir_serialize.h"
 #include "main/mtypes.h"
 #include "util/disk_cache.h"
 #include "util/macros.h"
@@ -79,6 +80,27 @@ gen_shader_sha1(struct brw_context *brw, struct gl_program 
*prog,
_mesa_sha1_compute(manifest, strlen(manifest), out_sha1);
 }
 
+static void
+fallback_to_full_recompile(struct brw_context *brw, struct gl_program *prog,
+   gl_shader_stage stage)
+{
+   prog->program_written_to_cache = false;
+   if (brw->ctx._Shader->Flags & GLSL_CACHE_INFO) {
+  fprintf(stderr, "falling back to nir %s.\n",
+  _mesa_shader_stage_to_abbrev(prog->info.stage));
+   }
+
+   if (!prog->nir) {
+  assert(prog->serialized_nir && prog->serialized_nir_size > 0);
+  const struct nir_shader_compiler_options *options =
+ brw->ctx.Const.ShaderCompilerOptions[stage].NirOptions;
+  struct blob_reader reader;
+  blob_reader_init(, prog->serialized_nir,
+   prog->serialized_nir_size);
+  prog->nir = nir_deserialize(NULL, options, );
+   }
+}
+
 static void
 read_program_data(struct gl_program *glprog, struct blob_reader *binary,
   struct brw_stage_prog_data *prog_data,
@@ -298,6 +320,9 @@ brw_disk_cache_upload_program(struct brw_context *brw, 
gl_shader_stage stage)
prog->sh.LinkedTransformFeedback->api_enabled)
   return false;
 
+   if (brw->ctx._Shader->Flags & GLSL_CACHE_FALLBACK)
+  goto FAIL;
+
if (prog->sh.data->LinkStatus != linking_skipped)
   goto FAIL;
 
@@ -311,7 +336,7 @@ brw_disk_cache_upload_program(struct brw_context *brw, 
gl_shader_stage stage)
return true;
 
 FAIL:
-   /*FIXME: Fall back and compile from source here. */
+   fallback_to_full_recompile(brw, prog, stage);
return false;
 }
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 17/32] intel/compiler: add new field for storing program size

[Jordan Justen]

From: Carl Worth 

This will be used by the on disk shader cache.

v2:
 * Set in brw_compile_* rather than brw_codegen_*. (Jason)

Signed-off-by: Timothy Arceri 
[jordan.l.jus...@intel.com: Only add to brw_stage_prog_data]
Signed-off-by: Jordan Justen 
---
 src/intel/compiler/brw_compiler.h  |  2 ++
 src/intel/compiler/brw_fs.cpp  |  8 ++--
 src/intel/compiler/brw_shader.cpp  | 12 
 src/intel/compiler/brw_vec4.cpp|  1 +
 src/intel/compiler/brw_vec4_gs_visitor.cpp | 14 ++
 src/intel/compiler/brw_vec4_tcs.cpp| 12 
 6 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index 014202d36c..b57834ddaa 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -588,6 +588,8 @@ struct brw_stage_prog_data {
unsigned total_scratch;
unsigned total_shared;
 
+   unsigned program_size;
+
/**
 * Register where the thread expects to find input data from the URB
 * (typically uniforms, followed by vertex or fragment attributes).
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 66cb33131b..77f704ec99 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -,7 +,9 @@ brw_compile_fs(const struct brw_compiler *compiler, void 
*log_data,
   prog_data->reg_blocks_0 = brw_register_blocks(simd16_grf_used);
}
 
-   return g.get_assembly(final_assembly_size);
+   const unsigned *assembly = g.get_assembly(final_assembly_size);
+   prog_data->base.program_size = *final_assembly_size;
+   return assembly;
 }
 
 fs_reg *
@@ -6865,7 +6867,9 @@ brw_compile_cs(const struct brw_compiler *compiler, void 
*log_data,
 
g.generate_code(cfg, prog_data->simd_size);
 
-   return g.get_assembly(final_assembly_size);
+   const unsigned *assembly = g.get_assembly(final_assembly_size);
+   prog_data->base.program_size = *final_assembly_size;
+   return assembly;
 }
 
 /**
diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp
index 83ad152f89..f00da96f68 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1166,6 +1166,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
 {
const struct gen_device_info *devinfo = compiler->devinfo;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
+   const unsigned *assembly;
 
nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
nir->info.inputs_read = key->inputs_read;
@@ -1274,7 +1275,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
 
   g.generate_code(v.cfg, 8);
 
-  return g.get_assembly(final_assembly_size);
+  assembly = g.get_assembly(final_assembly_size);
} else {
   brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
  nir, mem_ctx, shader_time_index);
@@ -1287,8 +1288,11 @@ brw_compile_tes(const struct brw_compiler *compiler,
   if (unlikely(INTEL_DEBUG & DEBUG_TES))
 v.dump_instructions();
 
-  return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
-   _data->base, v.cfg,
-   final_assembly_size);
+  assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
+_data->base, v.cfg,
+final_assembly_size);
}
+
+   prog_data->base.base.program_size = *final_assembly_size;
+   return assembly;
 }
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 04304fcb45..b7af8860e8 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2905,6 +2905,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
 final_assembly_size);
}
 
+   prog_data->base.base.program_size = *final_assembly_size;
return assembly;
 }
 
diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp 
b/src/intel/compiler/brw_vec4_gs_visitor.cpp
index 5df6d562ce..11b73f187c 100644
--- a/src/intel/compiler/brw_vec4_gs_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp
@@ -868,7 +868,9 @@ brw_compile_gs(const struct brw_compiler *compiler, void 
*log_data,
 g.enable_debug(name);
  }
  g.generate_code(v.cfg, 8);
- return g.get_assembly(final_assembly_size);
+ const unsigned *ret = g.get_assembly(final_assembly_size);
+ prog_data->base.base.program_size = *final_assembly_size;
+ return ret;
   }
}
 
@@ -897,9 +899,12 @@ brw_compile_gs(const struct brw_compiler *compiler, void 
*log_data,
  if (v.run()) {
 /* Success! Backup is not needed */
 ralloc_free(param);
-  

[Mesa-dev] [PATCH v2 08/32] nir: Zero nir_load_const_instr::value for valgrind & nir_serialize

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/compiler/nir/nir.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index fe48451694..cbba9c8749 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -481,6 +481,7 @@ nir_load_const_instr_create(nir_shader *shader, unsigned 
num_components,
 unsigned bit_size)
 {
nir_load_const_instr *instr = ralloc(shader, nir_load_const_instr);
+   memset(>value, 0, sizeof(instr->value));
instr_init(>instr, nir_instr_type_load_const);
 
nir_ssa_def_init(>instr, >def, num_components, bit_size, 
NULL);
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 10/32] glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serialize

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/compiler/glsl/glsl_to_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 1d1085ffbc..c659a25ca7 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -219,7 +219,7 @@ constant_copy(ir_constant *ir, void *mem_ctx)
if (ir == NULL)
   return NULL;
 
-   nir_constant *ret = ralloc(mem_ctx, nir_constant);
+   nir_constant *ret = rzalloc(mem_ctx, nir_constant);
 
const unsigned rows = ir->type->vector_elements;
const unsigned cols = ir->type->matrix_columns;
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 13/32] main: Add nir serialization fields to gl_program

[Jordan Justen]

These fields can be used to optionally save off a nir serialized form
of the program.

Signed-off-by: Jordan Justen 
---
 src/mesa/main/mtypes.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2802a0e360..a5a1398698 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2078,6 +2078,8 @@ struct gl_program
GLboolean _Used;/**< Ever used for drawing? Used for debugging */
 
struct nir_shader *nir;
+   uint8_t *serialized_nir;
+   size_t serialized_nir_size;
 
bool is_arb_asm; /** Is this an ARB assembly-style program */
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 16/32] i965: Don't rely on nir for uses_texture_gather

[Jordan Justen]

When a program is restored from the shader cache, prog->nir will be
NULL, but prog->info will be restored.

Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_wm.c   |  4 ++--
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 69d8e61e40..e511f0f70b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -330,7 +330,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
  }
 
  /* gather4 for RG32* is broken in multiple ways on Gen7. */
- if (devinfo->gen == 7 && prog->nir->info.uses_texture_gather) {
+ if (devinfo->gen == 7 && prog->info.uses_texture_gather) {
 switch (img->InternalFormat) {
 case GL_RG32I:
 case GL_RG32UI: {
@@ -368,7 +368,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
  /* Gen6's gather4 is broken for UINT/SINT; we treat them as
   * UNORM/FLOAT instead and fix it in the shader.
   */
- if (devinfo->gen == 6 && prog->nir->info.uses_texture_gather) {
+ if (devinfo->gen == 6 && prog->info.uses_texture_gather) {
 key->gen6_gather_wa[s] = 
gen6_gather_workaround(img->InternalFormat);
  }
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f4e9cf48c6..4f454dae44 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1198,15 +1198,15 @@ brw_update_texture_surfaces(struct brw_context *brw)
 * allows the surface format to be overriden for only the
 * gather4 messages. */
if (devinfo->gen < 8) {
-  if (vs && vs->nir->info.uses_texture_gather)
+  if (vs && vs->info.uses_texture_gather)
  update_stage_texture_surfaces(brw, vs, >vs.base, true, 0);
-  if (tcs && tcs->nir->info.uses_texture_gather)
+  if (tcs && tcs->info.uses_texture_gather)
  update_stage_texture_surfaces(brw, tcs, >tcs.base, true, 0);
-  if (tes && tes->nir->info.uses_texture_gather)
+  if (tes && tes->info.uses_texture_gather)
  update_stage_texture_surfaces(brw, tes, >tes.base, true, 0);
-  if (gs && gs->nir->info.uses_texture_gather)
+  if (gs && gs->info.uses_texture_gather)
  update_stage_texture_surfaces(brw, gs, >gs.base, true, 0);
-  if (fs && fs->nir->info.uses_texture_gather)
+  if (fs && fs->info.uses_texture_gather)
  update_stage_texture_surfaces(brw, fs, >wm.base, true, 0);
}
 
@@ -1253,7 +1253,7 @@ brw_update_cs_texture_surfaces(struct brw_context *brw)
 * gather4 messages.
 */
if (devinfo->gen < 8) {
-  if (cs && cs->nir->info.uses_texture_gather)
+  if (cs && cs->info.uses_texture_gather)
  update_stage_texture_surfaces(brw, cs, >cs.base, true, 0);
}
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 14/32] glsl/shader_cache: Save and restore serialized nir in gl_program

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/compiler/glsl/shader_cache.cpp | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/compiler/glsl/shader_cache.cpp 
b/src/compiler/glsl/shader_cache.cpp
index ca90cfde35..f43bd6b17e 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -1062,6 +1062,14 @@ write_shader_metadata(struct blob *metadata, 
gl_linked_shader *shader)
}
 
write_shader_parameters(metadata, glprog->Parameters);
+
+   assert((glprog->serialized_nir == NULL) ==
+  (glprog->serialized_nir_size == 0));
+   blob_write_uint32(metadata, (uint32_t)glprog->serialized_nir_size);
+   if (glprog->serialized_nir_size > 0) {
+  blob_write_bytes(metadata, glprog->serialized_nir,
+   glprog->serialized_nir_size);
+   }
 }
 
 static void
@@ -1116,6 +1124,14 @@ read_shader_metadata(struct blob_reader *metadata,
 
glprog->Parameters = _mesa_new_parameter_list();
read_shader_parameters(metadata, glprog->Parameters);
+
+   glprog->serialized_nir_size = (size_t)blob_read_uint32(metadata);
+   if (glprog->serialized_nir_size > 0) {
+  glprog->serialized_nir =
+ (uint8_t*)ralloc_size(glprog, glprog->serialized_nir_size);
+  blob_copy_bytes(metadata, glprog->serialized_nir,
+  glprog->serialized_nir_size);
+   }
 }
 
 static void
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 18/32] i965: add initial implementation of on disk shader cache

[Jordan Justen]

From: Timothy Arceri 

This uses the recently-added disk_cache.c to write out the final
linked binary for vertex and fragment shader programs.

This is based off the initial implementation done by Carl Worth.

v2:
 * Squash 'i965: add image param shader cache support'
 * Squash 'i965: add shader cache support for pull param pointers'
 * Sustantially simplified by a rework on top of Jason's 2975e4c56a7a.
 * Rename load_program_data to read_program_data. (Jason)

[jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program]
[jordan.l.jus...@intel.com: brw_shader_cache.c => brw_disk_cache.c]
[jordan.l.jus...@intel.com: don't map to write program when LLC is present]
[jordan.l.jus...@intel.com: set program_written_to_cache on read from cache]
[jordan.l.jus...@intel.com: only try cache when status is linking_skipped]
[jordan.l.jus...@intel.com: rework based on uniforms rework 2975e4c56a7a]
Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/Makefile.sources |   1 +
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 357 +
 src/mesa/drivers/dri/i965/brw_state.h  |   5 +
 src/mesa/drivers/dri/i965/meson.build  |   1 +
 4 files changed, 364 insertions(+)
 create mode 100644 src/mesa/drivers/dri/i965/brw_disk_cache.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 053d89b81e..2980cdb3c5 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -14,6 +14,7 @@ i965_FILES = \
brw_cs.h \
brw_curbe.c \
brw_defines.h \
+   brw_disk_cache.c \
brw_draw.c \
brw_draw.h \
brw_draw_upload.c \
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
new file mode 100644
index 00..6fe39a7997
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "compiler/blob.h"
+#include "compiler/glsl/ir_uniform.h"
+#include "compiler/glsl/shader_cache.h"
+#include "main/mtypes.h"
+#include "util/disk_cache.h"
+#include "util/macros.h"
+#include "util/mesa-sha1.h"
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_vs.h"
+#include "brw_wm.h"
+
+static size_t
+key_size(gl_shader_stage stage)
+{
+   switch (stage) {
+   case MESA_SHADER_VERTEX:
+  return sizeof(struct brw_vs_prog_key);
+   case MESA_SHADER_TESS_CTRL:
+  return sizeof(struct brw_tcs_prog_key);
+   case MESA_SHADER_TESS_EVAL:
+  return sizeof(struct brw_tes_prog_key);
+   case MESA_SHADER_GEOMETRY:
+  return sizeof(struct brw_gs_prog_key);
+   case MESA_SHADER_FRAGMENT:
+  return sizeof(struct brw_wm_prog_key);
+   case MESA_SHADER_COMPUTE:
+  return sizeof(struct brw_cs_prog_key);
+   default:
+  unreachable("Unsupported stage!");
+   }
+}
+
+static void
+gen_shader_sha1(struct brw_context *brw, struct gl_program *prog,
+gl_shader_stage stage, void *key, unsigned char *out_sha1)
+{
+   char sha1_buf[41];
+   unsigned char sha1[20];
+   char manifest[256];
+   int offset = 0;
+
+   _mesa_sha1_format(sha1_buf, prog->sh.data->sha1);
+   offset += snprintf(manifest, sizeof(manifest), "program: %s\n", sha1_buf);
+
+   _mesa_sha1_compute(key, key_size(stage), sha1);
+   _mesa_sha1_format(sha1_buf, sha1);
+   offset += snprintf(manifest + offset, sizeof(manifest) - offset,
+  "%s_key: %s\n", _mesa_shader_stage_to_abbrev(stage),
+  sha1_buf);
+
+   _mesa_sha1_compute(manifest, strlen(manifest), out_sha1);
+}
+
+static void
+read_program_data(struct gl_program *glprog, struct blob_reader *binary,
+  struct brw_stage_prog_data *prog_data,
+  struct 

[Mesa-dev] [PATCH v2 09/32] glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/compiler/glsl/glsl_to_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 63694fd41f..1d1085ffbc 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -311,7 +311,7 @@ nir_visitor::visit(ir_variable *ir)
if (ir->data.mode == ir_var_shader_shared)
   return;
 
-   nir_variable *var = ralloc(shader, nir_variable);
+   nir_variable *var = rzalloc(shader, nir_variable);
var->type = ir->type;
var->name = ralloc_strdup(var, ir->name);
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 15/32] i965/link: Serialize program to nir after linking for shader cache

[Jordan Justen]

If the shader cache is enabled, after linking the program, we
serialize the program to nir. This will be saved out by the glsl
shader cache support.

Later, if the same program is found in the cache, we can use the nir
for a fallback in the unlikely case that the gen binary program is not
found in the cache.

Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 1a28e63fca..2d10325e4a 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -27,6 +27,7 @@
 #include "compiler/glsl/ir.h"
 #include "compiler/glsl/ir_optimization.h"
 #include "compiler/glsl/program.h"
+#include "compiler/nir/nir_serialize.h"
 #include "program/program.h"
 #include "main/mtypes.h"
 #include "main/shaderapi.h"
@@ -323,6 +324,15 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
   NIR_PASS_V(prog->nir, nir_lower_samplers, shProg);
   NIR_PASS_V(prog->nir, nir_lower_atomics, shProg);
 
+  if (brw->ctx.Cache) {
+ struct blob writer;
+ blob_init();
+ nir_serialize(, prog->nir);
+ // TODO: ralloc and copy. what mem ctx?
+ prog->serialized_nir = writer.data;
+ prog->serialized_nir_size = writer.size;
+  }
+
   infos[stage] = >nir->info;
 
   update_xfb_info(prog->sh.LinkedTransformFeedback, infos[stage]);
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 01/32] glsl: move shader_cache type handling to glsl_types

[Jordan Justen]

From: Connor Abbott 

Not sure if this is the best place to put it, but we're going to need
this for NIR too.
---
 src/compiler/glsl/shader_cache.cpp | 171 -
 src/compiler/glsl_types.cpp| 171 +
 src/compiler/glsl_types.h  |   7 ++
 3 files changed, 178 insertions(+), 171 deletions(-)

diff --git a/src/compiler/glsl/shader_cache.cpp 
b/src/compiler/glsl/shader_cache.cpp
index f3c7a57699..ca90cfde35 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -74,177 +74,6 @@ compile_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog) {
}
 }
 
-static void
-get_struct_type_field_and_pointer_sizes(size_t *s_field_size,
-size_t *s_field_ptrs)
-{
-   *s_field_size = sizeof(glsl_struct_field);
-   *s_field_ptrs =
- sizeof(((glsl_struct_field *)0)->type) +
- sizeof(((glsl_struct_field *)0)->name);
-}
-
-static void
-encode_type_to_blob(struct blob *blob, const glsl_type *type)
-{
-   uint32_t encoding;
-
-   if (!type) {
-  blob_write_uint32(blob, 0);
-  return;
-   }
-
-   switch (type->base_type) {
-   case GLSL_TYPE_UINT:
-   case GLSL_TYPE_INT:
-   case GLSL_TYPE_FLOAT:
-   case GLSL_TYPE_BOOL:
-   case GLSL_TYPE_DOUBLE:
-   case GLSL_TYPE_UINT64:
-   case GLSL_TYPE_INT64:
-  encoding = (type->base_type << 24) |
- (type->vector_elements << 4) |
- (type->matrix_columns);
-  break;
-   case GLSL_TYPE_SAMPLER:
-  encoding = (type->base_type) << 24 |
- (type->sampler_dimensionality << 4) |
- (type->sampler_shadow << 3) |
- (type->sampler_array << 2) |
- (type->sampled_type);
-  break;
-   case GLSL_TYPE_SUBROUTINE:
-  encoding = type->base_type << 24;
-  blob_write_uint32(blob, encoding);
-  blob_write_string(blob, type->name);
-  return;
-   case GLSL_TYPE_IMAGE:
-  encoding = (type->base_type) << 24 |
- (type->sampler_dimensionality << 3) |
- (type->sampler_array << 2) |
- (type->sampled_type);
-  break;
-   case GLSL_TYPE_ATOMIC_UINT:
-  encoding = (type->base_type << 24);
-  break;
-   case GLSL_TYPE_ARRAY:
-  blob_write_uint32(blob, (type->base_type) << 24);
-  blob_write_uint32(blob, type->length);
-  encode_type_to_blob(blob, type->fields.array);
-  return;
-   case GLSL_TYPE_STRUCT:
-   case GLSL_TYPE_INTERFACE:
-  blob_write_uint32(blob, (type->base_type) << 24);
-  blob_write_string(blob, type->name);
-  blob_write_uint32(blob, type->length);
-
-  size_t s_field_size, s_field_ptrs;
-  get_struct_type_field_and_pointer_sizes(_field_size, _field_ptrs);
-
-  for (unsigned i = 0; i < type->length; i++) {
- encode_type_to_blob(blob, type->fields.structure[i].type);
- blob_write_string(blob, type->fields.structure[i].name);
-
- /* Write the struct field skipping the pointers */
- blob_write_bytes(blob,
-  ((char *)>fields.structure[i]) + s_field_ptrs,
-  s_field_size - s_field_ptrs);
-  }
-
-  if (type->is_interface()) {
- blob_write_uint32(blob, type->interface_packing);
- blob_write_uint32(blob, type->interface_row_major);
-  }
-  return;
-   case GLSL_TYPE_VOID:
-   case GLSL_TYPE_ERROR:
-   default:
-  assert(!"Cannot encode type!");
-  encoding = 0;
-  break;
-   }
-
-   blob_write_uint32(blob, encoding);
-}
-
-static const glsl_type *
-decode_type_from_blob(struct blob_reader *blob)
-{
-   uint32_t u = blob_read_uint32(blob);
-
-   if (u == 0) {
-  return NULL;
-   }
-
-   glsl_base_type base_type = (glsl_base_type) (u >> 24);
-
-   switch (base_type) {
-   case GLSL_TYPE_UINT:
-   case GLSL_TYPE_INT:
-   case GLSL_TYPE_FLOAT:
-   case GLSL_TYPE_BOOL:
-   case GLSL_TYPE_DOUBLE:
-   case GLSL_TYPE_UINT64:
-   case GLSL_TYPE_INT64:
-  return glsl_type::get_instance(base_type, (u >> 4) & 0x0f, u & 0x0f);
-   case GLSL_TYPE_SAMPLER:
-  return glsl_type::get_sampler_instance((enum glsl_sampler_dim) ((u >> 4) 
& 0x07),
- (u >> 3) & 0x01,
- (u >> 2) & 0x01,
- (glsl_base_type) ((u >> 0) & 
0x03));
-   case GLSL_TYPE_SUBROUTINE:
-  return glsl_type::get_subroutine_instance(blob_read_string(blob));
-   case GLSL_TYPE_IMAGE:
-  return glsl_type::get_image_instance((enum glsl_sampler_dim) ((u >> 3) & 
0x07),
- (u >> 2) & 0x01,
- (glsl_base_type) ((u >> 0) & 
0x03));
-   case GLSL_TYPE_ATOMIC_UINT:
-  return glsl_type::atomic_uint_type;
-   case GLSL_TYPE_ARRAY: {
-  unsigned length = blob_read_uint32(blob);
-  return glsl_type::get_array_instance(decode_type_from_blob(blob),
-

[Mesa-dev] [PATCH v2 05/32] glsl: Zero per_vertex_accumulator::fields for valgrind & nir_serialize

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/compiler/glsl/builtin_variables.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/glsl/builtin_variables.cpp 
b/src/compiler/glsl/builtin_variables.cpp
index ea2d897cc8..d3cf12475b 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -318,6 +318,7 @@ per_vertex_accumulator::per_vertex_accumulator()
: fields(),
  num_fields(0)
 {
+   memset(fields, 0, sizeof(fields));
 }
 
 
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 07/32] intel/nir: Zero local index const struct for valgrind & nir_serialize

[Jordan Justen]

Signed-off-by: Jordan Justen 
---
 src/intel/compiler/brw_nir_lower_cs_intrinsics.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c 
b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
index f9322654e7..d27727624c 100644
--- a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
+++ b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
@@ -116,6 +116,7 @@ lower_cs_intrinsics_convert_block(struct 
lower_intrinsics_state *state,
  nir_ssa_def *local_index = nir_load_local_invocation_index(b);
 
  nir_const_value uvec3;
+ memset(, 0, sizeof(uvec3));
  uvec3.u32[0] = 1;
  uvec3.u32[1] = size[0];
  uvec3.u32[2] = size[0] * size[1];
-- 
2.15.0.rc0

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[Mesa-dev] [PATCH v2 02/32] nir: Get rid of nir_shader::stage

[Jordan Justen]

From: Jason Ekstrand 

It's redundant with nir_shader::info::stage.
---
 src/amd/common/ac_nir_to_llvm.c| 30 ++---
 src/amd/common/ac_shader_info.c|  2 +-
 src/amd/vulkan/radv_shader.c   |  4 +-
 src/compiler/glsl/glsl_to_nir.cpp  | 10 ++---
 src/compiler/nir/nir.c | 16 ---
 src/compiler/nir/nir.h |  3 --
 src/compiler/nir/nir_clone.c   |  2 +-
 src/compiler/nir/nir_gather_info.c | 14 +++---
 src/compiler/nir/nir_linking_helpers.c | 14 +++---
 src/compiler/nir/nir_lower_alpha_test.c|  2 +-
 src/compiler/nir/nir_lower_atomics.c   |  2 +-
 src/compiler/nir/nir_lower_bitmap.c|  2 +-
 src/compiler/nir/nir_lower_clamp_color_outputs.c   |  2 +-
 .../nir/nir_lower_clip_cull_distance_arrays.c  |  8 ++--
 src/compiler/nir/nir_lower_drawpixels.c|  2 +-
 src/compiler/nir/nir_lower_io.c|  4 +-
 src/compiler/nir/nir_lower_io_to_temporaries.c |  4 +-
 src/compiler/nir/nir_lower_io_types.c  |  2 +-
 src/compiler/nir/nir_lower_samplers.c  |  3 +-
 src/compiler/nir/nir_lower_samplers_as_deref.c |  2 +-
 src/compiler/nir/nir_lower_two_sided_color.c   |  2 +-
 src/compiler/nir/nir_lower_wpos_center.c   |  2 +-
 src/compiler/nir/nir_lower_wpos_ytransform.c   |  2 +-
 src/compiler/nir/nir_print.c   |  6 +--
 src/compiler/nir/nir_validate.c|  2 +-
 src/compiler/spirv/spirv_to_nir.c  | 52 +++---
 src/compiler/spirv/vtn_variables.c | 16 +++
 src/gallium/auxiliary/nir/tgsi_to_nir.c|  2 +-
 src/gallium/drivers/freedreno/ir3/ir3_cmdline.c|  4 +-
 src/gallium/drivers/freedreno/ir3/ir3_nir.c|  4 +-
 src/gallium/drivers/radeonsi/si_shader_nir.c   | 22 -
 src/gallium/drivers/vc4/vc4_program.c  |  2 +-
 src/intel/blorp/blorp_priv.h   |  2 +-
 src/intel/compiler/brw_nir.c   | 24 +-
 src/intel/compiler/brw_nir_analyze_ubo_ranges.c|  2 +-
 src/intel/compiler/brw_nir_lower_cs_intrinsics.c   |  2 +-
 src/intel/compiler/brw_nir_tcs_workarounds.c   |  2 +-
 src/intel/compiler/brw_shader.cpp  |  2 +-
 src/intel/compiler/brw_vec4_generator.cpp  | 10 ++---
 src/intel/vulkan/anv_nir_apply_pipeline_layout.c   | 13 +++---
 src/intel/vulkan/anv_nir_lower_input_attachments.c |  2 +-
 src/intel/vulkan/anv_nir_lower_multiview.c | 14 +++---
 src/intel/vulkan/anv_pipeline.c|  2 +-
 src/mesa/drivers/dri/i965/brw_link.cpp |  6 ++-
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp |  4 +-
 src/mesa/state_tracker/st_glsl_to_nir.cpp  | 10 ++---
 46 files changed, 172 insertions(+), 167 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3ba3ebf051..4e0a6f7aaa 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6247,7 +6247,7 @@ static unsigned
 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
  const struct nir_shader *nir)
 {
-   switch (nir->stage) {
+   switch (nir->info.stage) {
case MESA_SHADER_TESS_CTRL:
return chip_class >= CIK ? 128 : 64;
case MESA_SHADER_GEOMETRY:
@@ -6277,7 +6277,7 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct 
ac_shader_abi *abi,
if (nctx)
nctx->nir = 
 
-   ctx.stage = nir->stage;
+   ctx.stage = nir->info.stage;
 
ctx.main_function = 
LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
 
@@ -6295,7 +6295,7 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct 
ac_shader_abi *abi,
 
setup_locals(, func);
 
-   if (nir->stage == MESA_SHADER_COMPUTE)
+   if (nir->info.stage == MESA_SHADER_COMPUTE)
setup_shared(, nir);
 
visit_cf_list(, >impl->body);
@@ -6345,7 +6345,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 
ctx.builder = LLVMCreateBuilderInContext(ctx.context);
ctx.ac.builder = ctx.builder;
-   ctx.stage = nir->stage;
+   ctx.stage = nir->info.stage;
ctx.max_workgroup_size = 
ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
 
for (i = 0; i < AC_UD_MAX_SETS; i++)
@@ -6355,18 +6355,18 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 
create_function();
 
-   if (nir->stage == MESA_SHADER_GEOMETRY) {
+   if (nir->info.stage == MESA_SHADER_GEOMETRY) {
ctx.gs_next_vertex = ac_build_alloca(, ctx.i32, 
"gs_next_vertex");
 
ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
-   } else if (nir->stage == MESA_SHADER_TESS_EVAL) 

[Mesa-dev] [PATCH v2 00/32] i965 disk shader cache

[Jordan Justen]

git://people.freedesktop.org/~jljusten/mesa i965-shader-cache-v2

The series adds support for a disk shader cache for i965, but it does
not enable it by default. To enable the i965 shader cache you need to
set the environment variable MESA_GLSL_CACHE_DISABLE=0.

v2:

 * Fallback now uses Connor & Jason's nir serialization patch. This
   simplified the fallback code considerably.

 * Reworked uniform handling based on Jason's new uniform handling. We
   no longer have to use pointer magic, which simplified the push/pull
   constant save/restore.

 * Patches 1 - 12 are for nir serialization

Carl Worth (1):
  intel/compiler: add new field for storing program size

Connor Abbott (2):
  glsl: move shader_cache type handling to glsl_types
  nir: add serialization and deserialization

Jason Ekstrand (4):
  nir: Get rid of nir_shader::stage
  nir/intrinsics: Set the correct num_indices for load_output
  compiler/types: Support [de]serializing void types
  nir: Add hooks for testing serialization

Jordan Justen (19):
  glsl: Zero per_vertex_accumulator::fields for valgrind & nir_serialize
  nir: Zero local_size const struct for valgrind & nir_serialize
  intel/nir: Zero local index const struct for valgrind & nir_serialize
  nir: Zero nir_load_const_instr::value for valgrind & nir_serialize
  glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize
  glsl_to_nir: Zero nir_constant in constant_copy for valgrind &
nir_serialize
  main: Add nir serialization fields to gl_program
  glsl/shader_cache: Save and restore serialized nir in gl_program
  i965/link: Serialize program to nir after linking for shader cache
  i965: Don't rely on nir for uses_texture_gather
  i965: Add shader cache support for compute
  i965: add cache fallback support using serialized nir
  i965: Don't link when the program was found in the disk cache
  i965: Initialize sha1 hash of dri config options
  glsl/shader_cache: Save fs (BlendSupport) metadata
  disk_cache: Fix issue reading GLSL metadata
  dri drivers: Always add the sha1 build-id
  i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false
  disk_cache: Add support for MESA_GLSL_CACHE_TIMESTAMP in debug builds

Timothy Arceri (6):
  i965: add initial implementation of on disk shader cache
  i965: Add shader cache support for vertex and fragment stages
  i965: add shader cache support for geometry shaders
  i965: add shader cache support for tess stages
  mesa/glsl: add api_enabled flag to gl_transform_feedback_info
  i965: add support for cached shaders with xfb qualifiers

 src/amd/common/ac_nir_to_llvm.c|   30 +-
 src/amd/common/ac_shader_info.c|2 +-
 src/amd/vulkan/radv_shader.c   |4 +-
 src/compiler/Makefile.sources  |2 +
 src/compiler/glsl/builtin_variables.cpp|1 +
 src/compiler/glsl/glsl_to_nir.cpp  |   14 +-
 src/compiler/glsl/link_varyings.cpp|5 +-
 src/compiler/glsl/shader_cache.cpp |  193 +---
 src/compiler/glsl_types.cpp|  174 +++
 src/compiler/glsl_types.h  |7 +
 src/compiler/nir/meson.build   |2 +
 src/compiler/nir/nir.c |   17 +-
 src/compiler/nir/nir.h |   20 +-
 src/compiler/nir/nir_clone.c   |2 +-
 src/compiler/nir/nir_gather_info.c |   14 +-
 src/compiler/nir/nir_intrinsics.h  |2 +-
 src/compiler/nir/nir_linking_helpers.c |   14 +-
 src/compiler/nir/nir_lower_alpha_test.c|2 +-
 src/compiler/nir/nir_lower_atomics.c   |2 +-
 src/compiler/nir/nir_lower_bitmap.c|2 +-
 src/compiler/nir/nir_lower_clamp_color_outputs.c   |2 +-
 .../nir/nir_lower_clip_cull_distance_arrays.c  |8 +-
 src/compiler/nir/nir_lower_drawpixels.c|2 +-
 src/compiler/nir/nir_lower_io.c|4 +-
 src/compiler/nir/nir_lower_io_to_temporaries.c |4 +-
 src/compiler/nir/nir_lower_io_types.c  |2 +-
 src/compiler/nir/nir_lower_samplers.c  |3 +-
 src/compiler/nir/nir_lower_samplers_as_deref.c |2 +-
 src/compiler/nir/nir_lower_system_values.c |1 +
 src/compiler/nir/nir_lower_two_sided_color.c   |2 +-
 src/compiler/nir/nir_lower_wpos_center.c   |2 +-
 src/compiler/nir/nir_lower_wpos_ytransform.c   |2 +-
 src/compiler/nir/nir_print.c   |6 +-
 src/compiler/nir/nir_serialize.c   | 1220 
 src/compiler/nir/nir_serialize.h   |   43 +
 src/compiler/nir/nir_validate.c|2 +-
 src/compiler/spirv/spirv_to_nir.c  |   52 +-
 src/compiler/spirv/vtn_variables.c |   16 +-
 src/gallium/auxiliary/nir/tgsi_to_nir.c|2 

[Mesa-dev] [PATCH v2 19/32] i965: Add shader cache support for vertex and fragment stages

[Jordan Justen]

From: Timothy Arceri 

This enables the cache on vertex and fragment shaders only.

v2:
 * Use MAYBE_UNUSED. (Matt)

[jordan.l.jus...@intel.com: reword subject]
[jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen 
---
 src/mesa/drivers/dri/i965/brw_state_upload.c |  2 ++
 src/mesa/drivers/dri/i965/brw_vs.c   | 20 +---
 src/mesa/drivers/dri/i965/brw_wm.c   | 24 +++-
 3 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 16f44d03bb..1ee99648cb 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -442,6 +442,8 @@ brw_upload_programs(struct brw_context *brw,
  brw_upload_clip_prog(brw);
  brw_upload_sf_prog(brw);
   }
+
+  brw_disk_cache_write_program(brw);
} else if (pipeline == BRW_COMPUTE_PIPELINE) {
   brw_upload_cs_prog(brw);
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c 
b/src/mesa/drivers/dri/i965/brw_vs.c
index fb5ea4e7ed..49855de127 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -344,13 +344,19 @@ brw_upload_vs_prog(struct brw_context *brw)
 
brw_vs_populate_key(brw, );
 
-   if (!brw_search_cache(>cache, BRW_CACHE_VS_PROG,
-, sizeof(key),
->vs.base.prog_offset, >vs.base.prog_data)) {
-  bool success = brw_codegen_vs_prog(brw, vp, );
-  (void) success;
-  assert(success);
-   }
+   if (brw_search_cache(>cache, BRW_CACHE_VS_PROG,
+, sizeof(key),
+>vs.base.prog_offset, >vs.base.prog_data))
+  return;
+
+   if (brw_disk_cache_upload_program(brw, MESA_SHADER_VERTEX))
+  return;
+
+   vp = (struct brw_program *) brw->programs[MESA_SHADER_VERTEX];
+   vp->id = key.program_string_id;
+
+   MAYBE_UNUSED bool success = brw_codegen_vs_prog(brw, vp, );
+   assert(success);
 }
 
 bool
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index e511f0f70b..ca0738c895 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -588,15 +588,21 @@ brw_upload_wm_prog(struct brw_context *brw)
 
brw_wm_populate_key(brw, );
 
-   if (!brw_search_cache(>cache, BRW_CACHE_FS_PROG,
- , sizeof(key),
- >wm.base.prog_offset,
- >wm.base.prog_data)) {
-  bool success = brw_codegen_wm_prog(brw, fp, ,
- >vue_map_geom_out);
-  (void) success;
-  assert(success);
-   }
+   if (brw_search_cache(>cache, BRW_CACHE_FS_PROG,
+, sizeof(key),
+>wm.base.prog_offset,
+>wm.base.prog_data))
+  return;
+
+   if (brw_disk_cache_upload_program(brw, MESA_SHADER_FRAGMENT))
+  return;
+
+   fp = (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT];
+   fp->id = key.program_string_id;
+
+   MAYBE_UNUSED bool success = brw_codegen_wm_prog(brw, fp, ,
+   >vue_map_geom_out);
+   assert(success);
 }
 
 bool
-- 
2.15.0.rc0

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Re: [Mesa-dev] [PATCH 04/21] intel: Rewrite the world of push/pull params

[Matt Turner]

On Fri, Sep 29, 2017 at 2:25 PM, Jason Ekstrand  wrote:
> diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c 
> b/src/mesa/drivers/dri/i965/gen6_constant_state.c
> index b2e357f..93a12c7 100644
> --- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
> @@ -24,21 +24,84 @@
>  #include "brw_context.h"
>  #include "brw_state.h"
>  #include "brw_defines.h"
> +#include "brw_program.h"
>  #include "intel_batchbuffer.h"
>  #include "intel_buffer_objects.h"
>  #include "program/prog_parameter.h"
>
> +static uint32_t
> +f_as_u32(float f)
> +{
> +   return *(uint32_t *)
> +}

PSA: This breaks C's aliasing rules and is not allowed in Mesa. GCC
warns about this, at least when optimizing.

I've pushed a trivial patch that uses a union instead:

-   return *(uint32_t *)
+   union fi fi = { .f = f };
+   return fi.ui;
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Re: [Mesa-dev] [PATCH 3/4] meson: build libEGL

[Dylan Baker]

Quoting Eric Engestrom (2017-10-18 17:25:05)
> On Wednesday, 2017-10-18 23:56:00 +, Dylan Baker wrote:
> > This is based heavily on Daniel Stone's work for the same, rebased on
> > master and with a number of TODO's fixed.
> > 
> > This does not implement glvnd (which is coming in a later patch)
> > 
> > Meson builds egl slightly differently than autotools, namely it doesn't
> > build an intermediate shared library. It doesn't do this because meson
> > doesn't have problems with the name of the library being dynamically
> > generated, so the glvnd and non-glvnd code can follow the same path.
> > 
> > Signed-off-by: Dylan Baker 
> > ---
> >  include/meson.build|   8 ++
> >  meson.build|  81 ++--
> >  meson_options.txt  |   9 +-
> >  src/egl/meson.build| 144 
> > +
> >  src/egl/wayland/wayland-drm/meson.build|  14 ++
> >  .../{wayland-drm => wayland-egl}/meson.build   |  29 +++--
> >  src/gbm/meson.build|  12 +-
> >  src/glx/meson.build|  22 
> >  src/meson.build|   7 +-
> >  9 files changed, 281 insertions(+), 45 deletions(-)
> >  create mode 100644 src/egl/meson.build
> >  copy src/egl/wayland/{wayland-drm => wayland-egl}/meson.build (66%)
> > 
> > diff --git a/include/meson.build b/include/meson.build
> > index e33a8569d76..88e66a1a8f4 100644
> > --- a/include/meson.build
> > +++ b/include/meson.build
> > @@ -58,3 +58,11 @@ endif
> >  if with_osmesa
> >install_headers('GL/osmesa.h', subdir : 'GL')
> >  endif
> > +
> > +if with_egl
> > +  install_headers(
> > +'EGL/eglext.h', 'EGL/egl.h', 'EGL/eglextchromium.h', 
> > 'EGL/eglmesaext.h',
> > +'EGL/eglplatform.h',
> > +subdir : 'EGL',
> > +  )
> > +endif
> > diff --git a/meson.build b/meson.build
> > index 13d9e400ba7..9eef48340d7 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -130,16 +130,20 @@ endif
> >  # TODO: other OSes
> >  with_dri_platform = 'drm'
> >  
> > -# TODO: there are more platforms required for non-vulkan drivers
> > +# TODO: android platform
> >  with_platform_wayland = false
> >  with_platform_x11 = false
> >  with_platform_drm = false
> > +with_platform_surfaceless = false
> > +egl_native_platform = ''
> >  _platforms = get_option('platforms')
> >  if _platforms != ''
> >_split = _platforms.split(',')
> >with_platform_x11 = _split.contains('x11')
> >with_platform_wayland = _split.contains('wayland')
> >with_platform_drm = _split.contains('drm')
> > +  with_platform_surfaceless = _split.contains('surfaceless')
> > +  egl_native_platform = _split[0]
> >  endif
> 
> I quite liked daniels' `foreach if/elif/else` structure, it had the
> added advantage of being able to reject invalid platforms instead of
> silently ignoring them.

Well, I keep hoping that this will land and we can switch to it:
https://github.com/mesonbuild/meson/pull/2390
And this approach requires no changes if/when that happens, but I guess I don't
have a problem with the loop either.

> 
> >  
> >  with_gbm = get_option('gbm')
> > @@ -154,6 +158,27 @@ else
> >with_gbm = false
> >  endif
> >  
> > +with_egl = get_option('egl')
> > +if with_egl == 'auto'
> > +  with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
> 
> I don't like the var name reuse, once as a string, then as a bool.
> How about `_egl = get_option('egl')`, as with `_platforms` above?
> 
> I'll have another look tomorrow, but I think other than that this patch
> is good (not giving my r-b just yet though).

I can change that.

> 
> > +elif with_egl == 'yes'
> > +  if not with_dri
> > +error('EGL requires dri')
> > +  elif not with_shared_glapi
> > +error('EGL requires shared-glapi')
> > +  elif egl_native_platform == ''
> > +error('No platforms specified, consider -Dplatforms=drm,x11 at least')
> > +  endif
> > +  with_egl = true
> > +else
> > +  with_egl = false
> > +endif
> > +
> > +# TODO: or virgl
> > +if with_egl and with_gallium_radeonsi and not (with_platform_drm or 
> > with_platform_surfaceless)
> > +  error('RadeonSI requires drm or surfaceless platform when using EGL')
> > +endif
> > +
> >  pre_args += '-DGLX_USE_TLS'
> >  with_glx = get_option('glx')
> >  if with_glx != 'disabled'
> > @@ -228,7 +253,7 @@ if with_any_vk and (with_platform_x11 and not with_dri3)
> >error('Vulkan drivers require dri3 for X11 support')
> >  endif
> >  if with_dri or with_gallium
> > -  if with_glx == 'disabled' # TODO: or egl
> > +  if with_glx == 'disabled' and not with_egl
> >  error('building dri or gallium drivers require at least one window 
> > system')
> >endif
> >  endif
> > @@ -250,6 +275,7 @@ if _drivers != ''
> >  with_gallium_omx or with_gallium_va)
> >  endif
> >  
> > 

[Mesa-dev] [PATCH] radv: fix CLEAR_STATE packet length.

[Dave Airlie]

From: Dave Airlie 

Looking at shader traces I noticed some registers were missing,
one of them was being eaten by the wrong clear state length.

Fixes: 4f42ea4dc (radv: use CLEAR_STATE for initializing some registers)
Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/si_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 1e8b43d4fa8..690f30b6abc 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -341,7 +341,7 @@ si_emit_config(struct radv_physical_device *physical_device,
radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
 
if (physical_device->has_clear_state) {
-   radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 1, 0));
+   radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
radeon_emit(cs, 0);
}
 
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 2/2] drirc: Group a few games in the glthread whitelist together.

[Marek Olšák]

I pushed the series, thanks!

Marek

On Mon, Oct 16, 2017 at 12:22 AM, Darren Salt  wrote:
> ---
>  src/util/drirc | 27 +--
>  1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/src/util/drirc b/src/util/drirc
> index 3cf3d8dc69..39ac3c858c 100644
> --- a/src/util/drirc
> +++ b/src/util/drirc
> @@ -166,27 +166,37 @@ TODO: document the other workarounds.
>  
>  
>  
> -
> -
> -
> +
>  
>  
>  
> +
>  
>  
>  
> +
>  
>  
>  
> +
> +
> +
> +
>  
>  
>  
> +
>  
>  
>  
> +
>   executable="abbeycore_steam">
>  
>  
> +
> +
> +
> +
>   executable="SaintsRow3.i386">
>  
>  
> @@ -196,39 +206,44 @@ TODO: document the other workarounds.
>   executable="SaintsRow4GooH.i386">
>  
>  
> +
>   executable="CivBE">
>  
>  
> +
>  
>  
>  
> +
>  
>  
>  
>  
>  
>  
> +
>  
>  
>  
>  
>  
>  
> +
>  
>  
>  
> +
>  
>  
>  
> -
> -
> -
>  
>  
>  
> +
>  
>  
>  
> +
>   executable="specops.i386">
>  
>  
> --
> 2.11.0
>
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH 14/16] radv: Add GFX9 HS emitting code.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_cmd_buffer.c | 21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3e31fbafd34..a746777ca40 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -711,11 +711,22 @@ radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
radv_emit_prefetch(cmd_buffer, va, shader->code_size);
 
-   radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
-   radeon_emit(cmd_buffer->cs, va >> 8);
-   radeon_emit(cmd_buffer->cs, va >> 40);
-   radeon_emit(cmd_buffer->cs, shader->rsrc1);
-   radeon_emit(cmd_buffer->cs, shader->rsrc2);
+   if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+   radeon_set_sh_reg_seq(cmd_buffer->cs, 
R_00B410_SPI_SHADER_PGM_LO_LS, 2);
+   radeon_emit(cmd_buffer->cs, va >> 8);
+   radeon_emit(cmd_buffer->cs, va >> 40);
+
+   radeon_set_sh_reg_seq(cmd_buffer->cs, 
R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
+   radeon_emit(cmd_buffer->cs, shader->rsrc1);
+   radeon_emit(cmd_buffer->cs, shader->rsrc2 |
+   
S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
+   } else {
+   radeon_set_sh_reg_seq(cmd_buffer->cs, 
R_00B420_SPI_SHADER_PGM_LO_HS, 4);
+   radeon_emit(cmd_buffer->cs, va >> 8);
+   radeon_emit(cmd_buffer->cs, va >> 40);
+   radeon_emit(cmd_buffer->cs, shader->rsrc1);
+   radeon_emit(cmd_buffer->cs, shader->rsrc2);
+   }
 }
 
 static void
-- 
2.14.2

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[Mesa-dev] [PATCH 13/16] radv: Remove remaining hard coded references to VS.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_cmd_buffer.c | 19 ++-
 src/amd/vulkan/radv_pipeline.c   | 14 --
 src/amd/vulkan/radv_private.h|  2 ++
 3 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 78dca2a9790..3e31fbafd34 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -493,6 +493,14 @@ radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
  gl_shader_stage stage,
  int idx)
 {
+   if (stage == MESA_SHADER_VERTEX) {
+   if (pipeline->shaders[MESA_SHADER_VERTEX])
+   return 
>shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
+   if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+   return 
>shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
+   if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+   return 
>shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
+   }
return >shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 }
 
@@ -716,9 +724,12 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
 {
struct radv_shader_variant *vs;
 
-   assert (pipeline->shaders[MESA_SHADER_VERTEX]);
+   radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 
pipeline->graphics.vgt_primitiveid_en);
 
+   /* Skip shaders merged into HS/GS */
vs = pipeline->shaders[MESA_SHADER_VERTEX];
+   if (!vs)
+   return;
 
if (vs->info.vs.as_ls)
radv_emit_hw_ls(cmd_buffer, vs);
@@ -726,8 +737,6 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
radv_emit_hw_es(cmd_buffer, vs, >info.vs.es_info);
else
radv_emit_hw_vs(cmd_buffer, pipeline, vs, >info.vs.outinfo);
-
-   radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 
pipeline->graphics.vgt_primitiveid_en);
 }
 
 
@@ -1698,7 +1707,7 @@ radv_cmd_buffer_update_vertex_descriptors(struct 
radv_cmd_buffer *cmd_buffer)
 
if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline 
|| cmd_buffer->state.vb_dirty) &&
cmd_buffer->state.pipeline->vertex_elements.count &&
-   
cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers)
 {
+   
radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers)
 {
struct radv_vertex_elements_info *velems = 
_buffer->state.pipeline->vertex_elements;
unsigned vb_offset;
void *vb_ptr;
@@ -2990,7 +2999,7 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer 
*cmd_buffer,
struct radeon_winsys_cs *cs = cmd_buffer->cs;
unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
  : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
-   bool draw_id_enable = 
cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
+   bool draw_id_enable = 
radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
assert(base_reg);
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 16e4b307e65..4369c3a6b1b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1207,6 +1207,16 @@ static void si_multiwave_lds_size_workaround(struct 
radv_device *device,
*lds_size = MAX2(*lds_size, 8);
 }
 
+struct radv_shader_variant *
+radv_get_vertex_shader(struct radv_pipeline *pipeline)
+{
+   if (pipeline->shaders[MESA_SHADER_VERTEX])
+   return pipeline->shaders[MESA_SHADER_VERTEX];
+   if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+   return pipeline->shaders[MESA_SHADER_TESS_CTRL];
+   return pipeline->shaders[MESA_SHADER_GEOMETRY];
+}
+
 static void
 calculate_tess_state(struct radv_pipeline *pipeline,
 const VkGraphicsPipelineCreateInfo *pCreateInfo)
@@ -1223,7 +1233,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
 
/* This calculates how shader inputs and outputs among VS, TCS, and TES
 * are laid out in LDS. */
-   num_tcs_inputs = 
util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
+   num_tcs_inputs = 
util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
 
num_tcs_outputs = 
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
 //tcs->outputs_written
num_tcs_output_cp = 
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS 
VERTICES OUT
@@ -2024,7 +2034,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
if (loc->sgpr_idx != -1) {

[Mesa-dev] [PATCH 15/16] radv: Set correct registers for merged shader rings.

[Bas Nieuwenhuizen]

We need different regs to end up in s0/s1.
---
 src/amd/vulkan/radv_device.c | 36 
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index fd705fe726d..125498809ec 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1580,19 +1580,31 @@ radv_get_preamble_cs(struct radv_queue *queue,
}
 
if (descriptor_bo) {
-   uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
-  R_00B130_SPI_SHADER_USER_DATA_VS_0,
-  R_00B230_SPI_SHADER_USER_DATA_GS_0,
-  R_00B330_SPI_SHADER_USER_DATA_ES_0,
-  R_00B430_SPI_SHADER_USER_DATA_HS_0,
-  R_00B530_SPI_SHADER_USER_DATA_LS_0};
-
uint64_t va = radv_buffer_get_va(descriptor_bo);
-
-   for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   if (queue->device->physical_device->rad_info.chip_class 
>= GFX9) {
+   uint32_t regs[] = 
{R_00B030_SPI_SHADER_USER_DATA_PS_0,
+   
R_00B130_SPI_SHADER_USER_DATA_VS_0,
+   
R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
+   
R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
+
+   for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
+   radeon_set_sh_reg_seq(cs, regs[i], 2);
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+   }
+   } else {
+   uint32_t regs[] = 
{R_00B030_SPI_SHADER_USER_DATA_PS_0,
+   
R_00B130_SPI_SHADER_USER_DATA_VS_0,
+   
R_00B230_SPI_SHADER_USER_DATA_GS_0,
+   
R_00B330_SPI_SHADER_USER_DATA_ES_0,
+   
R_00B430_SPI_SHADER_USER_DATA_HS_0,
+   
R_00B530_SPI_SHADER_USER_DATA_LS_0};
+
+   for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
+   radeon_set_sh_reg_seq(cs, regs[i], 2);
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+   }
}
}
 
-- 
2.14.2

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[Mesa-dev] [PATCH 12/16] radv: Update GFX9 user data regs for GS/tess.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_cmd_buffer.c | 14 +++---
 src/amd/vulkan/radv_pipeline.c   |  2 +-
 src/amd/vulkan/radv_shader.c | 19 +++
 src/amd/vulkan/radv_shader.h |  4 ++--
 4 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 901d382f968..78dca2a9790 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -503,7 +503,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer 
*cmd_buffer,
   int idx, uint64_t va)
 {
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, 
idx);
-   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
if (loc->sgpr_idx == -1)
return;
assert(loc->num_sgprs == 2);
@@ -545,7 +545,7 @@ radv_update_multisample_state(struct radv_cmd_buffer 
*cmd_buffer,
if 
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
uint32_t offset;
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, 
MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
if (loc->sgpr_idx == -1)
return;
assert(loc->num_sgprs == 1);
@@ -765,7 +765,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, 
AC_UD_TCS_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
assert(loc->num_sgprs == 4);
assert(!loc->indirect);
radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx 
* 4, 4);
@@ -778,7 +778,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, 
AC_UD_TES_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
 
@@ -788,7 +788,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, 
AC_UD_VS_LS_TCS_IN_LAYOUT);
if (loc->sgpr_idx != -1) {
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
 
@@ -1488,7 +1488,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer 
*cmd_buffer,
   gl_shader_stage stage)
 {
struct ac_userdata_info *desc_set_loc = 
>shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
-   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
 
if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
return;
@@ -2859,7 +2859,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer 
*cmd_buffer, unsigned in
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, 
stage, AC_UD_VIEW_INDEX);
if (loc->sgpr_idx == 

[Mesa-dev] [PATCH 16/16] radv: Modify rsrc1/rsrc2 generation for merged tess.

[Bas Nieuwenhuizen]

No OC_LDS_EN for HS, and the included LS vgpr_comp_cnt is at
a different offset.
---
 src/amd/vulkan/radv_shader.c | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index a7836543998..a86ba2a01c0 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -340,12 +340,21 @@ radv_fill_shader_variant(struct radv_device *device,
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
S_00B12C_SCRATCH_EN(scratch_enabled);
 
+   variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
+   S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
+   S_00B848_DX10_CLAMP(1) |
+   S_00B848_FLOAT_MODE(variant->config.float_mode);
+
switch (stage) {
case MESA_SHADER_TESS_EVAL:
vgpr_comp_cnt = 3;
-   /* fallthrough */
+   variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+   break;
case MESA_SHADER_TESS_CTRL:
-   variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
+   if (device->physical_device->rad_info.chip_class >= GFX9)
+   vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+   else
+   variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
break;
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
@@ -365,11 +374,11 @@ radv_fill_shader_variant(struct radv_device *device,
break;
}
 
-   variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
-   S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
-   S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
-   S_00B848_DX10_CLAMP(1) |
-   S_00B848_FLOAT_MODE(variant->config.float_mode);
+   if (device->physical_device->rad_info.chip_class >= GFX9 &&
+   stage == MESA_SHADER_TESS_CTRL)
+   variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
+   else
+   variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 
void *ptr = radv_alloc_shader_memory(device, variant);
memcpy(ptr, binary->code, binary->code_size);
-- 
2.14.2

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[Mesa-dev] [PATCH 09/16] ac/nir: Compile the bodies of multiple shaders.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 133 +---
 1 file changed, 83 insertions(+), 50 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 67945a353e8..cb011bd88bb 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6428,7 +6428,8 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct 
ac_shader_abi *abi,
 
 static
 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
-   struct nir_shader *nir,
+   struct nir_shader *const *shaders,
+   int shader_count,
struct ac_shader_variant_info 
*shader_info,
const struct ac_nir_compiler_options 
*options)
 {
@@ -6441,11 +6442,6 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 
ac_llvm_context_init(, ctx.context, options->chip_class);
ctx.ac.module = ctx.module;
-
-   memset(shader_info, 0, sizeof(*shader_info));
-
-   ac_nir_shader_info_pass(nir, options, _info->info);
-
LLVMSetTarget(ctx.module, options->supports_spill ? 
"amdgcn-mesa-mesa3d" : "amdgcn--");
 
LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
@@ -6455,72 +6451,109 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
LLVMDisposeMessage(data_layout_str);
 
setup_types();
-
ctx.builder = LLVMCreateBuilderInContext(ctx.context);
ctx.ac.builder = ctx.builder;
-   ctx.stage = nir->stage;
-   ctx.max_workgroup_size = 
ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
+
+   memset(shader_info, 0, sizeof(*shader_info));
+
+   for(int i = 0; i < shader_count; ++i)
+   ac_nir_shader_info_pass(shaders[i], options, 
_info->info);
 
for (i = 0; i < AC_UD_MAX_SETS; i++)
shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
for (i = 0; i < AC_UD_MAX_UD; i++)
shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
 
-   create_function(, nir->stage, false, MESA_SHADER_VERTEX);
+   ctx.max_workgroup_size = 
ac_nir_get_max_workgroup_size(ctx.options->chip_class, shaders[0]);
+
+   create_function(, shaders[shader_count - 1]->stage, shader_count >= 
2,
+   shader_count >= 2 ? shaders[shader_count - 2]->stage  : 
MESA_SHADER_VERTEX);
 
-   if (nir->stage == MESA_SHADER_GEOMETRY) {
-   ctx.gs_next_vertex = ac_build_alloca(, ctx.i32, 
"gs_next_vertex");
+   ctx.abi.inputs = [0];
+   ctx.abi.emit_outputs = handle_shader_outputs_post;
+   ctx.abi.load_ssbo = radv_load_ssbo;
+   ctx.abi.load_sampler_desc = radv_get_sampler_desc;
 
-   ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
-   } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
-   ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
-   } else if (nir->stage == MESA_SHADER_VERTEX) {
-   if (shader_info->info.vs.needs_instance_id) {
-   ctx.shader_info->vs.vgpr_comp_cnt =
-   MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
+   for(int i = 0; i < shader_count; ++i) {
+   ctx.stage = shaders[i]->stage;
+   ctx.output_mask = 0;
+   ctx.tess_outputs_written = 0;
+   ctx.num_output_clips = 
shaders[i]->info.clip_distance_array_size;
+   ctx.num_output_culls = 
shaders[i]->info.cull_distance_array_size;
+
+   if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
+   ctx.gs_next_vertex = ac_build_alloca(, ctx.i32, 
"gs_next_vertex");
+
+   ctx.gs_max_out_vertices = 
shaders[i]->info.gs.vertices_out;
+   } else if (shaders[i]->stage == MESA_SHADER_TESS_EVAL) {
+   ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
+   } else if (shaders[i]->stage == MESA_SHADER_VERTEX) {
+   if (shader_info->info.vs.needs_instance_id) {
+   ctx.shader_info->vs.vgpr_comp_cnt =
+   MAX2(3, 
ctx.shader_info->vs.vgpr_comp_cnt);
+   }
+   } else if (shaders[i]->stage == MESA_SHADER_FRAGMENT) {
+   shader_info->fs.can_discard = 
shaders[i]->info.fs.uses_discard;
}
-   } else if (nir->stage == MESA_SHADER_FRAGMENT) {
-   shader_info->fs.can_discard = nir->info.fs.uses_discard;
-   }
 
-   ac_setup_rings();
+   if (i)
+   emit_barrier();
 
-   ctx.num_output_clips = nir->info.clip_distance_array_size;
-   ctx.num_output_culls = nir->info.cull_distance_array_size;
+   ac_setup_rings();
 
-   if (nir->stage == 

[Mesa-dev] [PATCH 10/16] ac/nir: Add LS-HS input VGPR workaround.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cb011bd88bb..242675654d2 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6377,6 +6377,20 @@ ac_nir_get_max_workgroup_size(enum chip_class chip_class,
return max_workgroup_size;
 }
 
+/* Fixup the HW not emitting the TCS regs if there are no HS threads. */
+static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
+{
+   LLVMValueRef count = ac_build_bfe(>ac, ctx->merged_wave_info,
+ LLVMConstInt(ctx->ac.i32, 8, false),
+ LLVMConstInt(ctx->ac.i32, 8, false), 
false);
+   LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
+ LLVMConstInt(ctx->ac.i32, 0, 
false), "");
+   ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->rel_auto_id, ctx->abi.instance_id, "");
+   ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->abi.vertex_id, ctx->vs_prim_id, "");
+   ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->tcs_rel_ids, ctx->rel_auto_id, "");
+   ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->tcs_patch_id, ctx->abi.vertex_id, "");
+}
+
 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
  struct nir_shader *nir, struct nir_to_llvm_context *nctx)
 {
@@ -6474,6 +6488,10 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_ssbo = radv_load_ssbo;
ctx.abi.load_sampler_desc = radv_get_sampler_desc;
 
+   if (ctx.ac.chip_class == GFX9 &&
+   shaders[shader_count - 1]->stage == MESA_SHADER_TESS_CTRL)
+   ac_nir_fixup_ls_hs_input_vgprs();
+
for(int i = 0; i < shader_count; ++i) {
ctx.stage = shaders[i]->stage;
ctx.output_mask = 0;
-- 
2.14.2

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[Mesa-dev] [PATCH 02/16] ac/nir: Add HS calling convention.

[Bas Nieuwenhuizen]

Needed for GFX9 merged shaders.
---
 src/amd/common/ac_nir_to_llvm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3ba3ebf051e..1df97b59a2e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -39,6 +39,7 @@ enum radeon_llvm_calling_convention {
RADEON_LLVM_AMDGPU_GS = 88,
RADEON_LLVM_AMDGPU_PS = 89,
RADEON_LLVM_AMDGPU_CS = 90,
+   RADEON_LLVM_AMDGPU_HS = 93,
 };
 
 #define CONST_ADDR_SPACE 2
@@ -223,13 +224,15 @@ static void set_llvm_calling_convention(LLVMValueRef func,
 
switch (stage) {
case MESA_SHADER_VERTEX:
-   case MESA_SHADER_TESS_CTRL:
case MESA_SHADER_TESS_EVAL:
calling_conv = RADEON_LLVM_AMDGPU_VS;
break;
case MESA_SHADER_GEOMETRY:
calling_conv = RADEON_LLVM_AMDGPU_GS;
break;
+   case MESA_SHADER_TESS_CTRL:
+   calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : 
RADEON_LLVM_AMDGPU_VS;
+   break;
case MESA_SHADER_FRAGMENT:
calling_conv = RADEON_LLVM_AMDGPU_PS;
break;
-- 
2.14.2

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[Mesa-dev] [PATCH 05/16] ac/nir: Make scan_shader_output_decl less dependent on the context.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 31 +--
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 38f47b34e10..f01ca8799b9 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5151,7 +5151,9 @@ static LLVMValueRef si_build_alloca_undef(struct 
ac_llvm_context *ac,
 
 static void
 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
-   struct nir_variable *variable)
+   struct nir_variable *variable,
+   struct nir_shader *shader,
+   gl_shader_stage stage)
 {
int idx = variable->data.location + variable->data.index;
unsigned attrib_count = glsl_count_attribute_slots(variable->type, 
false);
@@ -5160,22 +5162,23 @@ scan_shader_output_decl(struct nir_to_llvm_context *ctx,
variable->data.driver_location = idx * 4;
 
/* tess ctrl has it's own load/store paths for outputs */
-   if (ctx->stage == MESA_SHADER_TESS_CTRL)
+   if (stage == MESA_SHADER_TESS_CTRL)
return;
 
mask_attribs = ((1ull << attrib_count) - 1) << idx;
-   if (ctx->stage == MESA_SHADER_VERTEX ||
-   ctx->stage == MESA_SHADER_TESS_EVAL ||
-   ctx->stage == MESA_SHADER_GEOMETRY) {
+   if (stage == MESA_SHADER_VERTEX ||
+   stage == MESA_SHADER_TESS_EVAL ||
+   stage == MESA_SHADER_GEOMETRY) {
if (idx == VARYING_SLOT_CLIP_DIST0) {
-   int length = ctx->num_output_clips + 
ctx->num_output_culls;
-   if (ctx->stage == MESA_SHADER_VERTEX) {
-   ctx->shader_info->vs.outinfo.clip_dist_mask = 
(1 << ctx->num_output_clips) - 1;
-   ctx->shader_info->vs.outinfo.cull_dist_mask = 
(1 << ctx->num_output_culls) - 1;
+   int length = shader->info.clip_distance_array_size +
+shader->info.cull_distance_array_size;
+   if (stage == MESA_SHADER_VERTEX) {
+   ctx->shader_info->vs.outinfo.clip_dist_mask = 
(1 << shader->info.clip_distance_array_size) - 1;
+   ctx->shader_info->vs.outinfo.cull_dist_mask = 
(1 << shader->info.cull_distance_array_size) - 1;
}
-   if (ctx->stage == MESA_SHADER_TESS_EVAL) {
-   ctx->shader_info->tes.outinfo.clip_dist_mask = 
(1 << ctx->num_output_clips) - 1;
-   ctx->shader_info->tes.outinfo.cull_dist_mask = 
(1 << ctx->num_output_culls) - 1;
+   if (stage == MESA_SHADER_TESS_EVAL) {
+   ctx->shader_info->tes.outinfo.clip_dist_mask = 
(1 << shader->info.clip_distance_array_size) - 1;
+   ctx->shader_info->tes.outinfo.cull_dist_mask = 
(1 << shader->info.cull_distance_array_size) - 1;
}
 
if (length > 4)
@@ -6389,7 +6392,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_sampler_desc = radv_get_sampler_desc;
 
nir_foreach_variable(variable, >outputs)
-   scan_shader_output_decl(, variable);
+   scan_shader_output_decl(, variable, nir, nir->stage);
 
ac_nir_translate(, , nir, );
 
@@ -6687,7 +6690,7 @@ void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
ctx.nir = _ctx;
 
nir_foreach_variable(variable, _shader->outputs) {
-   scan_shader_output_decl(, variable);
+   scan_shader_output_decl(, variable, geom_shader, 
MESA_SHADER_VERTEX);
handle_shader_output_decl(_ctx, geom_shader, variable);
}
 
-- 
2.14.2

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[Mesa-dev] [PATCH 08/16] ac/nir: Expand user SGPR descriptions a bit.

[Bas Nieuwenhuizen]

To prevent VS/TCS collisions in merged shaders.
---
 src/amd/common/ac_nir_to_llvm.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 66d539dec47..360d613d58d 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -103,13 +103,13 @@ enum ac_ud_index {
AC_UD_PS_MAX_UD,
AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
AC_UD_CS_MAX_UD,
-   AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_SHADER_START,
+   AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
AC_UD_GS_MAX_UD,
-   AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
+   AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
AC_UD_TCS_MAX_UD,
AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
AC_UD_TES_MAX_UD,
-   AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
+   AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 };
 
 /* descriptor index into scratch ring offsets */
-- 
2.14.2

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[Mesa-dev] [PATCH 03/16] ac/nir: Change interface to allow multiple source shaders.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 82 ++---
 src/amd/common/ac_nir_to_llvm.h |  3 +-
 src/amd/vulkan/radv_shader.c|  2 +-
 3 files changed, 48 insertions(+), 39 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1df97b59a2e..38f47b34e10 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6540,53 +6540,61 @@ static void ac_compile_llvm_module(LLVMTargetMachineRef 
tm,
 shader_info->num_input_sgprs + 3);
 }
 
+static void
+ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct 
nir_shader *nir, const struct ac_nir_compiler_options *options)
+{
+switch (nir->stage) {
+case MESA_SHADER_COMPUTE:
+for (int i = 0; i < 3; ++i)
+shader_info->cs.block_size[i] = 
nir->info.cs.local_size[i];
+break;
+case MESA_SHADER_FRAGMENT:
+shader_info->fs.early_fragment_test = 
nir->info.fs.early_fragment_tests;
+break;
+case MESA_SHADER_GEOMETRY:
+shader_info->gs.vertices_in = nir->info.gs.vertices_in;
+shader_info->gs.vertices_out = nir->info.gs.vertices_out;
+shader_info->gs.output_prim = nir->info.gs.output_primitive;
+shader_info->gs.invocations = nir->info.gs.invocations;
+break;
+case MESA_SHADER_TESS_EVAL:
+shader_info->tes.primitive_mode = 
nir->info.tess.primitive_mode;
+shader_info->tes.spacing = nir->info.tess.spacing;
+shader_info->tes.ccw = nir->info.tess.ccw;
+shader_info->tes.point_mode = nir->info.tess.point_mode;
+shader_info->tes.as_es = options->key.tes.as_es;
+break;
+case MESA_SHADER_TESS_CTRL:
+shader_info->tcs.tcs_vertices_out = 
nir->info.tess.tcs_vertices_out;
+break;
+case MESA_SHADER_VERTEX:
+shader_info->vs.as_es = options->key.vs.as_es;
+shader_info->vs.as_ls = options->key.vs.as_ls;
+/* in LS mode we need at least 1, invocation id needs 3, 
handled elsewhere */
+if (options->key.vs.as_ls)
+shader_info->vs.vgpr_comp_cnt = MAX2(1, 
shader_info->vs.vgpr_comp_cnt);
+break;
+default:
+break;
+}
+}
+
 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct ac_shader_variant_info *shader_info,
-   struct nir_shader *nir,
+   struct nir_shader *const *nir,
+   int nir_count,
const struct ac_nir_compiler_options *options,
   bool dump_shader)
 {
 
-   LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, 
shader_info,
+   LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir[0], 
shader_info,
 options);
 
-   ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, 
nir->stage, dump_shader, options->supports_spill);
-   switch (nir->stage) {
-   case MESA_SHADER_COMPUTE:
-   for (int i = 0; i < 3; ++i)
-   shader_info->cs.block_size[i] = 
nir->info.cs.local_size[i];
-   break;
-   case MESA_SHADER_FRAGMENT:
-   shader_info->fs.early_fragment_test = 
nir->info.fs.early_fragment_tests;
-   break;
-   case MESA_SHADER_GEOMETRY:
-   shader_info->gs.vertices_in = nir->info.gs.vertices_in;
-   shader_info->gs.vertices_out = nir->info.gs.vertices_out;
-   shader_info->gs.output_prim = nir->info.gs.output_primitive;
-   shader_info->gs.invocations = nir->info.gs.invocations;
-   break;
-   case MESA_SHADER_TESS_EVAL:
-   shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
-   shader_info->tes.spacing = nir->info.tess.spacing;
-   shader_info->tes.ccw = nir->info.tess.ccw;
-   shader_info->tes.point_mode = nir->info.tess.point_mode;
-   shader_info->tes.as_es = options->key.tes.as_es;
-   break;
-   case MESA_SHADER_TESS_CTRL:
-   shader_info->tcs.tcs_vertices_out = 
nir->info.tess.tcs_vertices_out;
-   break;
-   case MESA_SHADER_VERTEX:
-   shader_info->vs.as_es = options->key.vs.as_es;
-   shader_info->vs.as_ls = options->key.vs.as_ls;
-   /* in LS mode we need at least 1, invocation id needs 3, 
handled elsewhere */
-   if (options->key.vs.as_ls)
-   

[Mesa-dev] [PATCH 07/16] ac/nir: Don't write to the dynamic HS word on GFX9.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 27 ---
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c6c56f30b81..67945a353e8 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6047,26 +6047,31 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
tf_base = ctx->tess_factor_offset;
byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
  LLVMConstInt(ctx->i32, 4 * stride, false), 
"");
+   unsigned tf_offset = 0;
 
-   ac_nir_build_if(_if_ctx, ctx,
-   LLVMBuildICmp(ctx->builder, LLVMIntEQ,
- rel_patch_id, ctx->i32zero, ""));
+   if (ctx->options->chip_class <= VI) {
+   ac_nir_build_if(_if_ctx, ctx,
+   LLVMBuildICmp(ctx->builder, LLVMIntEQ,
+ rel_patch_id, ctx->i32zero, ""));
 
-   /* Store the dynamic HS control word. */
-   ac_build_buffer_store_dword(>ac, buffer,
-   LLVMConstInt(ctx->i32, 0x8000, false),
-   1, ctx->i32zero, tf_base,
-   0, 1, 0, true, false);
-   ac_nir_build_endif(_if_ctx);
+   /* Store the dynamic HS control word. */
+   ac_build_buffer_store_dword(>ac, buffer,
+   LLVMConstInt(ctx->i32, 0x8000, 
false),
+   1, ctx->i32zero, tf_base,
+   0, 1, 0, true, false);
+   tf_offset += 4;
+
+   ac_nir_build_endif(_if_ctx);
+   }
 
/* Store the tessellation factors. */
ac_build_buffer_store_dword(>ac, buffer, vec0,
MIN2(stride, 4), byteoffset, tf_base,
-   4, 1, 0, true, false);
+   tf_offset, 1, 0, true, false);
if (vec1)
ac_build_buffer_store_dword(>ac, buffer, vec1,
stride - 4, byteoffset, tf_base,
-   20, 1, 0, true, false);
+   16 + tf_offset, 1, 0, true, false);
 
//TODO store to offchip for TES to read - only if TES reads them
if (1) {
-- 
2.14.2

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[Mesa-dev] [PATCH 04/16] ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 8a1e64ce7e1..66d539dec47 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -154,7 +154,7 @@ struct ac_shader_variant_info {
unsigned num_input_sgprs;
unsigned num_input_vgprs;
bool need_indirect_descriptor_sets;
-   union {
+   struct {
struct {
struct ac_vs_output_info outinfo;
struct ac_es_output_info es_info;
-- 
2.14.2

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[Mesa-dev] [PATCH 11/16] radv: Add code to compile merged shaders.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.h |  1 +
 src/amd/vulkan/radv_pipeline.c  | 29 +
 src/amd/vulkan/radv_shader.c| 17 ++---
 src/amd/vulkan/radv_shader.h|  5 +++--
 4 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 360d613d58d..eecc2cb8d49 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -52,6 +52,7 @@ struct ac_tes_variant_key {
 };
 
 struct ac_tcs_variant_key {
+   struct ac_vs_variant_key vs_key;
unsigned primitive_mode;
unsigned input_vertices;
 };
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7102d07a03a..4f840d156fa 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1637,7 +1637,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 
if (nir[MESA_SHADER_FRAGMENT]) {
pipeline->shaders[MESA_SHADER_FRAGMENT] =
-   radv_shader_variant_create(device, 
modules[MESA_SHADER_FRAGMENT], nir[MESA_SHADER_FRAGMENT],
+   radv_shader_variant_create(device, 
modules[MESA_SHADER_FRAGMENT], [MESA_SHADER_FRAGMENT], 1,
   pipeline->layout, keys ? 
keys + MESA_SHADER_FRAGMENT : 0,
   
[MESA_SHADER_FRAGMENT], _sizes[MESA_SHADER_FRAGMENT]);
 
@@ -1652,14 +1652,35 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
pipeline->active_stages |= 
mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
}
 
+   if (device->physical_device->rad_info.chip_class >= GFX9 &&
+   modules[MESA_SHADER_TESS_CTRL] && 
!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
+   struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], 
nir[MESA_SHADER_TESS_CTRL]};
+   struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+   key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
+   pipeline->shaders[MESA_SHADER_TESS_CTRL] = 
radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], 
combined_nir, 2,
+   
  pipeline->layout,
+   
  , [MESA_SHADER_TESS_CTRL],
+   
  _sizes[MESA_SHADER_TESS_CTRL]);
+   modules[MESA_SHADER_VERTEX] = NULL;
+   }
+
+   if (device->physical_device->rad_info.chip_class >= GFX9 &&
+   modules[MESA_SHADER_GEOMETRY] && 
!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
+   gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? 
MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
+   struct nir_shader *combined_nir[] = {nir[pre_stage], 
nir[MESA_SHADER_GEOMETRY]};
+   pipeline->shaders[MESA_SHADER_GEOMETRY] = 
radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 
2,
+   
 pipeline->layout,
+   
 [pre_stage] , [MESA_SHADER_GEOMETRY],
+   
 _sizes[MESA_SHADER_GEOMETRY]);
+   modules[pre_stage] = NULL;
+   }
+
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if(modules[i] && !pipeline->shaders[i]) {
-   pipeline->shaders[i] = 
radv_shader_variant_create(device, modules[i], nir[i],
+   pipeline->shaders[i] = 
radv_shader_variant_create(device, modules[i], [i], 1,
  
pipeline->layout,
  keys 
? keys + i : 0, [i],
  
_sizes[i]);
-
-   pipeline->active_stages |= mesa_to_vk_shader_stage(i);
}
}
 
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 19153aac6c9..ed76e1d0242 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -378,7 +378,8 @@ radv_fill_shader_variant(struct radv_device *device,
 static struct radv_shader_variant *
 shader_variant_create(struct radv_device *device,
  struct radv_shader_module *module,
- struct nir_shader *shader,
+ struct nir_shader * const *shaders,
+ int shader_count,
  gl_shader_stage stage,
  struct ac_nir_compiler_options *options,
  bool gs_copy_shader,
@@ -406,11 +407,12 @@ shader_variant_create(struct radv_device 

[Mesa-dev] [PATCH 01/16] ac: Parse the new HS RSRC1 register.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_binary.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 1bf52c78328..cf0125c415f 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -252,6 +252,7 @@ void ac_shader_binary_read_config(struct ac_shader_binary 
*binary,
case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
case R_00B848_COMPUTE_PGM_RSRC1:
+   case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
conf->num_sgprs = MAX2(conf->num_sgprs, 
(G_00B028_SGPRS(value) + 1) * 8);
conf->num_vgprs = MAX2(conf->num_vgprs, 
(G_00B028_VGPRS(value) + 1) * 4);
conf->float_mode =  G_00B028_FLOAT_MODE(value);
-- 
2.14.2

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[Mesa-dev] [PATCH 06/16] ac/nir: Add function creation for merged LS+HS.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 254 
 1 file changed, 178 insertions(+), 76 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f01ca8799b9..c6c56f30b81 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -108,6 +108,7 @@ struct nir_to_llvm_context {
LLVMValueRef tcs_out_layout;
LLVMValueRef tcs_in_layout;
LLVMValueRef oc_lds;
+   LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
LLVMValueRef tcs_patch_id;
LLVMValueRef tcs_rel_ids;
@@ -627,36 +628,133 @@ static void allocate_user_sgprs(struct 
nir_to_llvm_context *ctx,
}
 }
 
-static void create_function(struct nir_to_llvm_context *ctx)
+static void
+radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
+ gl_shader_stage stage,
+ bool has_previous_stage,
+ gl_shader_stage previous_stage,
+ const struct user_sgpr_info 
*user_sgpr_info,
+ struct arg_info *args,
+ LLVMValueRef *desc_sets)
 {
unsigned num_sets = ctx->options->layout ? 
ctx->options->layout->num_sets : 0;
-   uint8_t user_sgpr_idx;
-   struct user_sgpr_info user_sgpr_info;
-   struct arg_info args = {};
-   LLVMValueRef desc_sets;
-
-   allocate_user_sgprs(ctx, _sgpr_info);
-   if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
-   add_user_sgpr_argument(, const_array(ctx->v4i32, 16), 
>ring_offsets); /* address of rings */
-   }
+   unsigned stage_mask = 1 << stage;
+   if (has_previous_stage)
+   stage_mask |= 1 << previous_stage;
 
/* 1 for each descriptor set */
-   if (!user_sgpr_info.indirect_all_descriptor_sets) {
+   if (!user_sgpr_info->indirect_all_descriptor_sets) {
for (unsigned i = 0; i < num_sets; ++i) {
-   if (ctx->options->layout->set[i].layout->shader_stages 
& (1 << ctx->stage)) {
-   add_user_sgpr_array_argument(, 
const_array(ctx->i8, 1024 * 1024), >descriptor_sets[i]);
+   if (ctx->options->layout->set[i].layout->shader_stages 
& stage_mask) {
+   add_user_sgpr_array_argument(args, 
const_array(ctx->i8, 1024 * 1024), >descriptor_sets[i]);
}
}
} else
-   add_user_sgpr_array_argument(, 
const_array(const_array(ctx->i8, 1024 * 1024), 32), _sets);
+   add_user_sgpr_array_argument(args, 
const_array(const_array(ctx->i8, 1024 * 1024), 32), desc_sets);
 
if (ctx->shader_info->info.needs_push_constants) {
/* 1 for push constants and dynamic descriptors */
-   add_user_sgpr_array_argument(, const_array(ctx->i8, 1024 * 
1024), >push_constants);
+   add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 
1024), >push_constants);
}
+}
 
-   switch (ctx->stage) {
+static void
+radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
+ gl_shader_stage stage,
+ bool has_previous_stage,
+ gl_shader_stage previous_stage,
+ const struct user_sgpr_info 
*user_sgpr_info,
+LLVMValueRef desc_sets,
+ uint8_t *user_sgpr_idx)
+{
+   unsigned num_sets = ctx->options->layout ? 
ctx->options->layout->num_sets : 0;
+   unsigned stage_mask = 1 << stage;
+   if (has_previous_stage)
+   stage_mask |= 1 << previous_stage;
+
+   if (!user_sgpr_info->indirect_all_descriptor_sets) {
+   for (unsigned i = 0; i < num_sets; ++i) {
+   if (ctx->options->layout->set[i].layout->shader_stages 
& stage_mask) {
+   
set_userdata_location(>shader_info->user_sgprs_locs.descriptor_sets[i], 
user_sgpr_idx, 2);
+   } else
+   ctx->descriptor_sets[i] = NULL;
+   }
+   } else {
+   uint32_t desc_sgpr_idx = *user_sgpr_idx;
+   set_userdata_location_shader(ctx, 
AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
+
+   for (unsigned i = 0; i < num_sets; ++i) {
+   if (ctx->options->layout->set[i].layout->shader_stages 
& stage_mask) {
+   
set_userdata_location_indirect(>shader_info->user_sgprs_locs.descriptor_sets[i],
 desc_sgpr_idx, 2, i * 8);
+   ctx->descriptor_sets[i] = 
ac_build_load_to_sgpr(>ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
+
+

Re: [Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

[Matt Turner]

On Wed, Oct 18, 2017 at 4:59 PM, Kenneth Graunke  wrote:
> Commit a73116ecc60414ade89802150b tried to make add_barrier_deps()
> walk to the next barrier, and stop.  To accomplish that, it added an
> is_barrier flag.  Unfortunately, this only works half of the time.
>
> The issue is that add_barrier_deps() walks both backward (to the
> previous barrier), and forward (to the next barrier).  It also sets
> is_barrier.  Assuming that we're processing instructions in forward
> order, this means that is_barrier will be set for previous instructions,
> but not future ones.  So we'll never see it, and walk further than we
> need to.

Dang. I should have realized that in my original patch.

With the typo Dylan pointed out fixed, both are:

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH 3/4] meson: build libEGL

[Eric Engestrom]

On Wednesday, 2017-10-18 23:56:00 +, Dylan Baker wrote:
> This is based heavily on Daniel Stone's work for the same, rebased on
> master and with a number of TODO's fixed.
> 
> This does not implement glvnd (which is coming in a later patch)
> 
> Meson builds egl slightly differently than autotools, namely it doesn't
> build an intermediate shared library. It doesn't do this because meson
> doesn't have problems with the name of the library being dynamically
> generated, so the glvnd and non-glvnd code can follow the same path.
> 
> Signed-off-by: Dylan Baker 
> ---
>  include/meson.build|   8 ++
>  meson.build|  81 ++--
>  meson_options.txt  |   9 +-
>  src/egl/meson.build| 144 
> +
>  src/egl/wayland/wayland-drm/meson.build|  14 ++
>  .../{wayland-drm => wayland-egl}/meson.build   |  29 +++--
>  src/gbm/meson.build|  12 +-
>  src/glx/meson.build|  22 
>  src/meson.build|   7 +-
>  9 files changed, 281 insertions(+), 45 deletions(-)
>  create mode 100644 src/egl/meson.build
>  copy src/egl/wayland/{wayland-drm => wayland-egl}/meson.build (66%)
> 
> diff --git a/include/meson.build b/include/meson.build
> index e33a8569d76..88e66a1a8f4 100644
> --- a/include/meson.build
> +++ b/include/meson.build
> @@ -58,3 +58,11 @@ endif
>  if with_osmesa
>install_headers('GL/osmesa.h', subdir : 'GL')
>  endif
> +
> +if with_egl
> +  install_headers(
> +'EGL/eglext.h', 'EGL/egl.h', 'EGL/eglextchromium.h', 'EGL/eglmesaext.h',
> +'EGL/eglplatform.h',
> +subdir : 'EGL',
> +  )
> +endif
> diff --git a/meson.build b/meson.build
> index 13d9e400ba7..9eef48340d7 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -130,16 +130,20 @@ endif
>  # TODO: other OSes
>  with_dri_platform = 'drm'
>  
> -# TODO: there are more platforms required for non-vulkan drivers
> +# TODO: android platform
>  with_platform_wayland = false
>  with_platform_x11 = false
>  with_platform_drm = false
> +with_platform_surfaceless = false
> +egl_native_platform = ''
>  _platforms = get_option('platforms')
>  if _platforms != ''
>_split = _platforms.split(',')
>with_platform_x11 = _split.contains('x11')
>with_platform_wayland = _split.contains('wayland')
>with_platform_drm = _split.contains('drm')
> +  with_platform_surfaceless = _split.contains('surfaceless')
> +  egl_native_platform = _split[0]
>  endif

I quite liked daniels' `foreach if/elif/else` structure, it had the
added advantage of being able to reject invalid platforms instead of
silently ignoring them.

>  
>  with_gbm = get_option('gbm')
> @@ -154,6 +158,27 @@ else
>with_gbm = false
>  endif
>  
> +with_egl = get_option('egl')
> +if with_egl == 'auto'
> +  with_egl = with_dri and with_shared_glapi and egl_native_platform != ''

I don't like the var name reuse, once as a string, then as a bool.
How about `_egl = get_option('egl')`, as with `_platforms` above?

I'll have another look tomorrow, but I think other than that this patch
is good (not giving my r-b just yet though).

> +elif with_egl == 'yes'
> +  if not with_dri
> +error('EGL requires dri')
> +  elif not with_shared_glapi
> +error('EGL requires shared-glapi')
> +  elif egl_native_platform == ''
> +error('No platforms specified, consider -Dplatforms=drm,x11 at least')
> +  endif
> +  with_egl = true
> +else
> +  with_egl = false
> +endif
> +
> +# TODO: or virgl
> +if with_egl and with_gallium_radeonsi and not (with_platform_drm or 
> with_platform_surfaceless)
> +  error('RadeonSI requires drm or surfaceless platform when using EGL')
> +endif
> +
>  pre_args += '-DGLX_USE_TLS'
>  with_glx = get_option('glx')
>  if with_glx != 'disabled'
> @@ -228,7 +253,7 @@ if with_any_vk and (with_platform_x11 and not with_dri3)
>error('Vulkan drivers require dri3 for X11 support')
>  endif
>  if with_dri or with_gallium
> -  if with_glx == 'disabled' # TODO: or egl
> +  if with_glx == 'disabled' and not with_egl
>  error('building dri or gallium drivers require at least one window 
> system')
>endif
>  endif
> @@ -250,6 +275,7 @@ if _drivers != ''
>  with_gallium_omx or with_gallium_va)
>  endif
>  
> +gl_pkgconfig_c_flags = []
>  if with_platform_x11
>if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
>  pre_args += '-DHAVE_X11_PLATFORM'
> @@ -269,6 +295,18 @@ if with_platform_x11
>pre_args += '-DGLX_USE_DRM'
>  endif
>endif
> +else
> +  pre_args += '-DMESA_EGL_NO_X11_HEADERS'
> +  gl_pkgconfig_c_flags += '-DMESA_EGL_NO_X11_HEADERS'
> +endif
> +if with_platform_drm
> +  if with_egl and not with_gbm
> +error('EGL drm platform requires gbm')
> +  endif
> +  pre_args += '-DHAVE_DRM_PLATFORM'
> +endif
> +if 

Re: [Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

[Dylan Baker]

typo in subject "is_barier" -> "is_barrier"

Quoting Kenneth Graunke (2017-10-18 16:59:12)
> Commit a73116ecc60414ade89802150b tried to make add_barrier_deps()
> walk to the next barrier, and stop.  To accomplish that, it added an
> is_barrier flag.  Unfortunately, this only works half of the time.
> 
> The issue is that add_barrier_deps() walks both backward (to the
> previous barrier), and forward (to the next barrier).  It also sets
> is_barrier.  Assuming that we're processing instructions in forward
> order, this means that is_barrier will be set for previous instructions,
> but not future ones.  So we'll never see it, and walk further than we
> need to.
> 
> dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23
> now compiles its shaders in 3.6 seconds instead of 3.3 minutes.
> ---
>  src/intel/compiler/brw_schedule_instructions.cpp | 32 
> 
>  1 file changed, 10 insertions(+), 22 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_schedule_instructions.cpp 
> b/src/intel/compiler/brw_schedule_instructions.cpp
> index b3f7e877c80..a1e825c661c 100644
> --- a/src/intel/compiler/brw_schedule_instructions.cpp
> +++ b/src/intel/compiler/brw_schedule_instructions.cpp
> @@ -94,8 +94,6 @@ public:
>  * successors is an exit node.
>  */
> schedule_node *exit;
> -
> -   bool is_barrier;
>  };
>  
>  /**
> @@ -800,7 +798,6 @@ schedule_node::schedule_node(backend_instruction *inst,
> this->cand_generation = 0;
> this->delay = 0;
> this->exit = NULL;
> -   this->is_barrier = false;
>  
> /* We can't measure Gen6 timings directly but expect them to be much
>  * closer to Gen7 than Gen4.
> @@ -921,6 +918,14 @@ instruction_scheduler::add_dep(schedule_node *before, 
> schedule_node *after)
> add_dep(before, after, before->latency);
>  }
>  
> +static bool
> +is_scheduling_barrier(const backend_instruction *inst)
> +{
> +   return inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
> +  inst->is_control_flow() ||
> +  inst->has_side_effects();
> +}
> +
>  /**
>   * Sometimes we really want this node to execute after everything that
>   * was before it and before everything that followed it.  This adds
> @@ -932,12 +937,10 @@ instruction_scheduler::add_barrier_deps(schedule_node 
> *n)
> schedule_node *prev = (schedule_node *)n->prev;
> schedule_node *next = (schedule_node *)n->next;
>  
> -   n->is_barrier = true;
> -
> if (prev) {
>while (!prev->is_head_sentinel()) {
>   add_dep(prev, n, 0);
> - if (prev->is_barrier)
> + if (is_scheduling_barrier(prev->inst))
>  break;
>   prev = (schedule_node *)prev->prev;
>}
> @@ -946,7 +949,7 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
> if (next) {
>while (!next->is_tail_sentinel()) {
>   add_dep(n, next, 0);
> - if (next->is_barrier)
> + if (is_scheduling_barrier(next->inst))
>  break;
>   next = (schedule_node *)next->next;
>}
> @@ -962,14 +965,6 @@ fs_instruction_scheduler::is_compressed(fs_inst *inst)
> return inst->exec_size == 16;
>  }
>  
> -static bool
> -is_scheduling_barrier(const fs_inst *inst)
> -{
> -   return inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
> -  inst->is_control_flow() ||
> -  inst->has_side_effects();
> -}
> -
>  void
>  fs_instruction_scheduler::calculate_deps()
>  {
> @@ -1233,13 +1228,6 @@ fs_instruction_scheduler::calculate_deps()
> }
>  }
>  
> -static bool
> -is_scheduling_barrier(const vec4_instruction *inst)
> -{
> -   return inst->is_control_flow() ||
> -  inst->has_side_effects();
> -}
> -
>  void
>  vec4_instruction_scheduler::calculate_deps()
>  {
> -- 
> 2.14.2
> 
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Re: [Mesa-dev] [PATCH 1/4] meson: Don't allow glx to be built without platform_x11

[Eric Engestrom]

On Wednesday, 2017-10-18 23:56:05 +, Dylan Baker wrote:
> Previously this failed to change with_glx to disabled from auto if
> platform_x11 was unset or if no opengl apis were being built.
> 
> Signed-off-by: Dylan Baker 
> ---
>  meson.build | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index 82c4d2ed12c..13d9e400ba7 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -157,8 +157,12 @@ endif
>  pre_args += '-DGLX_USE_TLS'
>  with_glx = get_option('glx')
>  if with_glx != 'disabled'
> -  if not (with_platform_x11 and with_any_opengl) and with_glx != 'auto'
> -error('Cannot build GLX support without X11 platform support and at 
> least one OpenGL API')
> +  if not (with_platform_x11 and with_any_opengl)
> +if with_glx != 'auto'
> +  error('Cannot build GLX support without X11 platform support and at 
> least one OpenGL API')
> +else
> +  with_glx = 'disabled'

Nit: swap the branches?

  if glx == auto
glx = disabled
  else
error()

Patches 1 & 2 are
Reviewed-by: Eric Engestrom 

> +endif
>elif with_glx == 'gallium-xlib' 
>  if not with_gallium
>error('Gallium-xlib based GLX requires at least one gallium driver')
> -- 
> 2.14.2
> 
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Re: [Mesa-dev] Upstream support for FreeSync / Adaptive Sync

[Manasi Navare]

On Wed, Oct 18, 2017 at 03:20:57PM -0400, Harry Wentland wrote:
> On 2017-10-18 04:10 AM, Daniel Vetter wrote:
> > On Tue, Oct 17, 2017 at 09:01:52PM +0200, Nicolai Hähnle wrote:
> >> On 17.10.2017 19:16, Daniel Vetter wrote:
> >>> On Tue, Oct 17, 2017 at 5:40 PM, Michel Dänzer  wrote:
>  On 17/10/17 05:04 PM, Daniel Vetter wrote:
> > On Tue, Oct 17, 2017 at 03:46:24PM +0200, Michel Dänzer wrote:
> >> On 17/10/17 02:22 PM, Daniel Vetter wrote:
> >>> On Tue, Oct 17, 2017 at 12:28:17PM +0200, Michel Dänzer wrote:
>  On 17/10/17 11:34 AM, Nicolai Hähnle wrote:
> >>>
> > Common sense suggests that there need to be two side to FreeSync / 
> > VESA
> > Adaptive Sync support:
> >
> > 1. Query the display capabilities. This means querying minimum / 
> > maximum
> > refresh duration, plus possibly a query for when the earliest/latest
> > timing of the *next* refresh.
> >
> > 2. Signal desired present time. This means passing a target timer 
> > value
> > instead of a target vblank count, e.g. something like this for the 
> > KMS
> > interface:
> >
> >int drmModePageFlipTarget64(int fd, uint32_t crtc_id, uint32_t 
> > fb_id,
> >uint32_t flags, void *user_data,
> >uint64_t target);
> >
> >+ a flag to indicate whether target is the vblank count or the
> > CLOCK_MONOTONIC (?) time in ns.
> 
>  drmModePageFlip(Target) is part of the pre-atomic KMS API, but 
>  adapative
>  sync should probably only be supported via the atomic API, presumably
>  via output properties.
> >>>
> >>> +1
> >>>
> >>> At least now that DC is on track to land properly, and you want to do 
> >>> this
> >>> for DC-only anyway there's no reason to pimp the legacy interfaces
> >>> further. And atomic is soo much easier to extend.
> >>>
> >>> The big question imo is where we need to put the flag on the kms side,
> >>> since freesync is not just about presenting earlier, but also about
> >>> presenting later. But for backwards compat we can't stretch the 
> >>> refresh
> >>> rate by default for everyone, or clients that rely on high precision
> >>> timestamps and regular refresh will get a bad surprise.
> >>
> >> The idea described above is that adaptive sync would be used for flips
> >> with a target timestamp. Apps which don't want to use adaptive sync
> >> wouldn't set a target timestamp.
> >>
> >>
> >>> I think a boolean enable_freesync property is probably what we want, 
> >>> which
> >>> enables freesync for as long as it's set.
> >>
> >> The question then becomes under what circumstances the property is 
> >> (not)
> >> set. Not sure offhand this will actually solve any problem, or just 
> >> push
> >> it somewhere else.
> >
> > I thought that's what the driconf switch is for, with a policy of 
> > "please
> > schedule asap" instead of a specific timestamp.
> 
>  The driconf switch is just for the user's intention to use adaptive sync
>  when possible. A property as you suggest cannot be set by the client
>  directly, because it can't know when adaptive sync can actually be used
>  (only when its window is fullscreen and using page flipping). So the
>  property would have to be set by the X server/driver / Wayland
>  compositor / ... instead. The question is whether such a property is
>  actually needed, or whether the kernel could just enable adaptive sync
>  when there's a flip with a target timestamp, and disable it when there's
>  a flip without a target timestamp, or something like that.
> >>>
> >>> If your adaptive sync also supports extending the vblank beyond the
> >>> nominal limit, then you can't do that with a per-flip flag. Because
> >>> absent of a userspace requesting adaptive sync you must flip at the
> >>> nominal vrefresh rate. So if your userspace is a tad bit late with the
> >>> frame and would like to extend the frame to avoid missing a frame
> >>> entirely it'll be too late by the time the vblank actually gets
> >>> submitted. That's a bit a variation of what Ville brought up about
> >>> what we're going to do when the timestamp was missed by the time all
> >>> the depending fences signalled.
> >>
> >> These are very good points. It does sound like we'd need both an
> >> "AdaptiveSync" boolean property and an (optional) "DesiredPresentTime"
> >> property.
> >>
> >> The DesiredPresentTime property applies only to a single commit and could
> >> perhaps be left out in a first version. The AdaptiveSync property is
> >> persistent. When enabled, it means:
> >>
> >> - handle page flip requests as soon as possible
> >> - while 

[Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

[Kenneth Graunke]

Commit a73116ecc60414ade89802150b tried to make add_barrier_deps()
walk to the next barrier, and stop.  To accomplish that, it added an
is_barrier flag.  Unfortunately, this only works half of the time.

The issue is that add_barrier_deps() walks both backward (to the
previous barrier), and forward (to the next barrier).  It also sets
is_barrier.  Assuming that we're processing instructions in forward
order, this means that is_barrier will be set for previous instructions,
but not future ones.  So we'll never see it, and walk further than we
need to.

dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23
now compiles its shaders in 3.6 seconds instead of 3.3 minutes.
---
 src/intel/compiler/brw_schedule_instructions.cpp | 32 
 1 file changed, 10 insertions(+), 22 deletions(-)

diff --git a/src/intel/compiler/brw_schedule_instructions.cpp 
b/src/intel/compiler/brw_schedule_instructions.cpp
index b3f7e877c80..a1e825c661c 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -94,8 +94,6 @@ public:
 * successors is an exit node.
 */
schedule_node *exit;
-
-   bool is_barrier;
 };
 
 /**
@@ -800,7 +798,6 @@ schedule_node::schedule_node(backend_instruction *inst,
this->cand_generation = 0;
this->delay = 0;
this->exit = NULL;
-   this->is_barrier = false;
 
/* We can't measure Gen6 timings directly but expect them to be much
 * closer to Gen7 than Gen4.
@@ -921,6 +918,14 @@ instruction_scheduler::add_dep(schedule_node *before, 
schedule_node *after)
add_dep(before, after, before->latency);
 }
 
+static bool
+is_scheduling_barrier(const backend_instruction *inst)
+{
+   return inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
+  inst->is_control_flow() ||
+  inst->has_side_effects();
+}
+
 /**
  * Sometimes we really want this node to execute after everything that
  * was before it and before everything that followed it.  This adds
@@ -932,12 +937,10 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
schedule_node *prev = (schedule_node *)n->prev;
schedule_node *next = (schedule_node *)n->next;
 
-   n->is_barrier = true;
-
if (prev) {
   while (!prev->is_head_sentinel()) {
  add_dep(prev, n, 0);
- if (prev->is_barrier)
+ if (is_scheduling_barrier(prev->inst))
 break;
  prev = (schedule_node *)prev->prev;
   }
@@ -946,7 +949,7 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
if (next) {
   while (!next->is_tail_sentinel()) {
  add_dep(n, next, 0);
- if (next->is_barrier)
+ if (is_scheduling_barrier(next->inst))
 break;
  next = (schedule_node *)next->next;
   }
@@ -962,14 +965,6 @@ fs_instruction_scheduler::is_compressed(fs_inst *inst)
return inst->exec_size == 16;
 }
 
-static bool
-is_scheduling_barrier(const fs_inst *inst)
-{
-   return inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
-  inst->is_control_flow() ||
-  inst->has_side_effects();
-}
-
 void
 fs_instruction_scheduler::calculate_deps()
 {
@@ -1233,13 +1228,6 @@ fs_instruction_scheduler::calculate_deps()
}
 }
 
-static bool
-is_scheduling_barrier(const vec4_instruction *inst)
-{
-   return inst->is_control_flow() ||
-  inst->has_side_effects();
-}
-
 void
 vec4_instruction_scheduler::calculate_deps()
 {
-- 
2.14.2

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[Mesa-dev] [PATCH 1/2] i965: Move fs_inst::has_side_effects()'s eot check to the parent class.

[Kenneth Graunke]

This eliminates a layer of wrapping, and makes a backend_instruction
sufficient.  The downside is that it exposes 'eot' to the vec4 backend,
which it doesn't need, but can basically happily ignore.
---
 src/intel/compiler/brw_fs.cpp   | 6 --
 src/intel/compiler/brw_ir_fs.h  | 2 --
 src/intel/compiler/brw_shader.cpp   | 2 +-
 src/intel/compiler/brw_shader.h | 1 +
 src/intel/compiler/brw_vec4_visitor.cpp | 1 +
 5 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 66cb33131b6..30e8841242d 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -393,12 +393,6 @@ fs_inst::can_change_types() const
 !src[1].abs && !src[1].negate));
 }
 
-bool
-fs_inst::has_side_effects() const
-{
-   return this->eot || backend_instruction::has_side_effects();
-}
-
 void
 fs_reg::init()
 {
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index 58beae0d1f0..0e7c55bcc03 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -347,7 +347,6 @@ public:
unsigned size_read(int arg) const;
bool can_do_source_mods(const struct gen_device_info *devinfo);
bool can_change_types() const;
-   bool has_side_effects() const;
bool has_source_and_destination_hazard() const;
 
/**
@@ -367,7 +366,6 @@ public:
 
uint8_t sources; /**< Number of fs_reg sources. */
 
-   bool eot:1;
bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 };
 
diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp
index 53d0742d2e8..4eb602b000a 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1000,7 +1000,7 @@ backend_instruction::has_side_effects() const
case TCS_OPCODE_RELEASE_INPUT:
   return true;
default:
-  return false;
+  return eot;
}
 }
 
diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index 30e7bf75c58..d632f6dcd4e 100644
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -167,6 +167,7 @@ struct backend_instruction {
bool no_dd_check:1;
bool saturate:1;
bool shadow_compare:1;
+   bool eot:1;
 
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 * mod and predication.
diff --git a/src/intel/compiler/brw_vec4_visitor.cpp 
b/src/intel/compiler/brw_vec4_visitor.cpp
index ae516196b15..a62c79ee7f3 100644
--- a/src/intel/compiler/brw_vec4_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_visitor.cpp
@@ -46,6 +46,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const 
dst_reg ,
this->predicate_inverse = false;
this->target = 0;
this->shadow_compare = false;
+   this->eot = false;
this->ir = NULL;
this->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;
this->header_size = 0;
-- 
2.14.2

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[Mesa-dev] [PATCH 4/4] meson: Add support for EGL glvnd

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/egl/meson.build | 46 --
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/src/egl/meson.build b/src/egl/meson.build
index ade6810bf91..8ea8a5bbb69 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -70,6 +70,34 @@ linux_dmabuf_unstable_v1_client_protocol_h = custom_target(
   command : [prog_wl_scanner, 'client-header', '@INPUT@', '@OUTPUT@'],
 )
 
+g_egldispatchstubs_c = custom_target(
+  'g_egldispatchstubs.c',
+  input : [
+'generate/gen_egl_dispatch.py', 'generate/eglFunctionList.py',
+'generate/egl.xml', 'generate/egl_other.xml'
+  ],
+  output : 'g_egldispatchstubs.c',
+  command : [
+prog_python2, '@INPUT0@', 'source', '@INPUT1@', '@INPUT2@', '@INPUT3@'
+  ],
+  depend_files : files('generate/genCommon.py'),
+  capture : true,
+)
+
+g_egldispatchstubs_h = custom_target(
+  'g_egldispatchstubs.h',
+  input : [
+'generate/gen_egl_dispatch.py', 'generate/eglFunctionList.py',
+'generate/egl.xml', 'generate/egl_other.xml'
+  ],
+  output : 'g_egldispatchstubs.h',
+  command : [
+prog_python2, '@INPUT0@', 'header', '@INPUT1@', '@INPUT2@', '@INPUT3@'
+  ],
+  depend_files : files('generate/genCommon.py'),
+  capture : true,
+)
+
 if with_platform_x11
   files_egl += files('drivers/dri2/platform_x11.c')
   if with_dri3
@@ -107,8 +135,22 @@ if cc.has_function('mincore')
   c_args_for_egl += '-DHAVE_MINCORE'
 endif
 
+if not with_glvnd
+  egl_lib_name = 'EGL'
+  egl_lib_version = '1.0.0'
+else
+  egl_lib_name = 'EGL_mesa'
+  egl_lib_version = '0'
+  files_egl += [g_egldispatchstubs_h, g_egldispatchstubs_c]
+  files_egl += files('main/eglglvnd.c', 'main/egldispatchstubs.c')
+  install_data(
+'main/50_mesa.json',
+install_dir : join_paths(get_option('datadir'), 'glvnd', 'egl_vendor.d')
+  )
+endif
+
 libegl = shared_library(
-  'EGL',
+  egl_lib_name,
   files_egl,
   c_args : [
 c_vis_args,
@@ -125,7 +167,7 @@ libegl = shared_library(
   link_args : [ld_args_bsymbolic, ld_args_gc_sections],
   dependencies : [deps_for_egl, dep_dl, dep_libdrm, dep_clock, dep_thread],
   install : true,
-  version : '1.0.0',
+  version : egl_lib_version,
 )
 
 pkg.generate(
-- 
2.14.2

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[Mesa-dev] [PATCH 3/4] meson: build libEGL

[Dylan Baker]

This is based heavily on Daniel Stone's work for the same, rebased on
master and with a number of TODO's fixed.

This does not implement glvnd (which is coming in a later patch)

Meson builds egl slightly differently than autotools, namely it doesn't
build an intermediate shared library. It doesn't do this because meson
doesn't have problems with the name of the library being dynamically
generated, so the glvnd and non-glvnd code can follow the same path.

Signed-off-by: Dylan Baker 
---
 include/meson.build|   8 ++
 meson.build|  81 ++--
 meson_options.txt  |   9 +-
 src/egl/meson.build| 144 +
 src/egl/wayland/wayland-drm/meson.build|  14 ++
 .../{wayland-drm => wayland-egl}/meson.build   |  29 +++--
 src/gbm/meson.build|  12 +-
 src/glx/meson.build|  22 
 src/meson.build|   7 +-
 9 files changed, 281 insertions(+), 45 deletions(-)
 create mode 100644 src/egl/meson.build
 copy src/egl/wayland/{wayland-drm => wayland-egl}/meson.build (66%)

diff --git a/include/meson.build b/include/meson.build
index e33a8569d76..88e66a1a8f4 100644
--- a/include/meson.build
+++ b/include/meson.build
@@ -58,3 +58,11 @@ endif
 if with_osmesa
   install_headers('GL/osmesa.h', subdir : 'GL')
 endif
+
+if with_egl
+  install_headers(
+'EGL/eglext.h', 'EGL/egl.h', 'EGL/eglextchromium.h', 'EGL/eglmesaext.h',
+'EGL/eglplatform.h',
+subdir : 'EGL',
+  )
+endif
diff --git a/meson.build b/meson.build
index 13d9e400ba7..9eef48340d7 100644
--- a/meson.build
+++ b/meson.build
@@ -130,16 +130,20 @@ endif
 # TODO: other OSes
 with_dri_platform = 'drm'
 
-# TODO: there are more platforms required for non-vulkan drivers
+# TODO: android platform
 with_platform_wayland = false
 with_platform_x11 = false
 with_platform_drm = false
+with_platform_surfaceless = false
+egl_native_platform = ''
 _platforms = get_option('platforms')
 if _platforms != ''
   _split = _platforms.split(',')
   with_platform_x11 = _split.contains('x11')
   with_platform_wayland = _split.contains('wayland')
   with_platform_drm = _split.contains('drm')
+  with_platform_surfaceless = _split.contains('surfaceless')
+  egl_native_platform = _split[0]
 endif
 
 with_gbm = get_option('gbm')
@@ -154,6 +158,27 @@ else
   with_gbm = false
 endif
 
+with_egl = get_option('egl')
+if with_egl == 'auto'
+  with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
+elif with_egl == 'yes'
+  if not with_dri
+error('EGL requires dri')
+  elif not with_shared_glapi
+error('EGL requires shared-glapi')
+  elif egl_native_platform == ''
+error('No platforms specified, consider -Dplatforms=drm,x11 at least')
+  endif
+  with_egl = true
+else
+  with_egl = false
+endif
+
+# TODO: or virgl
+if with_egl and with_gallium_radeonsi and not (with_platform_drm or 
with_platform_surfaceless)
+  error('RadeonSI requires drm or surfaceless platform when using EGL')
+endif
+
 pre_args += '-DGLX_USE_TLS'
 with_glx = get_option('glx')
 if with_glx != 'disabled'
@@ -228,7 +253,7 @@ if with_any_vk and (with_platform_x11 and not with_dri3)
   error('Vulkan drivers require dri3 for X11 support')
 endif
 if with_dri or with_gallium
-  if with_glx == 'disabled' # TODO: or egl
+  if with_glx == 'disabled' and not with_egl
 error('building dri or gallium drivers require at least one window system')
   endif
 endif
@@ -250,6 +275,7 @@ if _drivers != ''
 with_gallium_omx or with_gallium_va)
 endif
 
+gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
 pre_args += '-DHAVE_X11_PLATFORM'
@@ -269,6 +295,18 @@ if with_platform_x11
   pre_args += '-DGLX_USE_DRM'
 endif
   endif
+else
+  pre_args += '-DMESA_EGL_NO_X11_HEADERS'
+  gl_pkgconfig_c_flags += '-DMESA_EGL_NO_X11_HEADERS'
+endif
+if with_platform_drm
+  if with_egl and not with_gbm
+error('EGL drm platform requires gbm')
+  endif
+  pre_args += '-DHAVE_DRM_PLATFORM'
+endif
+if with_platform_surfaceless
+  pre_args += '-DHAVE_SURFACELESS_PLATFORM'
 endif
 
 prog_python2 = find_program('python2')
@@ -646,18 +684,22 @@ endif
 
 # TODO: symbol mangling
 
-# TODO: egl configuration
-
 if with_platform_wayland
   prog_wl_scanner = find_program('wayland-scanner')
   dep_wl_protocols = dependency('wayland-protocols', version : '>= 1.8')
   dep_wayland_client = dependency('wayland-client', version : '>=1.11')
   dep_wayland_server = dependency('wayland-server', version : '>=1.11')
+  wayland_dmabuf_xml = join_paths(
+dep_wl_protocols.get_pkgconfig_variable('pkgdatadir'), 'unstable',
+'linux-dmabuf', 'linux-dmabuf-unstable-v1.xml'
+  )
+  pre_args += ['-DHAVE_WAYLAND_PLATFORM', '-DWL_HIDE_DEPRECATED']
 else
   

[Mesa-dev] [PATCH 0/4] meson egl support

[Dylan Baker]

This small series adds support to the meson build system for building EGL in
both the glvnd and traditional configurations. I have tested it against the i965
using piglit and didn't see any regressions in the egl tests.

This work is based on work that Daniel Stone started, although I rewrote the
patches from scratch, I heavily referenced his work. I'd also like to thank
Jason Ekstrand for helping me debug a wayland-egl issue I ran into.

This is available at my github:
https://github.com/dcbaker/mesa submit/meson-egl

Dylan Baker (4):
  meson: Don't allow glx to be built without platform_x11
  meson: move wayland_drm_protocol generation to wayland-drm
  meson: build libEGL
  meson: Add support for EGL glvnd

 include/meson.build|   8 +
 meson.build|  89 --
 meson_options.txt  |   9 +-
 src/egl/meson.build| 186 +
 src/egl/wayland/wayland-drm/meson.build|  28 +++-
 .../{wayland-drm => wayland-egl}/meson.build   |  23 ++-
 src/gbm/meson.build|  12 +-
 src/glx/meson.build|  22 ---
 src/meson.build|   7 +-
 src/vulkan/wsi/meson.build |  14 --
 10 files changed, 345 insertions(+), 53 deletions(-)
 create mode 100644 src/egl/meson.build
 copy src/egl/wayland/{wayland-drm => wayland-egl}/meson.build (66%)

-- 
2.14.2

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[Mesa-dev] [PATCH 2/4] meson: move wayland_drm_protocol generation to wayland-drm

[Dylan Baker]

These files are needed by both vulkan wayland-wsi and by egl
wayland-wsi, since the XML file is in src/egl/wayland/wayland-drm and we
can include this directory in such a way that it will be loaded before
egl and vulkan this allows us to avoid multiple calls to the same
generator.

Signed-off-by: Dylan Baker 
---
 src/egl/wayland/wayland-drm/meson.build | 14 +-
 src/vulkan/wsi/meson.build  | 14 --
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/src/egl/wayland/wayland-drm/meson.build 
b/src/egl/wayland/wayland-drm/meson.build
index 0a94626f287..92adc295531 100644
--- a/src/egl/wayland/wayland-drm/meson.build
+++ b/src/egl/wayland/wayland-drm/meson.build
@@ -18,4 +18,16 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-wayland_drm_xml = files('wayland-drm.xml')
+wayland_drm_protocol_c = custom_target(
+  'wayland-drm-protocol.c',
+  input : 'wayland-drm.xml',
+  output : 'wayland-drm-protocol.c',
+  command : [prog_wl_scanner, 'code', '@INPUT@', '@OUTPUT@'],
+)
+
+wayland_drm_client_protocol_h = custom_target(
+  'wayland-drm-client-protocol.h',
+  input : 'wayland-drm.xml',
+  output : 'wayland-drm-client-protocol.h',
+  command : [prog_wl_scanner, 'client-header', '@INPUT@', '@OUTPUT@'],
+)
diff --git a/src/vulkan/wsi/meson.build b/src/vulkan/wsi/meson.build
index c42af8e4cde..3aa02d5e63f 100644
--- a/src/vulkan/wsi/meson.build
+++ b/src/vulkan/wsi/meson.build
@@ -18,20 +18,6 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-wayland_drm_protocol_c = custom_target(
-  'wayland-drm-protocol.c',
-  input : wayland_drm_xml,
-  output : 'wayland-drm-protocol.c',
-  command : [prog_wl_scanner, 'code', '@INPUT@', '@OUTPUT@'],
-)
-
-wayland_drm_client_protocol_h = custom_target(
-  'wayland-drm-client-protocol.h',
-  input : wayland_drm_xml,
-  output : 'wayland-drm-client-protocol.h',
-  command : [prog_wl_scanner, 'client-header', '@INPUT@', '@OUTPUT@'],
-)
-
 vulkan_wsi_args = []
 vulkan_wsi_deps = []
 
-- 
2.14.2

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[Mesa-dev] [PATCH 1/4] meson: Don't allow glx to be built without platform_x11

[Dylan Baker]

Previously this failed to change with_glx to disabled from auto if
platform_x11 was unset or if no opengl apis were being built.

Signed-off-by: Dylan Baker 
---
 meson.build | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/meson.build b/meson.build
index 82c4d2ed12c..13d9e400ba7 100644
--- a/meson.build
+++ b/meson.build
@@ -157,8 +157,12 @@ endif
 pre_args += '-DGLX_USE_TLS'
 with_glx = get_option('glx')
 if with_glx != 'disabled'
-  if not (with_platform_x11 and with_any_opengl) and with_glx != 'auto'
-error('Cannot build GLX support without X11 platform support and at least 
one OpenGL API')
+  if not (with_platform_x11 and with_any_opengl)
+if with_glx != 'auto'
+  error('Cannot build GLX support without X11 platform support and at 
least one OpenGL API')
+else
+  with_glx = 'disabled'
+endif
   elif with_glx == 'gallium-xlib' 
 if not with_gallium
   error('Gallium-xlib based GLX requires at least one gallium driver')
-- 
2.14.2

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Re: [Mesa-dev] [PATCH v2] docs: add documentation for building with meson

[Dylan Baker]

Quoting Eric Engestrom (2017-10-18 15:27:39)
> On Wednesday, 2017-10-18 18:09:22 +, Dylan Baker wrote:
> > v2: - Add information about CC, CXX, CFLAGS, and CXXFLAGS (Nicolai)
> > - Add message at top that meson for mesa is still a work in progress
> > - Add trailing "/" to directories (Eric E.)
> > - Fix a number of spelling/grammar/style suggestions from Eric E.
> > - Make a number of changes as suggested by Emil.
> > 
> > Signed-off-by: Dylan Baker 
> > ---
> >  docs/contents.html |   1 +
> >  docs/meson.html| 126 
> > +
> >  2 files changed, 127 insertions(+)
> >  create mode 100644 docs/meson.html
> > 
> > diff --git a/docs/contents.html b/docs/contents.html
> > index d5455421091..9a86019e2f6 100644
> > --- a/docs/contents.html
> > +++ b/docs/contents.html
> > @@ -43,6 +43,7 @@
> >  Compiling / Installing
> >
> >  Autoconf
> > +Meson
> >
> >  
> >  Precompiled Libraries
> > diff --git a/docs/meson.html b/docs/meson.html
> > new file mode 100644
> > index 000..9f933382965
> > --- /dev/null
> > +++ b/docs/meson.html
> > @@ -0,0 +1,126 @@
> > + > "http://www.w3.org/TR/html4/loose.dtd;>
> > +
> > +
> > +  
> > +  Compilation and Installation using Meson
> > +  
> > +
> > +
> > +
> > +
> > +  The Mesa 3D Graphics Library
> > +
> > +
> > +
> > +
> > +
> > +Compilation and Installation using Meson
> > +
> > +1. Basic Usage
> > +
> > +The Meson build system for Mesa is still under active 
> > development,
> > +and should not be used in production environments.
> > +
> > +
> > +The meson program is used to configure the source directory and generates
> > +either a ninja build file, or Visual Studio® build files. The latter, and 
> > must
> 
> s/, and//
> 
> > +be enabled via the --backend switch, as ninja is always the default. Meson 
> > only
> > +supports out-of-tree builds, and must be passed a directory to put built 
> > and
> > +generated sources into. We'll call that directory "build" for examples.
> > +
> > +
> > +
> > +meson build/
> > +
> > +
> > +
> > +To see a description of your options you can run "meson configure" with no
> > +arguments. This will show your meson global arguments and project 
> > arguments,
> > +along with their defaults and your local settings.
> > +
> > +
> > +
> > +meson configure build/
> > +
> > +
> > +
> > +With arguments "meson configure" is used to change options on already
> > +configured build directory. All options passed to this command are in the 
> > form
> > +-D"command"="value".
> 
> s/command/option/, and I think you can drop the quotes?
> 
> > +
> > +
> > +
> > +meson configure build/ -Dprefix=/tmp/install -Dglx=true
> > +
> > +
> > +
> > +Once you've run meson successfully you can use your configured backend to 
> > build
> > +the project. With ninja, the -C option can be be used to point at a 
> > directory
> > +to build.
> > +
> > +
> > +
> > +ninja -C build/
> > +
> > +
> > +
> > +Without arguments, it will produce libGL.so and/or several other libraries
> > +depending on the options you have chosen. Later, if you want to rebuild 
> > for a
> > +different configuration, you should run ninja clean before
> > +rebuilding, or create a new out of tree build directory (meson supports an
> > +unlimited number of them) for each configuration you want to build.
> > +
> > +
> > +CC, CFLAGS, CXX, CXXFLAGS
> > +These environment variables
> > +control the C and C++ compilers used during the build. The default 
> > compilers
> > +depends on your operating system. Meson supports most of the popular 
> > compilers,
> > +a complete list is available
> > + > href="http://mesonbuild.com/Reference-tables.html#compiler-ids;>here.
> > +
> > +These arguments are consumed and stored by meson when it is initialized or
> > +re-initialized. Therefore passing them to meson configure will not do 
> > anything,
> > +and passing them to ninja will only do something if ninja decides to
> > +re-initialze meson, for example, if a meson.build file has been changed.
> > +Changing these variables will not cause all targets to be rebuilt, so 
> > running
> > +ninja clean is recomended when changing any of these variables.
> > +
> > +
> > +
> > +CC=clang CXX=clang++ meson build-clang
> > +ninja -C build-clang
> > +
> > +touch meson.build
> > +ninja -C build-clang clean
> > +CFLAGS=-Wno-typedef-redefinition ninja -C build-clang
> 
> `touch` should be after `clean`, otherwise `clean` will execute the
> regeneration, and the CFLAGS will come too late.
> 
> Do you want to also mention Lyude's question about using a non-standard
> llvm-config here? It was surprisingly trivial to do :)

Yes, I should do that. I hadn't verified that it actually worked, so I didn't
want to document it as such...

> Other than that, this v2 is:
> Reviewed-by: Eric Engestrom 

Thanks!

> 
> > +
> > +
> > +PKG_CONFIG_PATH
> > +The
> > 

Re: [Mesa-dev] Upstream support for FreeSync / Adaptive Sync

[Harry Wentland]

On 2017-10-18 04:10 AM, Daniel Vetter wrote:
> On Tue, Oct 17, 2017 at 09:01:52PM +0200, Nicolai Hähnle wrote:
>> On 17.10.2017 19:16, Daniel Vetter wrote:
>>> On Tue, Oct 17, 2017 at 5:40 PM, Michel Dänzer  wrote:
 On 17/10/17 05:04 PM, Daniel Vetter wrote:
> On Tue, Oct 17, 2017 at 03:46:24PM +0200, Michel Dänzer wrote:
>> On 17/10/17 02:22 PM, Daniel Vetter wrote:
>>> On Tue, Oct 17, 2017 at 12:28:17PM +0200, Michel Dänzer wrote:
 On 17/10/17 11:34 AM, Nicolai Hähnle wrote:
>>>
> Common sense suggests that there need to be two side to FreeSync / 
> VESA
> Adaptive Sync support:
>
> 1. Query the display capabilities. This means querying minimum / 
> maximum
> refresh duration, plus possibly a query for when the earliest/latest
> timing of the *next* refresh.
>
> 2. Signal desired present time. This means passing a target timer 
> value
> instead of a target vblank count, e.g. something like this for the KMS
> interface:
>
>int drmModePageFlipTarget64(int fd, uint32_t crtc_id, uint32_t 
> fb_id,
>uint32_t flags, void *user_data,
>uint64_t target);
>
>+ a flag to indicate whether target is the vblank count or the
> CLOCK_MONOTONIC (?) time in ns.

 drmModePageFlip(Target) is part of the pre-atomic KMS API, but 
 adapative
 sync should probably only be supported via the atomic API, presumably
 via output properties.
>>>
>>> +1
>>>
>>> At least now that DC is on track to land properly, and you want to do 
>>> this
>>> for DC-only anyway there's no reason to pimp the legacy interfaces
>>> further. And atomic is soo much easier to extend.
>>>
>>> The big question imo is where we need to put the flag on the kms side,
>>> since freesync is not just about presenting earlier, but also about
>>> presenting later. But for backwards compat we can't stretch the refresh
>>> rate by default for everyone, or clients that rely on high precision
>>> timestamps and regular refresh will get a bad surprise.
>>
>> The idea described above is that adaptive sync would be used for flips
>> with a target timestamp. Apps which don't want to use adaptive sync
>> wouldn't set a target timestamp.
>>
>>
>>> I think a boolean enable_freesync property is probably what we want, 
>>> which
>>> enables freesync for as long as it's set.
>>
>> The question then becomes under what circumstances the property is (not)
>> set. Not sure offhand this will actually solve any problem, or just push
>> it somewhere else.
>
> I thought that's what the driconf switch is for, with a policy of "please
> schedule asap" instead of a specific timestamp.

 The driconf switch is just for the user's intention to use adaptive sync
 when possible. A property as you suggest cannot be set by the client
 directly, because it can't know when adaptive sync can actually be used
 (only when its window is fullscreen and using page flipping). So the
 property would have to be set by the X server/driver / Wayland
 compositor / ... instead. The question is whether such a property is
 actually needed, or whether the kernel could just enable adaptive sync
 when there's a flip with a target timestamp, and disable it when there's
 a flip without a target timestamp, or something like that.
>>>
>>> If your adaptive sync also supports extending the vblank beyond the
>>> nominal limit, then you can't do that with a per-flip flag. Because
>>> absent of a userspace requesting adaptive sync you must flip at the
>>> nominal vrefresh rate. So if your userspace is a tad bit late with the
>>> frame and would like to extend the frame to avoid missing a frame
>>> entirely it'll be too late by the time the vblank actually gets
>>> submitted. That's a bit a variation of what Ville brought up about
>>> what we're going to do when the timestamp was missed by the time all
>>> the depending fences signalled.
>>
>> These are very good points. It does sound like we'd need both an
>> "AdaptiveSync" boolean property and an (optional) "DesiredPresentTime"
>> property.
>>
>> The DesiredPresentTime property applies only to a single commit and could
>> perhaps be left out in a first version. The AdaptiveSync property is
>> persistent. When enabled, it means:
>>
>> - handle page flip requests as soon as possible
>> - while no page flip is requested, delay vblank as long as possible
>>
>> How does that sound?
> 
> Yeah, that's what I had in mind. No idea it'll work out on real hw/full
> stack.
> 

A bit late to the thread but whatever has been suggested sounds quite good.

Our experience generally has been that we don't want 

Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

[Eric Engestrom]

On Wednesday, 2017-10-18 22:08:04 +, Dylan Baker wrote:
> Quoting Eric Engestrom (2017-10-18 14:48:49)
> > On Wednesday, 2017-10-18 18:45:19 +, Nicholas Miell wrote:
> > > On 10/17/2017 12:21 PM, Dylan Baker wrote:
> > > > +
> > > > +To see a description of your options you can run "meson configure". 
> > > > This will
> > > > +show your meson project configuration options as well as your local
> > > > +configuration options. One meson option to be aware of is that meson's 
> > > > default
> > > > +build type is "debug" (-O0 -g on gcc/clang).
> > > > +
> > > > +
> > > > +
> > > > +meson configure build
> > > > +
> > > > +
> > > 
> > > There should probably be a warning here about how there's no way to 
> > > export a
> > > build configuration and how every minor or point update of meson requires
> > > you to delete your build directories and reconfigure everything from
> > > scratch.
> > 
> > Agreed, the delete & reconfigure thing is really annoying, I'm hoping
> > this will be fixed eventually :/
> > 
> > As for exporting the config, I'm actually working on this area of
> > meson's code right now, it would be quite easy for me to add a 'dump'
> > feature.
> > I'm guessing something like autotool's `./config.status --config` that
> > can just be fed back to the next run of `meson` would be good?
> > 
> > I haven't actually yet figured out if I can only print the options that
> > don't have their default value, so what I can do for now is a trivial
> > 'dump all the current values'. Would that be interesting to you?
> 
> I don't think that the meson IR has an concept of default values for options,
> the interpreter just passes the default value as the value if one isn't 
> given. I

Yeah, that's the impression I got, but I hadn't dug enough to be sure.
I really want to have a 'reset to default value' in my TUI though, so
I just might have to add that concept to meson :P

> do think this is a nice feature, and I was thinking about doing it myself, 
> once
> the 0.43.1 release happens and upstream starts pulling feature requests again.
> One though I had was just to save the command line options in a text file so 
> you
> could do something like:
> 
> meson build-1.0 `cat build-0.9/options.txt`

Not a bad idea! I'll add an optional `outfile` param to `--dump` :)

I have the dump feature basically working in my branch [1] btw, I'll make a nice
clean patch series out of it and submit a pull request when the TUI is
usable.

[1] https://github.com/1ace/meson/tree/feature/mesonconf-tui

> 
> Dylan
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Re: [Mesa-dev] [PATCH v2 4/8] egl: add dri2_egl_surface_update_buffer_age() helper (v2)

[Gurchetan Singh]

The comment "we don't use get_back_bo() since ..." only makes sense in
context on droid_swap_buffers.  Why aren't you calling this helper
in dri2_drm_swap_buffers and dri2_wl_swap_buffers_with_damage?  It seems
like you can.


On Tue, Oct 17, 2017 at 7:38 AM, Emil Velikov 
wrote:

> On 6 October 2017 at 22:38, Gwan-gyeong Mun  wrote:
> > To share common update buffer age code.
> > This updates old buffer's age and sets current back buffer's age to 1.
> >
> > In preparation to adding of new platform which uses this helper.
> >
> > v2:
> >  - Fixes from Eric's review:
> >a) Split out series of refactor for helpers to a separate series.
> >b) Add the new helper function and use them to replace the old code
> in the
> >   same patch.
> >  - Fixes from Rob's review:
> >Remove unneeded ifdef block
> >
> Reviewed-by: Emil Velikov 
>
> -Emil
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Re: [Mesa-dev] [PATCH mesa] egl: set UseFallback if LIBGL_ALWAYS_SOFTWARE is set

[Gurchetan Singh]

Reviewed-by: Gurchetan Singh 

On Wed, Oct 18, 2017 at 9:09 AM, Eric Engestrom 
wrote:

> Suggested-by: Emil Velikov 
> Signed-off-by: Eric Engestrom 
> ---
>  src/egl/drivers/dri2/platform_surfaceless.c | 3 +--
>  src/egl/drivers/dri2/platform_wayland.c | 3 +--
>  src/egl/drivers/dri2/platform_x11.c | 2 +-
>  src/egl/main/egldriver.c| 5 -
>  4 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/platform_surfaceless.c
> b/src/egl/drivers/dri2/platform_surfaceless.c
> index 2af4a40b1a6b87edb9d2..977b046016665aa99148 100644
> --- a/src/egl/drivers/dri2/platform_surfaceless.c
> +++ b/src/egl/drivers/dri2/platform_surfaceless.c
> @@ -36,7 +36,6 @@
>  #include "egl_dri2.h"
>  #include "egl_dri2_fallbacks.h"
>  #include "loader.h"
> -#include "util/debug.h"
>
>  static __DRIimage*
>  surfaceless_alloc_image(struct dri2_egl_display *dri2_dpy,
> @@ -325,7 +324,7 @@ dri2_initialize_surfaceless(_EGLDriver *drv,
> _EGLDisplay *disp)
> dri2_dpy->fd = -1;
> disp->DriverData = (void *) dri2_dpy;
>
> -   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false)) {
> +   if (!disp->Options.UseFallback) {
>driver_loaded = surfaceless_probe_device(disp, false);
>if (!driver_loaded)
>   _eglLog(_EGL_WARNING,
> diff --git a/src/egl/drivers/dri2/platform_wayland.c
> b/src/egl/drivers/dri2/platform_wayland.c
> index 14db55ca747b07fa23f5..b38eb1c3354cfb0c5015 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -42,7 +42,6 @@
>  #include "egl_dri2.h"
>  #include "egl_dri2_fallbacks.h"
>  #include "loader.h"
> -#include "util/debug.h"
>  #include "util/u_vector.h"
>  #include "eglglobals.h"
>
> @@ -1972,7 +1971,7 @@ dri2_initialize_wayland(_EGLDriver *drv,
> _EGLDisplay *disp)
>  {
> EGLBoolean initialized = EGL_FALSE;
>
> -   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false))
> +   if (!disp->Options.UseFallback)
>initialized = dri2_initialize_wayland_drm(drv, disp);
>
> if (!initialized)
> diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/
> platform_x11.c
> index 9c20ea8f8a98c4c2b6bd..5bcdb2dac748cc0e9901 100644
> --- a/src/egl/drivers/dri2/platform_x11.c
> +++ b/src/egl/drivers/dri2/platform_x11.c
> @@ -1460,7 +1460,7 @@ dri2_initialize_x11(_EGLDriver *drv, _EGLDisplay
> *disp)
>  {
> EGLBoolean initialized = EGL_FALSE;
>
> -   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false)) {
> +   if (!disp->Options.UseFallback) {
>  #ifdef HAVE_DRI3
>if (!env_var_as_boolean("LIBGL_DRI3_DISABLE", false))
>   initialized = dri2_initialize_x11_dri3(drv, disp);
> diff --git a/src/egl/main/egldriver.c b/src/egl/main/egldriver.c
> index 33f8f57aeb11e06f92f2..1ff37850e05f729dd35a 100644
> --- a/src/egl/main/egldriver.c
> +++ b/src/egl/main/egldriver.c
> @@ -44,6 +44,8 @@
>  #include "egldriver.h"
>  #include "egllog.h"
>
> +#include "util/debug.h"
> +
>  static mtx_t _eglModuleMutex = _MTX_INITIALIZER_NP;
>  static _EGLDriver *_eglDriver;
>
> @@ -86,7 +88,8 @@ _eglMatchDriver(_EGLDisplay *dpy)
> assert(!dpy->Initialized);
>
> /* set options */
> -   dpy->Options.UseFallback = EGL_FALSE;
> +   dpy->Options.UseFallback =
> +  env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false);
>
> best_drv = _eglMatchAndInitialize(dpy);
> if (!best_drv) {
> --
> Cheers,
>   Eric
>
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Re: [Mesa-dev] [PATCH v2 1/8] egl: add dri2_egl_surface_free_outdated_buffers_and_update_size() helper (v2)

[Gurchetan Singh]

> Then again, I'd suggest keeping that as separate series. These patches
> started as a way to minimise the duplication we have in drivers/dri2.

I'm fine with dri2_$action_$object.  We can modify the existing functions
later, but I recommend adopting more concise conventions in this patchset,
i.e:

dri2_egl_surface_record_buffers_and_update_back_buffer -->
dri2_set_back_buffer_surface
dri2_egl_surface_free_outdated_buffers_and_update_size -->
dri2_fixup_surface
dri2_egl_surface_update_buffer_age --> dri2_update_age_surface
dri2_egl_surface_get_image_front --> dri2_get_front_image_surface

> goal the series is to a) remove a handful of the ifdef spaghetti and

I agree, struct dri2_egl_surface can be refactored. I would advocate a
solution where the surface (a) has everything a platform needs but nothing
else (b) has a minimal amount of duplication.  I would like to look at the
struct and see if it defines buffers[5], it must mean the platform
implements get_buffers_with_format for example.  If a platform doesn't
define color_buffers, it means EXT_buffer_age is not used for whatever
reason.  Everything has dri_image_front -- then everything must use the
image extension.  I think this type of self-consistency is useful, from a
code is documentation point of view.  Here's pseudo-code of what I would
want:

#if not defined(SURFACELESS)

__DRIbuffer  buffers[5];

#if not defined(PLATFORM_X11)

struct {
 void *native_buffer; // aka wl_buffer/gbm_bo/ANativeWindowBuffer
 boollocked;
 int age;
 void *private // aka dri_image, linear_copy, *data used by platform_wayland
} color_buffers[COLOR_BUFFERS_SIZE], *back, *current;

/* EGL-owned buffers */
__DRIbuffer   *local_buffers[__DRI_BUFFER_COUNT];

#endif
#endif

WDYT?

On Wed, Oct 18, 2017 at 2:55 AM, Emil Velikov 
wrote:

> On 17 October 2017 at 21:38, Gurchetan Singh
>  wrote:
> > The naming is verbose and somewhat inconsistent.  We have:
> >
> > dri2_init_surface
> > dri2_fini_surface
> > dri2_egl_surface_alloc_local_buffer
> > dri2_egl_surface_free_local_buffers
> >
> > I suggest you implement the following convention:
> >
> > dri2_surface_init
> > dri2_surface_fini
> > dri2_surface_alloc_attachment (instead of 'local_buffers')
> > dri2_surface_free_attachments  (instead of 'local_buffers')
> >
> Suggestions seems great, although I'm a bit unsure on the naming
> convention - dri2_$object_$action vs dri2_$action_$object.
> Most of src/egl/drivers/dri2/ alongside all of src/egl/main/ use the
> latter.
>
> Then again, I'd suggest keeping that as separate series. These patches
> started as a way to minimise the duplication we have in drivers/dri2.
> So that new platforms such as Tizen do not need to copy the lot, again.
>
> > and instead of dri2_egl_surface_free_outdated_buffers_and_update_size,
> we
> > can just have:
> >
> > dri2_surface_update
> >
> Modulo naming convention (aka dri2_update_surface) I like the name.
>
> > And can you wrap these functions around the:
> >
> > #if defined(HAVE_WAYLAND_PLATFORM) || defined(HAVE_DRM_PLATFORM) ||
> > defined(HAVE_ANDROID_PLATFORM)
> >
> > pre-processors checks just to make clear what platforms use the
> attachment
> > (aka 'local_buffers') functionality.
> >
> While technically correct, I'd opt against this. Sort of a secondary
> goal the series is to a) remove a handful of the ifdef spaghetti and
> b) unify the diverging platforms.
> Of which surfaceless and android being the [rather] odd ones out.
>
> We could continue to minimise the diversion as time goes by, and this
> steers us in the right direction.
>
> Thanks
> Emil
>
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Re: [Mesa-dev] [PATCH 1/2] radv: stop redundent setting of active_stages

[Timothy Arceri]

Whoops I've fixed redundent -> redundant locally
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Re: [Mesa-dev] [PATCH v2] docs: add documentation for building with meson

[Eric Engestrom]

On Wednesday, 2017-10-18 18:09:22 +, Dylan Baker wrote:
> v2: - Add information about CC, CXX, CFLAGS, and CXXFLAGS (Nicolai)
> - Add message at top that meson for mesa is still a work in progress
> - Add trailing "/" to directories (Eric E.)
> - Fix a number of spelling/grammar/style suggestions from Eric E.
> - Make a number of changes as suggested by Emil.
> 
> Signed-off-by: Dylan Baker 
> ---
>  docs/contents.html |   1 +
>  docs/meson.html| 126 
> +
>  2 files changed, 127 insertions(+)
>  create mode 100644 docs/meson.html
> 
> diff --git a/docs/contents.html b/docs/contents.html
> index d5455421091..9a86019e2f6 100644
> --- a/docs/contents.html
> +++ b/docs/contents.html
> @@ -43,6 +43,7 @@
>  Compiling / Installing
>
>  Autoconf
> +Meson
>
>  
>  Precompiled Libraries
> diff --git a/docs/meson.html b/docs/meson.html
> new file mode 100644
> index 000..9f933382965
> --- /dev/null
> +++ b/docs/meson.html
> @@ -0,0 +1,126 @@
> + "http://www.w3.org/TR/html4/loose.dtd;>
> +
> +
> +  
> +  Compilation and Installation using Meson
> +  
> +
> +
> +
> +
> +  The Mesa 3D Graphics Library
> +
> +
> +
> +
> +
> +Compilation and Installation using Meson
> +
> +1. Basic Usage
> +
> +The Meson build system for Mesa is still under active development,
> +and should not be used in production environments.
> +
> +
> +The meson program is used to configure the source directory and generates
> +either a ninja build file, or Visual Studio® build files. The latter, and 
> must

s/, and//

> +be enabled via the --backend switch, as ninja is always the default. Meson 
> only
> +supports out-of-tree builds, and must be passed a directory to put built and
> +generated sources into. We'll call that directory "build" for examples.
> +
> +
> +
> +meson build/
> +
> +
> +
> +To see a description of your options you can run "meson configure" with no
> +arguments. This will show your meson global arguments and project arguments,
> +along with their defaults and your local settings.
> +
> +
> +
> +meson configure build/
> +
> +
> +
> +With arguments "meson configure" is used to change options on already
> +configured build directory. All options passed to this command are in the 
> form
> +-D"command"="value".

s/command/option/, and I think you can drop the quotes?

> +
> +
> +
> +meson configure build/ -Dprefix=/tmp/install -Dglx=true
> +
> +
> +
> +Once you've run meson successfully you can use your configured backend to 
> build
> +the project. With ninja, the -C option can be be used to point at a directory
> +to build.
> +
> +
> +
> +ninja -C build/
> +
> +
> +
> +Without arguments, it will produce libGL.so and/or several other libraries
> +depending on the options you have chosen. Later, if you want to rebuild for a
> +different configuration, you should run ninja clean before
> +rebuilding, or create a new out of tree build directory (meson supports an
> +unlimited number of them) for each configuration you want to build.
> +
> +
> +CC, CFLAGS, CXX, CXXFLAGS
> +These environment variables
> +control the C and C++ compilers used during the build. The default compilers
> +depends on your operating system. Meson supports most of the popular 
> compilers,
> +a complete list is available
> +http://mesonbuild.com/Reference-tables.html#compiler-ids;>here.
> +
> +These arguments are consumed and stored by meson when it is initialized or
> +re-initialized. Therefore passing them to meson configure will not do 
> anything,
> +and passing them to ninja will only do something if ninja decides to
> +re-initialze meson, for example, if a meson.build file has been changed.
> +Changing these variables will not cause all targets to be rebuilt, so running
> +ninja clean is recomended when changing any of these variables.
> +
> +
> +
> +CC=clang CXX=clang++ meson build-clang
> +ninja -C build-clang
> +
> +touch meson.build
> +ninja -C build-clang clean
> +CFLAGS=-Wno-typedef-redefinition ninja -C build-clang

`touch` should be after `clean`, otherwise `clean` will execute the
regeneration, and the CFLAGS will come too late.

Do you want to also mention Lyude's question about using a non-standard
llvm-config here? It was surprisingly trivial to do :)

Other than that, this v2 is:
Reviewed-by: Eric Engestrom 

> +
> +
> +PKG_CONFIG_PATH
> +The
> +pkg-config utility is a hard requirement for configuring and
> +building Mesa on Linux and BSD. It is used to search for external libraries
> +on the system. This environment variable is used to control the search
> +path for pkg-config. For instance, setting
> +PKG_CONFIG_PATH=/usr/X11R6/lib/pkgconfig will search for
> +package metadata in /usr/X11R6 before the standard
> +directories.
> +
> +
> +
> +
> +One of the oddities of meson is that some options are different when passed 
> to
> +the meson than to meson 

[Mesa-dev] [PATCH 2/2] radv: copy indirect lowering settings from radeonsi

[Timothy Arceri]

It looks the original indirect mask was probably copied from
ANV.

Sascha Willems demo results:

tessellation ~4000 -> ~4200 fps

V2: continue lowering local indirect due to llvm deficiencies.

Cc: Alex Smith 
---
 src/amd/vulkan/radv_shader.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 055787a705..faba0c50e9 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -238,22 +238,47 @@ radv_shader_compile_to_nir(struct radv_device *device,
NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
NIR_PASS_V(nir, nir_lower_system_values);
NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
}
 
/* Vulkan uses the separate-shader linking model */
nir->info.separate_shader = true;
 
nir_shader_gather_info(nir, entry_point->impl);
 
+   /* While it would be nice not to have this flag, we are constrained
+* by the reality that LLVM 5.0 doesn't have working VGPR indexing
+* on GFX9.
+*/
+   bool llvm_has_working_vgpr_indexing =
+   device->physical_device->rad_info.chip_class <= VI;
+
+   /* TODO: Indirect indexing of GS inputs is unimplemented.
+*
+* TCS and TES load inputs directly from LDS or offchip memory, so
+* indirect indexing is trivial.
+*/
nir_variable_mode indirect_mask = 0;
-   indirect_mask |= nir_var_shader_in;
+   if (nir->stage == MESA_SHADER_GEOMETRY ||
+   (nir->stage != MESA_SHADER_TESS_CTRL &&
+nir->stage != MESA_SHADER_TESS_EVAL &&
+!llvm_has_working_vgpr_indexing)) {
+   indirect_mask |= nir_var_shader_in;
+   }
+
+   /* TODO: We shouldn't need to do this, however LLVM isn't currently
+* smart enough to handle indirects without causing excess spilling
+* causing the gpu to hang.
+*
+* See the following thread for more details of the problem:
+* https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
+*/
indirect_mask |= nir_var_local;
 
nir_lower_indirect_derefs(nir, indirect_mask);
 
static const nir_lower_tex_options tex_options = {
  .lower_txp = ~0,
};
 
nir_lower_tex(nir, _options);
 
-- 
2.13.6

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[Mesa-dev] [PATCH 1/2] radv: stop redundent setting of active_stages

[Timothy Arceri]

We already set it when above in the nir compilation loop.
---
 src/amd/vulkan/radv_pipeline.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7102d07a03..15ef428be4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1641,32 +1641,28 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
   pipeline->layout, keys ? 
keys + MESA_SHADER_FRAGMENT : 0,
   
[MESA_SHADER_FRAGMENT], _sizes[MESA_SHADER_FRAGMENT]);
 
/* TODO: These are no longer used as keys we should refactor 
this */
if (keys) {
keys[MESA_SHADER_VERTEX].vs.export_prim_id =

pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =

pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
}
-
-   pipeline->active_stages |= 
mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
}
 
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if(modules[i] && !pipeline->shaders[i]) {
pipeline->shaders[i] = 
radv_shader_variant_create(device, modules[i], nir[i],
  
pipeline->layout,
  keys 
? keys + i : 0, [i],
  
_sizes[i]);
-
-   pipeline->active_stages |= mesa_to_vk_shader_stage(i);
}
}
 
if(modules[MESA_SHADER_GEOMETRY]) {
void *gs_copy_code = NULL;
unsigned gs_copy_code_size = 0;
if (!pipeline->gs_copy_shader) {
pipeline->gs_copy_shader = radv_create_gs_copy_shader(
device, nir[MESA_SHADER_GEOMETRY], 
_copy_code,
_copy_code_size,
-- 
2.13.6

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Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

[Dylan Baker]

Quoting Nicholas Miell (2017-10-18 11:45:19)
> On 10/17/2017 12:21 PM, Dylan Baker wrote:
> > +
> > +To see a description of your options you can run "meson configure". This 
> > will
> > +show your meson project configuration options as well as your local
> > +configuration options. One meson option to be aware of is that meson's 
> > default
> > +build type is "debug" (-O0 -g on gcc/clang).
> > +
> > +
> > +
> > +meson configure build
> > +
> > +
> 
> There should probably be a warning here about how there's no way to 
> export a build configuration and how every minor or point update of 
> meson requires you to delete your build directories and reconfigure 
> everything from scratch.
> 
> Also how user-supplied C/C++ flags get merged in with Meson's idea of 
> what the flags should be with the debug/debugoptimized/release 
> configurations and if you want complete control of the build flags you 
> should use the "plain" build type.

I can add something about setting -Ox and -g options should be used with
--buildtype=plain

Dylan


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Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

[Dylan Baker]

Quoting Eric Engestrom (2017-10-18 14:48:49)
> On Wednesday, 2017-10-18 18:45:19 +, Nicholas Miell wrote:
> > On 10/17/2017 12:21 PM, Dylan Baker wrote:
> > > +
> > > +To see a description of your options you can run "meson configure". This 
> > > will
> > > +show your meson project configuration options as well as your local
> > > +configuration options. One meson option to be aware of is that meson's 
> > > default
> > > +build type is "debug" (-O0 -g on gcc/clang).
> > > +
> > > +
> > > +
> > > +meson configure build
> > > +
> > > +
> > 
> > There should probably be a warning here about how there's no way to export a
> > build configuration and how every minor or point update of meson requires
> > you to delete your build directories and reconfigure everything from
> > scratch.
> 
> Agreed, the delete & reconfigure thing is really annoying, I'm hoping
> this will be fixed eventually :/
> 
> As for exporting the config, I'm actually working on this area of
> meson's code right now, it would be quite easy for me to add a 'dump'
> feature.
> I'm guessing something like autotool's `./config.status --config` that
> can just be fed back to the next run of `meson` would be good?
> 
> I haven't actually yet figured out if I can only print the options that
> don't have their default value, so what I can do for now is a trivial
> 'dump all the current values'. Would that be interesting to you?

I don't think that the meson IR has an concept of default values for options,
the interpreter just passes the default value as the value if one isn't given. I
do think this is a nice feature, and I was thinking about doing it myself, once
the 0.43.1 release happens and upstream starts pulling feature requests again.
One though I had was just to save the command line options in a text file so you
could do something like:

meson build-1.0 `cat build-0.9/options.txt`

Dylan


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Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

[Eric Engestrom]

On Wednesday, 2017-10-18 18:45:19 +, Nicholas Miell wrote:
> On 10/17/2017 12:21 PM, Dylan Baker wrote:
> > +
> > +To see a description of your options you can run "meson configure". This 
> > will
> > +show your meson project configuration options as well as your local
> > +configuration options. One meson option to be aware of is that meson's 
> > default
> > +build type is "debug" (-O0 -g on gcc/clang).
> > +
> > +
> > +
> > +meson configure build
> > +
> > +
> 
> There should probably be a warning here about how there's no way to export a
> build configuration and how every minor or point update of meson requires
> you to delete your build directories and reconfigure everything from
> scratch.

Agreed, the delete & reconfigure thing is really annoying, I'm hoping
this will be fixed eventually :/

As for exporting the config, I'm actually working on this area of
meson's code right now, it would be quite easy for me to add a 'dump'
feature.
I'm guessing something like autotool's `./config.status --config` that
can just be fed back to the next run of `meson` would be good?

I haven't actually yet figured out if I can only print the options that
don't have their default value, so what I can do for now is a trivial
'dump all the current values'. Would that be interesting to you?

> 
> Also how user-supplied C/C++ flags get merged in with Meson's idea of what
> the flags should be with the debug/debugoptimized/release configurations and
> if you want complete control of the build flags you should use the "plain"
> build type.
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Re: [Mesa-dev] [PATCH] tgsi: fix tgsi_util_get_inst_usage_mask

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Wed, Oct 18, 2017 at 11:17 PM,   wrote:
> From: Roland Scheidegger 
>
> The logic for handling shadow coords was completely broken.
> Fixes be3ab867bd444594f9d9e0f8e59d305d15769afd.
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103265
> ---
>  src/gallium/auxiliary/tgsi/tgsi_util.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c 
> b/src/gallium/auxiliary/tgsi/tgsi_util.c
> index be8bcdf..cfce590 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_util.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
> @@ -292,17 +292,17 @@ tgsi_util_get_inst_usage_mask(const struct 
> tgsi_full_instruction *inst,
> case TGSI_OPCODE_TXL2:
> case TGSI_OPCODE_LODQ:
> case TGSI_OPCODE_TG4: {
> -  unsigned dim_layer_shadow =
> +  unsigned dim_layer =
>   tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
> -  unsigned dim_layer, dim;
> +  unsigned dim_layer_shadow, dim;
>
> -  /* Remove shadow. */
> +  /* Add shadow. */
>if (tgsi_is_shadow_target(inst->Texture.Texture)) {
> - dim_layer = dim_layer_shadow - 1;
> + dim_layer_shadow = dim_layer + 1;
>   if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D)
> -dim_layer = 1;
> +dim_layer_shadow = 3;
>} else {
> - dim_layer = dim_layer_shadow;
> + dim_layer_shadow = dim_layer;
>}
>
>/* Remove layer. */
> --
> 2.7.4
>
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[Mesa-dev] [PATCH] tgsi: fix tgsi_util_get_inst_usage_mask

[sroland]

From: Roland Scheidegger 

The logic for handling shadow coords was completely broken.
Fixes be3ab867bd444594f9d9e0f8e59d305d15769afd.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103265
---
 src/gallium/auxiliary/tgsi/tgsi_util.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c 
b/src/gallium/auxiliary/tgsi/tgsi_util.c
index be8bcdf..cfce590 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -292,17 +292,17 @@ tgsi_util_get_inst_usage_mask(const struct 
tgsi_full_instruction *inst,
case TGSI_OPCODE_TXL2:
case TGSI_OPCODE_LODQ:
case TGSI_OPCODE_TG4: {
-  unsigned dim_layer_shadow =
+  unsigned dim_layer =
  tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
-  unsigned dim_layer, dim;
+  unsigned dim_layer_shadow, dim;
 
-  /* Remove shadow. */
+  /* Add shadow. */
   if (tgsi_is_shadow_target(inst->Texture.Texture)) {
- dim_layer = dim_layer_shadow - 1;
+ dim_layer_shadow = dim_layer + 1;
  if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D)
-dim_layer = 1;
+dim_layer_shadow = 3;
   } else {
- dim_layer = dim_layer_shadow;
+ dim_layer_shadow = dim_layer;
   }
 
   /* Remove layer. */
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it

[Samuel Pitoiset]

Quite bad fix.. I will have a better look tomorrow.

Please ignore.

On 10/18/2017 10:15 PM, Samuel Pitoiset wrote:

Only on CIK and later. We should only update VGT_INDEX_TYPE but
it seems easier to re-emit all the index buffer packets.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_cmd_buffer.c | 8 
  1 file changed, 8 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ae2f28f5fd..02eef2e4c1 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1777,6 +1777,14 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer 
*cmd_buffer,
cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
}
  
+	/* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE, so the

+* state must be re-emitted before the next indexed draw.
+*/
+   if (!indexed_draw &&
+   cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
+   cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
+   }
+
radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
  
  	radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);



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[Mesa-dev] [PATCH] radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it

[Samuel Pitoiset]

Only on CIK and later. We should only update VGT_INDEX_TYPE but
it seems easier to re-emit all the index buffer packets.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ae2f28f5fd..02eef2e4c1 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1777,6 +1777,14 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer 
*cmd_buffer,
cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
}
 
+   /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE, so the
+* state must be re-emitted before the next indexed draw.
+*/
+   if (!indexed_draw &&
+   cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
+   cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
+   }
+
radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
 
radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 02/15] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v2)

[Mario Kleiner]

On 10/10/2017 12:51 PM, Tapani Pälli wrote:

On 10/06/2017 07:11 PM, Mario Kleiner wrote:

Expose formats which are supported at least back to Gen 5 Ironlake,
possibly further. Allow creation of 10 bpc winsys buffers for drawables.

glxinfo now lists new RGBA 10 10 10 2/0 formats.
Works correctly under DRI2 without compositing.

v2: Move the BGRA/BGRX1010102 formats before the RGBA/RGBX
 32 bit formats, as the code comments require. Thanks Emil!
 Update num_formats from 3 to 5, to keep the special Android
 handling intact.

Signed-off-by: Mario Kleiner 
---
  src/mesa/drivers/dri/i965/intel_screen.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c

index 712cd40..9c0539d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1567,7 +1567,13 @@ intelCreateBuffer(__DRIscreen *dri_screen,
    fb->Visual.samples = num_samples;
 }
-   if (mesaVis->redBits == 5) {
+   if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
+  rgbFormat = mesaVis->redMask == 0x3ff0 ? 
MESA_FORMAT_B10G10R10A2_UNORM
+ : 
MESA_FORMAT_R10G10B10A2_UNORM;

+   } else if (mesaVis->redBits == 10) {
+  rgbFormat = mesaVis->redMask == 0x3ff0 ? 
MESA_FORMAT_B10G10R10X2_UNORM
+ : 
MESA_FORMAT_R10G10B10X2_UNORM;

+   } else if (mesaVis->redBits == 5) {
    rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
 : MESA_FORMAT_B5G6R5_UNORM;
 } else if (mesaVis->sRGBCapable) {
@@ -1949,6 +1955,10 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
    MESA_FORMAT_B8G8R8A8_UNORM,
    MESA_FORMAT_B8G8R8X8_UNORM,
+  /* For 10 bpc, 30 bit depth framebuffers. */
+  MESA_FORMAT_B10G10R10A2_UNORM,
+  MESA_FORMAT_B10G10R10X2_UNORM,
+
    /* The 32-bit RGBA format must not precede the 32-bit BGRA 
format.
 * Likewise for RGBX and BGRX.  Otherwise, the GLX client and 
the GLX
 * server may disagree on which format the GLXFBConfig 
represents,

@@ -1988,7 +1998,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING))
    num_formats = ARRAY_SIZE(formats);
 else
-  num_formats = 3;
+  num_formats = 5;


How about following:
num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */

(I'm suggesting it here https://patchwork.freedesktop.org/patch/177410/)

Not a big deal though, with or without this patch looks correct.

Reviewed-by: Tapani Pälli 

// Tapani


Good idea. I've changed that patch accordingly. Thanks for the review.
-mario

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Re: [Mesa-dev] [PATCH 2/2] radv: do not re-emit the index buffer for every draw call

[Samuel Pitoiset]

On 10/18/2017 09:54 PM, Dave Airlie wrote:

On 19 October 2017 at 04:56, Bas Nieuwenhuizen  wrote:

Interesting that we already had RADV_CMD_DIRTY_INDEX_BUFFER. r-b for the series.

On Wed, Oct 18, 2017 at 2:17 PM, Samuel Pitoiset
 wrote:

It can only be changed when CmdBindIndexBuffer() is called
or when a secondary buffer is used. Though not always, but
let's re-emit the packets in this situation for now.


There is some hw issue around resetting the index type that my brain
can't come up with,

/* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
  * so the state must be re-emitted before the next indexed draw.
  */

Just make sure we still do the right thing here before pushing.


Mmmh, I have pushed the patch already, I'm going to have a look.



Dave.


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Re: [Mesa-dev] [PATCH 2/2] radv: do not re-emit the index buffer for every draw call

[Dave Airlie]

On 19 October 2017 at 04:56, Bas Nieuwenhuizen  wrote:
> Interesting that we already had RADV_CMD_DIRTY_INDEX_BUFFER. r-b for the 
> series.
>
> On Wed, Oct 18, 2017 at 2:17 PM, Samuel Pitoiset
>  wrote:
>> It can only be changed when CmdBindIndexBuffer() is called
>> or when a secondary buffer is used. Though not always, but
>> let's re-emit the packets in this situation for now.

There is some hw issue around resetting the index type that my brain
can't come up with,

/* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
 * so the state must be re-emitted before the next indexed draw.
 */

Just make sure we still do the right thing here before pushing.

Dave.
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Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

[Eric Engestrom]

On Wednesday, 2017-10-18 17:29:20 +, Dylan Baker wrote:
> Quoting Eric Engestrom (2017-10-18 04:02:07)
> > On Tuesday, 2017-10-17 19:21:10 +, Dylan Baker wrote:
> > > Signed-off-by: Dylan Baker 
> > > ---
> > > 
> > > I'm sending this out now so that others can look at it, review it, and 
> > > reference
> > > it, but this should not end up in the 17.3 release, as the meson build 
> > > for mesa
> > > will not be ready to go into the 17.3 release.
> > 
> > Good point, but we could also merge it with a note at the top of the
> > page:
> > > Mesa has not yet been fully converted to use Meson. You should not use
> > > Meson for production builds yet.
> 
> Sure, that would work too.

Just realized I forgot to say, this is:
Reviewed-by: Eric Engestrom 

> 
> > 
> > > 
> > >  docs/contents.html |  1 +
> > >  docs/meson.html| 99 
> > > ++
> > >  2 files changed, 100 insertions(+)
> > >  create mode 100644 docs/meson.html
> > > 
> > > diff --git a/docs/contents.html b/docs/contents.html
> > > index d5455421091..9a86019e2f6 100644
> > > --- a/docs/contents.html
> > > +++ b/docs/contents.html
> > > @@ -43,6 +43,7 @@
> > >  Compiling / Installing
> > >
> > >  Autoconf
> > > +Meson
> > >
> > >  
> > >  Precompiled Libraries
> > > diff --git a/docs/meson.html b/docs/meson.html
> > > new file mode 100644
> > > index 000..f45a62c9da4
> > > --- /dev/null
> > > +++ b/docs/meson.html
> > > @@ -0,0 +1,99 @@
> > > + > > "http://www.w3.org/TR/html4/loose.dtd;>
> > > +
> > > +
> > > +  
> > > +  Compilation and Installation using Meson
> > > +  
> > > +
> > > +
> > > +
> > > +
> > > +  The Mesa 3D Graphics Library
> > > +
> > > +
> > > +
> > > +
> > > +
> > > +Compilation and Installation using Meson
> > > +
> > > +1. Basic Usage
> > > +
> > > +
> > > +The meson program is used to configure the source directory and generates
> > > +either a ninja build file, or visual studio build files. The meson Visual
> > > +Studio® backend is only available on Microsoft® Windows®, and must be 
> > > enabled
> > > +via the --backend switch, as ninja is always the default. Meson only 
> > > supports
> > > +out-of-tree builds, and must be passed a directory to put built and 
> > > generated
> > > +sources into. We'll call that directory "build" for examples.
> > 
> > Suggestion: use `build/` with a trailing slash to make it explicit that
> > this is a directory, unlike make targets for instance.
> > 
> > > +
> > > +
> > > +
> > > +meson build
> > > +
> > > +
> > > +
> > > +To see a description of your options you can run "meson configure". This 
> > > will
> > 
> > s/This will/Without arguments, it will/
> > 
> > > +show your meson project configuration options as well as your local
> > > +configuration options.
> > 
> > + You can set any of these options by passing `-Doptionname=value`.
> > + Only the option passed in is affected, there is no need to specify
> > + already set options again.
> > 
> > Side note, I'm working on a TUI for meson, similar to cmake's `ccmake` :)
> > 
> > > +One meson option to be aware of is that meson's default
> > > +build type is "debug" (-O0 -g on gcc/clang).
> > > +
> > > +
> > > +
> > > +meson configure build
> > > +
> > > +
> > > +Once you're run meson successfully you can use your configured backend 
> > > to build
> > 
> > typo: "you've"
> > 
> > > +the project, for Linux/*BSD and macOS that will be ninja. If you're 
> > > unfamiliar
> > > +with ninja, it automatically detects your CPU's and sets it's jobs
> > 
> > "detects your number of cores and set its number of jobs"
> > 
> > > +appropriately. The -C option allows us to point ninja at the build 
> > > directory
> > > +without changing into it.
> > > +
> > > +
> > > +ninja -C build
> > > +
> > > +
> > > +
> > > +This will produce libGL.so and/or several other libraries depending on 
> > > the
> > > +options you have chosen. Later, if you want to rebuild for a different
> > > +configuration run ninja clean before rebuilding, or create 
> > > a new
> > 
> > "configuration, you should run"
> > 
> > > +out of tree build directory, meson supports an unlimited number of them, 
> > > for 
> > 
> > nit: use brackets here, instead of commas
> > 
> > > +each configuration you want to build.
> > > +
> > > +
> > > +CC, CFLAGS, CXX, CXXFLAGS
> > > +These environment variables
> > > +control the C and C++ compilers used during the build. The default 
> > > compilers
> > > +depends on your operating system. Meson supports GCC, Clang, and MSVC as 
> > > first
> > > +class compilers. There is some support for the Intel ICC compiler. No 
> > > other
> > > +C/C++ compilers are currently supported.
> > > +
> > > +
> > > +PKG_CONFIG_PATH
> > > +The
> > > +pkg-config utility is a hard requirement for configuring and
> > > +building mesa. It is used to search for external libraries
> > 
> > s/mesa/Mesa/
> > 
> > > +on the system. 

Re: [Mesa-dev] Upstream support for FreeSync / Adaptive Sync

[Daniel Vetter]

On Wed, Oct 18, 2017 at 6:59 PM, Michel Dänzer  wrote:
> On 18/10/17 12:15 PM, Nicolai Hähnle wrote:
>> On 18.10.2017 10:10, Daniel Vetter wrote:
>>> On Tue, Oct 17, 2017 at 09:01:52PM +0200, Nicolai Hähnle wrote:
 On 17.10.2017 19:16, Daniel Vetter wrote:
> On Tue, Oct 17, 2017 at 5:40 PM, Michel Dänzer 
> wrote:
>> On 17/10/17 05:04 PM, Daniel Vetter wrote:
>>> On Tue, Oct 17, 2017 at 03:46:24PM +0200, Michel Dänzer wrote:
 On 17/10/17 02:22 PM, Daniel Vetter wrote:
> On Tue, Oct 17, 2017 at 12:28:17PM +0200, Michel Dänzer wrote:
>> On 17/10/17 11:34 AM, Nicolai Hähnle wrote:
>
>>> Common sense suggests that there need to be two side to
>>> FreeSync / VESA
>>> Adaptive Sync support:
>>>
>>> 1. Query the display capabilities. This means querying minimum
>>> / maximum
>>> refresh duration, plus possibly a query for when the
>>> earliest/latest
>>> timing of the *next* refresh.
>>>
>>> 2. Signal desired present time. This means passing a target
>>> timer value
>>> instead of a target vblank count, e.g. something like this for
>>> the KMS
>>> interface:
>>>
>>> int drmModePageFlipTarget64(int fd, uint32_t crtc_id,
>>> uint32_t fb_id,
>>> uint32_t flags, void *user_data,
>>> uint64_t target);
>>>
>>> + a flag to indicate whether target is the vblank count or
>>> the
>>> CLOCK_MONOTONIC (?) time in ns.
>>
>> drmModePageFlip(Target) is part of the pre-atomic KMS API, but
>> adapative
>> sync should probably only be supported via the atomic API,
>> presumably
>> via output properties.
>
> +1
>
> At least now that DC is on track to land properly, and you want
> to do this
> for DC-only anyway there's no reason to pimp the legacy interfaces
> further. And atomic is soo much easier to extend.
>
> The big question imo is where we need to put the flag on the kms
> side,
> since freesync is not just about presenting earlier, but also about
> presenting later. But for backwards compat we can't stretch the
> refresh
> rate by default for everyone, or clients that rely on high
> precision
> timestamps and regular refresh will get a bad surprise.

 The idea described above is that adaptive sync would be used for
 flips
 with a target timestamp. Apps which don't want to use adaptive sync
 wouldn't set a target timestamp.


> I think a boolean enable_freesync property is probably what we
> want, which
> enables freesync for as long as it's set.

 The question then becomes under what circumstances the property
 is (not)
 set. Not sure offhand this will actually solve any problem, or
 just push
 it somewhere else.
>>>
>>> I thought that's what the driconf switch is for, with a policy of
>>> "please
>>> schedule asap" instead of a specific timestamp.
>>
>> The driconf switch is just for the user's intention to use adaptive
>> sync
>> when possible. A property as you suggest cannot be set by the client
>> directly, because it can't know when adaptive sync can actually be
>> used
>> (only when its window is fullscreen and using page flipping). So the
>> property would have to be set by the X server/driver / Wayland
>> compositor / ... instead. The question is whether such a property is
>> actually needed, or whether the kernel could just enable adaptive sync
>> when there's a flip with a target timestamp, and disable it when
>> there's
>> a flip without a target timestamp, or something like that.
>
> If your adaptive sync also supports extending the vblank beyond the
> nominal limit, then you can't do that with a per-flip flag. Because
> absent of a userspace requesting adaptive sync you must flip at the
> nominal vrefresh rate. So if your userspace is a tad bit late with the
> frame and would like to extend the frame to avoid missing a frame
> entirely it'll be too late by the time the vblank actually gets
> submitted. That's a bit a variation of what Ville brought up about
> what we're going to do when the timestamp was missed by the time all
> the depending fences signalled.

 These are very good points. It does sound like we'd need both an
 "AdaptiveSync" boolean property and an (optional) "DesiredPresentTime"
 property.

 The DesiredPresentTime property applies only to a single commit and
 could
 perhaps be left out in a first 

Re: [Mesa-dev] [PATCH] radv/winsys: bump the buffer hash table size to 4096

[Samuel Pitoiset]

On 10/18/2017 08:53 PM, Bas Nieuwenhuizen wrote:

I'd prefer not to. The current size is already huge when you consider
that a lot of applications use pretty small command buffers, adding
another 12k per command buffer is a bit much. I'd prefer not having
that overhead, since the GL_vs_VK benchmarks were IIRC not really
representative.


Yeah, good point, and I don't think this can improve any real applications.



On Wed, Oct 18, 2017 at 2:47 PM, Samuel Pitoiset
 wrote:

This reduces the number of conflicts when a bunch of buffers
are added to the CS list. It improves the benchmark #3 (from
GL_vs_VK) by +3/4%.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 53d428681c..4adbe27b2e 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -59,7 +59,7 @@ struct radv_amdgpu_cs {
 boolfailed;
 boolis_chained;

-   int buffer_hash_table[1024];
+   int buffer_hash_table[4096];
 unsignedhw_ip;

 unsignednum_virtual_buffers;
--
2.14.2

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[Mesa-dev] [Bug 103266] [llvmpipe] piglit sampler-cube-shadow regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103266

Roland Scheidegger  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |DUPLICATE

--- Comment #1 from Roland Scheidegger  ---
This is all really the same bug, so don't need multiple bugs.

*** This bug has been marked as a duplicate of bug 103265 ***

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[Mesa-dev] [Bug 103265] [llvmpipe] piglit depth-tex-compare regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103265

--- Comment #4 from Roland Scheidegger  ---
*** Bug 103266 has been marked as a duplicate of this bug. ***

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[Mesa-dev] [Bug 103265] [llvmpipe] piglit depth-tex-compare regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103265

--- Comment #3 from Roland Scheidegger  ---
*** Bug 103268 has been marked as a duplicate of this bug. ***

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[Mesa-dev] [Bug 103268] [llvmpipe] piglit texdepth regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103268
Bug 103268 depends on bug 103350, which changed state.

Bug 103350 Summary: llvmpipe regressions due to be3ab867
https://bugs.freedesktop.org/show_bug.cgi?id=103350

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |DUPLICATE

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[Mesa-dev] [Bug 103265] [llvmpipe] piglit depth-tex-compare regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103265
Bug 103265 depends on bug 103350, which changed state.

Bug 103350 Summary: llvmpipe regressions due to be3ab867
https://bugs.freedesktop.org/show_bug.cgi?id=103350

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |DUPLICATE

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[Mesa-dev] [Bug 103350] llvmpipe regressions due to be3ab867

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103350

Roland Scheidegger  changed:

   What|Removed |Added

 Resolution|--- |DUPLICATE
 Status|NEW |RESOLVED

--- Comment #1 from Roland Scheidegger  ---
There's already 3 bugs for this, we don't need a fourth.

*** This bug has been marked as a duplicate of bug 103265 ***

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