[Mesa-dev] [Bug 106315] The witness + dxvk suffers flickering garbage

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106315

soredake  changed:

   What|Removed |Added

 CC||fds...@krutt.org

-- 
You are receiving this mail because:
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 18/19] radv: Remove deref chain support in radv shader info pass.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_shader_info.c | 98 ++-
 1 file changed, 5 insertions(+), 93 deletions(-)

diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index bdf30ead2f8..ab424720de1 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -47,49 +47,9 @@ static void mark_tess_output(struct radv_shader_info *info,
info->tcs.outputs_written |= (mask << param);
 }
 
-static void get_deref_offset(nir_deref_var *deref, unsigned *const_out)
-{
-   nir_deref *tail = >deref;
-   unsigned const_offset = 0;
-
-   if (deref->var->data.compact) {
-   assert(tail->child->deref_type == nir_deref_type_array);
-   
assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
-
-   nir_deref_array *deref_array = nir_deref_as_array(tail->child);
-   /* We always lower indirect dereferences for "compact" array 
vars. */
-   assert(deref_array->deref_array_type == 
nir_deref_array_type_direct);
-
-   *const_out = deref_array->base_offset;
-   return;
-   }
-
-   while (tail->child != NULL) {
-   const struct glsl_type *parent_type = tail->type;
-   tail = tail->child;
-
-   if (tail->deref_type == nir_deref_type_array) {
-   nir_deref_array *deref_array = nir_deref_as_array(tail);
-   unsigned size = glsl_count_attribute_slots(tail->type, 
false);
-
-   const_offset += size * deref_array->base_offset;
-   } else if (tail->deref_type == nir_deref_type_struct) {
-   nir_deref_struct *deref_struct = 
nir_deref_as_struct(tail);
-
-   for (unsigned i = 0; i < deref_struct->index; i++) {
-   const struct glsl_type *ft = 
glsl_get_struct_field(parent_type, i);
-   const_offset += glsl_count_attribute_slots(ft, 
false);
-   }
-   } else
-   unreachable("unsupported deref type");
-   }
-
-   *const_out = const_offset;
-}
-
 static void
-get_deref_instr_offset(nir_deref_instr *instr,
-   unsigned *const_out)
+get_deref_offset(nir_deref_instr *instr,
+ unsigned *const_out)
 {
 nir_variable *var = nir_deref_instr_get_variable(instr);
 nir_deref_path path;
@@ -135,7 +95,6 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
  struct radv_shader_info *info)
 {
switch (instr->intrinsic) {
-   case nir_intrinsic_interp_var_at_sample:
case nir_intrinsic_interp_deref_at_sample:
info->ps.needs_sample_positions = true;
break;
@@ -189,41 +148,6 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
case nir_intrinsic_vulkan_resource_index:
info->desc_set_used_mask |= (1 << 
nir_intrinsic_desc_set(instr));
break;
-   case nir_intrinsic_image_var_load:
-   case nir_intrinsic_image_var_store:
-   case nir_intrinsic_image_var_atomic_add:
-   case nir_intrinsic_image_var_atomic_min:
-   case nir_intrinsic_image_var_atomic_max:
-   case nir_intrinsic_image_var_atomic_and:
-   case nir_intrinsic_image_var_atomic_or:
-   case nir_intrinsic_image_var_atomic_xor:
-   case nir_intrinsic_image_var_atomic_exchange:
-   case nir_intrinsic_image_var_atomic_comp_swap:
-   case nir_intrinsic_image_var_size: {
-   const struct glsl_type *type = 
glsl_without_array(instr->variables[0]->var->type);
-
-   enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
-   if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
-   dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
-   info->ps.layer_input = true;
-   info->ps.uses_input_attachments = true;
-   }
-   mark_sampler_desc(instr->variables[0]->var, info);
-
-   if (nir_intrinsic_image_var_store ||
-   nir_intrinsic_image_var_atomic_add ||
-   nir_intrinsic_image_var_atomic_min ||
-   nir_intrinsic_image_var_atomic_max ||
-   nir_intrinsic_image_var_atomic_and ||
-   nir_intrinsic_image_var_atomic_or ||
-   nir_intrinsic_image_var_atomic_xor ||
-   nir_intrinsic_image_var_atomic_exchange ||
-   nir_intrinsic_image_var_atomic_comp_swap) {
-   if (nir->info.stage == MESA_SHADER_FRAGMENT)
-   info->ps.writes_memory = true;
-   }
-   break;
-   }
case nir_intrinsic_image_deref_load:
case nir_intrinsic_image_deref_store:
case nir_intrinsic_image_deref_atomic_add:

[Mesa-dev] [PATCH 14/19] radeonsi: Add deref support to the nir scan pass.

[Bas Nieuwenhuizen]

---
 src/gallium/drivers/radeonsi/si_shader_nir.c | 74 
 1 file changed, 59 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index b4fba8b8812..21551a76d6b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -32,6 +32,30 @@
 #include "compiler/nir/nir.h"
 #include "compiler/nir_types.h"
 
+static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
+{
+   if (instr->texture)
+   return instr->texture->var;
+
+   for (unsigned i = 0; i < instr->num_srcs; i++) {
+   switch (instr->src[i].src_type) {
+   case nir_tex_src_texture_deref:
+   return 
nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
+   default:
+   break;
+   }
+   }
+
+   return NULL;
+}
+
+static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
+{
+   if (instr->variables[0])
+   return instr->variables[0]->var;
+
+   return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
+}
 
 static void scan_instruction(struct tgsi_shader_info *info,
 nir_instr *instr)
@@ -53,12 +77,13 @@ static void scan_instruction(struct tgsi_shader_info *info,
}
} else if (instr->type == nir_instr_type_tex) {
nir_tex_instr *tex = nir_instr_as_tex(instr);
+   nir_variable *texture = tex_get_texture_var(tex);
 
-   if (!tex->texture) {
+   if (!texture) {
info->samplers_declared |=
u_bit_consecutive(tex->sampler_index, 1);
} else {
-   if (tex->texture->var->data.bindless)
+   if (texture->data.bindless)
info->uses_bindless_samplers = true;
}
 
@@ -126,8 +151,11 @@ static void scan_instruction(struct tgsi_shader_info *info,
break;
case nir_intrinsic_image_var_load:
case nir_intrinsic_image_var_size:
-   case nir_intrinsic_image_var_samples: {
-   nir_variable *var = intr->variables[0]->var;
+   case nir_intrinsic_image_var_samples:
+   case nir_intrinsic_image_deref_load:
+   case nir_intrinsic_image_deref_size:
+   case nir_intrinsic_image_deref_samples: {
+   nir_variable *var = intrinsic_get_var(intr);
if (var->data.bindless)
info->uses_bindless_images = true;
 
@@ -141,8 +169,17 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_image_var_atomic_or:
case nir_intrinsic_image_var_atomic_xor:
case nir_intrinsic_image_var_atomic_exchange:
-   case nir_intrinsic_image_var_atomic_comp_swap: {
-   nir_variable *var = intr->variables[0]->var;
+   case nir_intrinsic_image_var_atomic_comp_swap:
+   case nir_intrinsic_image_deref_store:
+   case nir_intrinsic_image_deref_atomic_add:
+   case nir_intrinsic_image_deref_atomic_min:
+   case nir_intrinsic_image_deref_atomic_max:
+   case nir_intrinsic_image_deref_atomic_and:
+   case nir_intrinsic_image_deref_atomic_or:
+   case nir_intrinsic_image_deref_atomic_xor:
+   case nir_intrinsic_image_deref_atomic_exchange:
+   case nir_intrinsic_image_deref_atomic_comp_swap: {
+   nir_variable *var = intrinsic_get_var(intr);
if (var->data.bindless)
info->uses_bindless_images = true;
 
@@ -161,8 +198,9 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_ssbo_atomic_comp_swap:
info->writes_memory = true;
break;
-   case nir_intrinsic_load_var: {
-   nir_variable *var = intr->variables[0]->var;
+   case nir_intrinsic_load_var:
+   case nir_intrinsic_load_deref: {
+   nir_variable *var = intrinsic_get_var(intr);
nir_variable_mode mode = var->data.mode;
enum glsl_base_type base_type =

glsl_get_base_type(glsl_without_array(var->type));
@@ -197,23 +235,29 @@ static void scan_instruction(struct tgsi_shader_info 
*info,
}
case nir_intrinsic_interp_var_at_centroid:
case nir_intrinsic_interp_var_at_sample:
-   case nir_intrinsic_interp_var_at_offset: {
-   enum glsl_interp_mode interp =
-

[Mesa-dev] [PATCH 06/19] ac/nir: Add deref support to image intrinsics.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 130 
 1 file changed, 97 insertions(+), 33 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1a22cadb750..0f27ba66374 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2125,18 +2125,61 @@ static LLVMValueRef 
adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
return sample_index;
 }
 
+static bool is_var_image_intrinsic(const nir_intrinsic_instr *instr)
+{
+   switch(instr->intrinsic) {
+   case nir_intrinsic_image_var_samples:
+   case nir_intrinsic_image_var_load:
+   case nir_intrinsic_image_var_store:
+   case nir_intrinsic_image_var_atomic_add:
+   case nir_intrinsic_image_var_atomic_min:
+   case nir_intrinsic_image_var_atomic_max:
+   case nir_intrinsic_image_var_atomic_and:
+   case nir_intrinsic_image_var_atomic_or:
+   case nir_intrinsic_image_var_atomic_xor:
+   case nir_intrinsic_image_var_atomic_exchange:
+   case nir_intrinsic_image_var_atomic_comp_swap:
+   case nir_intrinsic_image_var_size:
+   return true;
+   default:
+   return false;
+   }
+}
+
+static nir_variable *get_image_variable(const nir_intrinsic_instr *instr)
+{
+   if (is_var_image_intrinsic(instr))
+   return instr->variables[0]->var;
+
+   assert(instr->src[0].is_ssa);
+   return 
nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+}
+
+static LLVMValueRef get_image_descriptor(struct ac_nir_context *ctx,
+ const nir_intrinsic_instr *instr,
+ enum ac_descriptor_type desc_type,
+ bool write)
+{
+   if (is_var_image_intrinsic(instr))
+   return get_sampler_desc(ctx, instr->variables[0], NULL, 
desc_type, NULL, true, true);
+
+   return get_sampler_desc(ctx, NULL, 
nir_instr_as_deref(instr->src[0].ssa->parent_instr), desc_type, NULL, true, 
true);
+}
+
 static void get_image_coords(struct ac_nir_context *ctx,
 const nir_intrinsic_instr *instr,
 struct ac_image_args *args)
 {
-   const struct glsl_type *type = 
glsl_without_array(instr->variables[0]->var->type);
+   /* As the deref instrinsics have the deref as src 0, everything is 
shifted. */
+   int src_shift = is_var_image_intrinsic(instr) ? 0 : 1;
+   const struct glsl_type *type = 
glsl_without_array(get_image_variable(instr)->type);
 
-   LLVMValueRef src0 = get_src(ctx, instr->src[0]);
+   LLVMValueRef src0 = get_src(ctx, instr->src[src_shift]);
LLVMValueRef masks[] = {
LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 
1, false),
LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 
3, false),
};
-   LLVMValueRef sample_index = ac_llvm_extract_elem(>ac, get_src(ctx, 
instr->src[1]), 0);
+   LLVMValueRef sample_index = ac_llvm_extract_elem(>ac, get_src(ctx, 
instr->src[src_shift + 1]), 0);
 
int count;
enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
@@ -2171,10 +2214,10 @@ static void get_image_coords(struct ac_nir_context *ctx,
   
fmask_load_address[1],
   
fmask_load_address[2],
   sample_index,
-  
get_sampler_desc(ctx, instr->variables[0], NULL, AC_DESC_FMASK, NULL, true, 
false));
+  
get_image_descriptor(ctx, instr, AC_DESC_FMASK, false));
}
if (count == 1 && !gfx9_1d) {
-   if (instr->src[0].ssa->num_components)
+   if (instr->src[src_shift].ssa->num_components)
args->coords[0] = 
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
else
args->coords[0] = src0;
@@ -2217,7 +2260,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
 static LLVMValueRef get_image_buffer_descriptor(struct ac_nir_context *ctx,
 const nir_intrinsic_instr 
*instr, bool write)
 {
-   LLVMValueRef rsrc = get_sampler_desc(ctx, instr->variables[0], NULL, 
AC_DESC_BUFFER, NULL, true, write);
+   LLVMValueRef rsrc = get_image_descriptor(ctx, instr, AC_DESC_BUFFER, 
write);
if (ctx->abi->gfx9_stride_size_workaround) {
LLVMValueRef elem_count = 
LLVMBuildExtractElement(ctx->ac.builder, rsrc, LLVMConstInt(ctx->ac.i32, 2, 0), 
"");
LLVMValueRef stride = LLVMBuildExtractElement(ctx->ac.builder, 
rsrc, LLVMConstInt(ctx->ac.i32, 1, 0), "");
@@ -2237,22 +2280,22 @@ 

[Mesa-dev] [PATCH 15/19] radv: Stop lowering deref instructions.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_shader.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index d52471fe9e4..72c05afef4e 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -179,8 +179,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(exec_list_length(>functions) == 1);
struct exec_node *node = exec_list_get_head(>functions);
entry_point = exec_node_data(nir_function, node, node);
-
-   NIR_PASS_V(nir, nir_lower_deref_instrs, ~0);
} else {
uint32_t *spirv = (uint32_t *) module->data;
assert(module->size % 4 == 0);
@@ -255,8 +253,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(exec_list_length(>functions) == 1);
entry_point->name = ralloc_strdup(entry_point, "main");
 
-   NIR_PASS_V(nir, nir_lower_deref_instrs, ~0);
-
/* Make sure we lower constant initializers on output variables 
so that
 * nir_remove_dead_variables below sees the corresponding stores
 */
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 19/19] radeonsi: Remove deref chain support in nir scan pass.

[Bas Nieuwenhuizen]

---
 src/gallium/drivers/radeonsi/si_shader_nir.c | 34 +++-
 1 file changed, 4 insertions(+), 30 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 21551a76d6b..c46d0ab5a82 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -34,9 +34,6 @@
 
 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
 {
-   if (instr->texture)
-   return instr->texture->var;
-
for (unsigned i = 0; i < instr->num_srcs; i++) {
switch (instr->src[i].src_type) {
case nir_tex_src_texture_deref:
@@ -51,9 +48,6 @@ static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
 
 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
 {
-   if (instr->variables[0])
-   return instr->variables[0]->var;
-
return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
 }
 
@@ -149,9 +143,6 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_load_tess_level_outer:
info->reads_tess_factors = true;
break;
-   case nir_intrinsic_image_var_load:
-   case nir_intrinsic_image_var_size:
-   case nir_intrinsic_image_var_samples:
case nir_intrinsic_image_deref_load:
case nir_intrinsic_image_deref_size:
case nir_intrinsic_image_deref_samples: {
@@ -161,15 +152,6 @@ static void scan_instruction(struct tgsi_shader_info *info,
 
break;
}
-   case nir_intrinsic_image_var_store:
-   case nir_intrinsic_image_var_atomic_add:
-   case nir_intrinsic_image_var_atomic_min:
-   case nir_intrinsic_image_var_atomic_max:
-   case nir_intrinsic_image_var_atomic_and:
-   case nir_intrinsic_image_var_atomic_or:
-   case nir_intrinsic_image_var_atomic_xor:
-   case nir_intrinsic_image_var_atomic_exchange:
-   case nir_intrinsic_image_var_atomic_comp_swap:
case nir_intrinsic_image_deref_store:
case nir_intrinsic_image_deref_atomic_add:
case nir_intrinsic_image_deref_atomic_min:
@@ -198,7 +180,6 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_ssbo_atomic_comp_swap:
info->writes_memory = true;
break;
-   case nir_intrinsic_load_var:
case nir_intrinsic_load_deref: {
nir_variable *var = intrinsic_get_var(intr);
nir_variable_mode mode = var->data.mode;
@@ -233,9 +214,6 @@ static void scan_instruction(struct tgsi_shader_info *info,
}
break;
}
-   case nir_intrinsic_interp_var_at_centroid:
-   case nir_intrinsic_interp_var_at_sample:
-   case nir_intrinsic_interp_var_at_offset:
case nir_intrinsic_interp_deref_at_centroid:
case nir_intrinsic_interp_deref_at_sample:
case nir_intrinsic_interp_deref_at_offset: {
@@ -243,21 +221,17 @@ static void scan_instruction(struct tgsi_shader_info 
*info,
switch (interp) {
case INTERP_MODE_SMOOTH:
case INTERP_MODE_NONE:
-   if (intr->intrinsic == 
nir_intrinsic_interp_var_at_centroid ||
-   intr->intrinsic == 
nir_intrinsic_interp_deref_at_centroid)
+   if (intr->intrinsic == 
nir_intrinsic_interp_deref_at_centroid)
info->uses_persp_opcode_interp_centroid 
= true;
-   else if (intr->intrinsic == 
nir_intrinsic_interp_var_at_sample ||
-intr->intrinsic == 
nir_intrinsic_interp_deref_at_sample)
+   else if (intr->intrinsic == 
nir_intrinsic_interp_deref_at_sample)
info->uses_persp_opcode_interp_sample = 
true;
else
info->uses_persp_opcode_interp_offset = 
true;
break;
case INTERP_MODE_NOPERSPECTIVE:
-   if (intr->intrinsic == 
nir_intrinsic_interp_var_at_centroid ||
-   intr->intrinsic == 
nir_intrinsic_interp_deref_at_centroid)
+   if (intr->intrinsic == 
nir_intrinsic_interp_deref_at_centroid)

info->uses_linear_opcode_interp_centroid = true;
-   else if (intr->intrinsic == 

[Mesa-dev] [PATCH 12/19] radv: Use deref instructions for tex derefs in meta shaders.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_meta.c| 20 ++
 src/amd/vulkan/radv_meta_blit.c   | 30 +++
 src/amd/vulkan/radv_meta_blit2d.c | 21 ---
 src/amd/vulkan/radv_meta_bufimage.c   | 22 
 src/amd/vulkan/radv_meta_fast_clear.c |  7 ---
 5 files changed, 62 insertions(+), 38 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 56b72d1c99b..00a20d155e7 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -515,18 +515,20 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
nir_ssa_def *tmp;
nir_if *outer_if = NULL;
 
-   nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
+   nir_ssa_def *input_img_deref = _build_deref_var(b, 
input_img)->dest.ssa;
+
+   nir_tex_instr *tex = nir_tex_instr_create(b->shader, 3);
tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
tex->op = nir_texop_txf_ms;
tex->src[0].src_type = nir_tex_src_coord;
tex->src[0].src = nir_src_for_ssa(img_coord);
tex->src[1].src_type = nir_tex_src_ms_index;
tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
+   tex->src[2].src_type = nir_tex_src_texture_deref;
+   tex->src[2].src = nir_src_for_ssa(input_img_deref);
tex->dest_type = nir_type_float;
tex->is_array = false;
tex->coord_components = 2;
-   tex->texture = nir_deref_var_create(tex, input_img);
-   tex->sampler = NULL;
 
nir_ssa_dest_init(>instr, >dest, 4, 32, "tex");
nir_builder_instr_insert(b, >instr);
@@ -534,16 +536,16 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
tmp = >dest.ssa;
 
if (!is_integer && samples > 1) {
-   nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 
1);
+   nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 
2);
tex_all_same->sampler_dim = GLSL_SAMPLER_DIM_MS;
tex_all_same->op = nir_texop_samples_identical;
tex_all_same->src[0].src_type = nir_tex_src_coord;
tex_all_same->src[0].src = nir_src_for_ssa(img_coord);
+   tex_all_same->src[1].src_type = nir_tex_src_texture_deref;
+   tex_all_same->src[1].src = nir_src_for_ssa(input_img_deref);
tex_all_same->dest_type = nir_type_float;
tex_all_same->is_array = false;
tex_all_same->coord_components = 2;
-   tex_all_same->texture = nir_deref_var_create(tex_all_same, 
input_img);
-   tex_all_same->sampler = NULL;
 
nir_ssa_dest_init(_all_same->instr, _all_same->dest, 1, 
32, "tex");
nir_builder_instr_insert(b, _all_same->instr);
@@ -555,18 +557,18 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 
b->cursor = nir_after_cf_list(_stmt->then_list);
for (int i = 1; i < samples; i++) {
-   nir_tex_instr *tex_add = 
nir_tex_instr_create(b->shader, 2);
+   nir_tex_instr *tex_add = 
nir_tex_instr_create(b->shader, 3);
tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
tex_add->op = nir_texop_txf_ms;
tex_add->src[0].src_type = nir_tex_src_coord;
tex_add->src[0].src = nir_src_for_ssa(img_coord);
tex_add->src[1].src_type = nir_tex_src_ms_index;
tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(b, 
i));
+   tex_add->src[2].src_type = nir_tex_src_texture_deref;
+   tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
tex_add->dest_type = nir_type_float;
tex_add->is_array = false;
tex_add->coord_components = 2;
-   tex_add->texture = nir_deref_var_create(tex_add, 
input_img);
-   tex_add->sampler = NULL;
 
nir_ssa_dest_init(_add->instr, _add->dest, 4, 
32, "tex");
nir_builder_instr_insert(b, _add->instr);
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 3ff48498d80..a6ee0cb7e93 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -131,16 +131,20 @@ build_nir_copy_fragment_shader(enum glsl_sampler_dim 
tex_dim)
sampler->data.descriptor_set = 0;
sampler->data.binding = 0;
 
-   nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
+   nir_ssa_def *tex_deref = _build_deref_var(, sampler)->dest.ssa;
+
+   nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
tex->sampler_dim = tex_dim;
tex->op = nir_texop_tex;
tex->src[0].src_type = nir_tex_src_coord;
tex->src[0].src = nir_src_for_ssa(tex_pos);
+   tex->src[1].src_type = nir_tex_src_texture_deref;
+   

[Mesa-dev] [PATCH 16/19] st/nir: Stop lowering deref instructions.

[Bas Nieuwenhuizen]

---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 3fdfebdc1fe..8d80c8cae22 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -580,8 +580,6 @@ st_nir_get_mesa_program(struct gl_context *ctx,
 
nir_shader *nir = st_glsl_to_nir(st, prog, shader_program, shader->Stage);
 
-   nir_lower_deref_instrs(nir, (nir_lower_deref_flags)~0);
-
set_st_program(prog, shader_program, nir);
prog->nir = nir;
 }
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 08/19] ac/nir: Add deref based var loads/stores.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 207 
 1 file changed, 160 insertions(+), 47 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0f27ba66374..73ac6c482d3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -27,6 +27,7 @@
 #include "ac_binary.h"
 #include "sid.h"
 #include "nir/nir.h"
+#include "nir/nir_deref.h"
 #include "util/bitscan.h"
 #include "util/u_math.h"
 #include "ac_shader_abi.h"
@@ -1627,6 +1628,75 @@ static LLVMValueRef visit_load_ubo_buffer(struct 
ac_nir_context *ctx,
get_def_type(ctx, >dest.ssa), "");
 }
 
+static void
+get_deref_instr_offset(struct ac_nir_context *ctx, nir_deref_instr *instr,
+  bool vs_in, unsigned *vertex_index_out,
+  LLVMValueRef *vertex_index_ref,
+  unsigned *const_out, LLVMValueRef *indir_out)
+{
+   nir_variable *var = nir_deref_instr_get_variable(instr);
+   nir_deref_path path;
+   unsigned idx_lvl = 1;
+
+   nir_deref_path_init(, instr, NULL);
+
+   if (vertex_index_out != NULL || vertex_index_ref != NULL) {
+   if (vertex_index_ref) {
+   *vertex_index_ref = get_src(ctx, 
path.path[idx_lvl]->arr.index);
+   if (vertex_index_out)
+   *vertex_index_out = 0;
+   } else {
+   nir_const_value *v = 
nir_src_as_const_value(path.path[idx_lvl]->arr.index);
+   assert(v);
+   *vertex_index_out = v->u32[0];
+   }
+   ++idx_lvl;
+   }
+
+   uint32_t const_offset = 0;
+   LLVMValueRef offset = NULL;
+
+   if (var->data.compact) {
+   assert(instr->deref_type == nir_deref_type_array);
+   nir_const_value *v = nir_src_as_const_value(instr->arr.index);
+   assert(v);
+   const_offset = v->u32[0];
+   goto out;
+   }
+
+   for (; path.path[idx_lvl]; ++idx_lvl) {
+   const struct glsl_type *parent_type = path.path[idx_lvl - 
1]->type;
+   if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
+   unsigned index = path.path[idx_lvl]->strct.index;
+
+   for (unsigned i = 0; i < index; i++) {
+   const struct glsl_type *ft = 
glsl_get_struct_field(parent_type, i);
+   const_offset += glsl_count_attribute_slots(ft, 
vs_in);
+   }
+   } else if(path.path[idx_lvl]->deref_type == 
nir_deref_type_array) {
+   unsigned size = 
glsl_count_attribute_slots(path.path[idx_lvl]->type, vs_in);
+   LLVMValueRef array_off = LLVMBuildMul(ctx->ac.builder, 
LLVMConstInt(ctx->ac.i32, size, 0),
+ get_src(ctx, 
path.path[idx_lvl]->arr.index), "");
+   if (offset)
+   offset = LLVMBuildAdd(ctx->ac.builder, offset, 
array_off, "");
+   else
+   offset = array_off;
+   } else
+   unreachable("Uhandled deref type in 
get_deref_instr_offset");
+   }
+
+out:
+   nir_deref_path_finish();
+
+   if (const_offset && offset)
+   offset = LLVMBuildAdd(ctx->ac.builder, offset,
+ LLVMConstInt(ctx->ac.i32, const_offset, 
0),
+ "");
+
+   *const_out = const_offset;
+   *indir_out = offset;
+}
+
 static void
 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
 bool vs_in, unsigned *vertex_index_out,
@@ -1753,14 +1823,25 @@ static LLVMValueRef load_tess_varyings(struct 
ac_nir_context *ctx,
LLVMValueRef vertex_index = NULL;
LLVMValueRef indir_index = NULL;
unsigned const_index = 0;
-   unsigned location = instr->variables[0]->var->data.location;
-   unsigned driver_location = 
instr->variables[0]->var->data.driver_location;
-   const bool is_patch =  instr->variables[0]->var->data.patch;
-   const bool is_compact = instr->variables[0]->var->data.compact;
 
-   get_deref_offset(ctx, instr->variables[0],
-false, NULL, is_patch ? NULL : _index,
-_index, _index);
+   bool uses_deref_chain = instr->intrinsic == nir_intrinsic_load_var;
+   nir_variable *var = uses_deref_chain ? instr->variables[0]->var :
+
nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+
+   unsigned location = var->data.location;
+   unsigned driver_location = var->data.driver_location;
+   const bool is_patch =  var->data.patch;
+   const bool is_compact = var->data.compact;
+
+   

[Mesa-dev] [PATCH 10/19] ac/nir: Add shared atomic deref instr support.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 73ac6c482d3..d8cb33e26ed 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2806,7 +2806,8 @@ static LLVMValueRef visit_var_atomic(struct 
ac_nir_context *ctx,
LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
 
if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
-   instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
+   instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap ||
+   instr->intrinsic == nir_intrinsic_deref_atomic_comp_swap) {
LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
ptr, src, src1,
@@ -2819,38 +2820,47 @@ static LLVMValueRef visit_var_atomic(struct 
ac_nir_context *ctx,
switch (instr->intrinsic) {
case nir_intrinsic_var_atomic_add:
case nir_intrinsic_shared_atomic_add:
+   case nir_intrinsic_deref_atomic_add:
op = LLVMAtomicRMWBinOpAdd;
break;
case nir_intrinsic_var_atomic_umin:
case nir_intrinsic_shared_atomic_umin:
+   case nir_intrinsic_deref_atomic_umin:
op = LLVMAtomicRMWBinOpUMin;
break;
case nir_intrinsic_var_atomic_umax:
case nir_intrinsic_shared_atomic_umax:
+   case nir_intrinsic_deref_atomic_umax:
op = LLVMAtomicRMWBinOpUMax;
break;
case nir_intrinsic_var_atomic_imin:
case nir_intrinsic_shared_atomic_imin:
+   case nir_intrinsic_deref_atomic_imin:
op = LLVMAtomicRMWBinOpMin;
break;
case nir_intrinsic_var_atomic_imax:
case nir_intrinsic_shared_atomic_imax:
+   case nir_intrinsic_deref_atomic_imax:
op = LLVMAtomicRMWBinOpMax;
break;
case nir_intrinsic_var_atomic_and:
case nir_intrinsic_shared_atomic_and:
+   case nir_intrinsic_deref_atomic_and:
op = LLVMAtomicRMWBinOpAnd;
break;
case nir_intrinsic_var_atomic_or:
case nir_intrinsic_shared_atomic_or:
+   case nir_intrinsic_deref_atomic_or:
op = LLVMAtomicRMWBinOpOr;
break;
case nir_intrinsic_var_atomic_xor:
case nir_intrinsic_shared_atomic_xor:
+   case nir_intrinsic_deref_atomic_xor:
op = LLVMAtomicRMWBinOpXor;
break;
case nir_intrinsic_var_atomic_exchange:
case nir_intrinsic_shared_atomic_exchange:
+   case nir_intrinsic_deref_atomic_exchange:
op = LLVMAtomicRMWBinOpXchg;
break;
default:
@@ -3233,6 +3243,20 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = visit_var_atomic(ctx, instr, ptr, 0);
break;
}
+   case nir_intrinsic_deref_atomic_add:
+   case nir_intrinsic_deref_atomic_imin:
+   case nir_intrinsic_deref_atomic_umin:
+   case nir_intrinsic_deref_atomic_imax:
+   case nir_intrinsic_deref_atomic_umax:
+   case nir_intrinsic_deref_atomic_and:
+   case nir_intrinsic_deref_atomic_or:
+   case nir_intrinsic_deref_atomic_xor:
+   case nir_intrinsic_deref_atomic_exchange:
+   case nir_intrinsic_deref_atomic_comp_swap: {
+   LLVMValueRef ptr = get_src(ctx, instr->src[0]);
+   result = visit_var_atomic(ctx, instr, ptr, 1);
+   break;
+   }
case nir_intrinsic_interp_var_at_centroid:
case nir_intrinsic_interp_var_at_sample:
case nir_intrinsic_interp_var_at_offset:
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 13/19] radv: Remove image_var stores.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_meta_bufimage.c   | 40 +--
 src/amd/vulkan/radv_meta_fast_clear.c | 10 +++
 src/amd/vulkan/radv_meta_resolve_cs.c | 10 +++
 3 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_bufimage.c 
b/src/amd/vulkan/radv_meta_bufimage.c
index 147d2ea46ef..aa17c25833b 100644
--- a/src/amd/vulkan/radv_meta_bufimage.c
+++ b/src/amd/vulkan/radv_meta_bufimage.c
@@ -115,11 +115,11 @@ build_nir_itob_compute_shader(struct radv_device *dev, 
bool is_3d)
nir_ssa_def *coord = nir_vec4(, tmp, tmp, tmp, tmp);
 
nir_ssa_def *outval = >dest.ssa;
-   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_var_store);
-   store->src[0] = nir_src_for_ssa(coord);
-   store->src[1] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
-   store->src[2] = nir_src_for_ssa(outval);
-   store->variables[0] = nir_deref_var_create(store, output_img);
+   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_deref_store);
+   store->src[0] = nir_src_for_ssa(_build_deref_var(, 
output_img)->dest.ssa);
+   store->src[1] = nir_src_for_ssa(coord);
+   store->src[2] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
+   store->src[3] = nir_src_for_ssa(outval);
 
nir_builder_instr_insert(, >instr);
return b.shader;
@@ -341,11 +341,11 @@ build_nir_btoi_compute_shader(struct radv_device *dev, 
bool is_3d)
nir_builder_instr_insert(, >instr);
 
nir_ssa_def *outval = >dest.ssa;
-   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_var_store);
-   store->src[0] = nir_src_for_ssa(img_coord);
-   store->src[1] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
-   store->src[2] = nir_src_for_ssa(outval);
-   store->variables[0] = nir_deref_var_create(store, output_img);
+   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_deref_store);
+   store->src[0] = nir_src_for_ssa(_build_deref_var(, 
output_img)->dest.ssa);
+   store->src[1] = nir_src_for_ssa(img_coord);
+   store->src[2] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
+   store->src[3] = nir_src_for_ssa(outval);
 
nir_builder_instr_insert(, >instr);
return b.shader;
@@ -556,11 +556,11 @@ build_nir_itoi_compute_shader(struct radv_device *dev, 
bool is_3d)
nir_builder_instr_insert(, >instr);
 
nir_ssa_def *outval = >dest.ssa;
-   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_var_store);
-   store->src[0] = nir_src_for_ssa(dst_coord);
-   store->src[1] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
-   store->src[2] = nir_src_for_ssa(outval);
-   store->variables[0] = nir_deref_var_create(store, output_img);
+   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_deref_store);
+   store->src[0] = nir_src_for_ssa(_build_deref_var(, 
output_img)->dest.ssa);
+   store->src[1] = nir_src_for_ssa(dst_coord);
+   store->src[2] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
+   store->src[3] = nir_src_for_ssa(outval);
 
nir_builder_instr_insert(, >instr);
return b.shader;
@@ -752,11 +752,11 @@ build_nir_cleari_compute_shader(struct radv_device *dev, 
bool is_3d)
comps[3] = nir_imm_int(, 0);
global_id = nir_vec(, comps, 4);
 
-   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_var_store);
-   store->src[0] = nir_src_for_ssa(global_id);
-   store->src[1] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
-   store->src[2] = nir_src_for_ssa(_val->dest.ssa);
-   store->variables[0] = nir_deref_var_create(store, output_img);
+   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_deref_store);
+   store->src[0] = nir_src_for_ssa(_build_deref_var(, 
output_img)->dest.ssa);
+   store->src[1] = nir_src_for_ssa(global_id);
+   store->src[2] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
+   store->src[3] = nir_src_for_ssa(_val->dest.ssa);
 
nir_builder_instr_insert(, >instr);
return b.shader;
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c 
b/src/amd/vulkan/radv_meta_fast_clear.c
index 411d02f231f..041c9e44c45 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -91,11 +91,11 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
nir_builder_instr_insert(, >instr);
 
nir_ssa_def *outval = >dest.ssa;
-   nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, 
nir_intrinsic_image_var_store);
-   store->src[0] = nir_src_for_ssa(global_id);
-   store->src[1] = nir_src_for_ssa(nir_ssa_undef(, 1, 32));
-   store->src[2] = nir_src_for_ssa(outval);
-   store->variables[0] = nir_deref_var_create(store, output_img);
+ 

[Mesa-dev] [PATCH 17/19] ac/nir: Remove deref chain support.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 404 
 1 file changed, 50 insertions(+), 354 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 762520a93a0..0fae6b799ca 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -54,7 +54,6 @@ struct ac_nir_context {
 };
 
 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
-const nir_deref_var *deref,
 nir_deref_instr *deref_instr,
 enum ac_descriptor_type desc_type,
 const nir_tex_instr *instr,
@@ -1323,7 +1322,7 @@ static LLVMValueRef build_tex_intrinsic(struct 
ac_nir_context *ctx,
 
if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
nir_deref_instr *texture_deref_instr = 
get_tex_texture_deref(instr);
-   nir_variable *var = texture_deref_instr ? 
nir_deref_instr_get_variable(texture_deref_instr) : instr->texture->var;
+   nir_variable *var = 
nir_deref_instr_get_variable(texture_deref_instr);
enum glsl_base_type stype = 
glsl_get_sampler_result_type(var->type);
if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
return lower_gather4_integer(>ac, var, args, 
instr);
@@ -1629,10 +1628,10 @@ static LLVMValueRef visit_load_ubo_buffer(struct 
ac_nir_context *ctx,
 }
 
 static void
-get_deref_instr_offset(struct ac_nir_context *ctx, nir_deref_instr *instr,
-  bool vs_in, unsigned *vertex_index_out,
-  LLVMValueRef *vertex_index_ref,
-  unsigned *const_out, LLVMValueRef *indir_out)
+get_deref_offset(struct ac_nir_context *ctx, nir_deref_instr *instr,
+ bool vs_in, unsigned *vertex_index_out,
+ LLVMValueRef *vertex_index_ref,
+ unsigned *const_out, LLVMValueRef *indir_out)
 {
nir_variable *var = nir_deref_instr_get_variable(instr);
nir_deref_path path;
@@ -1697,124 +1696,6 @@ out:
*indir_out = offset;
 }
 
-static void
-get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
-bool vs_in, unsigned *vertex_index_out,
-LLVMValueRef *vertex_index_ref,
-unsigned *const_out, LLVMValueRef *indir_out)
-{
-   unsigned const_offset = 0;
-   nir_deref *tail = >deref;
-   LLVMValueRef offset = NULL;
-
-   if (vertex_index_out != NULL || vertex_index_ref != NULL) {
-   tail = tail->child;
-   nir_deref_array *deref_array = nir_deref_as_array(tail);
-   if (vertex_index_out)
-   *vertex_index_out = deref_array->base_offset;
-
-   if (vertex_index_ref) {
-   LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, 
deref_array->base_offset, false);
-   if (deref_array->deref_array_type == 
nir_deref_array_type_indirect) {
-   vtx = LLVMBuildAdd(ctx->ac.builder, vtx, 
get_src(ctx, deref_array->indirect), "");
-   }
-   *vertex_index_ref = vtx;
-   }
-   }
-
-   if (deref->var->data.compact) {
-   assert(tail->child->deref_type == nir_deref_type_array);
-   
assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
-   nir_deref_array *deref_array = nir_deref_as_array(tail->child);
-   /* We always lower indirect dereferences for "compact" array 
vars. */
-   assert(deref_array->deref_array_type == 
nir_deref_array_type_direct);
-
-   const_offset = deref_array->base_offset;
-   goto out;
-   }
-
-   while (tail->child != NULL) {
-   const struct glsl_type *parent_type = tail->type;
-   tail = tail->child;
-
-   if (tail->deref_type == nir_deref_type_array) {
-   nir_deref_array *deref_array = nir_deref_as_array(tail);
-   LLVMValueRef index, stride, local_offset;
-   unsigned size = glsl_count_attribute_slots(tail->type, 
vs_in);
-
-   const_offset += size * deref_array->base_offset;
-   if (deref_array->deref_array_type == 
nir_deref_array_type_direct)
-   continue;
-
-   assert(deref_array->deref_array_type == 
nir_deref_array_type_indirect);
-   index = get_src(ctx, deref_array->indirect);
-   stride = LLVMConstInt(ctx->ac.i32, size, 0);
-   local_offset = LLVMBuildMul(ctx->ac.builder, stride, 
index, "");
-
-   if (offset)
-   offset = LLVMBuildAdd(ctx->ac.builder, offset, 
local_offset, "");
-   else
-

[Mesa-dev] [PATCH 11/19] ac/nir: Add deref interp support.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 33 +++--
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index d8cb33e26ed..762520a93a0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2897,24 +2897,42 @@ static LLVMValueRef visit_interp(struct ac_nir_context 
*ctx,
LLVMValueRef src_c0 = NULL;
LLVMValueRef src_c1 = NULL;
LLVMValueRef src0 = NULL;
-   int input_index = instr->variables[0]->var->data.location - 
VARYING_SLOT_VAR0;
+   bool uses_deref_chain;
switch (instr->intrinsic) {
case nir_intrinsic_interp_var_at_centroid:
+   case nir_intrinsic_interp_var_at_sample:
+   case nir_intrinsic_interp_var_at_offset:
+   uses_deref_chain = true;
+   break;
+   default:
+   uses_deref_chain = false;
+   break;
+   }
+
+   nir_variable *var = uses_deref_chain ? instr->variables[0]->var : 
nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+   int input_index = var->data.location - VARYING_SLOT_VAR0;
+   switch (instr->intrinsic) {
+   case nir_intrinsic_interp_var_at_centroid:
+   case nir_intrinsic_interp_deref_at_centroid:
location = INTERP_CENTROID;
break;
case nir_intrinsic_interp_var_at_sample:
case nir_intrinsic_interp_var_at_offset:
+   case nir_intrinsic_interp_deref_at_sample:
+   case nir_intrinsic_interp_deref_at_offset:
location = INTERP_CENTER;
-   src0 = get_src(ctx, instr->src[0]);
+   src0 = get_src(ctx, instr->src[uses_deref_chain ? 0 : 1]);
break;
default:
break;
}
 
-   if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
+   if (instr->intrinsic == nir_intrinsic_interp_var_at_offset ||
+   instr->intrinsic == nir_intrinsic_interp_deref_at_offset) {
src_c0 = ac_to_float(>ac, 
LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
src_c1 = ac_to_float(>ac, 
LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
-   } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
+   } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample ||
+  instr->intrinsic == nir_intrinsic_interp_deref_at_sample) {
LLVMValueRef sample_position;
LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
 
@@ -2926,7 +2944,7 @@ static LLVMValueRef visit_interp(struct ac_nir_context 
*ctx,
src_c1 = LLVMBuildExtractElement(ctx->ac.builder, 
sample_position, ctx->ac.i32_1, "");
src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
}
-   interp_param = ctx->abi->lookup_interp_param(ctx->abi, 
instr->variables[0]->var->data.interpolation, location);
+   interp_param = ctx->abi->lookup_interp_param(ctx->abi, 
var->data.interpolation, location);
attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
 
if (location == INTERP_CENTER) {
@@ -2990,7 +3008,7 @@ static LLVMValueRef visit_interp(struct ac_nir_context 
*ctx,
}
}
return ac_build_varying_gather_values(>ac, result, 
instr->num_components,
- 
instr->variables[0]->var->data.location_frac);
+ var->data.location_frac);
 }
 
 static void visit_intrinsic(struct ac_nir_context *ctx,
@@ -3260,6 +3278,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_interp_var_at_centroid:
case nir_intrinsic_interp_var_at_sample:
case nir_intrinsic_interp_var_at_offset:
+   case nir_intrinsic_interp_deref_at_centroid:
+   case nir_intrinsic_interp_deref_at_sample:
+   case nir_intrinsic_interp_deref_at_offset:
result = visit_interp(ctx, instr);
break;
case nir_intrinsic_emit_vertex:
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 04/19] ac/nir: Support deref instructions in tex instructions.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c   | 39 ---
 src/amd/vulkan/radv_shader_info.c | 13 +++
 2 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 29a7ce8e2dc..c6c7af47630 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3237,21 +3237,44 @@ static void tex_fetch_ptrs(struct ac_nir_context *ctx,
   LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
   LLVMValueRef *fmask_ptr)
 {
+   nir_deref_instr *texture_deref_instr = NULL;
+   nir_deref_instr *sampler_deref_instr = NULL;
+   nir_deref_var *texture_deref_var = NULL;
+   nir_deref_var *sampler_deref_var = NULL;
+
+   for (unsigned i = 0; i < instr->num_srcs; i++) {
+   switch (instr->src[i].src_type) {
+   case nir_tex_src_texture_deref:
+   texture_deref_instr = 
nir_src_as_deref(instr->src[i].src);
+   break;
+   case nir_tex_src_sampler_deref:
+   sampler_deref_instr = 
nir_src_as_deref(instr->src[i].src);
+   break;
+   default:
+   break;
+   }
+   }
+
+   if (!sampler_deref_instr)
+   sampler_deref_instr = texture_deref_instr;
+
+   if (!texture_deref_instr) {
+   texture_deref_var = instr->texture;
+   sampler_deref_var = instr->sampler ? instr->sampler : 
instr->texture;
+   }
+
if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF)
-   *res_ptr = get_sampler_desc(ctx, instr->texture, NULL, 
AC_DESC_BUFFER, instr, false, false);
+   *res_ptr = get_sampler_desc(ctx, texture_deref_var, 
texture_deref_instr, AC_DESC_BUFFER, instr, false, false);
else
-   *res_ptr = get_sampler_desc(ctx, instr->texture, NULL, 
AC_DESC_IMAGE, instr, false, false);
+   *res_ptr = get_sampler_desc(ctx, texture_deref_var, 
texture_deref_instr, AC_DESC_IMAGE, instr, false, false);
if (samp_ptr) {
-   if (instr->sampler)
-   *samp_ptr = get_sampler_desc(ctx, instr->sampler, NULL, 
AC_DESC_SAMPLER, instr, false, false);
-   else
-   *samp_ptr = get_sampler_desc(ctx, instr->texture, NULL, 
AC_DESC_SAMPLER, instr, false, false);
+   *samp_ptr = get_sampler_desc(ctx, sampler_deref_var, 
sampler_deref_instr, AC_DESC_SAMPLER, instr, false, false);
if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
*samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, 
*samp_ptr);
}
if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
-instr->op == 
nir_texop_samples_identical))
-   *fmask_ptr = get_sampler_desc(ctx, instr->texture, NULL, 
AC_DESC_FMASK, instr, false, false);
+instr->op == 
nir_texop_samples_identical))
+   *fmask_ptr = get_sampler_desc(ctx, instr->texture, 
texture_deref_instr, AC_DESC_FMASK, instr, false, false);
 }
 
 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 1fb350faed3..57175b3d37b 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -255,6 +255,19 @@ static void
 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
struct radv_shader_info *info)
 {
+   for (unsigned i = 0; i < instr->num_srcs; i++) {
+   switch (instr->src[i].src_type) {
+   case nir_tex_src_texture_deref:
+   
mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)),
 info);
+   break;
+   case nir_tex_src_sampler_deref:
+   
mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)),
 info);
+   break;
+   default:
+   break;
+   }
+   }
+
if (instr->sampler)
mark_sampler_desc(instr->sampler->var, info);
if (instr->texture)
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 09/19] radv: Gather info for deref instr based load/store.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_shader_info.c | 64 +++
 1 file changed, 57 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 5b31703f9cf..bdf30ead2f8 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -23,7 +23,7 @@
 #include "radv_private.h"
 #include "radv_shader.h"
 #include "nir/nir.h"
-
+#include "nir/nir_deref.h"
 static void mark_sampler_desc(const nir_variable *var,
  struct radv_shader_info *info)
 {
@@ -87,12 +87,56 @@ static void get_deref_offset(nir_deref_var *deref, unsigned 
*const_out)
*const_out = const_offset;
 }
 
+static void
+get_deref_instr_offset(nir_deref_instr *instr,
+   unsigned *const_out)
+{
+nir_variable *var = nir_deref_instr_get_variable(instr);
+nir_deref_path path;
+unsigned idx_lvl = 1;
+
+   if (var->data.compact) {
+   assert(instr->deref_type == nir_deref_type_array);
+   nir_const_value *v = nir_src_as_const_value(instr->arr.index);
+   assert(v);
+   *const_out = v->u32[0];
+   return;
+   }
+
+   nir_deref_path_init(, instr, NULL);
+
+   uint32_t const_offset = 0;
+
+   for (; path.path[idx_lvl]; ++idx_lvl) {
+   const struct glsl_type *parent_type = path.path[idx_lvl - 
1]->type;
+   if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
+   unsigned index = path.path[idx_lvl]->strct.index;
+
+   for (unsigned i = 0; i < index; i++) {
+   const struct glsl_type *ft = 
glsl_get_struct_field(parent_type, i);
+   const_offset += glsl_count_attribute_slots(ft, 
false);
+   }
+   } else if(path.path[idx_lvl]->deref_type == 
nir_deref_type_array) {
+   unsigned size = 
glsl_count_attribute_slots(path.path[idx_lvl]->type, false);
+   nir_const_value *v = 
nir_src_as_const_value(path.path[idx_lvl]->arr.index);
+   if (v)
+   const_offset += v->u32[0] * size;
+   } else
+   unreachable("Uhandled deref type in 
get_deref_instr_offset");
+   }
+
+   *const_out = const_offset;
+
+   nir_deref_path_finish();
+}
+
 static void
 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
  struct radv_shader_info *info)
 {
switch (instr->intrinsic) {
case nir_intrinsic_interp_var_at_sample:
+   case nir_intrinsic_interp_deref_at_sample:
info->ps.needs_sample_positions = true;
break;
case nir_intrinsic_load_draw_id:
@@ -231,9 +275,10 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
info->ps.writes_memory = true;
break;
case nir_intrinsic_load_var:
+   case nir_intrinsic_load_deref:
if (nir->info.stage == MESA_SHADER_VERTEX) {
-   nir_deref_var *dvar = instr->variables[0];
-   nir_variable *var = dvar->var;
+   nir_variable *var = instr->intrinsic == 
nir_intrinsic_load_var ? instr->variables[0]->var :
+   
nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 
if (var->data.mode == nir_var_shader_in) {
unsigned idx = var->data.location;
@@ -243,9 +288,10 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
}
}
break;
-   case nir_intrinsic_store_var: {
-   nir_deref_var *dvar = instr->variables[0];
-   nir_variable *var = dvar->var;
+   case nir_intrinsic_store_var:
+   case nir_intrinsic_store_deref: {
+   nir_variable *var = instr->intrinsic == nir_intrinsic_store_var 
? instr->variables[0]->var :
+ 
nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 
if (var->data.mode == nir_var_shader_out) {
unsigned attrib_count = 
glsl_count_attribute_slots(var->type, false);
@@ -253,7 +299,11 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
unsigned comp = var->data.location_frac;
unsigned const_offset = 0;
 
-   get_deref_offset(dvar, _offset);
+
+   if (instr->intrinsic == nir_intrinsic_store_var)
+   get_deref_offset(instr->variables[0], 
_offset);
+   else
+   

[Mesa-dev] [PATCH 01/19] fixup! anv, i965, radv, st, ir3: Call nir_lower_deref_instrs

[Bas Nieuwenhuizen]

Also apply the pass to radv meta shaders.
---
 src/amd/vulkan/radv_shader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index afafea46f0c..d52471fe9e4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -179,6 +179,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(exec_list_length(>functions) == 1);
struct exec_node *node = exec_list_get_head(>functions);
entry_point = exec_node_data(nir_function, node, node);
+
+   NIR_PASS_V(nir, nir_lower_deref_instrs, ~0);
} else {
uint32_t *spirv = (uint32_t *) module->data;
assert(module->size % 4 == 0);
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 00/19] AMD support for NIR deref instructions.

[Bas Nieuwenhuizen]

This implements support in radv and radeonsi for NIR deref
instructions instead of deref chains.

It contains 4 parts:
- patch 1 is a fixup for the initial series by Jason
- Add support everywhere for instruction based derefs
- Stop lowering them to deref chains (may need to be synchronized
  with other drivers and core nir code to keep things bisectable)
- Remove support for deref chains.

You can find this series at

https://github.com/bnieuwenhuizen/mesa/commits/derefs-v1


Bas Nieuwenhuizen (19):
  fixup! anv,i965,radv,st,ir3: Call nir_lower_deref_instrs
  ac/nir: Implement the deref instr for shared memory.
  ac/nir: Support deref instructions in get_sampler_desc.
  ac/nir: Support deref instructions in tex instructions.
  ac/nir: Implement derefs for integer gather4 lowering.
  ac/nir: Add deref support to image intrinsics.
  radv: Add shader info support for image deref instructions.
  ac/nir: Add deref based var loads/stores.
  radv: Gather info for deref instr based load/store.
  ac/nir: Add shared atomic deref instr support.
  ac/nir: Add deref interp support.
  radv: Use deref instructions for tex derefs in meta shaders.
  radv: Remove image_var stores.
  radeonsi: Add deref support to the nir scan pass.
  radv: Stop lowering deref instructions.
  st/nir: Stop lowering deref instructions.
  ac/nir: Remove deref chain support.
  radv: Remove deref chain support in radv shader info pass.
  radeonsi: Remove deref chain support in nir scan pass.

 src/amd/common/ac_nir_to_llvm.c  | 547 ++-
 src/amd/vulkan/radv_meta.c   |  20 +-
 src/amd/vulkan/radv_meta_blit.c  |  30 +-
 src/amd/vulkan/radv_meta_blit2d.c|  21 +-
 src/amd/vulkan/radv_meta_bufimage.c  |  62 ++-
 src/amd/vulkan/radv_meta_fast_clear.c|  17 +-
 src/amd/vulkan/radv_meta_resolve_cs.c|  10 +-
 src/amd/vulkan/radv_shader.c |   2 -
 src/amd/vulkan/radv_shader_info.c| 133 ++---
 src/gallium/drivers/radeonsi/si_shader_nir.c |  72 ++-
 src/mesa/state_tracker/st_glsl_to_nir.cpp|   2 -
 11 files changed, 491 insertions(+), 425 deletions(-)

-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 02/19] ac/nir: Implement the deref instr for shared memory.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index b77d62a39b0..333ecdb834e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3583,6 +3583,34 @@ static void visit_jump(struct ac_llvm_context *ctx,
}
 }
 
+static void visit_deref(struct ac_nir_context *ctx,
+nir_deref_instr *instr)
+{
+   if (instr->mode != nir_var_shared)
+   return;
+
+   LLVMValueRef result = NULL;
+   switch(instr->deref_type) {
+   case nir_deref_type_var: {
+   struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, 
instr->var);
+   result = entry->data;
+   break;
+   }
+   case nir_deref_type_struct:
+   result = ac_build_gep0(>ac, get_src(ctx, instr->parent),
+  LLVMConstInt(ctx->ac.i32, 
instr->strct.index, 0));
+   break;
+   case nir_deref_type_array:
+   result = ac_build_gep0(>ac, get_src(ctx, instr->parent),
+  get_src(ctx, instr->arr.index));
+   break;
+   default:
+   unreachable("Unhandled deref_instr deref type");
+   }
+
+   _mesa_hash_table_insert(ctx->defs, >dest, result);
+}
+
 static void visit_cf_list(struct ac_nir_context *ctx,
   struct exec_list *list);
 
@@ -3613,6 +3641,9 @@ static void visit_block(struct ac_nir_context *ctx, 
nir_block *block)
case nir_instr_type_jump:
visit_jump(>ac, nir_instr_as_jump(instr));
break;
+   case nir_instr_type_deref:
+   visit_deref(ctx, nir_instr_as_deref(instr));
+   break;
default:
fprintf(stderr, "Unknown NIR instr type: ");
nir_print_instr(instr, stderr);
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 07/19] radv: Add shader info support for image deref instructions.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_shader_info.c | 40 ---
 1 file changed, 37 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 57175b3d37b..5b31703f9cf 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -156,9 +156,7 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
case nir_intrinsic_image_var_atomic_exchange:
case nir_intrinsic_image_var_atomic_comp_swap:
case nir_intrinsic_image_var_size: {
-   const struct glsl_type *type = instr->variables[0]->var->type;
-   if(instr->variables[0]->deref.child)
-   type = instr->variables[0]->deref.child->type;
+   const struct glsl_type *type = 
glsl_without_array(instr->variables[0]->var->type);
 
enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
@@ -182,6 +180,42 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
}
break;
}
+   case nir_intrinsic_image_deref_load:
+   case nir_intrinsic_image_deref_store:
+   case nir_intrinsic_image_deref_atomic_add:
+   case nir_intrinsic_image_deref_atomic_min:
+   case nir_intrinsic_image_deref_atomic_max:
+   case nir_intrinsic_image_deref_atomic_and:
+   case nir_intrinsic_image_deref_atomic_or:
+   case nir_intrinsic_image_deref_atomic_xor:
+   case nir_intrinsic_image_deref_atomic_exchange:
+   case nir_intrinsic_image_deref_atomic_comp_swap:
+   case nir_intrinsic_image_deref_size: {
+   nir_variable *var = 
nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+   const struct glsl_type *type = glsl_without_array(var->type);
+
+   enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
+   if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
+   dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
+   info->ps.layer_input = true;
+   info->ps.uses_input_attachments = true;
+   }
+   mark_sampler_desc(var, info);
+
+   if (nir_intrinsic_image_deref_store ||
+   nir_intrinsic_image_deref_atomic_add ||
+   nir_intrinsic_image_deref_atomic_min ||
+   nir_intrinsic_image_deref_atomic_max ||
+   nir_intrinsic_image_deref_atomic_and ||
+   nir_intrinsic_image_deref_atomic_or ||
+   nir_intrinsic_image_deref_atomic_xor ||
+   nir_intrinsic_image_deref_atomic_exchange ||
+   nir_intrinsic_image_deref_atomic_comp_swap) {
+   if (nir->info.stage == MESA_SHADER_FRAGMENT)
+   info->ps.writes_memory = true;
+   }
+   break;
+   }
case nir_intrinsic_store_ssbo:
case nir_intrinsic_ssbo_atomic_add:
case nir_intrinsic_ssbo_atomic_imin:
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 03/19] ac/nir: Support deref instructions in get_sampler_desc.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 58 -
 1 file changed, 43 insertions(+), 15 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 333ecdb834e..29a7ce8e2dc 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -54,6 +54,7 @@ struct ac_nir_context {
 
 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
 const nir_deref_var *deref,
+nir_deref_instr *deref_instr,
 enum ac_descriptor_type desc_type,
 const nir_tex_instr *instr,
 bool image, bool write);
@@ -2151,7 +2152,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
   
fmask_load_address[1],
   
fmask_load_address[2],
   sample_index,
-  
get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
+  
get_sampler_desc(ctx, instr->variables[0], NULL, AC_DESC_FMASK, NULL, true, 
false));
}
if (count == 1 && !gfx9_1d) {
if (instr->src[0].ssa->num_components)
@@ -2197,7 +2198,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
 static LLVMValueRef get_image_buffer_descriptor(struct ac_nir_context *ctx,
 const nir_intrinsic_instr 
*instr, bool write)
 {
-   LLVMValueRef rsrc = get_sampler_desc(ctx, instr->variables[0], 
AC_DESC_BUFFER, NULL, true, write);
+   LLVMValueRef rsrc = get_sampler_desc(ctx, instr->variables[0], NULL, 
AC_DESC_BUFFER, NULL, true, write);
if (ctx->abi->gfx9_stride_size_workaround) {
LLVMValueRef elem_count = 
LLVMBuildExtractElement(ctx->ac.builder, rsrc, LLVMConstInt(ctx->ac.i32, 2, 0), 
"");
LLVMValueRef stride = LLVMBuildExtractElement(ctx->ac.builder, 
rsrc, LLVMConstInt(ctx->ac.i32, 1, 0), "");
@@ -2247,7 +2248,7 @@ static LLVMValueRef visit_image_load(struct 
ac_nir_context *ctx,
struct ac_image_args args = {};
args.opcode = ac_image_load;
get_image_coords(ctx, instr, );
-   args.resource = get_sampler_desc(ctx, instr->variables[0],
+   args.resource = get_sampler_desc(ctx, instr->variables[0], NULL,
 AC_DESC_IMAGE, NULL, true, 
false);
args.dim = get_ac_image_dim(>ac, 
glsl_get_sampler_dim(type),
glsl_sampler_type_is_array(type));
@@ -2290,7 +2291,7 @@ static void visit_image_store(struct ac_nir_context *ctx,
args.opcode = ac_image_store;
args.data[0] = ac_to_float(>ac, get_src(ctx, 
instr->src[2]));
get_image_coords(ctx, instr, );
-   args.resource = get_sampler_desc(ctx, instr->variables[0],
+   args.resource = get_sampler_desc(ctx, instr->variables[0], NULL,
 AC_DESC_IMAGE, NULL, true, 
false);
args.dim = get_ac_image_dim(>ac, 
glsl_get_sampler_dim(type),
glsl_sampler_type_is_array(type));
@@ -2381,7 +2382,7 @@ static LLVMValueRef visit_image_atomic(struct 
ac_nir_context *ctx,
if (cmpswap)
args.data[1] = params[1];
get_image_coords(ctx, instr, );
-   args.resource = get_sampler_desc(ctx, instr->variables[0],
+   args.resource = get_sampler_desc(ctx, instr->variables[0], NULL,
 AC_DESC_IMAGE, NULL, true, 
false);
args.dim = get_ac_image_dim(>ac, 
glsl_get_sampler_dim(type),
glsl_sampler_type_is_array(type));
@@ -2400,7 +2401,7 @@ static LLVMValueRef visit_image_samples(struct 
ac_nir_context *ctx,
args.dim = get_ac_sampler_dim(>ac, glsl_get_sampler_dim(type),
  glsl_sampler_type_is_array(type));
args.dmask = 0xf;
-   args.resource = get_sampler_desc(ctx, instr->variables[0],
+   args.resource = get_sampler_desc(ctx, instr->variables[0], NULL,
 AC_DESC_IMAGE, NULL, true, false);
args.opcode = ac_image_get_resinfo;
args.lod = ctx->ac.i32_0;
@@ -2418,7 +2419,7 @@ static LLVMValueRef visit_image_size(struct 
ac_nir_context *ctx,
 
if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
return get_buffer_size(ctx,
-   get_sampler_desc(ctx, instr->variables[0],
+  

[Mesa-dev] [PATCH 05/19] ac/nir: Implement derefs for integer gather4 lowering.

[Bas Nieuwenhuizen]

---
 src/amd/common/ac_nir_to_llvm.c | 25 ++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c6c7af47630..1a22cadb750 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1134,10 +1134,11 @@ get_buffer_size(struct ac_nir_context *ctx, 
LLVMValueRef descriptor, bool in_ele
 }
 
 static LLVMValueRef lower_gather4_integer(struct ac_llvm_context *ctx,
+ nir_variable *var,
  struct ac_image_args *args,
  const nir_tex_instr *instr)
 {
-   enum glsl_base_type stype = 
glsl_get_sampler_result_type(instr->texture->var->type);
+   enum glsl_base_type stype = glsl_get_sampler_result_type(var->type);
LLVMValueRef half_texel[2];
LLVMValueRef compare_cube_wa = NULL;
LLVMValueRef result;
@@ -1244,6 +1245,22 @@ static LLVMValueRef lower_gather4_integer(struct 
ac_llvm_context *ctx,
return result;
 }
 
+static nir_deref_instr *get_tex_texture_deref(const nir_tex_instr *instr)
+{
+   nir_deref_instr *texture_deref_instr = NULL;
+
+   for (unsigned i = 0; i < instr->num_srcs; i++) {
+   switch (instr->src[i].src_type) {
+   case nir_tex_src_texture_deref:
+   texture_deref_instr = 
nir_src_as_deref(instr->src[i].src);
+   break;
+   default:
+   break;
+   }
+   }
+   return texture_deref_instr;
+}
+
 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
const nir_tex_instr *instr,
struct ac_image_args *args)
@@ -1304,9 +1321,11 @@ static LLVMValueRef build_tex_intrinsic(struct 
ac_nir_context *ctx,
}
 
if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
-   enum glsl_base_type stype = 
glsl_get_sampler_result_type(instr->texture->var->type);
+   nir_deref_instr *texture_deref_instr = 
get_tex_texture_deref(instr);
+   nir_variable *var = texture_deref_instr ? 
nir_deref_instr_get_variable(texture_deref_instr) : instr->texture->var;
+   enum glsl_base_type stype = 
glsl_get_sampler_result_type(var->type);
if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
-   return lower_gather4_integer(>ac, args, instr);
+   return lower_gather4_integer(>ac, var, args, 
instr);
}
}
 
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [RFC PATCH V2] radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT

[Bas Nieuwenhuizen]

On Sun, May 13, 2018 at 12:46 AM, Timothy Arceri  wrote:
> On 13/05/18 08:17, Bas Nieuwenhuizen wrote:
>>
>> Reviewed-by: Bas Nieuwenhuizen 
>>
>> if you also have a spec to go with the new bit. (and add it to the
>> headers)
>
>
> VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is already part of the spec. I
> think you are getting confused with the previous discussion for a threaded
> shader compiles bit.

Looks like I was indeed.

>
>
>>
>> On Tue, May 8, 2018 at 7:58 AM, Timothy Arceri 
>> wrote:
>>>
>>> When VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is set we skip NIR
>>> linking optimisations and only run over the NIR optimisation loop
>>> once similar to the GLSLOptimizeConservatively constant used by
>>> some GL drivers.
>>>
>>> We need to run over the opts at least once to avoid errors in LLVM
>>> (e.g. dead vars it can't handle) and also to reduce the time spent
>>> compiling the IR in LLVM.
>>>
>>> With this change the Blacksmith Unity demos compilation times
>>> go from 329760 ms -> 299881 ms when using Wine and DXVK.
>>>
>>> V2: add bit to radv_pipeline_key
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106246
>>> ---
>>>   src/amd/vulkan/radv_pipeline.c | 26 +-
>>>   src/amd/vulkan/radv_private.h  |  1 +
>>>   src/amd/vulkan/radv_shader.c   | 12 +++-
>>>   src/amd/vulkan/radv_shader.h   |  5 +++--
>>>   4 files changed, 28 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/src/amd/vulkan/radv_pipeline.c
>>> b/src/amd/vulkan/radv_pipeline.c
>>> index b4e4f3211e2..d443f8271e9 100644
>>> --- a/src/amd/vulkan/radv_pipeline.c
>>> +++ b/src/amd/vulkan/radv_pipeline.c
>>> @@ -1724,13 +1724,13 @@ radv_link_shaders(struct radv_pipeline *pipeline,
>>> nir_shader **shaders)
>>>
>>> ac_lower_indirect_derefs(ordered_shaders[i],
>>>
>>> pipeline->device->physical_device->rad_info.chip_class);
>>>  }
>>> -   radv_optimize_nir(ordered_shaders[i]);
>>> +   radv_optimize_nir(ordered_shaders[i], false);
>>>
>>>  if
>>> (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
>>>
>>> ac_lower_indirect_derefs(ordered_shaders[i - 1],
>>>
>>> pipeline->device->physical_device->rad_info.chip_class);
>>>  }
>>> -   radv_optimize_nir(ordered_shaders[i - 1]);
>>> +   radv_optimize_nir(ordered_shaders[i - 1], false);
>>>  }
>>>  }
>>>   }
>>> @@ -1750,6 +1750,9 @@ radv_generate_graphics_pipeline_key(struct
>>> radv_pipeline *pipeline,
>>>  struct radv_pipeline_key key;
>>>  memset(, 0, sizeof(key));
>>>
>>> +   if (pCreateInfo->flags &
>>> VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
>>> +   key.optimisations_disabled = 1;
>>> +
>>>  key.has_multiview_view_index = has_view_index;
>>>
>>>  uint32_t binding_input_rate = 0;
>>> @@ -1878,7 +1881,8 @@ void radv_create_shaders(struct radv_pipeline
>>> *pipeline,
>>>struct radv_device *device,
>>>struct radv_pipeline_cache *cache,
>>>struct radv_pipeline_key key,
>>> - const VkPipelineShaderStageCreateInfo
>>> **pStages)
>>> + const VkPipelineShaderStageCreateInfo
>>> **pStages,
>>> + const VkPipelineCreateFlags flags)
>>>   {
>>>  struct radv_shader_module fs_m = {0};
>>>  struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
>>> @@ -1944,7 +1948,8 @@ void radv_create_shaders(struct radv_pipeline
>>> *pipeline,
>>>
>>>  nir[i] = radv_shader_compile_to_nir(device, modules[i],
>>>  stage ? stage->pName
>>> : "main", i,
>>> -   stage ?
>>> stage->pSpecializationInfo : NULL);
>>> +   stage ?
>>> stage->pSpecializationInfo : NULL,
>>> +   flags);
>>>  pipeline->active_stages |= mesa_to_vk_shader_stage(i);
>>>
>>>  /* We don't want to alter meta shaders IR directly so
>>> clone it
>>> @@ -1963,8 +1968,10 @@ void radv_create_shaders(struct radv_pipeline
>>> *pipeline,
>>>  if (i != last)
>>>  mask = mask | nir_var_shader_out;
>>>
>>> -   nir_lower_io_to_scalar_early(nir[i], mask);
>>> -   radv_optimize_nir(nir[i]);
>>> +   if (!(flags &
>>> VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
>>> +   nir_lower_io_to_scalar_early(nir[i],
>>> mask);
>>> +   radv_optimize_nir(nir[i], false);
>>> +   }
>>>  }
>>>  }
>>>

Re: [Mesa-dev] [RFC PATCH V2] radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT

[Timothy Arceri]

On 13/05/18 08:17, Bas Nieuwenhuizen wrote:

Reviewed-by: Bas Nieuwenhuizen 

if you also have a spec to go with the new bit. (and add it to the headers)


VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is already part of the spec. 
I think you are getting confused with the previous discussion for a 
threaded shader compiles bit.




On Tue, May 8, 2018 at 7:58 AM, Timothy Arceri  wrote:

When VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is set we skip NIR
linking optimisations and only run over the NIR optimisation loop
once similar to the GLSLOptimizeConservatively constant used by
some GL drivers.

We need to run over the opts at least once to avoid errors in LLVM
(e.g. dead vars it can't handle) and also to reduce the time spent
compiling the IR in LLVM.

With this change the Blacksmith Unity demos compilation times
go from 329760 ms -> 299881 ms when using Wine and DXVK.

V2: add bit to radv_pipeline_key

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106246
---
  src/amd/vulkan/radv_pipeline.c | 26 +-
  src/amd/vulkan/radv_private.h  |  1 +
  src/amd/vulkan/radv_shader.c   | 12 +++-
  src/amd/vulkan/radv_shader.h   |  5 +++--
  4 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b4e4f3211e2..d443f8271e9 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1724,13 +1724,13 @@ radv_link_shaders(struct radv_pipeline *pipeline, 
nir_shader **shaders)
 ac_lower_indirect_derefs(ordered_shaders[i],
  
pipeline->device->physical_device->rad_info.chip_class);
 }
-   radv_optimize_nir(ordered_shaders[i]);
+   radv_optimize_nir(ordered_shaders[i], false);

 if (nir_lower_global_vars_to_local(ordered_shaders[i - 
1])) {
 ac_lower_indirect_derefs(ordered_shaders[i - 
1],
  
pipeline->device->physical_device->rad_info.chip_class);
 }
-   radv_optimize_nir(ordered_shaders[i - 1]);
+   radv_optimize_nir(ordered_shaders[i - 1], false);
 }
 }
  }
@@ -1750,6 +1750,9 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline 
*pipeline,
 struct radv_pipeline_key key;
 memset(, 0, sizeof(key));

+   if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
+   key.optimisations_disabled = 1;
+
 key.has_multiview_view_index = has_view_index;

 uint32_t binding_input_rate = 0;
@@ -1878,7 +1881,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
   struct radv_device *device,
   struct radv_pipeline_cache *cache,
   struct radv_pipeline_key key,
- const VkPipelineShaderStageCreateInfo **pStages)
+ const VkPipelineShaderStageCreateInfo **pStages,
+ const VkPipelineCreateFlags flags)
  {
 struct radv_shader_module fs_m = {0};
 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
@@ -1944,7 +1948,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,

 nir[i] = radv_shader_compile_to_nir(device, modules[i],
 stage ? stage->pName : 
"main", i,
-   stage ? 
stage->pSpecializationInfo : NULL);
+   stage ? 
stage->pSpecializationInfo : NULL,
+   flags);
 pipeline->active_stages |= mesa_to_vk_shader_stage(i);

 /* We don't want to alter meta shaders IR directly so clone it
@@ -1963,8 +1968,10 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 if (i != last)
 mask = mask | nir_var_shader_out;

-   nir_lower_io_to_scalar_early(nir[i], mask);
-   radv_optimize_nir(nir[i]);
+   if (!(flags & 
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
+   nir_lower_io_to_scalar_early(nir[i], mask);
+   radv_optimize_nir(nir[i], false);
+   }
 }
 }

@@ -1973,7 +1980,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 merge_tess_info([MESA_SHADER_TESS_EVAL]->info, 
[MESA_SHADER_TESS_CTRL]->info);
 }

-   radv_link_shaders(pipeline, nir);
+   if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
+   radv_link_shaders(pipeline, nir);

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #10 from mais...@archlinux.us ---
That would match AMDVLK, it exposes A2BGR10_SNORM for vertex, but not
UNIFORM_TEXEL_BUFFER.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [RFC PATCH V2] radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

if you also have a spec to go with the new bit. (and add it to the headers)

On Tue, May 8, 2018 at 7:58 AM, Timothy Arceri  wrote:
> When VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is set we skip NIR
> linking optimisations and only run over the NIR optimisation loop
> once similar to the GLSLOptimizeConservatively constant used by
> some GL drivers.
>
> We need to run over the opts at least once to avoid errors in LLVM
> (e.g. dead vars it can't handle) and also to reduce the time spent
> compiling the IR in LLVM.
>
> With this change the Blacksmith Unity demos compilation times
> go from 329760 ms -> 299881 ms when using Wine and DXVK.
>
> V2: add bit to radv_pipeline_key
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106246
> ---
>  src/amd/vulkan/radv_pipeline.c | 26 +-
>  src/amd/vulkan/radv_private.h  |  1 +
>  src/amd/vulkan/radv_shader.c   | 12 +++-
>  src/amd/vulkan/radv_shader.h   |  5 +++--
>  4 files changed, 28 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index b4e4f3211e2..d443f8271e9 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -1724,13 +1724,13 @@ radv_link_shaders(struct radv_pipeline *pipeline, 
> nir_shader **shaders)
> ac_lower_indirect_derefs(ordered_shaders[i],
>  
> pipeline->device->physical_device->rad_info.chip_class);
> }
> -   radv_optimize_nir(ordered_shaders[i]);
> +   radv_optimize_nir(ordered_shaders[i], false);
>
> if (nir_lower_global_vars_to_local(ordered_shaders[i 
> - 1])) {
> ac_lower_indirect_derefs(ordered_shaders[i - 
> 1],
>  
> pipeline->device->physical_device->rad_info.chip_class);
> }
> -   radv_optimize_nir(ordered_shaders[i - 1]);
> +   radv_optimize_nir(ordered_shaders[i - 1], false);
> }
> }
>  }
> @@ -1750,6 +1750,9 @@ radv_generate_graphics_pipeline_key(struct 
> radv_pipeline *pipeline,
> struct radv_pipeline_key key;
> memset(, 0, sizeof(key));
>
> +   if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
> +   key.optimisations_disabled = 1;
> +
> key.has_multiview_view_index = has_view_index;
>
> uint32_t binding_input_rate = 0;
> @@ -1878,7 +1881,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>   struct radv_device *device,
>   struct radv_pipeline_cache *cache,
>   struct radv_pipeline_key key,
> - const VkPipelineShaderStageCreateInfo **pStages)
> + const VkPipelineShaderStageCreateInfo **pStages,
> + const VkPipelineCreateFlags flags)
>  {
> struct radv_shader_module fs_m = {0};
> struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
> @@ -1944,7 +1948,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>
> nir[i] = radv_shader_compile_to_nir(device, modules[i],
> stage ? stage->pName : 
> "main", i,
> -   stage ? 
> stage->pSpecializationInfo : NULL);
> +   stage ? 
> stage->pSpecializationInfo : NULL,
> +   flags);
> pipeline->active_stages |= mesa_to_vk_shader_stage(i);
>
> /* We don't want to alter meta shaders IR directly so clone it
> @@ -1963,8 +1968,10 @@ void radv_create_shaders(struct radv_pipeline 
> *pipeline,
> if (i != last)
> mask = mask | nir_var_shader_out;
>
> -   nir_lower_io_to_scalar_early(nir[i], mask);
> -   radv_optimize_nir(nir[i]);
> +   if (!(flags & 
> VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
> +   nir_lower_io_to_scalar_early(nir[i], mask);
> +   radv_optimize_nir(nir[i], false);
> +   }
> }
> }
>
> @@ -1973,7 +1980,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
> merge_tess_info([MESA_SHADER_TESS_EVAL]->info, 
> [MESA_SHADER_TESS_CTRL]->info);
> }
>
> -   radv_link_shaders(pipeline, nir);
> +   if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
> +   radv_link_shaders(pipeline, nir);
>
> for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
> 

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #9 from Bas Nieuwenhuizen  ---
This bug should be fixed by

https://patchwork.freedesktop.org/series/43092/

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.

[Bas Nieuwenhuizen]

The hardware always interprets the alpha as unsigned and fixing it
in the shader is going to add unacceptable overheads.

CC: 18.0 18.1 
---
 src/amd/vulkan/radv_formats.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index f8438f43b85..1ac07b41a61 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -657,6 +657,25 @@ radv_physical_device_get_format_properties(struct 
radv_physical_device *physical
tiled |= VK_FORMAT_FEATURE_STORAGE_IMAGE_ATOMIC_BIT;
}
 
+   switch(format) {
+   case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
+   case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
+   case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
+   case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
+   case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+   case VK_FORMAT_A2B10G10R10_SINT_PACK32:
+   if (physical_device->rad_info.chip_class <= VI &&
+   physical_device->rad_info.family != CHIP_STONEY) {
+   buffer &= ~(VK_FORMAT_FEATURE_UNIFORM_TEXEL_BUFFER_BIT |
+   VK_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_BIT);
+   linear = 0;
+   tiled = 0;
+   }
+   break;
+   default:
+   break;
+   }
+
out_properties->linearTilingFeatures = linear;
out_properties->optimalTilingFeatures = tiled;
out_properties->bufferFeatures = buffer;
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] radv: Fix up 2_10_10_10 alpha sign.

[Bas Nieuwenhuizen]

Pre-Vega HW always interprets the alpha for this format as unsigned,
so we have to implement a fixup to do the sign correctly for signed
formats.

CC: 18.0 18.1 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 61 ---
 src/amd/vulkan/radv_pipeline.c| 30 +--
 src/amd/vulkan/radv_private.h |  1 +
 src/amd/vulkan/radv_shader.h  | 12 ++
 4 files changed, 95 insertions(+), 9 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index f98940f0d8f..9d9ecda63cf 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1865,6 +1865,47 @@ static LLVMValueRef radv_get_sampler_desc(struct 
ac_shader_abi *abi,
return ac_build_load_to_sgpr(>ac, list, index);
 }
 
+/* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
+ * so we may need to fix it up. */
+static LLVMValueRef
+adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
+  unsigned adjustment,
+  LLVMValueRef alpha)
+{
+   if (adjustment == RADV_ALPHA_ADJUST_NONE)
+   return alpha;
+
+   LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
+
+   if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
+   alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, 
"");
+   else
+   alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, 
"");
+
+   /* For the integer-like cases, do a natural sign extension.
+   *
+   * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
+   * and happen to contain 0, 1, 2, 3 as the two LSBs of the
+   * exponent.
+   */
+   alpha = LLVMBuildShl(ctx->ac.builder, alpha,
+adjustment == RADV_ALPHA_ADJUST_SNORM ?
+LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
+   alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
+
+   /* Convert back to the right type. */
+   if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
+   LLVMValueRef clamp;
+   LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
+   alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, 
"");
+   clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, 
neg_one, "");
+   alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, 
"");
+   } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
+   alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, 
"");
+   }
+
+   return alpha;
+}
 
 static void
 handle_vs_input_decl(struct radv_shader_context *ctx,
@@ -1884,9 +1925,11 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
 
variable->data.driver_location = idx * 4;
 
-   for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
-   if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + 
i))) {
-   uint32_t divisor = 
ctx->options->key.vs.instance_rate_divisors[index + i];
+   for (unsigned i = 0; i < attrib_count; ++i, ++idx, ++index) {
+   LLVMValueRef output[4];
+
+   if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
+   uint32_t divisor = 
ctx->options->key.vs.instance_rate_divisors[index];
 
if (divisor) {
buffer_index = LLVMBuildAdd(ctx->ac.builder, 
ctx->abi.instance_id,
@@ -1910,7 +1953,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
} else
buffer_index = LLVMBuildAdd(ctx->ac.builder, 
ctx->abi.vertex_id,
ctx->abi.base_vertex, "");
-   t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
+   t_offset = LLVMConstInt(ctx->ac.i32, index, false);
 
t_list = ac_build_load_to_sgpr(>ac, t_list_ptr, t_offset);
 
@@ -1923,9 +1966,15 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
 
for (unsigned chan = 0; chan < 4; chan++) {
LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, 
chan, false);
+   output[chan] = LLVMBuildExtractElement(ctx->ac.builder, 
input, llvm_chan, "");
+   }
+
+   unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> 
(index * 2)) & 3;
+   output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, 
output[3]);
+
+   for (unsigned chan = 0; chan < 4; chan++) {
ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
-   ac_to_integer(>ac, 
LLVMBuildExtractElement(ctx->ac.builder,
-   input, llvm_chan, ""));
+   ac_to_integer(>ac, output[chan]);
}
}
 }
diff --git 

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #8 from Bas Nieuwenhuizen  ---
Yes, We'll likely "fix" that by not claiming support for R10G10B10A2 SNORM/SINT
formats anymore since support is not required, and a fixup is not possible
without significantly impacting perofrmance for apps that don't use it.

VK_FORMAT_A2B10G10R10_SNORM_PACK32 and VK_FORMAT_A2B10G10R10_SINT_PACK32 are
not required formats according to the vulkan spec, so we can reasonably disable
those.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #7 from mais...@archlinux.us ---
FWIW, this also affects UNIFORM_TEXEL_BUFFER.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] anv, nir: add generated files to .gitignore(s)

[Jason Ekstrand]

Rb

On May 11, 2018 05:12:59 Rhys Perry  wrote:


---
src/compiler/nir/.gitignore | 2 ++
src/intel/vulkan/.gitignore | 1 +
2 files changed, 3 insertions(+)

diff --git a/src/compiler/nir/.gitignore b/src/compiler/nir/.gitignore
index 64828eba6d..8faf93f0b2 100644
--- a/src/compiler/nir/.gitignore
+++ b/src/compiler/nir/.gitignore
@@ -3,3 +3,5 @@ nir_opt_algebraic.c
nir_opcodes.c
nir_opcodes.h
nir_constant_expressions.c
+nir_intrinsics.c
+nir_intrinsics.h
diff --git a/src/intel/vulkan/.gitignore b/src/intel/vulkan/.gitignore
index 4ea978d6e4..b84b17134f 100644
--- a/src/intel/vulkan/.gitignore
+++ b/src/intel/vulkan/.gitignore
@@ -1,5 +1,6 @@
# Generated source files
/anv_extensions.c
+/anv_extensions.h
/anv_entrypoints.c
/anv_entrypoints.h
/anv_timestamp.h
--
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev




___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #6 from Bas Nieuwenhuizen  ---
That would explain, I tested on vega.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #5 from mais...@archlinux.us ---
Yes, I should clarify that this is RX470, so Polaris.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 19/21] i965: account for NIR uniforms without name

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

Right now, the BRW linker code assumes nir_variable::name is always
non-NULL, but thanks to ARB_gl_spirv we will soon be linking SPIR-V
programs, and those explicitly require matching uniforms by location.
The name is just a debug hint.

Instead of checking for the name this patch makes it check for
var->num_state_slots on the assumption that everything that had an
internal name also had some state slots. This seems likely because the
two code paths that are taken when the name begins with "gl_" already
have an assert that var->state_slots is not NULL.

v2: simplified, most of it moved to glsl/nir/spirv (Neil Roberts)
v3: check for num_state_slots instead of the name. This is needed
because we do actually have nameless builtins with SPIR-V such as
PatchVerticesIn and we want them to hit the
_mesa_add_state_reference code path (Neil Roberts)

Signed-off-by: Eduardo Lima 
Signed-off-by: Neil Roberts 
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 11 ---
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp |  2 +-
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 0203c44f1cb..c75721c06ca 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -321,13 +321,10 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
* get sent to the shader.
*/
   nir_foreach_variable(var, >nir->uniforms) {
- if (strncmp(var->name, "gl_", 3) == 0) {
-const nir_state_slot *const slots = var->state_slots;
-assert(var->state_slots != NULL);
-
-for (unsigned int i = 0; i < var->num_state_slots; i++) {
-   _mesa_add_state_reference(prog->Parameters, slots[i].tokens);
-}
+ const nir_state_slot *const slots = var->state_slots;
+ for (unsigned int i = 0; i < var->num_state_slots; i++) {
+assert(slots != NULL);
+_mesa_add_state_reference(prog->Parameters, slots[i].tokens);
  }
   }
}
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp 
b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 69da83ad364..64c745b609c 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -202,7 +202,7 @@ brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader 
*shader,
   if (var->interface_type != NULL || var->type->contains_atomic())
  continue;
 
-  if (strncmp(var->name, "gl_", 3) == 0) {
+  if (var->num_state_slots > 0) {
  brw_nir_setup_glsl_builtin_uniform(var, prog, stage_prog_data,
 is_scalar);
   } else {
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 18/21] i965: Update TexturesUsed after linking the shaders

[Alejandro Piñeiro]

From: Neil Roberts 

Otherwise if the shader is SPIR-V then SamplerUsed won’t have been
initialised yet so it will end up thinking no textures are used. This
was causing a crash later on if nothing causes it to regenerate
TexturesUsed before the next render.
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 996465f305a..0203c44f1cb 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -246,7 +246,6 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
   _mesa_copy_linked_program_data(shProg, shader);
 
   prog->ShadowSamplers = shader->shadow_samplers;
-  _mesa_update_shader_textures_used(shProg, prog);
 
   bool debug_enabled =
  (INTEL_DEBUG & intel_debug_flag_for_shader_stage(shader->Stage));
@@ -300,6 +299,9 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
  continue;
 
   struct gl_program *prog = shader->Program;
+
+  _mesa_update_shader_textures_used(shProg, prog);
+
   brw_shader_gather_info(prog->nir, prog);
 
   NIR_PASS_V(prog->nir, gl_nir_lower_samplers, shProg);
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 21/21] i965: Link uniforms of SPIR-V programs using the NIR linker

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

v2: nir_link_uniforms renamed to gl_nir_link_uniforms

Signed-off-by: Eduardo Lima 
Signed-off-by: Alejandro Piñeiro 
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index c75721c06ca..8bc97fa4f3e 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -261,6 +261,12 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
  compiler->scalar_stage[stage]);
}
 
+   /* SPIR-V programs use a NIR linker */
+   if (shProg->data->spirv) {
+  if (!gl_nir_link_uniforms(ctx, shProg))
+ return false;
+   }
+
/* Determine first and last stage. */
unsigned first = MESA_SHADER_STAGES;
unsigned last = 0;
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 16/21] nir/linker: Add nir_build_program_resource_list()

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

This function is equivalent to the linker.cpp
build_program_resource_list() but will extract the resources from NIR
shaders instead.

For now, only uniforms and program inputs are implemented.

v2: move from compiler/nir to compiler/glsl (Timothy Arceri)

Signed-off-by: Eduardo Lima 
Signed-off-by: Alejandro Piñeiro 
---
 src/compiler/Makefile.sources |  1 +
 src/compiler/glsl/gl_nir_linker.c | 93 +++
 src/compiler/glsl/gl_nir_linker.h |  3 ++
 src/compiler/glsl/meson.build |  1 +
 4 files changed, 98 insertions(+)
 create mode 100644 src/compiler/glsl/gl_nir_linker.c

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 8104dd32002..409252ee587 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -30,6 +30,7 @@ LIBGLSL_FILES = \
glsl/gl_nir_lower_samplers_as_deref.c \
glsl/gl_nir_link_uniform_initializers.c \
glsl/gl_nir_link_uniforms.c \
+   glsl/gl_nir_linker.c \
glsl/gl_nir_linker.h \
glsl/gl_nir.h \
glsl/glsl_parser_extras.cpp \
diff --git a/src/compiler/glsl/gl_nir_linker.c 
b/src/compiler/glsl/gl_nir_linker.c
new file mode 100644
index 000..155d94ef966
--- /dev/null
+++ b/src/compiler/glsl/gl_nir_linker.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "gl_nir_linker.h"
+#include "linker_util.h"
+#include "main/mtypes.h"
+#include "ir_uniform.h" /* for gl_uniform_storage */
+
+/* This file included general link methods, using NIR, instead of IR as
+ * the counter-part glsl/linker.cpp
+ *
+ * Also note that this is tailored for ARB_gl_spirv needs and particularities
+ */
+
+void
+nir_build_program_resource_list(struct gl_context *ctx,
+struct gl_shader_program *prog)
+{
+   /* Rebuild resource list. */
+   if (prog->data->ProgramResourceList) {
+  ralloc_free(prog->data->ProgramResourceList);
+  prog->data->ProgramResourceList = NULL;
+  prog->data->NumProgramResourceList = 0;
+   }
+
+   struct set *resource_set = _mesa_set_create(NULL,
+   _mesa_hash_pointer,
+   _mesa_key_pointer_equal);
+
+   /* Add uniforms
+*
+* Here, it is expected that nir_link_uniforms() has already been
+* called, so that UniformStorage table is already available.
+*/
+   for (unsigned i = 0; i < prog->data->NumUniformStorage; i++) {
+  struct gl_uniform_storage *uniform = >data->UniformStorage[i];
+
+  if (!link_util_add_program_resource(prog, resource_set, GL_UNIFORM, 
uniform,
+  uniform->active_shader_mask)) {
+ return;
+  }
+   }
+
+   /* Add inputs */
+   struct gl_linked_shader *sh = prog->_LinkedShaders[MESA_SHADER_VERTEX];
+   if (sh) {
+  nir_shader *nir = sh->Program->nir;
+  assert(nir);
+
+  nir_foreach_variable(var, >inputs) {
+ struct gl_shader_variable *sh_var =
+rzalloc(prog, struct gl_shader_variable);
+
+ /* ARB_gl_spirv: names are considered optional debug info, so the 
linker
+  * needs to work without them, and returning them is optional. For
+  * simplicity we ignore names.
+  */
+ sh_var->name = NULL;
+ sh_var->type = var->type;
+ sh_var->location = var->data.location;
+
+ /* @TODO: Fill in the rest of gl_shader_variable data. */
+
+ if (!link_util_add_program_resource(prog, resource_set, 
GL_PROGRAM_INPUT,
+ sh_var, 1 << MESA_SHADER_VERTEX)) 
{
+return;
+ }
+  }
+   }
+
+   _mesa_set_destroy(resource_set, NULL);
+}
diff --git 

[Mesa-dev] [PATCH v2 20/21] i965: Setup glsl uniforms by index rather than name matching

[Alejandro Piñeiro]

From: Neil Roberts 

Previously when setting up a uniform it would try to walk the uniform
storage slots and find one that matches the name of the given
variable. However, each variable already has a location which is an
index into the UniformStorage array so we can just directly jump to
the right slot. Some of the variables take up more than one slot so we
still need to calculate how many it uses.

The main reason to do this is to support ARB_gl_spirv because in that
case the uniforms don’t have names so the previous approach won’t
work.
---
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 50 +++---
 1 file changed, 37 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp 
b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 64c745b609c..32d92ac6f5d 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -118,35 +118,59 @@ brw_setup_image_uniform_values(gl_shader_stage stage,
}
 }
 
+static unsigned
+count_uniform_storage_slots(const struct glsl_type *type)
+{
+   /* gl_uniform_storage can cope with one level of array, so if the
+* type is a composite type or an array where each element occupies
+* more than one slot than we need to recursively process it.
+*/
+   if (glsl_type_is_struct(type)) {
+  unsigned location_count = 0;
+
+  for (unsigned i = 0; i < glsl_get_length(type); i++) {
+ const struct glsl_type *field_type = glsl_get_struct_field(type, i);
+
+ location_count += count_uniform_storage_slots(field_type);
+  }
+
+  return location_count;
+   }
+
+   if (glsl_type_is_array(type)) {
+  const struct glsl_type *element_type = glsl_get_array_element(type);
+
+  if (glsl_type_is_array(element_type) ||
+  glsl_type_is_struct(element_type)) {
+ unsigned element_count = count_uniform_storage_slots(element_type);
+ return element_count * glsl_get_length(type);
+  }
+   }
+
+   return 1;
+}
+
 static void
 brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
bool is_scalar)
 {
-   int namelen = strlen(var->name);
-
/* The data for our (non-builtin) uniforms is stored in a series of
 * gl_uniform_storage structs for each subcomponent that
 * glGetUniformLocation() could name.  We know it's been set up in the same
-* order we'd walk the type, so walk the list of storage and find anything
-* with our name, or the prefix of a component that starts with our name.
+* order we'd walk the type, so walk the list of storage that matches the
+* range of slots covered by this variable.
 */
unsigned uniform_index = var->data.driver_location / 4;
-   for (unsigned u = 0; u < prog->sh.data->NumUniformStorage; u++) {
+   unsigned num_slots = count_uniform_storage_slots(var->type);
+   for (unsigned u = 0; u < num_slots; u++) {
   struct gl_uniform_storage *storage =
- >sh.data->UniformStorage[u];
+ >sh.data->UniformStorage[var->data.location + u];
 
   if (storage->builtin || storage->type->is_sampler())
  continue;
 
-  if (strncmp(var->name, storage->name, namelen) != 0 ||
-  (storage->name[namelen] != 0 &&
-   storage->name[namelen] != '.' &&
-   storage->name[namelen] != '[')) {
- continue;
-  }
-
   if (storage->type->is_image()) {
  brw_setup_image_uniform_values(stage, stage_prog_data,
 uniform_index, storage);
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 15/21] compiler/link: move add_program_resource to linker_util

[Alejandro Piñeiro]

So it could be used by the GLSL and NIR linker.

v2: (Timothy Arceri)
   * Moved from compiler to compiler/glsl
   * Method renamed to link_util_add_program_resource
---
 src/compiler/Makefile.sources |  1 +
 src/compiler/glsl/linker.cpp  | 76 +++
 src/compiler/glsl/linker_util.cpp | 64 +
 src/compiler/glsl/linker_util.h   |  5 +++
 src/compiler/glsl/meson.build |  1 +
 5 files changed, 91 insertions(+), 56 deletions(-)
 create mode 100644 src/compiler/glsl/linker_util.cpp

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 27c135e913b..8104dd32002 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -75,6 +75,7 @@ LIBGLSL_FILES = \
glsl/linker.cpp \
glsl/linker.h \
glsl/linker_util.h \
+   glsl/linker_util.cpp \
glsl/link_atomics.cpp \
glsl/link_functions.cpp \
glsl/link_interface_blocks.cpp \
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f060c5316fa..f201a566c29 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -3613,42 +3613,6 @@ should_add_buffer_variable(struct gl_shader_program 
*shProg,
return false;
 }
 
-static bool
-add_program_resource(struct gl_shader_program *prog,
- struct set *resource_set,
- GLenum type, const void *data, uint8_t stages)
-{
-   assert(data);
-
-   /* If resource already exists, do not add it again. */
-   if (_mesa_set_search(resource_set, data))
-  return true;
-
-   prog->data->ProgramResourceList =
-  reralloc(prog->data,
-   prog->data->ProgramResourceList,
-   gl_program_resource,
-   prog->data->NumProgramResourceList + 1);
-
-   if (!prog->data->ProgramResourceList) {
-  linker_error(prog, "Out of memory during linking.\n");
-  return false;
-   }
-
-   struct gl_program_resource *res =
-  >data->ProgramResourceList[prog->data->NumProgramResourceList];
-
-   res->Type = type;
-   res->Data = data;
-   res->StageReferences = stages;
-
-   prog->data->NumProgramResourceList++;
-
-   _mesa_set_add(resource_set, data);
-
-   return true;
-}
-
 /* Function checks if a variable var is a packed varying and
  * if given name is part of packed varying's list.
  *
@@ -3942,8 +3906,8 @@ add_shader_variable(const struct gl_context *ctx,
   if (!sha_v)
  return false;
 
-  return add_program_resource(shProg, resource_set,
-  programInterface, sha_v, stage_mask);
+  return link_util_add_program_resource(shProg, resource_set,
+programInterface, sha_v, 
stage_mask);
}
}
 }
@@ -4372,9 +4336,9 @@ build_program_resource_list(struct gl_context *ctx,
   /* Add transform feedback varyings. */
   if (linked_xfb->NumVarying > 0) {
  for (int i = 0; i < linked_xfb->NumVarying; i++) {
-if (!add_program_resource(shProg, resource_set,
-  GL_TRANSFORM_FEEDBACK_VARYING,
-  _xfb->Varyings[i], 0))
+if (!link_util_add_program_resource(shProg, resource_set,
+GL_TRANSFORM_FEEDBACK_VARYING,
+_xfb->Varyings[i], 0))
 return;
  }
   }
@@ -4383,9 +4347,9 @@ build_program_resource_list(struct gl_context *ctx,
   for (unsigned i = 0; i < ctx->Const.MaxTransformFeedbackBuffers; i++) {
  if ((linked_xfb->ActiveBuffers >> i) & 1) {
 linked_xfb->Buffers[i].Binding = i;
-if (!add_program_resource(shProg, resource_set,
-  GL_TRANSFORM_FEEDBACK_BUFFER,
-  _xfb->Buffers[i], 0))
+if (!link_util_add_program_resource(shProg, resource_set,
+GL_TRANSFORM_FEEDBACK_BUFFER,
+_xfb->Buffers[i], 0))
 return;
  }
   }
@@ -4421,29 +4385,29 @@ build_program_resource_list(struct gl_context *ctx,
  >data->UniformStorage[i]);
   }
 
-  if (!add_program_resource(shProg, resource_set, type,
->data->UniformStorage[i], stageref))
+  if (!link_util_add_program_resource(shProg, resource_set, type,
+  >data->UniformStorage[i], 
stageref))
  return;
}
 
/* Add program uniform blocks. */
for (unsigned i = 0; i < shProg->data->NumUniformBlocks; i++) {
-  if (!add_program_resource(shProg, resource_set, GL_UNIFORM_BLOCK,
-  >data->UniformBlocks[i], 0))
+  if (!link_util_add_program_resource(shProg, resource_set, 
GL_UNIFORM_BLOCK,
+  

[Mesa-dev] [PATCH v2 17/21] i965: Build SPIR-V programs' resource list using NIR

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

v2: tweak after nir_linker.h being renamed to gl_nir_linker.h
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 39fa94c0f8d..996465f305a 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -25,11 +25,13 @@
 #include "compiler/brw_nir.h"
 #include "brw_program.h"
 #include "compiler/glsl/gl_nir.h"
+#include "compiler/glsl/gl_nir_linker.h"
 #include "compiler/glsl/ir.h"
 #include "compiler/glsl/ir_optimization.h"
 #include "compiler/glsl/program.h"
 #include "compiler/nir/nir_serialize.h"
 #include "program/program.h"
+#include "main/glspirv.h"
 #include "main/mtypes.h"
 #include "main/shaderapi.h"
 #include "main/shaderobj.h"
@@ -364,7 +366,11 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
if (brw->precompile && !brw_shader_precompile(ctx, shProg))
   return false;
 
-   build_program_resource_list(ctx, shProg);
+   /* SPIR-V programs build its resource list from linked NIR shaders. */
+   if (!shProg->data->spirv)
+  build_program_resource_list(ctx, shProg);
+   else
+  nir_build_program_resource_list(ctx, shProg);
 
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
   struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 14/21] nir/linker: Set the uniform initial values

[Alejandro Piñeiro]

From: Neil Roberts 

This is based on link_uniform_initializers.cpp.

v2: move from compiler/nir to compiler/glsl (Timothy Arceri)
---
 src/compiler/Makefile.sources  |   1 +
 .../glsl/gl_nir_link_uniform_initializers.c| 292 +
 src/compiler/glsl/gl_nir_link_uniforms.c   |   1 +
 src/compiler/glsl/gl_nir_linker.h  |   3 +
 src/compiler/glsl/meson.build  |   1 +
 5 files changed, 298 insertions(+)
 create mode 100644 src/compiler/glsl/gl_nir_link_uniform_initializers.c

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index ee2a25d53ac..27c135e913b 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -28,6 +28,7 @@ LIBGLSL_FILES = \
glsl/gl_nir_lower_atomics.c \
glsl/gl_nir_lower_samplers.c \
glsl/gl_nir_lower_samplers_as_deref.c \
+   glsl/gl_nir_link_uniform_initializers.c \
glsl/gl_nir_link_uniforms.c \
glsl/gl_nir_linker.h \
glsl/gl_nir.h \
diff --git a/src/compiler/glsl/gl_nir_link_uniform_initializers.c 
b/src/compiler/glsl/gl_nir_link_uniform_initializers.c
new file mode 100644
index 000..8eefa71c885
--- /dev/null
+++ b/src/compiler/glsl/gl_nir_link_uniform_initializers.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "gl_nir_linker.h"
+#include "compiler/glsl/ir_uniform.h" /* for gl_uniform_storage */
+#include "main/context.h"
+#include "main/mtypes.h"
+
+struct set_opaque_binding_closure {
+   struct gl_shader_program *shader_prog;
+   struct gl_program *prog;
+   const nir_variable *var;
+   int binding;
+   int location;
+};
+
+static void
+set_opaque_binding(struct set_opaque_binding_closure *data,
+   const struct glsl_type *type)
+{
+   if (glsl_type_is_array(type) &&
+   glsl_type_is_array(glsl_get_array_element(type))) {
+  const struct glsl_type *element_type = glsl_get_array_element(type);
+
+  for (unsigned int i = 0; i < glsl_get_length(type); i++)
+ set_opaque_binding(data, element_type);
+
+  return;
+   }
+
+   if (data->location < 0 ||
+   data->location >= data->prog->sh.data->NumUniformStorage)
+  return;
+
+   struct gl_uniform_storage *storage =
+  data->prog->sh.data->UniformStorage + data->location++;
+
+   const unsigned elements = MAX2(storage->array_elements, 1);
+
+   for (unsigned int i = 0; i < elements; i++)
+  storage->storage[i].i = data->binding++;
+
+   for (int sh = 0; sh < MESA_SHADER_STAGES; sh++) {
+  struct gl_linked_shader *shader = data->shader_prog->_LinkedShaders[sh];
+
+  if (!shader)
+ continue;
+  if (!storage->opaque[sh].active)
+ continue;
+
+  if (glsl_type_is_sampler(storage->type)) {
+ for (unsigned i = 0; i < elements; i++) {
+const unsigned index = storage->opaque[sh].index + i;
+
+if (storage->is_bindless) {
+   if (index >= shader->Program->sh.NumBindlessSamplers)
+  break;
+   shader->Program->sh.BindlessSamplers[index].unit =
+  storage->storage[i].i;
+   shader->Program->sh.BindlessSamplers[index].bound = true;
+   shader->Program->sh.HasBoundBindlessSampler = true;
+} else {
+   if (index >= ARRAY_SIZE(shader->Program->SamplerUnits))
+  break;
+   shader->Program->SamplerUnits[index] =
+  storage->storage[i].i;
+}
+ }
+  } else if (glsl_type_is_image(type)) {
+ for (unsigned i = 0; i < elements; i++) {
+const unsigned index = storage->opaque[sh].index + i;
+
+if (storage->is_bindless) {
+   if (index >= 

[Mesa-dev] [PATCH v2 13/21] nir/linker: Add gl_nir_link_uniforms()

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

This function will be the entry point for linking the uniforms from
the nir_shader objects associated with the gl_linked_shaders of a
program.

This patch includes initial support for linking uniforms from NIR
shaders. It is tailored for the ARB_gl_spirv needs, and it is far from
complete, but it should handle most cases of uniforms, array
uniforms, structs, samplers and images.

There are some FIXMEs related to specific features that will be
implemented in following patches, like atomic counters, UBOs and
SSBOs.

Also, note that ARB_gl_spirv makes mandatory explicit location for
normal uniforms, so this code only handles uniforms with explicit
location. But there are cases, like uniform atomic counters, that
doesn't have a location from the OpenGL point of view (they have a
binding), but that Mesa assign internally a location. That will be
handled on following patches.

A nir_linker.h file is also added. More NIR-linking related API will
be added in subsequent patches and those will include stuff from Mesa,
so reusing nir.h didn't seem a good idea.

v2: move from compiler/nir to compiler/glsl (Timothy Arceri)

Signed-off-by: Eduardo Lima 
Signed-off-by: Neil Roberts 
---
 src/compiler/Makefile.sources|   2 +
 src/compiler/glsl/gl_nir_link_uniforms.c | 460 +++
 src/compiler/glsl/gl_nir_linker.h|  41 +++
 src/compiler/glsl/meson.build|   2 +
 4 files changed, 505 insertions(+)
 create mode 100644 src/compiler/glsl/gl_nir_link_uniforms.c
 create mode 100644 src/compiler/glsl/gl_nir_linker.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 96af23fcd2c..ee2a25d53ac 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -28,6 +28,8 @@ LIBGLSL_FILES = \
glsl/gl_nir_lower_atomics.c \
glsl/gl_nir_lower_samplers.c \
glsl/gl_nir_lower_samplers_as_deref.c \
+   glsl/gl_nir_link_uniforms.c \
+   glsl/gl_nir_linker.h \
glsl/gl_nir.h \
glsl/glsl_parser_extras.cpp \
glsl/glsl_parser_extras.h \
diff --git a/src/compiler/glsl/gl_nir_link_uniforms.c 
b/src/compiler/glsl/gl_nir_link_uniforms.c
new file mode 100644
index 000..a8ebde73270
--- /dev/null
+++ b/src/compiler/glsl/gl_nir_link_uniforms.c
@@ -0,0 +1,460 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "gl_nir_linker.h"
+#include "compiler/glsl/ir_uniform.h" /* for gl_uniform_storage */
+#include "linker_util.h"
+#include "main/context.h"
+#include "main/mtypes.h"
+
+/* This file do the common link for GLSL uniforms, using NIR, instead of IR as
+ * the counter-part glsl/link_uniforms.cpp
+ *
+ * Also note that this is tailored for ARB_gl_spirv needs and particularities
+ * (like need to work/link without name available, explicit location for
+ * normal uniforms as mandatory, and so on).
+ */
+
+static void
+nir_setup_uniform_remap_tables(struct gl_context *ctx,
+   struct gl_shader_program *prog)
+{
+   prog->UniformRemapTable = rzalloc_array(prog,
+   struct gl_uniform_storage *,
+   prog->NumUniformRemapTable);
+   union gl_constant_value *data =
+  rzalloc_array(prog->data,
+union gl_constant_value, prog->data->NumUniformDataSlots);
+   if (!prog->UniformRemapTable || !data) {
+  linker_error(prog, "Out of memory during linking.\n");
+  return;
+   }
+   prog->data->UniformDataSlots = data;
+
+   unsigned data_pos = 0;
+
+   /* Reserve all the explicit locations of the active uniforms. */
+   for (unsigned i = 0; i < prog->data->NumUniformStorage; i++) {
+  struct 

[Mesa-dev] [PATCH v2 12/21] compiler/link: add linker_util.h, move linker_error/warning to it

[Alejandro Piñeiro]

Linker utilities common to the GLSL IR and NIR linker (the latter to
be used for ARB_gl_spirv).

We need to move it to a new header as the NIR linker doesn't need to
know about ir_variable, and others, included at linker.h.

v2: move from src/compiler to src/compiler/glsl (Timothy Arceri)
---
 src/compiler/Makefile.sources  |  1 +
 .../glsl/link_uniform_block_active_visitor.cpp |  1 +
 src/compiler/glsl/linker.h |  8 +---
 src/compiler/glsl/linker_util.h| 43 ++
 src/compiler/glsl/meson.build  |  1 +
 src/compiler/glsl/program.h|  8 
 6 files changed, 48 insertions(+), 14 deletions(-)
 create mode 100644 src/compiler/glsl/linker_util.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 3daa2c51334..96af23fcd2c 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -71,6 +71,7 @@ LIBGLSL_FILES = \
glsl/ir_visitor.h \
glsl/linker.cpp \
glsl/linker.h \
+   glsl/linker_util.h \
glsl/link_atomics.cpp \
glsl/link_functions.cpp \
glsl/link_interface_blocks.cpp \
diff --git a/src/compiler/glsl/link_uniform_block_active_visitor.cpp 
b/src/compiler/glsl/link_uniform_block_active_visitor.cpp
index cd1baf78e80..368981852c0 100644
--- a/src/compiler/glsl/link_uniform_block_active_visitor.cpp
+++ b/src/compiler/glsl/link_uniform_block_active_visitor.cpp
@@ -23,6 +23,7 @@
 
 #include "link_uniform_block_active_visitor.h"
 #include "program.h"
+#include "linker_util.h"
 
 static link_uniform_block_active *
 process_block(void *mem_ctx, struct hash_table *ht, ir_variable *var)
diff --git a/src/compiler/glsl/linker.h b/src/compiler/glsl/linker.h
index 454b65aebdf..6e9b4861673 100644
--- a/src/compiler/glsl/linker.h
+++ b/src/compiler/glsl/linker.h
@@ -25,6 +25,8 @@
 #ifndef GLSL_LINKER_H
 #define GLSL_LINKER_H
 
+#include "linker_util.h"
+
 struct gl_shader_program;
 struct gl_shader;
 struct gl_linked_shader;
@@ -192,12 +194,6 @@ private:
   const glsl_struct_field *named_ifc_member);
 };
 
-void
-linker_error(gl_shader_program *prog, const char *fmt, ...);
-
-void
-linker_warning(gl_shader_program *prog, const char *fmt, ...);
-
 /**
  * Sometimes there are empty slots left over in UniformRemapTable after we
  * allocate slots to explicit locations. This struct represents a single
diff --git a/src/compiler/glsl/linker_util.h b/src/compiler/glsl/linker_util.h
new file mode 100644
index 000..162db3e532f
--- /dev/null
+++ b/src/compiler/glsl/linker_util.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GLSL_LINKER_UTIL_H
+#define GLSL_LINKER_UTIL_H
+
+struct gl_shader_program;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void
+linker_error(struct gl_shader_program *prog, const char *fmt, ...);
+
+void
+linker_warning(struct gl_shader_program *prog, const char *fmt, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GLSL_LINKER_UTIL_H */
diff --git a/src/compiler/glsl/meson.build b/src/compiler/glsl/meson.build
index 055a84714c1..686a5a4ac0b 100644
--- a/src/compiler/glsl/meson.build
+++ b/src/compiler/glsl/meson.build
@@ -112,6 +112,7 @@ files_libglsl = files(
   'ir_visitor.h',
   'linker.cpp',
   'linker.h',
+  'linker_util.h',
   'link_atomics.cpp',
   'link_functions.cpp',
   'link_interface_blocks.cpp',
diff --git a/src/compiler/glsl/program.h b/src/compiler/glsl/program.h
index 480379b10b8..9df42ddc1c4 100644
--- a/src/compiler/glsl/program.h
+++ b/src/compiler/glsl/program.h
@@ -48,14 +48,6 @@ extern void
 build_program_resource_list(struct gl_context *ctx,
 struct gl_shader_program *shProg);
 
-extern void
-linker_error(struct gl_shader_program *prog, const char *fmt, ...)
-   

[Mesa-dev] [PATCH v2 10/21] anv/nir: Use nir_variable's type if interface_type is null

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

Previous patch 'spirv: Get rid of vtn_variable_mode_image/sampler'
made possible that interface_type of image/sampler nir_variable may be
null. This patch accounts for it and make use of the type of the
variable instead of the interface_type.

This prevents a number of crash regressions in Vulkan tests.

Signed-off-by: Eduardo Lima 
Signed-off-by: Neil Roberts 
---
 src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c 
b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index d5a08f712f1..25e892a676d 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -427,10 +427,13 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline 
*pipeline,
}
 
nir_foreach_variable(var, >uniforms) {
-  if (!glsl_type_is_image(var->interface_type))
+  const struct glsl_type *glsl_type = (var->interface_type ?
+   var->interface_type :
+   glsl_without_array(var->type));
+  if (!glsl_type_is_image(glsl_type))
  continue;
 
-  enum glsl_sampler_dim dim = glsl_get_sampler_dim(var->interface_type);
+  enum glsl_sampler_dim dim = glsl_get_sampler_dim(glsl_type);
 
   const uint32_t set = var->data.descriptor_set;
   const uint32_t binding = var->data.binding;
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 11/21] spirv: Set nir_variable->explicit_binding

[Alejandro Piñeiro]

From: Neil Roberts 

When SpvDecorationBinding is encountered in the SPIR-V source it now
sets explicit_binding on the nir_variable. This will be used to
determine whether to initialise sampler and image uniforms with the
binding value.
---
 src/compiler/spirv/vtn_private.h   | 1 +
 src/compiler/spirv/vtn_variables.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 98bec389fcd..5fc34f43809 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -452,6 +452,7 @@ struct vtn_variable {
 
unsigned descriptor_set;
unsigned binding;
+   bool explicit_binding;
unsigned input_attachment_index;
bool patch;
 
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 6d1eede5ed0..902b2373015 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1503,6 +1503,7 @@ var_decoration_cb(struct vtn_builder *b, struct vtn_value 
*val, int member,
switch (dec->decoration) {
case SpvDecorationBinding:
   vtn_var->binding = dec->literals[0];
+  vtn_var->explicit_binding = true;
   return;
case SpvDecorationDescriptorSet:
   vtn_var->descriptor_set = dec->literals[0];
@@ -1926,6 +1927,7 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
* for these. We should fix that.
*/
   var->var->data.binding = var->binding;
+  var->var->data.explicit_binding = var->explicit_binding;
   var->var->data.descriptor_set = var->descriptor_set;
   var->var->data.index = var->input_attachment_index;
 
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 09/21] spirv: Get rid of vtn_variable_mode_image/sampler

[Alejandro Piñeiro]

From: Neil Roberts 

vtn_variable_mode_image and _sampler are instead replaced with
vtn_variable_mode_uniform which encompasses both of them. In the few
places where it was neccessary to distinguish between the two, the
GLSL type of the pointer is used instead.

The main reason to do this is that on OpenGL it is permitted to put
images and samplers into structs and declare a uniform with them. That
means that variables can now have a mix of uniform, sampler and image
modes so picking a single one of those modes for a variable no longer
makes sense.

This fixes OpLoad on a sampler within a struct which was previously
using the variable mode to determine whether it was a sampler or not.
The type of the variable is a struct so it was not being considered to
be uniform mode even though the member being loaded should be sampler
mode.

Signed-off-by: Eduardo Lima 
Signed-off-by: Neil Roberts 
---
 src/compiler/spirv/spirv_to_nir.c  |  4 ++--
 src/compiler/spirv/vtn_cfg.c   |  4 ++--
 src/compiler/spirv/vtn_private.h   |  2 --
 src/compiler/spirv/vtn_variables.c | 43 +++---
 4 files changed, 16 insertions(+), 37 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 78437428aa7..7d4fbbc1909 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3722,10 +3722,10 @@ vtn_handle_body_instruction(struct vtn_builder *b, 
SpvOp opcode,
case SpvOpImageQuerySize: {
   struct vtn_pointer *image =
  vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
-  if (image->mode == vtn_variable_mode_image) {
+  if (glsl_type_is_image(image->type->type)) {
  vtn_handle_image(b, opcode, w, count);
   } else {
- vtn_assert(image->mode == vtn_variable_mode_sampler);
+ vtn_assert(glsl_type_is_sampler(image->type->type));
  vtn_handle_texture(b, opcode, w, count);
   }
   break;
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index e7d2f9ea614..2c3bf698cc2 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -124,10 +124,10 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
 without_array = without_array->array_element;
 
  if (glsl_type_is_image(without_array->type)) {
-vtn_var->mode = vtn_variable_mode_image;
+vtn_var->mode = vtn_variable_mode_uniform;
 param->interface_type = without_array->type;
  } else if (glsl_type_is_sampler(without_array->type)) {
-vtn_var->mode = vtn_variable_mode_sampler;
+vtn_var->mode = vtn_variable_mode_uniform;
 param->interface_type = without_array->type;
  } else {
 vtn_var->mode = vtn_variable_mode_param;
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 183024e14f4..98bec389fcd 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -406,8 +406,6 @@ enum vtn_variable_mode {
vtn_variable_mode_ubo,
vtn_variable_mode_ssbo,
vtn_variable_mode_push_constant,
-   vtn_variable_mode_image,
-   vtn_variable_mode_sampler,
vtn_variable_mode_workgroup,
vtn_variable_mode_input,
vtn_variable_mode_output,
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index eb8a9ca0084..6d1eede5ed0 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1544,9 +1544,7 @@ var_decoration_cb(struct vtn_builder *b, struct vtn_value 
*val, int member,
  vtn_var->mode == vtn_variable_mode_output) {
  is_vertex_input = false;
  location += vtn_var->patch ? VARYING_SLOT_PATCH0 : VARYING_SLOT_VAR0;
-  } else if (vtn_var->mode != vtn_variable_mode_uniform &&
- vtn_var->mode != vtn_variable_mode_sampler &&
- vtn_var->mode != vtn_variable_mode_image) {
+  } else if (vtn_var->mode != vtn_variable_mode_uniform) {
  vtn_warn("Location must be on input, output, uniform, sampler or "
   "image variable");
  return;
@@ -1624,12 +1622,7 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
   nir_mode = 0;
   break;
case SpvStorageClassUniformConstant:
-  if (glsl_type_is_image(interface_type->type))
- mode = vtn_variable_mode_image;
-  else if (glsl_type_is_sampler(interface_type->type))
- mode = vtn_variable_mode_sampler;
-  else
- mode = vtn_variable_mode_uniform;
+  mode = vtn_variable_mode_uniform;
   nir_mode = nir_var_uniform;
   break;
case SpvStorageClassPushConstant:
@@ -1772,11 +1765,11 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
case vtn_variable_mode_ssbo:
   b->shader->info.num_ssbos++;

[Mesa-dev] [PATCH v2 08/21] spirv: translate default-block uniforms

[Alejandro Piñeiro]

From: Nicolai Hähnle 

They are supported by SPIR-V for ARB_gl_spirv.

v2 (changes on top of Nicolai's original patch):
   * Handle UniformConstant storage class for uniforms other than
 samplers and images. (Eduardo Lima)
   * Handle location decoration also for samplers and images. (Eduardo
 Lima)
   * Rebase update (spirv_to_nir options added, logging changes, and
 others) (Alejandro Piñeiro)

Signed-off-by: Nicolai Hähnle 
Signed-off-by: Eduardo Lima 
Signed-off-by: Alejandro Piñeiro 
---
 src/compiler/spirv/vtn_private.h   |  1 +
 src/compiler/spirv/vtn_variables.c | 25 +++--
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index b501bbf9b4a..183024e14f4 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -402,6 +402,7 @@ enum vtn_variable_mode {
vtn_variable_mode_local,
vtn_variable_mode_global,
vtn_variable_mode_param,
+   vtn_variable_mode_uniform,
vtn_variable_mode_ubo,
vtn_variable_mode_ssbo,
vtn_variable_mode_push_constant,
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index fd8ab7f247a..eb8a9ca0084 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1544,8 +1544,11 @@ var_decoration_cb(struct vtn_builder *b, struct 
vtn_value *val, int member,
  vtn_var->mode == vtn_variable_mode_output) {
  is_vertex_input = false;
  location += vtn_var->patch ? VARYING_SLOT_PATCH0 : VARYING_SLOT_VAR0;
-  } else {
- vtn_warn("Location must be on input or output variable");
+  } else if (vtn_var->mode != vtn_variable_mode_uniform &&
+ vtn_var->mode != vtn_variable_mode_sampler &&
+ vtn_var->mode != vtn_variable_mode_image) {
+ vtn_warn("Location must be on input, output, uniform, sampler or "
+  "image variable");
  return;
   }
 
@@ -1611,7 +1614,9 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
  mode = vtn_variable_mode_ssbo;
  nir_mode = 0;
   } else {
- vtn_fail("Invalid uniform variable type");
+ /* Default-block uniforms, coming from gl_spirv */
+ mode = vtn_variable_mode_uniform;
+ nir_mode = nir_var_uniform;
   }
   break;
case SpvStorageClassStorageBuffer:
@@ -1619,15 +1624,13 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
   nir_mode = 0;
   break;
case SpvStorageClassUniformConstant:
-  if (glsl_type_is_image(interface_type->type)) {
+  if (glsl_type_is_image(interface_type->type))
  mode = vtn_variable_mode_image;
- nir_mode = nir_var_uniform;
-  } else if (glsl_type_is_sampler(interface_type->type)) {
+  else if (glsl_type_is_sampler(interface_type->type))
  mode = vtn_variable_mode_sampler;
- nir_mode = nir_var_uniform;
-  } else {
- vtn_fail("Invalid uniform constant variable type");
-  }
+  else
+ mode = vtn_variable_mode_uniform;
+  nir_mode = nir_var_uniform;
   break;
case SpvStorageClassPushConstant:
   mode = vtn_variable_mode_push_constant;
@@ -1795,11 +1798,13 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
case vtn_variable_mode_global:
case vtn_variable_mode_image:
case vtn_variable_mode_sampler:
+   case vtn_variable_mode_uniform:
   /* For these, we create the variable normally */
   var->var = rzalloc(b->shader, nir_variable);
   var->var->name = ralloc_strdup(var->var, val->name);
   var->var->type = var->type->type;
   var->var->data.mode = nir_mode;
+  var->var->data.location = -1;
 
   switch (var->mode) {
   case vtn_variable_mode_image:
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 00/21] ARB_gl_spirv: support for uniforms and some extras

[Alejandro Piñeiro]

Hi, this is the second version for this series. The info for the
original one can be read here:

https://lists.freedesktop.org/archives/mesa-dev/2018-April/192512.html

Some of the patches are already reviewed (thanks to Timothy Arceri).

The main differences between v1 and v2 are:

 * The NIR linker was moved from compiler/nir to compiler/glsl as
   agreed with Timothy Arceri during the review of v1. Due this
   change, several methods were also renamed.

 * The patch "i965: account for NIR uniforms without name" changed
   too, due some issues we found since v1.

 * The patch "nir/linker: add some cross stage uniform validation" was
   dropped, as we found that was incomplete/wrong, and we would need
   to re-think this kind of validations. So this series doesn't
   include any cross-stage uniform validation. That it is ok for this
   series, as it is about the core of the uniform support, but not the
   full feature yet.

The tree for this series can be found on the following repository:

   * https://github.com/Igalia/mesa/tree/arb_gl_spirv-series2-uniforms-v1

And can be tested (although it would be needed to use
MESA_EXTENSION_OVERRIDE) with the following piglit series:

   * https://github.com/Igalia/piglit/tree/arb_gl_spirv-series1-uniforms-v1


Alejandro Piñeiro (4):
  i965: use gl_shader_program_data::spirv
  mesa/main: add NULL name check when searching for a resource name
  compiler/link: add linker_util.h, move linker_error/warning to it
  compiler/link: move add_program_resource to linker_util

Eduardo Lima Mitev (10):
  mesa/main: Add a 'spirv' flag to gl_shader_program_data
  nir/lower_samplers: Limit assert to GLSL shader programs
  nir/types: Add a glsl_get_component_slots() utility
  nir/types: Add a utility wrapper to glsl_type::sampler_index()
  anv/nir: Use nir_variable's type if interface_type is null
  nir/linker: Add gl_nir_link_uniforms()
  nir/linker: Add nir_build_program_resource_list()
  i965: Build SPIR-V programs' resource list using NIR
  i965: account for NIR uniforms without name
  i965: Link uniforms of SPIR-V programs using the NIR linker

Neil Roberts (6):
  nir: Add explicit_binding to nir_variable
  spirv: Get rid of vtn_variable_mode_image/sampler
  spirv: Set nir_variable->explicit_binding
  nir/linker: Set the uniform initial values
  i965: Update TexturesUsed after linking the shaders
  i965: Setup glsl uniforms by index rather than name matching

Nicolai Hähnle (1):
  spirv: translate default-block uniforms

 src/compiler/Makefile.sources  |   6 +
 .../glsl/gl_nir_link_uniform_initializers.c| 292 +
 src/compiler/glsl/gl_nir_link_uniforms.c   | 461 +
 src/compiler/glsl/gl_nir_linker.c  |  93 +
 src/compiler/glsl/gl_nir_linker.h  |  47 +++
 src/compiler/glsl/gl_nir_lower_samplers.c  |   3 +-
 src/compiler/glsl/glsl_to_nir.cpp  |   1 +
 .../glsl/link_uniform_block_active_visitor.cpp |   1 +
 src/compiler/glsl/linker.cpp   |  76 +---
 src/compiler/glsl/linker.h |   8 +-
 src/compiler/glsl/linker_util.cpp  |  64 +++
 src/compiler/glsl/linker_util.h|  48 +++
 src/compiler/glsl/meson.build  |   6 +
 src/compiler/glsl/program.h|   8 -
 src/compiler/nir/nir.h |   5 +
 src/compiler/nir_types.cpp |  13 +
 src/compiler/nir_types.h   |   2 +
 src/compiler/spirv/spirv_to_nir.c  |   4 +-
 src/compiler/spirv/vtn_cfg.c   |   4 +-
 src/compiler/spirv/vtn_private.h   |   4 +-
 src/compiler/spirv/vtn_variables.c |  56 +--
 src/intel/vulkan/anv_nir_apply_pipeline_layout.c   |   7 +-
 src/mesa/drivers/dri/i965/brw_link.cpp |  29 +-
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp |  52 ++-
 src/mesa/drivers/dri/i965/brw_program.c|   2 +-
 src/mesa/main/mtypes.h |   6 +
 src/mesa/main/shader_query.cpp |   5 +
 src/mesa/program/ir_to_mesa.cpp|   1 +
 28 files changed, 1167 insertions(+), 137 deletions(-)
 create mode 100644 src/compiler/glsl/gl_nir_link_uniform_initializers.c
 create mode 100644 src/compiler/glsl/gl_nir_link_uniforms.c
 create mode 100644 src/compiler/glsl/gl_nir_linker.c
 create mode 100644 src/compiler/glsl/gl_nir_linker.h
 create mode 100644 src/compiler/glsl/linker_util.cpp
 create mode 100644 src/compiler/glsl/linker_util.h

-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 06/21] nir/types: Add a glsl_get_component_slots() utility

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

It is basically a wrapper around glsl_type::component_slots().

Reviewed-by: Timothy Arceri 
---
 src/compiler/nir_types.cpp | 6 ++
 src/compiler/nir_types.h   | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 78b66803f08..51ca797497e 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -124,6 +124,12 @@ glsl_count_attribute_slots(const struct glsl_type *type,
return type->count_attribute_slots(is_vertex_input);
 }
 
+unsigned
+glsl_get_component_slots(const struct glsl_type *type)
+{
+   return type->component_slots();
+}
+
 const char *
 glsl_get_struct_elem_name(const struct glsl_type *type, unsigned index)
 {
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 5b441af1486..9c81980042f 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -73,6 +73,7 @@ unsigned glsl_get_aoa_size(const struct glsl_type *type);
 
 unsigned glsl_count_attribute_slots(const struct glsl_type *type,
 bool is_vertex_input);
+unsigned glsl_get_component_slots(const struct glsl_type *type);
 
 const char *glsl_get_struct_elem_name(const struct glsl_type *type,
   unsigned index);
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 07/21] nir/types: Add a utility wrapper to glsl_type::sampler_index()

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

I think it is more accurate to call it a sampler target (?).
---
 src/compiler/nir_types.cpp | 7 +++
 src/compiler/nir_types.h   | 1 +
 2 files changed, 8 insertions(+)

diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 51ca797497e..d2b2a93b207 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -150,6 +150,13 @@ glsl_get_sampler_result_type(const struct glsl_type *type)
return (glsl_base_type)type->sampled_type;
 }
 
+unsigned
+glsl_get_sampler_target(const struct glsl_type *type)
+{
+   assert(glsl_type_is_sampler(type));
+   return type->sampler_index();
+}
+
 unsigned
 glsl_get_record_location_offset(const struct glsl_type *type,
 unsigned length)
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 9c81980042f..1107cfd73f2 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -80,6 +80,7 @@ const char *glsl_get_struct_elem_name(const struct glsl_type 
*type,
 
 enum glsl_sampler_dim glsl_get_sampler_dim(const struct glsl_type *type);
 enum glsl_base_type glsl_get_sampler_result_type(const struct glsl_type *type);
+unsigned glsl_get_sampler_target(const struct glsl_type *type);
 
 unsigned glsl_get_record_location_offset(const struct glsl_type *type,
  unsigned length);
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 05/21] nir/lower_samplers: Limit assert to GLSL shader programs

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

Vulkan has the concept of separate image and sampler objects in the
SPIR-V code whereas GL conflates them into one. nir_lower_samplers
contains an assert to verify that sampler operand is not being set on
the nir instruction. However when the code comes from spirv_to_nir the
sampler operand is always set. GL_arb_gl_spirv explicitly states that
OpTypeSampler is not supported so it retains the GL behaviour of not
being able to seperate them. Therefore the sampler will always be the
same as the texture. This GL version of the lowering code ignores
instr->sampler and sets instr->sampler_index to the same value as
instr->texture_index. Some other places in the code (such as in
nir_print) assume that once the instruction is lowered then both
instr->texture and instr->sampler will be NULL, so to keep this
behaviour we now set instr->sampler to NULL after ignoring it to fill
in instr->sampler_index.

Signed-off-by: Eduardo Lima 
Signed-off-by: Neil Roberts 
---
 src/compiler/glsl/gl_nir_lower_samplers.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/gl_nir_lower_samplers.c 
b/src/compiler/glsl/gl_nir_lower_samplers.c
index a53fabb7e62..c54455f91de 100644
--- a/src/compiler/glsl/gl_nir_lower_samplers.c
+++ b/src/compiler/glsl/gl_nir_lower_samplers.c
@@ -93,7 +93,7 @@ lower_sampler(nir_tex_instr *instr, const struct 
gl_shader_program *shader_progr
   return false;
 
/* In GLSL, we only fill out the texture field.  The sampler is inferred */
-   assert(instr->sampler == NULL);
+   assert(instr->sampler == NULL || shader_program->data->spirv);
 
instr->texture_index = 0;
unsigned location = instr->texture->var->data.location;
@@ -125,6 +125,7 @@ lower_sampler(nir_tex_instr *instr, const struct 
gl_shader_program *shader_progr
instr->sampler_index = instr->texture_index;
 
instr->texture = NULL;
+   nir_instr_rewrite_deref(>instr, >sampler, NULL);
 
return true;
 }
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 03/21] mesa/main: add NULL name check when searching for a resource name

[Alejandro Piñeiro]

Since ARB_gl_spirv name reflection can be missing. piglit
shader_runner does several resource checking, so this commit is useful
to get even the more simple piglit tests running without crashing on
SPIR-V mode.

Reviewed-by: Timothy Arceri 
---
 src/mesa/main/shader_query.cpp | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 86064a98b97..11ecd71c575 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -533,6 +533,11 @@ _mesa_program_resource_find_name(struct gl_shader_program 
*shProg,
 
   /* Resource basename. */
   const char *rname = _mesa_program_resource_name(res);
+
+  /* Since ARB_gl_spirv lack of name reflections is a possibility */
+  if (rname == NULL)
+ continue;
+
   unsigned baselen = strlen(rname);
   unsigned baselen_without_array_index = baselen;
   const char *rname_last_square_bracket = strrchr(rname, '[');
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 01/21] mesa/main: Add a 'spirv' flag to gl_shader_program_data

[Alejandro Piñeiro]

From: Eduardo Lima Mitev 

This will be used by the linker code to differentiate between programs
made out of SPIR-V or GLSL shaders.

This was rejected in the past, assuming that it was equivalent to
check for "shProg->_LinkedShaders[stage]->spirv_data != NULL". But:

  * At some points of the linking process it would be needed to check
if _LinkerShaders[stage] is present, so the full check would be:

"shProg->_LinkedShaders[stage] != NULL &&
 shProg->_LinkedShaders[stage]->spirv_data != NULL"

  * Sometimes you would like to do some specific to SPIR-V
independently of the stage, or for any stage. For example, "link
all the uniforms, for all stages". In that case checking for the
flag would be equivalent to iterate all the _LinkedShaders and
check if there is any spirv_data available.

The former makes readibility really worse. Both could be solved by
adding two helpers. But adding a flag seems really more simple and
readable.

v2: added justification for the flag on the commit message (Alejandro)

Signed-off-by: Eduardo Lima 
Signed-off-by: Alejandro Piñeiro 
---
 src/mesa/main/mtypes.h  | 6 ++
 src/mesa/program/ir_to_mesa.cpp | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2ef12a444ea..236ed3e7f63 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2889,6 +2889,12 @@ struct gl_shader_program_data
 
/* Mask of stages this program was linked against */
unsigned linked_stages;
+
+   /* Whether the shaders of this program are loaded from SPIR-V binaries
+* (all have the SPIR_V_BINARY_ARB state). This was introduced by the
+* ARB_gl_spirv extension.
+*/
+   bool spirv;
 };
 
 /**
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 60fb24bf664..2908819d28e 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -3153,6 +3153,7 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
   "SPIR_V_BINARY_ARB state");
   }
}
+   prog->data->spirv = spirv;
 
if (prog->data->LinkStatus) {
   if (!spirv)
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 02/21] i965: use gl_shader_program_data::spirv

[Alejandro Piñeiro]

---
 src/mesa/drivers/dri/i965/brw_program.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index fc77926d6e0..39c2d2a3581 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -77,7 +77,7 @@ brw_create_nir(struct brw_context *brw,
 
/* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
if (shader_prog) {
-  if (shader_prog->_LinkedShaders[stage]->spirv_data)
+  if (shader_prog->data->spirv)
  nir = _mesa_spirv_to_nir(ctx, shader_prog, stage, options);
   else
  nir = glsl_to_nir(shader_prog, stage, options);
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 04/21] nir: Add explicit_binding to nir_variable

[Alejandro Piñeiro]

From: Neil Roberts 

This is copied from the corresponding value in ir_variable. The
intention is to eventually use it in a pure-NIR linker.

Reviewed-by: Timothy Arceri 
---
 src/compiler/glsl/glsl_to_nir.cpp | 1 +
 src/compiler/nir/nir.h| 5 +
 2 files changed, 6 insertions(+)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 8e5e9c34912..817e9dad2b8 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -435,6 +435,7 @@ nir_visitor::visit(ir_variable *ir)
var->data.index = ir->data.index;
var->data.descriptor_set = 0;
var->data.binding = ir->data.binding;
+   var->data.explicit_binding = ir->data.explicit_binding;
var->data.bindless = ir->data.bindless;
var->data.offset = ir->data.offset;
var->data.image.read_only = ir->data.memory_read_only;
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index a379928cdcd..1c1fef3b2ef 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -252,6 +252,11 @@ typedef struct nir_variable {
*/
   unsigned bindless:1;
 
+  /**
+   * Was an explicit binding set in the shader?
+   */
+  unsigned explicit_binding:1;
+
   /**
* \brief Layout qualifier for gl_FragDepth.
*
-- 
2.14.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] scons: Add PROGRAM_NIR_FILES.

[Vinson Lee]

Fix SCons build error.

  Linking build/linux-x86_64-debug/gallium/targets/libgl-xlib/libGL.so.1.5 ...
build/linux-x86_64-debug/mesa/libmesa.a(st_program.os): In function 
`st_translate_prog_to_nir':
src/mesa/state_tracker/st_program.c:392: undefined reference to `prog_to_nir'

Fixes: 5c33e8c7729e ("st/nir: use NIR for asm programs")
Signed-off-by: Vinson Lee 
---
 src/mesa/SConscript | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/SConscript b/src/mesa/SConscript
index ba98ad4323c5..5a21b64f561e 100644
--- a/src/mesa/SConscript
+++ b/src/mesa/SConscript
@@ -42,6 +42,7 @@ env.CFile('program/program_parse.tab.c', 
'program/program_parse.y')
 mesa_sources = (
 source_lists['MESA_FILES'] +
 source_lists['PROGRAM_FILES'] +
+source_lists['PROGRAM_NIR_FILES'] +
 source_lists['STATETRACKER_FILES']
 )
 
-- 
2.17.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [AppVeyor] mesa master #7686 completed

[AppVeyor]

Build mesa 7686 completed



Commit 26ddc4f9e1 by Vinson Lee on 5/12/2018 7:27 AM:

scons: Add PROGRAM_NIR_FILES.\n\nFix SCons build error.\n\n  Linking build/linux-x86_64-debug/gallium/targets/libgl-xlib/libGL.so.1.5 ...\nbuild/linux-x86_64-debug/mesa/libmesa.a(st_program.os): In function `st_translate_prog_to_nir':\nsrc/mesa/state_tracker/st_program.c:392: undefined reference to `prog_to_nir'\n\nFixes: 5c33e8c7729e ("st/nir: use NIR for asm programs")\nSigned-off-by: Vinson Lee 


Configure your notification preferences

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev