Re: [Mesa-dev] [PATCH 04/22] nir/opcodes: Make unpack_half_2x16_split_* variable-width

On Friday, August 17, 2018 1:06:10 PM PDT Jason Ekstrand wrote: > There is nothing inherent about these opcodes that requires them to only > take scalars. It's very convenient if we let them take vectors as well. > --- > src/compiler/nir/nir_opcodes.py | 8 > 1 file changed, 4

Re: [Mesa-dev] [PATCH 14/22] intel/compiler: Do image load/store lowering to NIR

On Friday, August 17, 2018 1:06:20 PM PDT Jason Ekstrand wrote: [snip] > +# Intel-specific query for loading from the brw_image_param struct passed > +# into the shader as a uniform. The variable is a deref to the image > +# variable. The const index specifies which of the six parameters to load.

[Mesa-dev] [PATCH 2/2] st/mesa, gallium: add a workaround for No Mans Sky

The spec seems clear this is not allowed but the Nvidia binary forces apps to add layout qualifiers so this works around the issue for No Mans Sky until the CTS can be sorted out. --- src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 + src/gallium/include/state_tracker/st_api.h |

[Mesa-dev] [PATCH 1/2] glsl: add a mechanism to allow layout qualifiers on function params

The spec is quite clear this is not allowed: From Section 4.4. (Layout Qualifiers) of the GLSL 4.60 spec: "Layout qualifiers can appear in several forms of declaration. They can appear as part of an interface block definition or block member, as shown in the grammar in

[Mesa-dev] [PATCH] ac/radeonsi: fix CIK copy max size

From: Dave Airlie While adding transfer queues to radv, I started writing some tests, the first test I wrote fell over copying a buffer larger than this limit. Checked AMDVLK and found the correct limit. Cc: --- src/amd/common/sid.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

Re: [Mesa-dev] [PATCH 3/3] i965/screen: Allow modifiers on sRGB formats

On Tue, Aug 28, 2018 at 5:22 PM Jason Ekstrand wrote: > This effectively reverts a26693493570a9d0f0fba1be617e01ee7bfff4db which > was a misguided attempt at protecting intel_query_dma_buf_modifiers from > invalid formats. Unfortunately, in some internal EGL cases, we can get > an SRGB format

[Mesa-dev] [PATCH v2] mesa: enable ARB_direct_state_access in compat for GL3.1+

We could enable it for lower versions of GL but this allows us to just use the existing version/extension checks that are already used by the core profile. v2: fix potential crash in no error path --- src/mapi/glapi/gen/apiexec.py| 194 +++

[Mesa-dev] [PATCH] glsl: skip stringification in preprocessor if in unreachable branch

This fixes compilation of some "No Mans Sky" shaders where the stringification happens in branches intended for DX12. --- Piglit tests: https://patchwork.freedesktop.org/series/48850/ src/compiler/glsl/glcpp/glcpp-lex.l | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] ac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI

BTW, radv doesn't use the function, so it will have this bug. Marek On Tue, Aug 28, 2018 at 5:47 PM, Bas Nieuwenhuizen wrote: > Reviewed-by: Bas Nieuwenhuizen > On Tue, Aug 28, 2018 at 8:41 PM Marek Olšák wrote: >> >> From: Marek Olšák >> >> This fixes VM faults and corruption. >> >> Cc:

Re: [Mesa-dev] [PATCH 5/9] nir: Add a local dead write vars removal pass

On Mon, Aug 27, 2018 at 4:55 PM Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > (Disregard the incomplete mail, still adapting to notmuch-emacs). > > Jason Ekstrand writes: > > >> +static nir_deref_path * > >> +get_path(struct state *state, nir_deref_instr *deref) > >> +{ > >>

[Mesa-dev] [PATCH] virgl: don't send a shader create with no data. (v2)

From: Dave Airlie This fixes the situation where we'd send a shader with just the header and no data. piglit/glsl-max-varyings test was causing this to happen, and the renderer fix was breaking it. v2: drop fprintf --- src/gallium/drivers/virgl/virgl_encode.c | 2 +- 1 file changed, 1

[Mesa-dev] [PATCH] virgl: don't send a shader create with no data.

From: Dave Airlie This fixes the situation where we'd send a shader with just the header and no data. piglit/glsl-max-varyings test was causing this to happen, and the renderer fix was breaking it. --- src/gallium/drivers/virgl/virgl_encode.c | 3 ++- 1 file changed, 2 insertions(+), 1

[Mesa-dev] [PATCH V2] i965/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set. V2: Fix bit mask (Chris Wilson) Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 4 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++ 2 files changed, 11 insertions(+)

Re: [Mesa-dev] [PATCH 4/5 v2] i965/fs: Emit BRW_AOP_INC or BRW_AOP_DEC for imageAtomicAdd of +1 or -1

Reviewed-by: Jason Ekstrand On Mon, Aug 27, 2018 at 3:55 PM Ian Romanick wrote: > From: Ian Romanick > > v2: Refactor selection of atomic opcode to a separate function. > Suggested by Jason. > > No changes on any other Intel platforms. > > Skylake > total instructions in shared programs:

Re: [Mesa-dev] [PATCH 2/5 v2] i965/fs: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1

Reviewed-by: Jason Ekstrand On Mon, Aug 27, 2018 at 3:54 PM Ian Romanick wrote: > From: Ian Romanick > > Funny story... a single shader was hurt for instructions, spills, fills. > That same shader was also the most helped for cycles. #GPUsAreWeird > > No changes on any other Intel platform.

Re: [Mesa-dev] [PATCH v4 7/7] nir: add loop unroll support for complex wrapper loops

On 29/08/18 03:59, Jason Ekstrand wrote: On Mon, Aug 27, 2018 at 4:10 AM Timothy Arceri > wrote: In GLSL IR we cheat with switch statements and simply convert them into loops with a single iteration. This allowed us to make use of the existing jump

[Mesa-dev] [PATCH 2/3] egl/dri2: Guard against invalid fourcc formats

We already reject attempts to import images with invalid fourcc formats but don't really guard the queries all that well. This makes us error out in any calls to eglQueryDmaBufModifiersEXT if the given format is not a valid fourcc format. We also add an assert to ensure that drivers don't

[Mesa-dev] [PATCH 3/3] i965/screen: Allow modifiers on sRGB formats

This effectively reverts a26693493570a9d0f0fba1be617e01ee7bfff4db which was a misguided attempt at protecting intel_query_dma_buf_modifiers from invalid formats. Unfortunately, in some internal EGL cases, we can get an SRGB format validly in this function. Rejecting such formats caused us to not

[Mesa-dev] [PATCH 1/3] egl/dri2: Add a helper for the number of planes for a FOURCC format

This also serves as a convenient "is this a fourcc format" check as well which we'll take advantage of in the next commit. Cc: mesa-sta...@lists.freedesktop.org --- src/egl/drivers/dri2/egl_dri2.c | 32 +--- 1 file changed, 21 insertions(+), 11 deletions(-) diff

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

On 08/28/2018 12:40 PM, Ian Romanick wrote: > On 08/28/2018 12:09 PM, Rogovin, Kevin wrote: >> Hi, >> >>> Is that tested? >> >> I have tested it in a simple shader test I made (i.e. not in a dedicated >> test suite such as dEQP, piglit or something else). The created assembly is >> identical.

Re: [Mesa-dev] [PATCH] mesa: allow GL_UNSIGNED_BYTE type for SNORM reads

This is: Tested-by: Andres Gomez On Mon, 2018-08-27 at 14:46 +0300, Tapani Pälli wrote: > OpenGL ES spec states: >"For normalized fixed-point rendering surfaces, the combination format > RGBA and type UNSIGNED_BYTE is accepted." > > This fixes following failing VK-GL-CTS tests: > >

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

On Tue, Aug 28, 2018 at 4:13 PM Rogovin, Kevin wrote: > Hi, > > > You are completely missing the point. Any test which tests the > > GL_ARB_fragment_shader_interlock extension with a > > beginInvocationInterlockARB() call inside of control-flow would be an > > invalid test for

[Mesa-dev] [PATCH] docs/relnotes: Add AMD_depth_clamp_separate for i965

Signed-off-by: Sagar Ghuge --- docs/relnotes/18.3.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html index 71fb41ca86..6e5e3ef93b 100644 --- a/docs/relnotes/18.3.0.html +++ b/docs/relnotes/18.3.0.html @@ -51,6 +51,7 @@ Note: some of

Re: [Mesa-dev] [PATCH] ac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI

Reviewed-by: Bas Nieuwenhuizen On Tue, Aug 28, 2018 at 8:41 PM Marek Olšák wrote: > > From: Marek Olšák > > This fixes VM faults and corruption. > > Cc: 18.1 18.2 > --- > src/amd/common/ac_surface.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

Andrii, Samuel, should we also include this in the stable queues ? On Wed, 2018-08-15 at 18:20 +0300, asimiklit.w...@gmail.com wrote: > From: Andrii Simiklit > > When the SVBI Payload Enable is false I guess the register R1.4 > which contains the Maximum Streamed Vertex Buffer Index is filled

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, > You are completely missing the point. Any test which tests the > GL_ARB_fragment_shader_interlock extension with a > beginInvocationInterlockARB() call inside of control-flow would be an > invalid test for GL_ARB_fragment_shader_interlock since that behavior is > undefined. Therefore, any

Re: [Mesa-dev] [PATCH 1/2] st/mesa: help fix stencil border color for GL_DEPTH_STENCIL textures

ping On Mon, Aug 20, 2018 at 11:20 PM, Marek Olšák wrote: > From: Marek Olšák > > GL_STENCIL_INDEX uses GL_INTENSITY for the border color, which is nicer > to hardware that doesn't read the stencil border value from the X channel. > > This fixes a bunch of dEQP tests on Vega & Raven. > > Cc:

[Mesa-dev] [PATCH] i965/screen: Allow modifiers on sRGB formats

This effectively reverts a26693493570a9d0f0fba1be617e01ee7bfff4db which was a misguided attempt at protecting intel_query_dma_buf_modifiers from invalid formats. Unfortunately, in some internal EGL cases, we can get an SRGB format validly in this function. Rejecting such formats caused us to not

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Kevin, Your email messages are missing the in-reply-to header, making this thread completely incomprehensible on the mailing list. Please fix your mail client to include the standard headers so we can follow what you are saying. -Mark "Rogovin, Kevin" writes: > Hi, > >> Having the same

Re: [Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

On Tue, Aug 28, 2018 at 10:57 AM Chris Wilson wrote: > > Quoting Anuj Phogat (2018-08-28 18:53:59) > > h/w specification requires this bit to be always set. > > > > Suggested-by: Kenneth Graunke > > Signed-off-by: Anuj Phogat > > --- > > src/mesa/drivers/dri/i965/brw_defines.h | 4 >

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

On 08/28/2018 12:09 PM, Rogovin, Kevin wrote: > Hi, > >> Is that tested? > > I have tested it in a simple shader test I made (i.e. not in a dedicated test > suite such as dEQP, piglit or something else). The created assembly is > identical. The specific example is a shader where I replace

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

On Tue, Aug 28, 2018 at 2:10 PM Rogovin, Kevin wrote: > Hi, > > > Is that tested? > > I have tested it in a simple shader test I made (i.e. not in a dedicated > test suite such as dEQP, piglit or something else). The created assembly is > identical. The specific example is a shader where I

[Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, > Is that tested? I have tested it in a simple shader test I made (i.e. not in a dedicated test suite such as dEQP, piglit or something else). The created assembly is identical. The specific example is a shader where I replace calls of beginFragmentShaderOrderingINTEL() with

Re: [Mesa-dev] [PATCH] gallium: fix drivers to report something for PIPE_CAP_VIEWPORT_SUBPIXEL_BITS

This is not correct. The problem here is that there's only a viewport subpixel accuracy query, but the state tracker uses this to both set subpixel (which is raterization subpixel accuracy) as well as viewport subpixel bits. The former needs to be at least 4 (dx10 requires 8), whereas the latter

[Mesa-dev] [PATCH] ac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI

From: Marek Olšák This fixes VM faults and corruption. Cc: 18.1 18.2 --- src/amd/common/ac_surface.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 2f4f0f8884f..94723dc9c09 100644 ---

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

On Tue, Aug 28, 2018 at 1:23 PM Rogovin, Kevin wrote: > Hi, > > > Having the same underlying compiler intrinsic and having the same > behavior > > are not the same thing. The INTEL extension allows strictly more > > functionality than the ARB extension so it needs even more testing. In > >

[Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, > Having the same underlying compiler intrinsic and having the same behavior > are not the same thing. The INTEL extension allows strictly more > functionality than the ARB extension so it needs even more testing. In > particular, it allows you to do the barrier in non-uniform control-flow

[Mesa-dev] [PATCH] gallium: fix drivers to report something for PIPE_CAP_VIEWPORT_SUBPIXEL_BITS

From: Marek Olšák --- src/gallium/drivers/etnaviv/etnaviv_screen.c | 4 +++- src/gallium/drivers/freedreno/freedreno_screen.c | 4 +++- src/gallium/drivers/i915/i915_screen.c | 4 +++- src/gallium/drivers/llvmpipe/lp_screen.c | 3 ++-

[Mesa-dev] [1/2] mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering.

Hi all, Patch addressing the missing enum warning is here: https://lists.freedesktop.org/archives/mesa-dev/2018-August/203796.html . Also, see my reply to Francisco why I think it is better to have a new intrinsic function for that. Best Regards, -Kevin

[Mesa-dev] [PATCH] mesa/state_tracker: explicitely handle case ir_intrinsic_begin_fragment_shader_ordering in visit_generic_intrinsic()

From: Kevin Rogovin --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 7b96947c60..48a7b030ce 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp

Re: [Mesa-dev] [PATCH 3/3] anv: Claim to support depthBounds for ID games

On Tue, Aug 28, 2018 at 12:40 PM Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > On 27/08/2018 23:48, Jason Ekstrand wrote: > > On Mon, Aug 27, 2018 at 12:50 PM Lionel Landwerlin < > lionel.g.landwer...@intel.com> wrote: > >> On 23/08/2018 16:13, Jason Ekstrand wrote: >> > --- >> >

Re: [Mesa-dev] [PATCH v4 7/7] nir: add loop unroll support for complex wrapper loops

On Mon, Aug 27, 2018 at 4:10 AM Timothy Arceri wrote: > In GLSL IR we cheat with switch statements and simply convert them > into loops with a single iteration. This allowed us to make use of > the existing jump instruction handling provided by the loop handing > code, it also allows dead code

Re: [Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

Quoting Anuj Phogat (2018-08-28 18:53:59) > h/w specification requires this bit to be always set. > > Suggested-by: Kenneth Graunke > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/brw_defines.h | 4 > src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++ > 2 files

Re: [Mesa-dev] [PATCH 07/14] st/mesa: set ctx->Const.SubPixelBits

On Tue, Aug 28, 2018 at 7:40 AM, Jakob Bornecrantz wrote: > On Thu, Aug 9, 2018 at 12:57 AM Marek Olšák wrote: >> >> From: Marek Olšák > > This patch causes regressions in dEQP[1] on virgl running on a > radeonSI device. Not a lot of drivers set > PIPE_CAP_VIEWPORT_SUBPIXEL_BITS but

[Mesa-dev] [PATCH] anv/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat --- src/intel/genxml/gen11.xml| 5 + src/intel/vulkan/genX_state.c | 14 ++ 2 files changed, 19 insertions(+) diff --git a/src/intel/genxml/gen11.xml

[Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 4 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++ 2 files changed, 11 insertions(+) diff --git

[Mesa-dev] [Bug 107477] [DXVK] Setting high shader quality in GTA V results in LLVM error

https://bugs.freedesktop.org/show_bug.cgi?id=107477 --- Comment #13 from Clément Guérin --- Let's try again: https://send.firefox.com/download/0a9b6178c5/#mjwYjQDZZbGvFqAKq5fhig -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the

Re: [Mesa-dev] [PATCH 3/3] anv: Claim to support depthBounds for ID games

On 27/08/2018 23:48, Jason Ekstrand wrote: On Mon, Aug 27, 2018 at 12:50 PM Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>> wrote: On 23/08/2018 16:13, Jason Ekstrand wrote: > --- >   src/intel/vulkan/anv_device.c | 9 + >   1 file changed, 9 insertions(+)

Re: [Mesa-dev] [PATCH v4 5/7] nir/opt_loop_unroll: Remove unneeded phis if we make progress

I'm not a huge fan of calling copy-prop here but I also don't see an easy way around it. Reviewed-by: Jason Ekstrand On Mon, Aug 27, 2018 at 4:09 AM Timothy Arceri wrote: > Now that SSA values can be derefs and they have special rules, we have > to be a bit more careful about our LCSSA phis.

Re: [Mesa-dev] [PATCH v4 6/7] nir: add loop unroll support for wrapper loops

Reviewed-by: Jason Ekstrand On Mon, Aug 27, 2018 at 4:09 AM Timothy Arceri wrote: > This adds support for unrolling the classic > > do { > // ... > } while (false) > > that is used to wrap multi-line macros. GLSL IR also wraps switch > statements in a loop like this. > >

Re: [Mesa-dev] [PATCH] anv: blorp: support multiple aspect blits

Thanks a lot! Looks like reviewing patches on gitlab could really help ;) - Lionel On 28/08/2018 18:18, Jason Ekstrand wrote: Assuming nothing got lost in the indent, looks good to me. Reviewed-by: Jason Ekstrand > On Tue, Aug 28, 2018 at 6:27 AM Lionel

Re: [Mesa-dev] [PATCH] anv: blorp: support multiple aspect blits

Assuming nothing got lost in the indent, looks good to me. Reviewed-by: Jason Ekstrand On Tue, Aug 28, 2018 at 6:27 AM Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > Newer blit tests are enabling depth blits. We currently don't > support it but can do by iterating over the aspects

Re: [Mesa-dev] [1/2] mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering.

On Tuesday, 2018-08-28 17:59:15 +0100, Rogovin, Kevin wrote: > Hi, > > Sighs; I missed that warning on the build since there is so much build > output. Fair enough; I'll send a few patches to drastically cut the build warnings later today/tomorrow :) > I can issue a small patch to handle the

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

"Works on an app" is not and never has been an acceptable testing plan for landing a new feature in Mesa. There need to be tests in piglit, dEQP, or one of the conformance suites. --Jason On Tue, Aug 28, 2018 at 11:15 AM Rogovin, Kevin wrote: > Hi, > > On the questions of tests: If people

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

On Tue, Aug 28, 2018 at 11:22 AM Manolova, Plamena < plamena.manol...@intel.com> wrote: > Hi Mark, > AFAIK there is no piglit test for this specific extension. However > underneath the hood it reuses the > functionality of ARB_fragment_shader_interlock, which has a test. I > believe the only

[Mesa-dev] [1/2] mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering.

Hi, Sighs; I missed that warning on the build since there is so much build output. I can issue a small patch to handle the missing enum. -Kevin ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH mesa] meson: consolidate langs lists

Quoting Eric Engestrom (2018-08-28 09:18:09) > Signed-off-by: Eric Engestrom > --- > src/util/xmlpool/meson.build | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/src/util/xmlpool/meson.build b/src/util/xmlpool/meson.build > index

Re: [Mesa-dev] [1/2] mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering.

On Monday, 2018-08-27 09:54:23 +0300, kevin.rogo...@intel.com wrote: > From: Kevin Rogovin > >This extension provides new GLSL built-in function >beginFragmentShaderOrderingIntel() that guarantees >(taking wording of GL_INTEL_fragment_shader_ordering >extension) that any memory

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

"Manolova, Plamena" writes: > Hi Mark, > AFAIK there is no piglit test for this specific extension. However > underneath the hood it reuses the functionality of > ARB_fragment_shader_interlock, which has a test. I believe the only > major difference between the two extensions is that unlike >

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, On 28.08.2018 19:15, Rogovin, Kevin wrote: On the questions of tests: If people want, I can adapt the test in piglit for ARB_fragment_shader_interlock to this INTEL one. In general, I have an app/library that uses the extension and testing of that does definitely work on i965 (which

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi Mark, AFAIK there is no piglit test for this specific extension. However underneath the hood it reuses the functionality of ARB_fragment_shader_interlock, which has a test. I believe the only major difference between the two extensions is that unlike beginInvocationInterlockARB,

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, Sorry for the doubly reply, but I wanted to add one more important bit in my thinking in addition to doing minimal code changes and following existing convention. The ARB/NV extensions defined a critical section where as the INTEL extension is just a barrier function. I suspect (but I do

[Mesa-dev] [PATCH mesa] meson: consolidate langs lists

Signed-off-by: Eric Engestrom --- src/util/xmlpool/meson.build | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/util/xmlpool/meson.build b/src/util/xmlpool/meson.build index 3d2de0cdc3a5fc45d1e4..8bdabcb825b776d06182 100644 --- a/src/util/xmlpool/meson.build

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, On the questions of tests: If people want, I can adapt the test in piglit for ARB_fragment_shader_interlock to this INTEL one. In general, I have an app/library that uses the extension and testing of that does definitely work on i965 (which should be utterly unsurprising since the

[Mesa-dev] [Bug 107727] [DXVK]Assassin's Creed Syndicate - Assertion "radv_image_view_init"

https://bugs.freedesktop.org/show_bug.cgi?id=107727 Bug ID: 107727 Summary: [DXVK]Assassin's Creed Syndicate - Assertion "radv_image_view_init" Product: Mesa Version: 18.2 Hardware: Other OS: All

Re: [Mesa-dev] [PATCH v4 2/7] nir: propagates if condition evaluation down some alu chains

On Mon, Aug 27, 2018 at 4:09 AM Timothy Arceri wrote: > v2: > - only allow nir_op_inot or nir_op_b2i when alu input is 1. > - use some helpers as suggested by Jason. > > shader-db IVB results: > > total instructions in shared programs: 9993483 -> 9993472 (-0.00%) > instructions in affected

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi, I followed the convention that was already present. The code from ARB/NV_fragment_shader_interlock had an intrinsic for begin critical section and an intrinsic for end critical section. I figured that since this extension has a completely different thinking (i.e. a memory barrier instead

Re: [Mesa-dev] [Mesa-stable] [PATCH] intel: decoder: unify MI_BB_START field naming

Quoting Lionel Landwerlin (2018-08-28 02:39:58) > Yes, I think so. You asked on another commit too, both are related and > this depends on other commits from Jason. > > Here is a list in order of cherry picking : > > commit f430a37fa75f534c3a114b0ec546fa14f05f5da1 > Author: Lionel Landwerlin >

Re: [Mesa-dev] [PATCH 1/2] mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering.

kevin.rogo...@intel.com writes: > From: Kevin Rogovin > >This extension provides new GLSL built-in function >beginFragmentShaderOrderingIntel() that guarantees >(taking wording of GL_INTEL_fragment_shader_ordering >extension) that any memory transactions issued by >shader

Re: [Mesa-dev] [PATCH 1/5] meson: Actually load translation files

Quoting Eric Engestrom (2018-08-28 07:34:26) > On Friday, 2018-08-24 07:13:41 -0700, Dylan Baker wrote: > > Currently we run the script but don't actually load any files, even in a > > tarball where they exist. > > > > Fixes: 3218056e0eb375eeda470058d06add1532acd6d4 > >("meson: Build i965

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Is there a piglit test that verifies that this feature works properly? writes: > From: Kevin Rogovin > > INTEL_fragment_shader_ordering provides the ability for shaders > to issue a call to gaurnantee memory write operation ordering > of overlapping pixels or samples. In contrast to >

Re: [Mesa-dev] [PATCH 2/2] i965: Add INTEL_fragment_shader_ordering support.

Are there any tests for this? --Jason On Mon, Aug 27, 2018 at 1:54 AM wrote: > From: Kevin Rogovin > > Adds suppport for INTEL_fragment_shader_ordering. We achieve > the fragment ordering by using the same instruction as for > beginInvocationInterlockARB() which is by issuing a

Re: [Mesa-dev] [PATCH v4 1/7] nir: evaluate if condition uses inside the if branches

On Mon, Aug 27, 2018 at 4:09 AM Timothy Arceri wrote: > Since we know what side of the branch we ended up on we can just > replace the use with a constant. > > All the spill changes in shader-db are from Dolphin uber shaders, > despite some small regressions the change is clearly positive. > >

[Mesa-dev] [Bug 106976] Compilation failure due to missing xcb_randr_lease_t

https://bugs.freedesktop.org/show_bug.cgi?id=106976 Sergii Romantsov changed: What|Removed |Added CC||b...@basnieuwenhuizen.nl ---

[Mesa-dev] [Bug 107146] swr doesn't compile with current LLVM 7.0 snapshots

https://bugs.freedesktop.org/show_bug.cgi?id=107146 --- Comment #3 from Alok Hota --- (In reply to Bernhard Rosenkraenzer from comment #0) > createInstructionSimplifierPass() has been removed in LLVM. This is used in > a few places in SWR; looks like this can safely be removed because it is >

Re: [Mesa-dev] [PATCH 1/5] meson: Actually load translation files

On Friday, 2018-08-24 07:13:41 -0700, Dylan Baker wrote: > Currently we run the script but don't actually load any files, even in a > tarball where they exist. > > Fixes: 3218056e0eb375eeda470058d06add1532acd6d4 >("meson: Build i965 and dri stack") > --- > src/util/xmlpool/meson.build |

Re: [Mesa-dev] [RFC 00/10] Let us welcome EGLDevice

Thanks Mathias, On 28 August 2018 at 08:31, Mathias Fröhlich wrote: > Hi Emil, > > On Friday, 3 August 2018 14:44:16 CEST Emil Velikov wrote: >> Hi all, >> >> This series implements the following extensions: >> - EGL_EXT_device_base >> - EGL_MESA_device_software >> - EGL_EXT_device_drm >> -

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

Hello, Thanks a lot) Regards, Andrii. On Tue, Aug 28, 2018 at 4:35 PM Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > On Tuesday, August 28, 2018 2:02:07 PM CEST Samuel Iglesias Gonsálvez > wrote: > > I'll do it later today. > > Done! > > Sam > > > > > Thanks for contributing! > > >

[Mesa-dev] [Bug 107477] [DXVK] Setting high shader quality in GTA V results in LLVM error

https://bugs.freedesktop.org/show_bug.cgi?id=107477 --- Comment #12 from Samuel Pitoiset --- Are you sure the link is correct? "This link has expired or never existed in the first place!" -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

On Tuesday, August 28, 2018 2:02:07 PM CEST Samuel Iglesias Gonsálvez wrote: > I'll do it later today. Done! Sam > > Thanks for contributing! > > Sam > > On 28/08/18 13:59, andrey simiklit wrote: > > Hi all, > > > > Could somebody push it if it seems good for all? > > > > Regards, > >

Re: [Mesa-dev] [PATCH 1/4] mesa: use C99 initializer in get_gl_override()

On Friday, 2018-08-24 14:05:57 +0100, Emil Velikov wrote: > From: Emil Velikov > > The overrides array contains entries indexed on the gl_api enum. > Use a C99 initializer to make it a bit more obvious. > > Signed-off-by: Emil Velikov Patches 1-3 are: Reviewed-by: Eric Engestrom Patch 4

Re: [Mesa-dev] [PATCH 07/14] st/mesa: set ctx->Const.SubPixelBits

On Tue, Aug 28, 2018 at 12:40:25PM +0100, Jakob Bornecrantz wrote: > On Thu, Aug 9, 2018 at 12:57 AM Marek Olšák wrote: > > > > From: Marek Olšák > > This patch causes regressions in dEQP[1] on virgl running on a > radeonSI device. Not a lot of drivers set > PIPE_CAP_VIEWPORT_SUBPIXEL_BITS but

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

I'll do it later today. Thanks for contributing! Sam On 28/08/18 13:59, andrey simiklit wrote: > Hi all, > > Could somebody push it if it seems good for all? > > Regards, > Andrii. > > On Thu, Aug 23, 2018 at 4:53 PM Samuel Iglesias Gonsálvez > mailto:sigles...@igalia.com>> wrote: > > The

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

Hi all, Could somebody push it if it seems good for all? Regards, Andrii. On Thu, Aug 23, 2018 at 4:53 PM Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > The patch seems fine to me. I also tested it on Intel CI and there were no > regressions. > > Reviewed-by: Samuel Iglesias

Re: [Mesa-dev] [PATCH 07/14] st/mesa: set ctx->Const.SubPixelBits

On Thu, Aug 9, 2018 at 12:57 AM Marek Olšák wrote: > > From: Marek Olšák This patch causes regressions in dEQP[1] on virgl running on a radeonSI device. Not a lot of drivers set PIPE_CAP_VIEWPORT_SUBPIXEL_BITS but SubPixelBits is by default set to 4, but this overwrites it without checking if

[Mesa-dev] [PATCH] anv: blorp: support multiple aspect blits

Newer blit tests are enabling depth blits. We currently don't support it but can do by iterating over the aspects masks (copy some logic from the CopyImage function). Signed-off-by: Lionel Landwerlin Fixes: 9f44745eca0e41 ("anv: Use blorp to implement VkBlitImage") ---

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Actually ignore my comment, I forgot that docs/features.txt is for non-vendor specific features only. I'll go ahead and push your patches. Sorry for the confusion. Thanks, Pam On Tue, Aug 28, 2018 at 1:04 PM Manolova, Plamena < plamena.manol...@intel.com> wrote: > Hi Kevin, > Could you also

[Mesa-dev] [Bug 107654] Account request Kevin Rogovin

https://bugs.freedesktop.org/show_bug.cgi?id=107654 Daniel Stone changed: What|Removed |Added CC||ja...@jlekstrand.net --- Comment #4

Re: [Mesa-dev] [PATCH 0/2] Implement INTEL_fragment_shader_ordering

Hi Kevin, Could you also mark the extension as done in docs/features.txt? Otherwise the series looks good to me and with that tiny change it's Reviewed-by: Plamena Manolova < plamena.manol...@intel.com> Thanks, Pam On Mon, Aug 27, 2018 at 9:56 AM wrote: > From: Kevin Rogovin > >

Re: [Mesa-dev] [PATCH] intel: decoder: handle 0 sized structs

Thanks Andres, Please see my response to Re: [Mesa-dev] [PATCH] intel: decoder: unify MI_BB_START field naming On 27/08/2018 22:20, Andres Gomez wrote: Lionel, should we also include this in the stable queues ? On Sat, 2018-08-25 at 18:23 +0100, Lionel Landwerlin wrote: Gen7.5 has a

Re: [Mesa-dev] [PATCH] intel: decoder: unify MI_BB_START field naming

Yes, I think so. You asked on another commit too, both are related and this depends on other commits from Jason. Here is a list in order of cherry picking : commit f430a37fa75f534c3a114b0ec546fa14f05f5da1 Author: Lionel Landwerlin Date:   Tue Aug 14 11:22:12 2018 +0100     intel: decoder:

Re: [Mesa-dev] [PATCH] nir: Remove outdated comment

On 28/08/18 03:18, Jason Ekstrand wrote: > Reviewed-by: Jason Ekstrand > > > On Mon, Aug 27, 2018 at 5:20 PM Caio Marcelo de Oliveira Filho > mailto:caio.olive...@intel.com>> wrote: > > --- > > The move of comapre functions landed before the suggestion to

[Mesa-dev] [Bug 107698] Ubuntu 18.10 kernel 4.18rc1-4.18.6 or kernel 4.19rc1

https://bugs.freedesktop.org/show_bug.cgi?id=107698 Michel Dänzer changed: What|Removed |Added CC||harry.wentl...@amd.com,

[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object

https://bugs.freedesktop.org/show_bug.cgi?id=105731 --- Comment #1 from vadym --- Patch: https://patchwork.freedesktop.org/patch/246171/ -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH] glsl/linker: Link all out vars from a shader objects on a single stage

Hi Timothy, Thanks for the review! Space was removed. Can you please push this patch since I haven't got write permissions ? Regards, Vadym вт, 28 авг. 2018 г. в 10:32, Vadym Shovkoplias : > From: "vadym.shovkoplias" > > During intra stage linking some out variables can be dropped because >

[Mesa-dev] [PATCH] glsl/linker: Link all out vars from a shader objects on a single stage

From: "vadym.shovkoplias" During intra stage linking some out variables can be dropped because it is not used in a shader with the main function. But these out vars can be referenced on later stages which can lead to further linking errors. Bugzilla:

Re: [Mesa-dev] [RFC 00/10] Let us welcome EGLDevice

Hi Emil, On Friday, 3 August 2018 14:44:16 CEST Emil Velikov wrote: > Hi all, > > This series implements the following extensions: > - EGL_EXT_device_base > - EGL_MESA_device_software > - EGL_EXT_device_drm > - EGL_platform_device > > As you know the APIs are used to enumerate, select and

Re: [Mesa-dev] [PATCH] glsl/linker: Allow unused in blocks which are not declated on previous stage

Hi Andreas, Similar patch for varyings linking was pushed 4 years ago, so I think this patch should be also stable. On Tue, Aug 28, 2018 at 12:20 AM, Andres Gomez wrote: > Vadym, should we also include this in the stable queues ? > > > On Mon, 2018-08-20 at 16:31 +0300, vadym.shovkoplias

[Mesa-dev] [Bug 107655] X segfaults on startup in r300_dri.so, making system unusable

https://bugs.freedesktop.org/show_bug.cgi?id=107655 Michal Srb changed: What|Removed |Added CC||michal...@gmail.com -- You are receiving