On Tue, Jan 22, 2019 at 10:26 PM Matt Turner wrote:
> Was this just something that you noticed by inspection?
With the patch reverted I see some validation failures in
dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.push_constant_8_to_16.scalar_uint
and friends.
mov(16) g10<4>B
On 1/22/19 9:25 PM, Nanley Chery wrote:
[...]
>
> The performance difference should be negligible if the function is
> declared static inline in the intel_mipmap_tree.h header. The compiler
> should include the body of function (which should be small) and avoid
> the overhead of a function call.
On Sun, Jul 8, 2018 at 5:27 PM, Jose Maria Casanova Crespo
wrote:
> When the destination is a BYTE type allow raw movs
> even if the stride is not exact multiple of destination
> type and exec type, execution type is Word and its size is 2.
>
> This restriction was only allowing stride==2
https://bugs.freedesktop.org/show_bug.cgi?id=109361
--- Comment #3 from Hai ---
If no next step, I will mark it as won't fix
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What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108877
--- Comment #5 from Hai ---
With these two patches, this issue can't reproduce.
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On 23/1/19 3:27 pm, Caio Marcelo de Oliveira Filho wrote:
Hi,
The different problem I've found was that uses in the phi instruction
after the then/else blocks was being replaced, causing churn in the
optimizations further on. As a hack, I've ignored phi instructions in
the use loop above.
https://bugs.freedesktop.org/show_bug.cgi?id=87738
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Hi,
> > The different problem I've found was that uses in the phi instruction
> > after the then/else blocks was being replaced, causing churn in the
> > optimizations further on. As a hack, I've ignored phi instructions in
> > the use loop above. HURTs are gone and HELPs continued.
> >
> >
The text segment is shared among multiple contexts, while each one has
its own bufctx. So when reallocating the text segment, some contexts may
end up with stale values in their bufctx's. Instead limit the exposure
to the bufctx to within a single draw.
Signed-off-by: Ilia Mirkin
---
nv50
Fixes the following piglit test on my VEGA and matches the behaviour in the
tgsi backend.
tests/spec/glsl-1.10/execution/samplers/glsl-fs-shadow2D-clamp-z.shader_test
Fixes: 625dcbbc4566 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
---
https://bugs.freedesktop.org/show_bug.cgi?id=109258
--- Comment #7 from Daniel van Vugt ---
> This revert makes Mesa ignore LIBGL_ALWAYS_SOFTWARE for the drm (and android)
> platforms.
That might be what it looks like, but as I understand it the opposite is
true...
The bug being fixed here is
On 23/1/19 11:27 am, Caio Marcelo de Oliveira Filho wrote:
Hi,
Did you look at any of the HURT? The problem I was seeing was this could end
up stopping copy propagation from working on some UBOs etc.
They were not UBO cases like yours, but looking at them I've found a
different problem.
I have no clue on aarch64, but looks all good to me.
For the series:
Reviewed-by: Roland Scheidegger
Am 23.01.19 um 00:12 schrieb Matt Turner:
> LLVM uses the single instruction "FRINTI" to implement llvm.nearbyint.
> Fixes the rounding tests of lp_test_arit.
>
> Bug:
>
On Tue, Jan 15, 2019 at 5:54 AM Iago Toral Quiroga wrote:
>
> We use ALign16 mode for this, since it is more convenient, but the PRM
> for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region
> restrictions', Section '1. Special Restrictions':
>
>"In Align16 mode, the channel
Hi,
> Did you look at any of the HURT? The problem I was seeing was this could end
> up stopping copy propagation from working on some UBOs etc.
They were not UBO cases like yours, but looking at them I've found a
different problem.
> However with this patch we end up with:
>
> load UBO at
Obviously you cannot test the Gen11 code, but it looks believable.
Reviewed-by: Matt Turner
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On Tue, Jan 15, 2019 at 5:54 AM Iago Toral Quiroga wrote:
>
> 3-src instructions don't support immediates, but since 36bc5f06dd22,
> we allow them on MAD and LRP relying on the combine constants pass to
> fix it up later. However, that pass is specialized for 32-bit float
> immediates and can't
On Thu, Jan 17, 2019 at 12:18 PM Jason Ekstrand wrote:
>
> On Tue, Jan 15, 2019 at 7:55 AM Iago Toral Quiroga wrote:
>>
>> Source0 and Destination extract the floating-point precision automatically
>> from the SrcType and DstType instruction fields respectively when they are
>> set to types :F
Reviewed-by: Matt Turner
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On Tue, Jan 15, 2019 at 5:55 AM Iago Toral Quiroga wrote:
>
> We are now using these bits, so don't assert that they are not set, just
> avoid compaction in that case.
>
> Reviewed-by: Topi Pohjolainen
> ---
> src/intel/compiler/brw_eu_compact.c | 5 -
> 1 file changed, 4 insertions(+), 1
On Tue, Jan 15, 2019 at 5:55 AM Iago Toral Quiroga wrote:
>
> This is available since gen8.
>
> v2: restore previously existing assertion.
>
> Reviewed-by: Topi Pohjolainen (v1)
> ---
> src/intel/compiler/brw_reg_type.c | 36 +++
> 1 file changed, 32 insertions(+), 4
On Tue, Jan 22, 2019 at 3:25 PM Francisco Jerez wrote:
>
> Matt Turner writes:
>
> > emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
> > flag_subreg set, so that the IR knows which flag is accessed. However
> > the flag is only used on Gen7 in Align1 mode.
> >
> > To avoid
Matt Turner writes:
> emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
> flag_subreg set, so that the IR knows which flag is accessed. However
> the flag is only used on Gen7 in Align1 mode.
>
> To avoid setting unnecessary bits in the instruction words, get the
> information we
emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
flag_subreg set, so that the IR knows which flag is accessed. However
the flag is only used on Gen7 in Align1 mode.
To avoid setting unnecessary bits in the instruction words, get the
information we need and reset the default flag
LLVM uses the single instruction "FRINTI" to implement llvm.nearbyint.
Fixes the rounding tests of lp_test_arit.
Bug: https://bugs.gentoo.org/665570
---
src/gallium/auxiliary/gallivm/lp_bld_arit.c | 4 +++-
src/gallium/drivers/llvmpipe/lp_test_arit.c | 3 ++-
2 files changed, 5 insertions(+), 2
NEON (now called ASIMD) is available on all aarch64 CPUs. It seems that
our code was missing an aarch64 path, leading to util_cpu_caps.has_neon
always being false on aarch64. I think that means that the NEON tiling
code in vc4 would not be enabled on aarch64 (vc4_load_lt_image_neon,
etc).
---
I
For the series:
Reviewed-by: Marek Olšák
Marek
On Mon, Jan 21, 2019 at 9:29 PM Timothy Arceri
wrote:
> ---
> src/amd/common/ac_nir_to_llvm.c | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c
>
Acked-by: Marek Olšák
Marek
On Tue, Jan 22, 2019 at 12:35 AM Timothy Arceri
wrote:
> This fixes the arb_gpu_shader5 interpolateAt* tests that contain
> structs.
> ---
>
> Extra piglit tests for structs:
>
> https://patchwork.freedesktop.org/patch/279466/
>
> src/amd/common/ac_nir_to_llvm.c
Matt Turner writes:
> emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
> flag_subreg set, so that the IR knows which flag is accessed. However
> the flag is only used on Gen7 in Align1 mode.
>
> To avoid setting unnecessary bits in the instruction words, get the
> information we
Acked-by: Timothy Arceri
On 23/1/19 3:16 am, Marek Olšák wrote:
From: Marek Olšák
This fixes pipe_surface "leaks".
Cc: 18.3
---
src/mesa/state_tracker/st_manager.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/state_tracker/st_manager.c
On 23/1/19 7:17 am, Caio Marcelo de Oliveira Filho wrote:
Hi,
I like this patch, did it get dropped for a specific reason or just
forgotten?
Did you look at any of the HURT? The problem I was seeing was this could
end up stopping copy propagation from working on some UBOs etc.
For example
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 22, 2019 at 7:27 PM Samuel Pitoiset
wrote:
>
> For example, if a pipeline has two stages VS and FS. And if only
> the fragment stage needs dynamic bindings, we shouldn't allocate
> an extra user SGPR for the vertex stage. Of course, if the vertex
>
On Tue, Jan 22, 2019 at 4:32 PM Samuel Pitoiset
wrote:
>
> For some R8 formats, it's useless to export two channels
> when no alpha blending is used. I assume the CB should
> automatically clamps its inputs.
>
> 29077 shaders in 15096 tests
> Totals:
> SGPRS: 1321106 -> 1320970 (-0.01 %)
> VGPRS:
On Thu, Nov 29, 2018 at 11:23 AM Koenig, Christian
wrote:
> Hi Marek,
>
> you stumbled over a pretty fundamental bug in the memory management here.
> Essentially we where leaking BOs when we ran into an OOM situation. Patch
> to fix this is on the mailing list.
>
> A second problem is that
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 22, 2019 at 10:20 PM Kristian Høgsberg wrote:
>
> On Tue, Jan 22, 2019 at 11:45 AM Rob Clark wrote:
> >
> > Normally modifiers take precendence over use flags, as they are more
> > explicit. But if the driver supports modifiers, but the xserver does
emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
flag_subreg set, so that the IR knows which flag is accessed. However
the flag is only used on Gen7 in Align1 mode.
To avoid setting unnecessary bits in the instruction words, get the
information we need and reset the default flag
On Tue, Jan 22, 2019 at 11:53 AM Francisco Jerez wrote:
>
> Matt Turner writes:
>
> > emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
> > flag_subreg set, so that the IR knows which flag is accessed. However
> > the flag is only used on Gen7 in Align1 mode, and it is used as an
On Tue, Jan 22, 2019 at 11:45 AM Rob Clark wrote:
>
> Normally modifiers take precendence over use flags, as they are more
> explicit. But if the driver supports modifiers, but the xserver does
> not, then we should fallback to the old mechanism of allocating a buffer
> using 'use' flags.
>
>
Build mesa 9821 completed
Commit 956c219c8f by Brian Paul on 1/22/2019 7:29 PM:
svga: add new gallium formats to the format conversion table\n\nFixes a static assertion which broke the build.\n\nFixes: 3ee240890 "gallium: add SINT formats to have exact
Hi,
I like this patch, did it get dropped for a specific reason or just
forgotten?
shader-db results skl:
total instructions in shared programs: 15049273 -> 15049211 (<.01%)
instructions in affected programs: 75678 -> 75616 (-0.08%)
helped: 197
HURT: 8
total cycles in shared programs:
Fixes regression caused by
42d672fa6a766363e5703f119607f7c7975918aa
st/nine: Bind src not dst in nine_context_box_upload
Before that patch, for user provided textures,
when the texture was destroyed, the safety
check for pending uploads, which according to
the code "Following condition cannot
Matt Turner writes:
> emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
> flag_subreg set, so that the IR knows which flag is accessed. However
> the flag is only used on Gen7 in Align1 mode, and it is used as an
> explicit source and destination.
>
> To avoid setting unnecessary
Reviewed-by: Marek Olšák
Sorry for breaking the build.
Marek
On Tue, Jan 22, 2019 at 2:31 PM Brian Paul wrote:
> Fixes a static assertion which broke the build.
>
> Fixes:3ee240890 "gallium: add SINT formats to have exact counterparts to
> SNORM formats"
> ---
>
Normally modifiers take precendence over use flags, as they are more
explicit. But if the driver supports modifiers, but the xserver does
not, then we should fallback to the old mechanism of allocating a buffer
using 'use' flags.
Fixes: 069fdd5f9facbd72fb6a289696c7b74e3237e70f
Signed-off-by: Rob
Looks good
Reviewed-by: Neha Bhende
Regards,
Neha
From: Brian Paul
Sent: Tuesday, January 22, 2019 11:31:13 AM
To: mesa-dev@lists.freedesktop.org
Cc: Jose Fonseca; Neha Bhende; Marek Olšák
Subject: [PATCH] svga: add new gallium formats to the format
emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
flag_subreg set, so that the IR knows which flag is accessed. However
the flag is only used on Gen7 in Align1 mode, and it is used as an
explicit source and destination.
To avoid setting unnecessary bits in the instruction words,
Fixes a static assertion which broke the build.
Fixes:3ee240890 "gallium: add SINT formats to have exact counterparts to SNORM
formats"
---
src/gallium/drivers/svga/svga_format.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/svga/svga_format.c
Reviewed-by: Matt Turner
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On Tue, Jan 22, 2019 at 01:15:25PM +0200, Eleni Maria Stea wrote:
> On 1/22/19 12:46 PM, Eleni Maria Stea wrote:
> >>> + /**
> >>> +* \brief Indicates that we fake the ETC2 compression support
> >>> +*
> >>> +* GPUs Gen < 8 don't support sampling and rendering of ETC2
> >>> formats
https://bugs.freedesktop.org/show_bug.cgi?id=107822
Alexander changed:
What|Removed |Added
Version|18.2|18.3
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What|Removed |Added
Resolution|FIXED |---
Status|RESOLVED
Build mesa 9820 failed
Commit d85917deaf by Marek Olšák on 1/19/2019 12:35 AM:
radeonsi: rename rfence -> sfence\n\nReviewed-by: Bas Nieuwenhuizen
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On Thu, Jan 17, 2019 at 1:07 PM Daniel Stone wrote:
> Hi,
>
> On Thu, 17 Jan 2019 at 16:35, Jason Ekstrand wrote:
> > On January 17, 2019 08:58:03 Erik Faye-Lund <
> erik.faye-l...@collabora.com> wrote:
> > > Whoops! I meant to say something like "we'd need to be able to
> > > distinguis
On Tue, Jan 22, 2019 at 02:17:16PM +0200, Eleni Maria Stea wrote:
> On 1/19/19 1:32 AM, Nanley Chery wrote:
> >> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> >> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> >> index e214fae140..4d1eafac91 100644
> >> ---
On Fri, Jan 18, 2019 at 8:22 PM Bas Nieuwenhuizen
wrote:
> On Sat, Jan 19, 2019 at 2:10 AM Marek Olšák wrote:
> >
> > On Fri, Jan 18, 2019 at 6:08 PM Bas Nieuwenhuizen <
> b...@basnieuwenhuizen.nl> wrote:
> >>
> >> On Fri, Jan 18, 2019 at 5:44 PM Marek Olšák wrote:
> >> >
> >> > From: Marek
Build mesa 9818 failed
Commit a75b12ce66 by Lionel Landwerlin on 1/22/2019 5:36 PM:
vulkan: make generated enum to strings helpers available from c++\n\nSigned-off-by: Lionel Landwerlin \nReviewed-by: Caio Marcelo de Oliveira Filho
Configure your
For example, if a pipeline has two stages VS and FS. And if only
the fragment stage needs dynamic bindings, we shouldn't allocate
an extra user SGPR for the vertex stage. Of course, if the vertex
stage loads constants, it needs an user SGPR.
This should reduce the number of SET_SH_REG packets
Thanks Caio, pushed to master.
On 22/01/2019 18:13, Caio Marcelo de Oliveira Filho wrote:
Reviewed-by: Caio Marcelo de Oliveira Filho
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On Tue, 2019-01-15 at 07:21 -0500, Rob Clark wrote:
> On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli wrote:
> >
> >
> > On 1/14/19 2:36 PM, Daniel Stone wrote:
> > > Hi,
> > >
> > > On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand wrote:
> > > > 5. There's no way with gitlab for Reviewed-by tags
Reviewed-by: Caio Marcelo de Oliveira Filho
On Tue, Jan 22, 2019 at 05:36:56PM +, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/vulkan/util/gen_enum_to_str.py | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/vulkan/util/gen_enum_to_str.py
>
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/139
The start of a Vulkan layer to display some basic swapchain/draws/submit
information.
Looks like this : https://i.imgur.com/4zyIiVb.png
There is probably plenty of improvements that can be made to get closer
to the gallium HUD.
Build mesa 9817 completed
Commit b1293c8745 by Alejandro Piñeiro on 11/7/2018 9:11 AM:
nir/linker: use nir_gather_xfb_info\n\nInstead of a custom ARB_gl_spirv xfb gather info pass.\n\nIn fact, this is not only about reusing code, but the current custom\ncode
Build mesa 9816 failed
Commit 1cfbed7587 by Marek Olšák on 1/19/2019 12:39 AM:
radeonsi: remove r600 from comments\n\nReviewed-by: Bas Nieuwenhuizen
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Signed-off-by: Lionel Landwerlin
---
src/vulkan/util/gen_enum_to_str.py | 8
1 file changed, 8 insertions(+)
diff --git a/src/vulkan/util/gen_enum_to_str.py
b/src/vulkan/util/gen_enum_to_str.py
index fb9ecd65c6d..06f74eb487c 100644
--- a/src/vulkan/util/gen_enum_to_str.py
+++
Similar configuration to the iMX platform, but interfaces with
the armada-drm driver.
Signed-off-by: Kyle Russell
---
configure.ac | 12 +-
meson.build | 6 -
meson_options.txt | 2 +-
ping
On Fri, Jan 18, 2019 at 11:27 AM Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/mesa/state_tracker/st_cb_queryobj.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_queryobj.c
> b/src/mesa/state_tracker/st_cb_queryobj.c
> index
https://bugs.freedesktop.org/show_bug.cgi?id=105371
--- Comment #21 from amonpaike ---
(In reply to mirh from comment #20)
> A couple of devs are working into reinventing the wheel so that you could
> basically have r600 cards work and be supported almost like they had been
> released in 2018
From: Marek Olšák
This fixes pipe_surface "leaks".
Cc: 18.3
---
src/mesa/state_tracker/st_manager.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index 7a3d9777101..7064b99743c 100644
---
On Tuesday, 2019-01-22 13:32:15 +, Emil Velikov wrote:
> On Mon, 21 Jan 2019 at 19:53, Eric Engestrom wrote:
> >
> AFAICT this triggers when egl is explicitly disabled and drm is
> explicitly listed in the with-platforms list.
> Please add the triggering configure line to the commit message.
For some R8 formats, it's useless to export two channels
when no alpha blending is used. I assume the CB should
automatically clamps its inputs.
29077 shaders in 15096 tests
Totals:
SGPRS: 1321106 -> 1320970 (-0.01 %)
VGPRS: 935936 -> 935948 (0.00 %)
Spilled SGPRs: 25186 -> 25204 (0.07 %)
Code
On Mon, 21 Jan 2019 at 19:53, Eric Engestrom wrote:
>
AFAICT this triggers when egl is explicitly disabled and drm is
explicitly listed in the with-platforms list.
Please add the triggering configure line to the commit message.
> Fixes: 2c4f6ceeb466cb15df34 "configure.ac: Fail if egl x11
On 1/19/19 1:32 AM, Nanley Chery wrote:
>> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> index e214fae140..4d1eafac91 100644
>> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> +++
Hello,
Could somebody help me with a push of the following patch?
https://patchwork.freedesktop.org/patch/254397
This fix is needed to fix these fails:
https://mesa-ci.01.org/global_logic/builds/56/group/ac3c5a0dc1f15492570367c6c8ec835c
When this fix is pushed we will be able to remove the
On 1/22/19 12:46 PM, Eleni Maria Stea wrote:
>>> + /**
>>> +* \brief Indicates that we fake the ETC2 compression support
>>> +*
>>> +* GPUs Gen < 8 don't support sampling and rendering of ETC2
>>> formats so
>>> +* we need to fake it. This variable is set to true when we
>>> fake
Reviewed-by: Karol Herbst
On Mon, Jan 21, 2019 at 4:27 AM Ilia Mirkin wrote:
>
> We may have to flush the cache if there are any textures presently bound
> that refer to the outgoing framebuffer. This is only checked at
> validation time.
>
> Fixes a number of
> > + /**
> > +* \brief Indicates that we fake the ETC2 compression support
> > +*
> > +* GPUs Gen < 8 don't support sampling and rendering of ETC2
> > formats so
> > +* we need to fake it. This variable is set to true when we
> > fake it.
> > +*/
> > + bool needs_fake_etc;
https://bugs.freedesktop.org/show_bug.cgi?id=109258
Eric Engestrom changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Hi Luigi,
Luigi Santivetti writes:
> Before this change, if bindContext() failed then dri2_make_current() would
> rebind the old EGL context and surfaces and return EGL_BAD_MATCH. However,
> it wouldn't rebind the DRI context and surfaces, thus leaving it in an
> inconsistent and unrecoverable
On Mon, 2019-01-21 at 18:48 -0600, Jason Ekstrand wrote:
> On Mon, Jan 21, 2019 at 4:55 AM Iago Toral wrote:
> > On Fri, 2019-01-18 at 11:51 -0600, Jason Ekstrand wrote:
> > > On Tue, Jan 15, 2019 at 7:55 AM Iago Toral Quiroga <
> > > ito...@igalia.com> wrote:
> > > > Broadwell hardware has a bug
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