t; + return nir_swizzle(b, value, swiz, 4, false);
Maybe skip if value already has 4 components?
Either way,
Reviewed-by: Bas Nieuwenhuizen
> +}
> +
> static void
> vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
> const uint32_t *w, unsigned count)
> @@ -
Reinserting code directly before a jump means the block gets split
and merged, removing the original block and replacing it in the
process.
Hence keeping a pointer to the continue block over a reinsert
causes issues.
This code changes nir_opt_if to simply look for the new continue
block.
CC:
nir_validate complains in case less than 4 components are
provided.
CC: 18.1
---
src/compiler/spirv/spirv_to_nir.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index
When no occlusion queries are active even if out of order is enabled.
---
src/amd/vulkan/radv_cmd_buffer.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b6729e40b4..78838d9939 100644
---
Seems like it increases performance by 2-3% for some demos and games.
---
src/amd/vulkan/radv_device.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8274b6ea09..71635ded49 100644
---
Overshot it by one every time.
CC:
---
src/amd/vulkan/radv_pipeline.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4c794d9515..27e13a2251 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++
CC:
---
src/amd/vulkan/radv_cmd_buffer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e066b160b6..b6729e40b4 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++
Used the wrong register ...
CC:
---
src/amd/vulkan/radv_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1f01d2ff4d..4c794d9515 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++
On Thu, Jul 12, 2018 at 5:26 PM, Jason Ekstrand wrote:
> On Thu, Jul 12, 2018 at 2:30 AM Bas Nieuwenhuizen
> wrote:
>>
>> On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand
>> wrote:
>> > While we're at it, add some extensions we missed along the way like the
&g
Not really a fan of this one, we can literally have thousands of
entries which seems largish when considering the stacks for heavily
threaded stuff are often much smaller.
On Thu, Jul 12, 2018 at 4:26 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
>
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand wrote:
> ---
> docs/features.txt | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 81fe8d0e751..0705ff9974b 1
DONE (anv, radv)
> + VK_KHR_draw_indirect_countnot started
done for radv.
With those two this patch is
Reviewed-by: Bas Nieuwenhuizen
>VK_KHR_external_fence_fd DONE (anv, radv)
>VK_KHR_external_fence_win32
On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand wrote:
> While we're at it, add some extensions we missed along the way like the
> VK_KHR_maintenanceN extensions.
> ---
> docs/features.txt | 39 +--
> 1 file changed, 25 insertions(+), 14 deletions(-)
>
> diff
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jul 10, 2018 at 4:13 PM, Samuel Pitoiset
wrote:
> Now that 'set' can't be NULL because the meta operations no
> longer bind a NULL descriptor, the logic can be simplified
> a little bit.
>
> Signed-off-by: Samuel Pitoiset
&
Assuming you confirmed this fixed something:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Jul 11, 2018 at 11:55 AM, Samuel Pitoiset
wrote:
> A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
> counters) must immediately precede every timestamp event to
> prevent a GPU han
Don't we need to disable predication too for the PipelineBarriers when
a layout change happens?
Also in cases the barrier or a blit/copy does different predication,
do we not need to do si_emit_set_predication_state again as the state
was overridden?
On Mon, Jul 9, 2018 at 2:57 PM, Samuel
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jul 9, 2018 at 6:02 PM, Samuel Pitoiset
wrote:
> This might fix some synchronization issues. I don't know if
> that will affect performance but it's required for correctness.
>
> v3: - wait for CP DMA in CmdPipelineBarrier()
> - clear
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jul 9, 2018 at 11:14 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This uses the common compiler passes abstraction to help radv
> avoid fixed cost compiler overheads. This uses a linked list per
> thread stored in thread local storage
On Mon, Jul 9, 2018 at 11:03 PM, Dave Airlie wrote:
> On 9 July 2018 at 05:58, Bas Nieuwenhuizen wrote:
>> On Thu, Jul 5, 2018 at 2:03 AM, Dave Airlie wrote:
>>> From: Dave Airlie
>>>
>>> This uses the common compiler passes abstraction to help radv
>
Where is the code to disable predication for copy/blit commands and
then enable it again afterwards?
On Mon, Jul 9, 2018 at 11:42 AM, Samuel Pitoiset
wrote:
> Inherited commands buffers are not supported.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 29
On Mon, Jul 9, 2018 at 10:19 AM, Samuel Pitoiset
wrote:
>
>
> On 07/08/2018 09:50 PM, Bas Nieuwenhuizen wrote:
>>
>> On Sun, Jul 8, 2018 at 5:47 PM, Samuel Pitoiset
>> wrote:
>>>
>>> Needed for VK_KHR_create_renderpass2.
>>>
>>&g
I'd like to nominate this for 18.1 stable releases.
On Mon, Jul 2, 2018 at 1:25 AM, Mauro Rossi wrote:
> pthread types are used in some files without explicitely including pthread.h.
> This leads to compile errors on Android 7.x nougat-x86
> e.g. in
On Thu, Jul 5, 2018 at 2:03 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This uses the common compiler passes abstraction to help radv
> avoid fixed cost compiler overheads. This uses a linked list per
> thread stored in thread local storage, with an entry in the list
> for each target
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Sun, Jul 8, 2018 at 5:47 PM, Samuel Pitoiset
wrote:
> VkCreateRenderPass2KHR() is quite similar to VkCreateRenderPass()
> but refactoring the code is a bit painful.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan
On Sun, Jul 8, 2018 at 5:47 PM, Samuel Pitoiset
wrote:
> Needed for VK_KHR_create_renderpass2.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
> src/amd/vulkan/radv_meta_clear.c | 4 ++--
> src/amd/vulkan/radv_meta_resolve.c| 14
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jul 3, 2018 at 12:43 PM, Samuel Pitoiset
wrote:
> That might reduce CPU overhead a little bit when using
> RADV_TRACE_FILE.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 11 +++
&g
Reviewed-by: Bas Nieuwenhuizen
On Sat, Jul 7, 2018 at 6:01 AM, Jason Ekstrand wrote:
> Commit 5fb69daa6076e56b deleted support from nir_print for printing the
> texture and sampler indices on texture instructions. This commit just
> brings it back as best as we can.
> ---
> s
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jul 5, 2018 at 6:56 PM, Samuel Pitoiset
wrote:
> For merged shaders, VS as HS for example.
>
> Signed-off-by: Samuel Pitoiset
> Cc:
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jul 5, 2018 at 5:07 PM, Samuel Pitoiset
wrote:
> v2: - do not use it in the chained path (because cdw isn't incremented)
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 23 ++-
&g
On Thu, Jul 5, 2018 at 1:51 PM, Samuel Pitoiset
wrote:
>
>
> On 07/05/2018 01:36 PM, Bas Nieuwenhuizen wrote:
>>
>> On Thu, Jul 5, 2018 at 12:54 PM, Samuel Pitoiset
>> wrote:
>>>
>>> If the given image doesn't enable CMASK, FMASK or DCC that's
>
On Thu, Jul 5, 2018 at 12:54 PM, Samuel Pitoiset
wrote:
> If the given image doesn't enable CMASK, FMASK or DCC that's
> useless to flush CB metadata.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 6 --
> src/amd/vulkan/radv_private.h| 11 +++
>
If you fix the typo in the title, this patch is
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jul 5, 2018 at 12:54 PM, Samuel Pitoiset
wrote:
> If the given image doesn't have HTILE, that's useless to flush
> DB metadata.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan
Reviewed-by: Bas Nieuwenhuizen
On Thu, 28 Jun 2018, 12:20 Samuel Pitoiset,
wrote:
> Always emitting a bottom-of-pipe event is quite dumb. Instead,
> start to optimize these functions by syncing PFP for the
> top-of-pipe and syncing ME for the post-index-fetch event.
>
>
Reviewed-by: Bas Nieuwenhuizen
On Wed, 27 Jun 2018, 14:14 Samuel Pitoiset,
wrote:
> This introduces radv_barrier() (same as the draw/dispatch codepath).
> This helper is used for merging the code from CmdWaitEvents() and
> CmdPipelineBarrier because it's quite similar.
>
&g
On Wed, Jul 4, 2018 at 11:00 PM, Jason Ekstrand wrote:
> On Wed, Jul 4, 2018 at 1:20 PM, Francisco Jerez
> wrote:
>>
>> Jason Ekstrand writes:
>>
>> > Many fragment shaders do a discard using relatively little information
>> > but still put the discard fairly far down in the shader for no good
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jul 2, 2018 at 1:25 AM, Mauro Rossi wrote:
> pthread types are used in some files without explicitely including pthread.h.
> This leads to compile errors on Android 7.x nougat-x86
> e.g. in src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
&g
m_options),
> + OStream(CodeString) {}
> + ~ac_llvm_per_thread_info() {
> + ac_llvm_compiler_dispose_internal(_info);
> + }
> +
> + struct ac_llvm_compiler_info llvm_info;
> + enum radeon_family family;
> + enum a
Reviewed-by: Bas Nieuwenhuizen
On Wed, Jun 27, 2018 at 10:39 AM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_shader.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_
On Wed, Jun 27, 2018 at 9:46 AM, Samuel Pitoiset
wrote:
>
>
> On 06/27/2018 02:12 AM, Bas Nieuwenhuizen wrote:
>>
>> Reviewed-by: Bas Nieuwenhuizen
>>
>> for patch 3-4. Not sure they should go to stable though, since they
>> are optimizations?
>
&
Reviewed-by: Bas Nieuwenhuizen
for patch 3-4. Not sure they should go to stable though, since they
are optimizations?
On Tue, Jun 26, 2018 at 11:49 PM, Fredrik Höglund wrote:
> This is to avoid repeating dependencies when more than one subpass
> has a dependency from external.
Don't we still need this when having layout transitions?
On Tue, Jun 26, 2018 at 11:49 PM, Fredrik Höglund wrote:
> The Vulkan specification says:
>
>"An execution dependency with only VK_PIPELINE_STAGE_BOTTOM_OF_-
> PIPE_BIT in the destination stage mask [...] does not delay
>
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jun 26, 2018 at 11:49 PM, Fredrik Höglund wrote:
> A subpass can have dependencies from multiple sources, and more
> than one subpass can have a dependency to external.
>
> Cc:
> Signed-off-by: Fredrik Höglund
> ---
> src/amd/vu
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jun 26, 2018 at 11:19 AM, Samuel Pitoiset
wrote:
> The Vulkan spec says:
>
>"pipelineBindPoint is a VkPipelineBindPoint indicating whether
> the descriptors will be used by graphics pipelines or compute
> pipelines. The
I assume the extra START when doing a stop and then a start
immediately is not a problem?
Reviewed-by: Bas Nieuwenhuizen
On Fri, Jun 22, 2018 at 7:16 PM, Samuel Pitoiset
wrote:
> Ported from RadeonSI.
> This appears to fix some random fails with:
> dEQP-VK.query_pool.statist
Did not see that we already had tests for it.
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jun 25, 2018 at 3:56 PM, Samuel Pitoiset
wrote:
> The driver already supports exporting the stencil value.
>
> The following CTS test now pass:
> dEQP-VK.pipeline.shader_stencil_export.op_replac
CC to stable?
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jun 25, 2018 at 4:22 PM, Samuel Pitoiset
wrote:
> From the Vulkan spec:
> "If this is a primary command buffer, then this value is ignored."
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cm
Reviewed-by: Bas Nieuwenhuizen
Still not sure why that would cause VM faults though.
On Mon, Jun 25, 2018 at 1:34 PM, Samuel Pitoiset
wrote:
> If the driver ends up by performing a slow depthstencil clear,
> the HTILE metadata won't be initialized correctly.
>
> This fixes rand
Not sure about the other extension, but the latest version of the
intel driver should support VK_EXT_shader_viewport_index_layer
already.
On Sun, Jun 24, 2018 at 1:13 AM, Александр Бесчасный wrote:
> Hello, can I ask if it is planned to implement VK extensions for i965:
> -
Reviewed-by: Bas Nieuwenhuizen
Thanks!
On Thu, Jun 21, 2018 at 12:52 AM, Keith Packard wrote:
> This extension provides fences and frame count information to direct
> display contexts. It uses new kernel ioctls to provide 64-bits of
> vblank sequence and nanosecond resolutio
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Thu, Jun 21, 2018 at 2:39 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_device.c | 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/vu
I'm wondering whether we need to do this more often in pipeline barriers?
Also I'd really appreciate if you could add a check to see if there is
any CP DMA activity in the first place.
On Thu, Jun 21, 2018 at 11:04 AM, Samuel Pitoiset
wrote:
> Ported from RadeonSI.
> This might fix some
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Thu, Jun 21, 2018 at 3:01 AM, Marek Olšák wrote:
> These were all discovered on Stoney except for the last patch, which is a
> precaution.
>
> Please review.
>
> Thanks,
> Marek
> __
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Wed, Jun 20, 2018 at 4:10 PM, Samuel Pitoiset
wrote:
> Ported from RadeonSI.
> Not sure why this is needed but AMDVLK does something similar.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/si_cmd_buffer.c | 12
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jun 19, 2018 at 2:25 PM, Samuel Pitoiset
wrote:
> We know the number of samples at compile time.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_nir_to_llvm.c | 40 +++
&g
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jun 19, 2018 at 4:57 PM, Samuel Pitoiset
wrote:
> Similar to the clear color values.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 35 ++--
> src/amd/vulkan
A case of making things worse while trying to fix something minor ...
Fixes: ef79457004e "radv: Merge the flush bits of CMASK & DCC clear."
---
src/amd/vulkan/radv_meta_clear.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jun 19, 2018 at 3:24 PM, Samuel Pitoiset
wrote:
> AMDVLK also always uses CACHE_FLUSH_AND_INV_TS_EVENT. The other
> workaround is to flush DB metadata after emitting the framebuffer,
> but that seems slower.
>
> Signed-off-by: Samuel Pitoise
Draws without pipeline are definitely not allowed.
Fixes Coverity issue 1434216.
---
src/amd/vulkan/radv_cmd_buffer.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ccaab63b84b..992d67606d0 100644
---
Probably won't be much different in practice, but still wrong.
Fixes Coverity issue 1435002.
Not CC'ing to stable since this is only hit if you enable MSAA
DCC via RADV_DEBUG.
---
src/amd/vulkan/radv_meta_clear.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Can't say I've reviewed them entirely, but
Acked-by: Bas Nieuwenhuizen
for both.
On Tue, Jun 19, 2018 at 3:57 AM, Marek Olšák wrote:
> Too big for mesa-dev:
> https://cgit.freedesktop.org/~mareko/mesa/commit/?id=39ba6addbf33208203bec034258aa5da8d2e78e6
>
> Please review,
>
&g
On Mon, Jun 18, 2018 at 10:39 PM, Marek Olšák wrote:
> On Mon, Jun 18, 2018 at 12:12 PM, Bas Nieuwenhuizen
> wrote:
>>
>> On Mon, Jun 18, 2018 at 6:08 PM, Marek Olšák wrote:
>> > Do you need this if you set compressZ = true for stencil?
>>
>> Technically n
gt; Marek
>
> On Mon, Jun 18, 2018 at 11:00 AM, Bas Nieuwenhuizen
> wrote:
>>
>> Tile index 3 is "16 bpp depth PRT (non-MSAA), don't support
>> uncompressed depth" while tile index 0 is "non-AA compressed depth
>> or any stencil" per the comme
Tile index 3 is "16 bpp depth PRT (non-MSAA), don't support
uncompressed depth" while tile index 0 is "non-AA compressed depth
or any stencil" per the comments at the top of the file.
On my Cape Verde this caused assertions due to the bank height of
tile index 3 being too low. (2 while needs to
Tile index 3 is "16 bpp depth PRT (non-MSAA), don't support
uncompressed depth" while tile index 0 is "non-AA compressed depth
or any stencil" per the comments at the top of the file.
On my Cape Verde this caused assertions due to the bank height of
tile index 3 being too low. (2 while needs to
We HTILE compress stencil-only surfaces too.
CC: 18.1
---
src/amd/common/ac_surface.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 6600ff6b7ef..618b755afc7 100644
--- a/src/amd/common/ac_surface.c
+++
Drops the number of time we set the scissor by 4x for F1 2017,
which results in a consistent performance improvement of about 4%.
---
src/amd/vulkan/radv_cmd_buffer.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c
Reviewed-by: Bas Nieuwenhuizen
On Fri, Jun 15, 2018 at 4:50 PM, Samuel Pitoiset
wrote:
> This fixes a rendering regression with RoTR.
>
> This reverts commit 4bdad9faddc82a4560603936ce5ade5707ecb254.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/r
r we
were already enabling it, but not putting the shader part in there for
non-multisample)
Reviewed-by: Bas Nieuwenhuizen
> ---
> src/amd/vulkan/radv_pipeline.c | 2 --
> src/amd/vulkan/radv_private.h | 1 -
> src/amd/vulkan/radv_shader.h | 1 -
> 3 files changed, 4 deletions(-)
Somehow valgrind misses that the value is initialized by the ioctl.
---
src/amd/common/ac_gpu_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index e908cc6fa96..e885c0538e9 100644
---
riday (June 13th), around or shortly after 10
> AM PDT.
June 15th?
>
> If you have any questions or suggestions - be that about the current patch
> queue or otherwise, please go ahead.
>
>
> Mesa stable queue
> -
>
> Nominated (6)
> ==
On Thu, Jun 14, 2018 at 3:23 PM, Samuel Pitoiset
wrote:
> The primitive ID is NULL if the vertex shader is LS. This
> generates an invalid select instruction which crashes
> because one operand is NULL.
>
> This fixes crashes in The Long Journey Home, Quantum Break
> and Just Cause 3 with DXVK.
>
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jun 14, 2018 at 2:28 PM, Samuel Pitoiset
wrote:
> This allows to run the LLVM verifier pass.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_debug.h | 1 +
> src/amd/vulkan/radv_device.c | 1 +
We need to init the cb_shader_format correctly with the changed
col_format, so this moves the col_format adjustment to before the
adjustment to before the cb_shader_mask gets generated.
Fixes: 06d3c650980 "radv: fix a GPU hang when MRTs are sparse"
Bugzilla:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Jun 13, 2018 at 8:19 PM, Samuel Pitoiset
wrote:
> This causes rendering issues in Shadow Warrior 2 with DXVK.
>
> Cc: mesa-sta...@lists.freedesktop.org
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912
> Signed-off-by:
Reviewed-by: Bas Nieuwenhuizen
for both. Thanks!
On Wed, Jun 13, 2018 at 3:15 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> The change from MIN2 to MAX2 is intentional.
> ---
> src/amd/common/ac_gpu_info.c | 82
> 1 file changed, 54
Reviewed-by: Bas Nieuwenhuizen
On Wed, Jun 13, 2018 at 2:27 PM, Samuel Pitoiset
wrote:
> On GFX8+, there is a bug that affects TC-compatible depth surfaces
> when the ZRange is not reset after LateZ kills pixels.
>
> The workaround is to always set DB_Z_INFO.ZRANGE_PRECISION to matc
Thanks for figuring out the remaning issues,
Reviewed-by: Bas Nieuwenhuizen
On Wed, Jun 13, 2018 at 12:04 PM, Samuel Pitoiset
wrote:
> On GFX8+, there is a bug that affects TC-compatible depth surfaces
> when the ZRange is not reset after LateZ kills pixels.
>
> The workaround is t
Reviewed-by: Bas Nieuwenhuizen
On Fri, Jun 8, 2018 at 5:59 PM, Samuel Pitoiset
wrote:
> ZRANGE_PRECISION(1) seems to be the default optimal value, but
> it was only set for VI and older chips.
>
> This fixes a rendering issue with Banished through DXVK, and
> migh
It doesn't fix a truncation though, as even though type is 8 chars we
never write the full size (I think our max is 5 chars), but GCC is
apparently not smart enough to see that.
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jun 7, 2018 at 2:30 AM, Timothy Arceri wrote:
> Fixes the gcc warn
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jun 7, 2018 at 1:49 AM, Timothy Arceri wrote:
> swizzle is unsigned so "desc->swizzle[c] < 0" is never true.
> ---
> src/amd/vulkan/radv_formats.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/s
The LLVM 6 code reduced it to a non-array call. We need to do that
with the new code too.
This fixes dEQP-VK.glsl.texture_functions.query.texturequerylod.*array* for
radv.
Fixes: a9a79934412 "amd/common: use the dimension-aware image intrinsics on
LLVM 7+"
---
src/amd/common/ac_llvm_build.c |
---
Forgot this one ...
src/amd/vulkan/radv_pipeline.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 34249bf843d..375f7c357d3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2039,8
except for the odd one out.
This should support many more formats.
---
src/amd/vulkan/radv_formats.c | 253 ++
1 file changed, 73 insertions(+), 180 deletions(-)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index
Acked-by: Bas Nieuwenhuizen
On Mon, Jun 4, 2018 at 1:12 PM, Eric Engestrom wrote:
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106784
> Fixes: 17201a2eb0b1b85387136 "radv: port to using updated anv
> entrypoint/extension generator."
&g
---
src/amd/vulkan/radv_pipeline.c | 4 ++--
src/amd/vulkan/radv_shader.c | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 59bbab714df..f4d076db795 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++
---
src/amd/vulkan/radv_pipeline.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 34249bf843d..375f7c357d3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2039,8 +2039,6 @@ void
The ordering of passes is such that this already generates deref_var
based stores before the lower_io_to_scalar pass is ready for it.
---
src/amd/vulkan/radv_shader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index
---
When removing the deref chain support you'll probably get a rebase conflict.
src_shift + 2 has to become 3 there.
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index
---
src/amd/vulkan/radv_pipeline.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 43719449784..34249bf843d 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2025,8
orks out much cleaner than earlier attempts based on working
> around deref chains :-)
>
> not a traditional patch-by-patch review, so not really sure r-b is
> appropriate, but I'm pretty happy with the result (and the amount of
> churn involved does make tranditional patch-by-patch
---
src/compiler/nir/nir_opt_undef.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c
index 1439ca9c165..e42a9af2bdf 100644
--- a/src/compiler/nir/nir_opt_undef.c
+++ b/src/compiler/nir/nir_opt_undef.c
Wrong place and we don't need it anymore anyway.
---
src/gallium/drivers/radeonsi/si_compute.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index a27e6284adb..e20bae0afc4 100644
---
These are some fixes for v4 of Jasons deref instruction series.
Furthermore patches 107-119:
radv: Remove image_var stores.
radv: Use deref instructions for tex derefs in meta shaders.
radeonsi: Add deref support to the nir scan pass.
ac/nir: Add deref interp support.
ac/nir: Add shared atomic
---
src/amd/vulkan/radv_shader.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index ff133ded722..929348d5e50 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -286,8 +286,6 @@
Otherwise on pre-GFX9, if the constant layout allows both TESS_EVAL and
GEOMETRY shaders, but the PIPELINE has only GEOMETRY, it would return the
GEOMETRY shader for the TESS_EVAL shader.
This would cause the flush_constants code to emit the GEOMETRY constants
to the TESS_EVAL registers and then
Fri, Jun 1, 2018 at 3:48 AM, Bas Nieuwenhuizen
> wrote:
>>
>> The casts are not lowered away in some of the CTS tests for radv:
>>
>> shader: MESA_SHADER_COMPUTE
>> local-size: 1, 1, 1
>> shared-size: 1
>> inputs: 0
>> outputs: 0
>> uniforms: 0
On Fri, Jun 1, 2018 at 7:01 AM, Jason Ekstrand wrote:
> This commit adds a pass for lowering deref instructions to deref chains
> as well as some smaller helpers to ease the transition.
>
> Reviewed-by: Caio Marcelo de Oliveira Filho
> ---
> src/compiler/Makefile.sources | 1 +
>
to need advanced
driver support (generic address space or storing Samplers in
variables). Though I'd be happy to hear if something has a better
idea.
On Fri, Jun 1, 2018 at 12:48 PM, Bas Nieuwenhuizen
wrote:
> The casts are not lowered away in some of the CTS tests for radv:
>
> shader:
On Fri, Jun 1, 2018 at 7:02 AM, Jason Ekstrand wrote:
> Reviewed-by: Caio Marcelo de Oliveira Filho
> ---
> src/compiler/nir/nir_opt_undef.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/nir_opt_undef.c
> b/src/compiler/nir/nir_opt_undef.c
> index
On Fri, Jun 1, 2018 at 7:07 AM, Jason Ekstrand wrote:
> From: Bas Nieuwenhuizen
>
> ---
> src/amd/common/ac_nir_to_llvm.c | 404
> +---
> 1 file changed, 50 insertions(+), 354 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to
601 - 700 of 2350 matches
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