Re: [Mesa-dev] [PATCH 10/12] intel/blorp: Handle clearing compressed surfaces

On Fri, Sep 15, 2017 at 9:01 AM, Jason Ekstrand wrote: > --- > src/intel/blorp/blorp_clear.c | 24 +--- > 1 file changed, 17 insertions(+), 7 deletions(-) > > diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c > index

Re: [Mesa-dev] [PATCH 01/11] glsl/lower_instruction: handle denorms and overflow in ldexp correctly

ion of ldexp in the GLSL ES spec does not contain > +* this sentence, so we do need to handle overflow correctly. Without contradictory evidence, I would expect that was an oversight and that it's also undefined in GLSL ES. Is this required to fix the

Re: [Mesa-dev] [PATCH 00/11] glsl, tgsi, radeonsi: ldexp and frexp bug fixes and features

On Thu, Sep 28, 2017 at 3:42 PM, Matt Turner <matts...@gmail.com> wrote: > On Sat, Sep 16, 2017 at 4:23 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: >> Hi all, >> >> This series was motivated by radeonsi failing some ldexp tests due to >> not handling denor

Re: [Mesa-dev] [PATCH 00/11] glsl, tgsi, radeonsi: ldexp and frexp bug fixes and features

On Sat, Sep 16, 2017 at 4:23 AM, Nicolai Hähnle wrote: > Hi all, > > This series was motivated by radeonsi failing some ldexp tests due to > not handling denorms correctly and not handling overflows (which GLSL > doesn't require, but GLSL ES does). > > The first patch fixes

Re: [Mesa-dev] XDC 2017 feedback

On Wed, Sep 27, 2017 at 10:07 PM, Rob Clark wrote: > If you had known of the khr dates, and brought it up in Feb (or really > somewhat earlier, given that XDC is roughly same time each year +/- > few weeks), that *might* have been early enough to move things. That's unfair.

Re: [Mesa-dev] [PATCH 00/13] i965: Align1 ternary instruction support for CNL

On Fri, Aug 25, 2017 at 6:25 PM, Matt Turner <matts...@gmail.com> wrote: > Cannonlake (Gen10) adds align1 access mode to ternary instructions. In align1 > mode, instructions can use more (and mixed) datatypes and a single 16-bit > immediate value. This series adds the infrast

Re: [Mesa-dev] initial meson port

On Thu, Sep 21, 2017 at 5:06 AM, Jakob Bornecrantz wrote: > On Thu, Sep 21, 2017 at 2:20 AM, Eric Anholt wrote: >> Dylan Baker writes: >>> Results >>> autotools : sh -c 535.34s user 30.33s system 310% cpu 3:02.05 total >>> meson

Re: [Mesa-dev] [PATCH 2/2] util/u_atomic: Add implementation of __sync_val_compare_and_swap_8

On Tue, Sep 19, 2017 at 7:47 AM, Juan A. Suarez Romero <jasua...@igalia.com> wrote: > On Fri, 2017-09-15 at 14:58 +0100, Emil Velikov wrote: >> On 14 September 2017 at 20:07, Matt Turner <matts...@gmail.com> wrote: >> > Needed for 32-bit PowerPC. >> >&

Re: [Mesa-dev] [PATCH 1/2] configure: check if -latomic is needed for __atomic_*

Oh, also, these should get a Cc: mesa-stable tag. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] configure: check if -latomic is needed for __atomic_*

$(MESA_UTIL_FILES) \ > $(MESA_UTIL_GENERATED_FILES) > > libmesautil_la_LIBADD = \ > $(CLOCK_LIB) \ > - $(ZLIB_LIBS) > + $(ZLIB_LIBS) \ > + $(LIBATOMIC_LIBS) I can't remember how this works -- will $(LIBATOMIC_LIBS) be added transitiv

Re: [Mesa-dev] [PATCH] i965: Add an INTEL_DEBUG=reemit option.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: fix build warning on clang

On Thu, Sep 14, 2017 at 12:26 AM, Tapani Pälli wrote: > fixes following warning: >warning: format specifies type 'long' but the argument has type 'uint64_t' > (aka 'unsigned long long') > > cast is needed to avoid this turning in to another warning on 32bit build: >

Re: [Mesa-dev] [PATCH 2/2] util/u_atomic: Add implementation of __sync_val_compare_and_swap_8

On Fri, Sep 15, 2017 at 2:04 AM, Grazvydas Ignotas wrote: > It was because on some platforms ./configure test looking for > __atomic_* passes because it's a compile (not link) test, even when > the compiler inserts library calls instead of actual implementation. > It looks like

Re: [Mesa-dev] [PATCH 1/3] glsl: don't drop intructions from unreachable terminators continue branch

On Wed, Sep 13, 2017 at 9:47 PM, Timothy Arceri wrote: > These instruction will be executed on every iteration of the loop > we cannot drop them. > --- > src/compiler/glsl/loop_analysis.h | 7 +++ > src/compiler/glsl/loop_controls.cpp | 15 +++ >

Re: [Mesa-dev] [PATCH 2/2] util/u_atomic: Add implementation of __sync_val_compare_and_swap_8

Grazvydas, I noticed that there are some __atomic functions in this file, but I'm not sure what they do or why they're necessary. Remind me? Thanks, Matt ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

[Mesa-dev] [PATCH 2/2] util/u_atomic: Add implementation of __sync_val_compare_and_swap_8

Needed for 32-bit PowerPC. --- src/util/u_atomic.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/util/u_atomic.c b/src/util/u_atomic.c index 44b75fb0c0..b32527fe34 100644 --- a/src/util/u_atomic.c +++ b/src/util/u_atomic.c @@ -61,6 +61,20 @@

[Mesa-dev] [PATCH 1/2] util: Link libmesautil into u_atomic_test

Platforms without particular atomic operations require the implementations in u_atomic.c --- src/util/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/util/Makefile.am b/src/util/Makefile.am index 4512dc99d5..9885bbe968 100644 --- a/src/util/Makefile.am +++

Re: [Mesa-dev] [PATCH] mesa: Deal with size differences between GLuint and GLhandleARB in GetAttachedObjectsARB

On 08/17, Jeremy Huddleston Sequoia wrote: Signed-off-by: Jeremy Huddleston Sequoia <jerem...@apple.com> CC: Nicolai Hähnle <nhaeh...@gmail.com> CC: Matt Turner <matts...@gmail.com> CC: Ian Romanick <i...@freedesktop.org> CC: Brian Paul <bri...@vmware.com> Th

Re: [Mesa-dev] [PATCH 26/27] i965: Initialize disk shader cache when INTEL_SHADER_CACHE env var is set

On 08/19, Jordan Justen wrote: We use the build-id of i965_dri.so for the timestamp, and the name from i965_pci_ids.h for the device name. Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.c| 2 ++ src/mesa/drivers/dri/i965/brw_disk_cache.c |

Re: [Mesa-dev] [PATCH 12/27] i965: add support for cached shaders with xfb qualifiers

On 08/19, Jordan Justen wrote: From: Timothy Arceri For now this disables the shader cache when transform feedback is enabled via the GL API as we don't currently allow for it when generating the sha for the shader. --- If I understand correctly, at this point

Re: [Mesa-dev] [PATCH 07/27] i965: Add shader cache support for vertex and fragment stages

On 08/19, Jordan Justen wrote: From: Timothy Arceri This enables the cache on vertex and fragment shaders only. [jordan.l.jus...@intel.com: reword subject] [jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen

Re: [Mesa-dev] [PATCH 06/27] i965: add initial implementation of on disk shader cache

On 08/19, Jordan Justen wrote: From: Timothy Arceri This uses the recently-added disk_cache.c to write out the final linked binary for vertex and fragment shader programs. This is based off the initial implementation done by Carl Worth.

Re: [Mesa-dev] [PATCH] i965: Record NOS dependencies for shader programs and only check those.

state or resources (such as binding new textures or changing uniforms). Improves performance in GFXBench4's gl_driver2_off on Apollolake at 1280x720 by 3.06834% +/- 0.722141% (n=25). That all makes sense and seems like an obviously good idea. Reviewed-by: Matt Turner <matts...@gmail.

Re: [Mesa-dev] [PATCH v2 01/15] i965: Delete a batch size assertion that isn't very useful.

The series looks good to me. I had a question on 03/15, mostly for clarification in the commit message. The series is Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list me

Re: [Mesa-dev] [PATCH v2 03/15] i965: Use a WC map and memcpy for the batch instead of pwrite.

On 09/13, Kenneth Graunke wrote: We'd like to eliminate the malloc'd shadow copy eventually, but there are still unresolved performance problems. In the meantime, let's at least get rid of pwrite. I don't know much about this. What is wrong with pwrite, and why is WC better? Does this change

Re: [Mesa-dev] [PATCH 2/3] intel/blorp/hiz: Always set sample number

On 09/11, Topi Pohjolainen wrote: Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Patches 2-3 (because I don't know a lot about this code) are Acked-by: Matt Turner <matts...@gmail.com> Chromium has been disabling HiZ on Braswell for stability reasons (trying to f

Re: [Mesa-dev] [PATCH 1/3] i965/gen8: Remove unused gen8_emit_3dstate_multisample()

On 09/11, Topi Pohjolainen wrote: Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedeskt

Re: [Mesa-dev] [PATCH] automake: enable libunwind in `make distcheck'

emil.veli...@collabora.com> --- Yes, please! Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH shader-db 3/3] run: add extension_in_string() helper

On Mon, Aug 21, 2017 at 3:27 AM, Emil Velikov wrote: > From: Emil Velikov > > memmem() does not attribute what the character after the searched string > is. Thus it will flag even when haystack is "foobar" while we're looking > for "foo". > >

Re: [Mesa-dev] [PATCH] intel/eu/validate: Look up types on demand in execution_type()

On 09/13, Emil Velikov wrote: As Andres pointed out this commit depends on 4fab67a4415 et al, which seems to be missing in 17.1 and 17.2. I've ported this to 17.2 by moving the brw_inst_src[01]_reg_type() calls as in the original patch. The brw_inst_src[01]_reg_file() ones are left as-is.

Re: [Mesa-dev] [PATCH] util/build_id: Include

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] intel/eu/validate: Look up types on demand in execution_type()

On Wed, Sep 13, 2017 at 6:03 AM, Andres Gomez wrote: > Jason, this patch landed tagged for mesa-stable but without mentioning > any specific branch. > > For 17.1 it depends on earlier commit 4fab67a4415 which did not land in > the branch so I'm keeping it out. > > I hope this

Re: [Mesa-dev] [PATCH] util: Query build-id by symbol address, not library name

could end up in a statically linked binary (much less more than one of them). Otherwise, it looks like a nice change. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965 : optimized bucket index calculation

On Tue, Sep 12, 2017 at 10:19 AM, Ian Romanick wrote: > On 09/12/2017 02:40 AM, Marathe, Yogesh wrote: >> Hi Jason, >> >> >> >> On the asserts you’ve mentioned below, I assume we need to add them >> after ‘bufmgr->num_buckets++’ in add_bucket() as num_buckets could be 0 >>

Re: [Mesa-dev] [PATCH mesa] glsl: compile unused function out

by: Eric Engestrom <eric.engest...@imgtec.com> As long as make check continues passing (I broke that by marking some function static): Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] intel: Remove unused Kabylake pci id

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] glsl: fix loop analysis of loop terminators

On Wed, Sep 6, 2017 at 3:48 PM, Timothy Arceri <tarc...@itsqueeze.com> wrote: > > On 07/09/17 06:59, Matt Turner wrote: >> >> I feel like the commit message is missing some important information. >> What does this fix? Do we have a piglit test? I don't see one from

Re: [Mesa-dev] [PATCH] glsl: fix loop analysis of loop terminators

I feel like the commit message is missing some important information. What does this fix? Do we have a piglit test? I don't see one from you. I see that someone has replied with a Tested-by, so presumably they know what it's intended to fix. ___ mesa-dev

Re: [Mesa-dev] [PATCH 1/5] intel: Remove unused Kabylake pci ids

The series is Reviewed-by: Matt Turner <matts...@gmail.com> I think It should be tagged for the stable branch as well. Does anyone else have an opinion? I tested a KBL-R system (the 0x5917 PCI ID) with it set as a GT1.5 and a GT2 and in both cases is passed piglit. Are you planning t

Re: [Mesa-dev] [PATCH] m4: Use older autoconf 2.63 compatible ax_check_compile_flag.

Reviewed-by: Matt Turner <matts...@gmail.com> I checked the revision history of this, and it changed between #serial 3 and 4 with a commit message saying it was "Modernizing" it [1]. Not compelling enough. [1] http://git.savannah.gnu.org/gitweb/?p=autoconf-archiv

Re: [Mesa-dev] [PATCH] intel/eu/validate: Look up types on demand in execution_type()

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/5] intel/eu: Use EXECUTE_1 for JMPI

73137997e23ff6c1145d036315d1a9ad96651281 | insn->header.execution_size = 1; But the execution size encodings are BRW_EXECUTE_1 = 0, BRW_EXECUTE_2 = 1, BRW_EXECUTE_4 = 2, etc. With an updated commit message that contains this information: Reviewed-by: Matt Turner <matts...@gmail.c

Re: [Mesa-dev] [Mesa-stable] [PATCH v2 1/2] gallivm: correct channel shift logic on big endian

On Tue, Aug 29, 2017 at 1:13 PM, Roland Scheidegger wrote: > That said, I already reviewed this: > https://lists.freedesktop.org/archives/mesa-dev/2017-August/167515.html Since I don't think Ben has commit access, it seems that you should be the one to commit it as well.

Re: [Mesa-dev] [PATCH 11/19] anv: Use GNU C empty brace initializer

On Tue, Aug 29, 2017 at 3:11 AM, Eric Engestrom <eric.engest...@imgtec.com> wrote: > On Monday, 2017-08-28 14:57:13 -0700, Matt Turner wrote: >> Avoids Clang's warning about the current code: >> >>warning: suggest braces around initialization of subobject > >

Re: [Mesa-dev] [PATCH 11/19] anv: Use GNU C empty brace initializer

On Tue, Aug 29, 2017 at 3:35 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 29 August 2017 at 11:11, Eric Engestrom <eric.engest...@imgtec.com> wrote: >> On Monday, 2017-08-28 14:57:13 -0700, Matt Turner wrote: >>> Avoids Clang's warning about the current cod

Re: [Mesa-dev] [PATCH 01/19] configure: Add and use AX_CHECK_COMPILE_FLAG

On Tue, Aug 29, 2017 at 6:15 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 28 August 2017 at 22:57, Matt Turner <matts...@gmail.com> wrote: > >> -# Flags to help ensure that certain portions of the code -- and only >> those >> -

[Mesa-dev] [PATCH 08/19] i965: Explicitly cast between different enums

Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~ ---

[Mesa-dev] [PATCH 14/19] anv: Mark functions used conditionally as UNUSED

The functions we're marking as UNUSED in genX_pipeline.c are used only when compiling for particular generations. --- src/intel/vulkan/anv_allocator.c | 2 +- src/intel/vulkan/gen8_cmd_buffer.c | 4 ++-- src/intel/vulkan/genX_cmd_buffer.c | 2 +- src/intel/vulkan/genX_pipeline.c | 4 ++-- 4

[Mesa-dev] [PATCH 18/19] blorp: Explicitly cast between different enums

Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~ ---

[Mesa-dev] [PATCH 19/19] glsl: define YY_NO_INPUT to prevent unused symbol warnings

Otherwise clang warns: glsl/glsl_lexer.cpp:3507:16: warning: function 'yyinput' is not needed and will not be emitted [-Wunneeded-internal-declaration] static int yyinput (yyscan_t yyscanner) ^ --- src/compiler/glsl/glsl_lexer.ll | 1 + 1 file changed, 1 insertion(+) diff

[Mesa-dev] [PATCH 15/19] intel/isl: Remove 'inline' keywords

Unless you have data, the compiler knows better than you whether a function should be inlined. Unlike all other cases in this series, the removal of the inline keyword from isl_format_has_channel_type actually changes the resulting binary with gcc-6.3.0: textdata bss dec hex

[Mesa-dev] [PATCH 13/19] anv: Explicitly cast between different enums

Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~ ---

[Mesa-dev] [PATCH 11/19] anv: Use GNU C empty brace initializer

Avoids Clang's warning about the current code: warning: suggest braces around initialization of subobject --- src/intel/vulkan/anv_formats.c | 2 +- src/intel/vulkan/anv_pipeline.c | 20 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git

[Mesa-dev] [PATCH 12/19] anv: Remove 'inline' keywords

Unless you have data, the compiler knows better than you whether a function should be inlined. No difference in the resulting binary with gcc-6.3.0 or clang-4.0. --- src/intel/vulkan/anv_batch_chain.c | 4 ++-- src/intel/vulkan/anv_blorp.c | 2 +- src/intel/vulkan/gen7_cmd_buffer.c | 2

[Mesa-dev] [PATCH 07/19] i965: Drop unnecessary conditional

Clang doesn't realize that 0 and 1 are the only possibilities, a thinks lots of variables might be uninitialized. --- src/intel/compiler/brw_eu_validate.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_eu_validate.c

[Mesa-dev] [PATCH 16/19] intel/isl: Explicitly cast between different enums

Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~ ---

[Mesa-dev] [PATCH 10/19] i965: Add $(WNO_OVERRIDE_INIT) to AM_CFLAGS

brw_surface_formats.c and genX_blorp_exec.c do this a lot, causing lots of warnings from clang. --- src/mesa/drivers/dri/i965/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/mesa/drivers/dri/i965/Makefile.am index f884a530eb..eccca643c3

[Mesa-dev] [PATCH 17/19] intel/isl: Mark functions used conditionally as UNUSED

The functions we're marking as UNUSED in isl_surface_state.c are used only when compiling for particular generations. --- src/intel/isl/isl_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c

[Mesa-dev] [PATCH 02/19] configure: Test for -Wno-initializer-overrides

Clang has "-Wno-initializer-overrides", while gcc has "-Wno-override-init". Quiets a lot of warnings with clang. --- configure.ac | 4 src/intel/Makefile.am | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 84b0805401..218c03dad5

[Mesa-dev] [PATCH 06/19] i965: Remove some 'inline' keywords

brw_texture_view_sane() is only used by an assert()... No difference in the resulting binary with gcc-6.3.0 or clang-4.0. --- src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 09/19] i965: Mark functions used conditionally as UNUSED

The functions we're marking as UNUSED in genX_state_upload.c are used only when compiling for particular generations. --- src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 03/19] compiler: Add $(WNO_OVERRIDE_INIT) to AM_CFLAGS

nir_intrinsics.h does this a lot, causing lots of warnings from clang. --- src/compiler/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/Makefile.am b/src/compiler/Makefile.am index 001ff81aeb..45b9cc5854 100644 --- a/src/compiler/Makefile.am +++

[Mesa-dev] [PATCH 05/19] nir: Remove series of unnecessary conversions

Clang warns: warning: absolute value function 'fabsf' given an argument of type 'const float64_t' (aka 'const double') but has parameter of type 'float' which may cause truncation of value [-Wabsolute-value] float64_t dst = bit_size == 64 ? fabs(src0) : fabsf(src0); The type of the

[Mesa-dev] [PATCH 01/19] configure: Add and use AX_CHECK_COMPILE_FLAG

This makes it a lot clearer what's happening (at least I think so), and will make future additions much simpler. --- configure.ac| 94 - m4/ax_check_compile_flag.m4 | 74 +++ 2 files changed, 99

[Mesa-dev] [PATCH 04/19] nir/spirv: Use unreachable("...") rather than assert(!"...")

Quiets a number of uninitialized variable warnings in clang. Reviewed-by: Jordan Justen --- src/compiler/spirv/spirv_to_nir.c | 18 +- src/compiler/spirv/vtn_variables.c | 8 2 files changed, 13 insertions(+), 13 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 7/7] i965/fs: Fix readInvocationARB and readFirstInvocationARB

On Mon, Aug 28, 2017 at 7:51 AM, Jason Ekstrand wrote: > The readInvocationARB built-in maps fairly nicely to our BROADCAST > opcode. However, the current implementation isn't quite right. This > commit fixes three different issues: > > 1) It was blindly taking component

Re: [Mesa-dev] [PATCH v2 6/7] i965/fs/nir: Don't stomp 64-bit values to D in get_nir_src

On Mon, Aug 28, 2017 at 11:13 AM, Jason Ekstrand wrote: > --- > src/intel/compiler/brw_fs_nir.cpp | 33 + > 1 file changed, 21 insertions(+), 12 deletions(-) > > diff --git a/src/intel/compiler/brw_fs_nir.cpp >

Re: [Mesa-dev] [PATCH] st/mesa: fix handling of vertex array double inputs

On Sat, Aug 26, 2017 at 9:42 PM, Ilia Mirkin wrote: > The is_double_vertex_input needs to be set for arrays of doubles as > well. > > Fixes KHR-GL45.enhanced_layouts.varying_array_locations > > Signed-off-by: Ilia Mirkin > Cc:

Re: [Mesa-dev] [PATCH] intel/compiler: Cast reg types explicitly

Kind of a stupid false-positive as far as Coverity goes, but Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] nir: Fix some whatespace

Both are Reviewed-by: Matt Turner <matts...@gmail.com> (Typo in the title of this patch) Should 2/2 go to stable? I'm not really sure how that code gets used. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedeskt

[Mesa-dev] [PATCH 13/13] i965/fs: Don't apply POW/FDIV workaround on Gen10+

The documentation says it applies only to Gens 8 and 9. --- src/intel/compiler/brw_fs_generator.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 03ee26ccd4..07fd6307f0 100644 ---

[Mesa-dev] [PATCH 07/13] i965: Add align1 ternary instruction field encodings

--- src/intel/compiler/brw_eu_defines.h | 35 +++ 1 file changed, 35 insertions(+) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index da482b73c5..3af55e830c 100644 --- a/src/intel/compiler/brw_eu_defines.h +++

[Mesa-dev] [PATCH 10/13] i965: Add align1 ternary instruction disassembler support

--- src/intel/compiler/brw_disasm.c | 399 +--- src/intel/compiler/brw_eu_defines.h | 11 - 2 files changed, 322 insertions(+), 88 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 3726172e5d..7215735967 100644

[Mesa-dev] [PATCH 09/13] i965: Add align1 ternary instruction-word support

--- src/intel/compiler/brw_inst.h | 114 ++ 1 file changed, 114 insertions(+) diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index e6169057e3..b9c03fa88f 100644 --- a/src/intel/compiler/brw_inst.h +++

[Mesa-dev] [PATCH 12/13] i965/fs: Use align1 mode on ternary instructions on Gen10+

Align1 mode offers some nice features over align16, like access to more data types and the ability to use a 16-bit immediate. This patch does not start using any new features. It just emits ternary instructions in align1 mode. --- src/intel/compiler/brw_fs_generator.cpp | 12 1 file

[Mesa-dev] [PATCH 05/13] i965: Rename brw_inst's functions that access the 3src register type

Put hw_ in the name so that it's clear these are the hardware encodings. Similar to commit 9fb832332868 ("i965: Rename brw_inst's functions that access the register type") --- src/intel/compiler/brw_disasm.c | 16 src/intel/compiler/brw_eu_emit.c | 16

[Mesa-dev] [PATCH 02/13] i965: Add functions for brw_reg_type <-> hw 3src type

--- src/intel/compiler/brw_reg_type.c | 50 +++ src/intel/compiler/brw_reg_type.h | 8 +++ 2 files changed, 58 insertions(+) diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index a0f674f0d7..d65ebaee48 100644 ---

[Mesa-dev] [PATCH 11/13] i965: Add align1 ternary instruction emission support

--- src/intel/compiler/brw_eu_emit.c | 196 --- 1 file changed, 143 insertions(+), 53 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index f1a2283de8..7f3980f83e 100644 --- a/src/intel/compiler/brw_eu_emit.c +++

[Mesa-dev] [PATCH 00/13] i965: Align1 ternary instruction support for CNL

Cannonlake (Gen10) adds align1 access mode to ternary instructions. In align1 mode, instructions can use more (and mixed) datatypes and a single 16-bit immediate value. This series adds the infrastructure to emit and disassemble such instructions. Patch 12 switches ternary instructions to align1

[Mesa-dev] [PATCH 03/13] i965: Print subreg in units of type-size on ternary instructions

The instruction word contains SubRegNum[4:2] so it's in units of dwords (hence the * 4 to get it in terms of bytes). Before this patch, the subreg would have been wrong for DF arguments. --- src/intel/compiler/brw_disasm.c | 31 ++- 1 file changed, 26 insertions(+), 5

[Mesa-dev] [PATCH 04/13] i965: Rename brw_inst 3src functions in preparation for align1

--- src/intel/compiler/brw_disasm.c | 46 +++ src/intel/compiler/brw_eu_compact.c | 30 - src/intel/compiler/brw_eu_emit.c| 46 +++ src/intel/compiler/brw_inst.h | 54 ++--- 4

[Mesa-dev] [PATCH 08/13] i965: Add align1 ternary instruction support to conversion functions

--- src/intel/compiler/brw_disasm.c | 12 --- src/intel/compiler/brw_inst.h | 4 +-- src/intel/compiler/brw_reg_type.c | 76 --- src/intel/compiler/brw_reg_type.h | 7 ++-- 4 files changed, 79 insertions(+), 20 deletions(-) diff --git

[Mesa-dev] [PATCH 06/13] i965: Add functions to abstract access to 3src register types

--- src/intel/compiler/brw_eu_emit.c | 22 ++ src/intel/compiler/brw_inst.h| 21 + 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index e4fcbe908d..f1a2283de8 100644

[Mesa-dev] [PATCH 01/13] i965: Move brw_reg_type_is_floating_point to brw_reg_type.h

I'm going to call this from brw_inst.h, and I don't want to have to include all of brw_reg.h. --- src/intel/compiler/brw_reg.h | 13 - src/intel/compiler/brw_reg_type.h | 15 +++ 2 files changed, 15 insertions(+), 13 deletions(-) diff --git

Re: [Mesa-dev] TGSI 16-bit support

On Fri, Aug 25, 2017 at 10:50 AM, Nicolai Hähnle wrote: > On 25.08.2017 13:58, Marek Olšák wrote: >> >> Nicolai, >> >> Have you thought about switching to NIR for radeonsi completely to get >> 16-bit support? We need NIR support anyway for spirv, right? Would be it be >>

Re: [Mesa-dev] [PATCH mesa] i965: add missing `const` in function signature

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 1/5] util/disk_cache: rename mesa cache dir and introduce cache versioning

On Wed, Aug 23, 2017 at 2:32 AM, Timothy Arceri wrote: > Steam is already analysing cache items What does this mean? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] spirv: Add support for the HelperInvocation builtin

On Wed, Aug 23, 2017 at 2:09 PM, Jason Ekstrand wrote: > On Wed, Aug 23, 2017 at 9:58 AM, Ian Romanick wrote: >> >> Reviewed-by: Ian Romanick >> >> Did you submit a CTS bug? > > > No, I didn't. It does get some coverage

Re: [Mesa-dev] [PATCH] glsl/linker: Make several functions not static

piler/glsl/tests: Reviewed-by: Matt Turner <matts...@gmail.com> Thanks! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 02/13] nir/spirv: Use unreachable("...") rather than assert(!"...")

On Thu, Aug 10, 2017 at 7:02 PM, Jordan Justen <jordan.l.jus...@intel.com> wrote: > On 2017-08-10 15:02:33, Matt Turner wrote: >> Quiets a number of uninitialized variable warnings in clang. >> --- >> src/compiler/spirv/spirv_to_nir.c | 24

Re: [Mesa-dev] [PATCH 3/7] util: Fix build on old glibc.

On 08/08, Eric Anholt wrote: We need to link librt for u_thread.h's clock_gettime() call. Fixes: b822d9dd67b5 ("gallium/util: move u_queue.{c,h} to src/util") --- Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: D

[Mesa-dev] [PATCH 12/13] glsl: Mark functions static

Cuts 3224 bytes of .text --- src/compiler/glsl/ast_function.cpp | 10 +- src/compiler/glsl/ast_to_hir.cpp| 6 +++--- src/compiler/glsl/glsl_parser_extras.cpp| 2 +- src/compiler/glsl/ir_validate.cpp | 2 +-

[Mesa-dev] [PATCH 09/13] i965/vec4: Return float from spill_cost_for_type()

--- src/intel/compiler/brw_vec4_reg_allocate.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_vec4_reg_allocate.cpp b/src/intel/compiler/brw_vec4_reg_allocate.cpp index a0ba77b867..bbad46ee6c 100644 --- a/src/intel/compiler/brw_vec4_reg_allocate.cpp

[Mesa-dev] [PATCH 11/13] i965: Mark functions static

Cuts 300 bytes of .text --- src/intel/compiler/brw_fs_surface_builder.cpp | 30 - src/intel/compiler/brw_vec4_nir.cpp | 5 +++-- src/intel/compiler/brw_vec4_surface_builder.cpp | 6 ++--- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git

[Mesa-dev] [PATCH 13/13] glsl: Add prototype for udivmod64()

--- src/compiler/glsl/builtin_functions.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/builtin_functions.h b/src/compiler/glsl/builtin_functions.h index 2053c82b74..89ec9b7d5d 100644 --- a/src/compiler/glsl/builtin_functions.h +++

[Mesa-dev] [PATCH 08/13] i965: Remove some 'inline' keywords

brw_texture_view_sane() is only used by an assert()... --- src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index

[Mesa-dev] [PATCH 10/13] i965/vec4: Use 'class' src_reg, rather than 'struct' src_reg

--- src/intel/compiler/brw_vec4.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 410922c62b..45e918127d 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -1950,7

[Mesa-dev] [PATCH 05/13] anv: Move clamp_int64() inside the IVB check

It's only used in the gen7_cmd_buffer_emit_scissor() function. --- src/intel/vulkan/gen7_cmd_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c index b1721c78ba..5f7b5a07e4 100644 ---

[Mesa-dev] [PATCH 04/13] glsl: Remove unused private fields

--- src/compiler/glsl/lower_int64.cpp | 4 +--- src/mesa/program/ir_to_mesa.cpp | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/src/compiler/glsl/lower_int64.cpp b/src/compiler/glsl/lower_int64.cpp index 9770d314af..aa2e1e063d 100644 ---

[Mesa-dev] [PATCH 06/13] anv: Remove 'inline' keywords

Unless you have data, the compiler knows better than you whether a function should be inlined. --- src/intel/vulkan/anv_batch_chain.c | 4 ++-- src/intel/vulkan/anv_blorp.c | 2 +- src/intel/vulkan/gen7_cmd_buffer.c | 2 +- src/intel/vulkan/gen8_cmd_buffer.c | 4 ++--

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