%/-0.22%). More importantly,
however, it simplifies the control flow graph, which could enable other
optimizations.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
Any measurable performance improvement
Reviewed-by: Matt Turner matts...@gmail.com
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Ready to commit?
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Old GL 1.x specs used 'b' but newer specs use 'p'. The line immediately
above the second hunk also uses 'p'.
---
src/mesa/main/mtypes.h |2 +-
src/mesa/main/texobj.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index
---
src/mesa/main/texobj.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index d0fcb12..28b8130 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -548,10 +548,11 @@ _mesa_test_texobj_completeness(
measured any performance improvement in the past, but that's
probably because compressed textures were all uncompressed anyway.
s/uncompressed/untiled/
Series is
Reviewed-by: Matt Turner matts...@gmail.com
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mesa-dev
Since they're actually GRFs, we can read from them.
total instructions in shared programs: 852751 - 851371 (-0.16%)
instructions in affected programs: 227286 - 225906 (-0.61%)
(no regressions)
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 --
1 files changed, 12
Since they're actually GRFs, we can read from them.
total instructions in shared programs: 344973 - 342483 (-0.72%)
instructions in affected programs: 245602 - 243112 (-1.01%)
(no regressions)
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 23 +--
1 files changed, 13
)/
--
1.8.2
I sent that patch to the list on 24.02.2013, but Matt Turner said that he has
a better solution that does not involve calling make...
Sorry for not handling it sooner. I really don't enjoy doing automake
stuff -- it's hard to find the motivation to push through a big series
that has even
I believe that prog can only be NULL for ARB programs. Neither
brw_fs_fp.cpp nor brw_vec4_vp.cpp call fail(), but not NULL checking
prog is obviously fragile.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8 +---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 8 +---
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 446b4cf..e129816 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++
On Tue, Apr 9, 2013 at 3:55 PM, Eric Anholt e...@anholt.net wrote:
Matt Turner matts...@gmail.com writes:
I believe that prog can only be NULL for ARB programs. Neither
brw_fs_fp.cpp nor brw_vec4_vp.cpp call fail(), but not NULL checking
prog is obviously fragile.
(shader != NULL) = (prog
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote:
These checks were all over, and every time I wrote one I had to try to
decide again what the cases were for partial updates.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 35
+++-
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote:
This instruction doesn't update its IR destination, it just moves from
payload to f0. This caused the dead code elimination pass I'm adding to
dead-code-eliminate the first step of interpolation.
This was because it had a
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote:
This is a poor substitute for proper global dead code elimination that
could replace both our current paths, but it was very easy to write. It
particularly helps with Valve's shaders that are translated out of DX
assembly,
(-0.82%)
There are also a few cleanup patches attached that have been kicking
around several optimization branches I have.
This series is on the local-dce branch of my tree.
Assuming the comment in #3 is addressed and my understanding of #4 is
correct, the series is
Reviewed-by: Matt Turner
Also change if (shader) to if (prog) for consistency.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 12 +++-
src/mesa/drivers/dri/i965/brw_vec4.cpp |8 +---
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
---
src/mesa/drivers/dri/i965/brw_vec4.cpp |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 4f7b8c0..6a2ce35 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++
while
trying to figure out why register_coalesce() does something that
opt_copy_propagate() doesn't.
Available at compile-warnings of my tree.
Series is
Reviewed-by: Matt Turner matts...@gmail.com
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On Thu, Apr 11, 2013 at 2:00 PM, Kenneth Graunke kenn...@whitecape.org wrote:
This provides an interface for applications (and OpenGL-based tools) to
access GPU performance counters. Since the exact performance counters
available vary between vendors and hardware generations, the extension
For the sake of consistency.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
src/glx/apple/Makefile | 2 +-
src/mapi/glapi/Makefile.am | 4 +-
src/mapi/glapi/Makefile.sources | 19 ++
A step toward working make dist/distcheck.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac | 37 -
src/Makefile.am | 30 +++---
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
Since last time:
- Stop building src/glx for xlib-glx, as noticed out by Eric and Andreas.
(Relies on the fact that $enable_dri and $enable_xlib_glx are mutually
It's always constant anyway.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac| 4
src/Makefile.am | 4 +++-
src/gallium/Makefile.am | 22 --
3 files changed, 3
Neither are used in Makefile.ams.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac | 2 --
1 file changed, 2 deletions(-)
diff --git a/configure.ac b/configure.ac
index 299007d..9eec334 100644
--- a/configure.ac
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac | 9 ++---
src/mesa/Makefile.am | 14 +-
src/mesa/drivers/Makefile.am | 22 --
3 files changed, 15
configure still uses it to print the enabled state trackers.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac | 45 +++
src/gallium/state_trackers/Makefile.am | 65
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
Since last time:
- Rebase and add freedreno.
configure.ac| 31 +++
src/gallium/drivers/Makefile.am | 84
And don't build it from other Makefiles. That's awful, and breaks
distclean.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac | 8
src/gallium/targets/opencl/Makefile.am | 3 ---
configure still uses it to print the enabled targets.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
Since last time:
- Rebase and add freedreno.
configure.ac| 2 +-
src/gallium/targets/Makefile.am |
configure still uses it to print the enabled winsys.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
Since last time:
- Rebase and add freedreno.
configure.ac | 38 +-
On Thu, Apr 11, 2013 at 11:35 PM, Jordan Justen jljus...@gmail.com wrote:
Assuming this matched your make-dist-1 branch,
It does.
Series Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Thanks!
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On Thu, Apr 11, 2013 at 4:29 PM, Matt Turner matts...@gmail.com wrote:
For the sake of consistency.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
Chad Jose,
Could you test the first two patches of this series
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2578bf8..704f219 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 704f219..a98892b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++
On Tue, Apr 16, 2013 at 2:54 AM, Andy Furniss andy...@ukfsn.org wrote:
On one of my builds I have libdrm/mesa/xorg living under my home, normally I
can build mesa by setting LDFLAGS and --prefix= but since the uvd commit I
get -
Making all in radeon
make[3]: Entering directory
On Tue, Apr 16, 2013 at 9:45 AM, Chia-I Wu olva...@gmail.com wrote:
If there is no objection, I'd like to merge it in a day or two.
My only objection is over adding a driver that is explicitly a toy,
the confusion it will cause users, and the developer time it will
waste. It wasn't uncommon for
On Tue, Apr 16, 2013 at 10:18 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On 04/16/2013 09:58 AM, Matt Turner wrote:
On Tue, Apr 16, 2013 at 9:45 AM, Chia-I Wu olva...@gmail.com wrote:
If there is no objection, I'd like to merge it in a day or two.
My only objection is over adding
On Tue, Apr 16, 2013 at 10:35 AM, Michael Karcher
michael.karc...@fu-berlin.de wrote:
I suspect there might be a comparable need for a i965g driver, as that
chip has no vertex shader hardware.
This isn't true.
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On Tue, Apr 16, 2013 at 11:11 AM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
= intel_allocate_image(dri_format, loaderPrivate);
+if (image == NULL)
+ return NULL;
+
if (offset + height * stride parent-region-bo-size) {
_mesa_warning(NULL, intel_create_sub_image: subimage out of bounds);
free(image);
--
1.8.1.4
Reviewed-by: Matt Turner matts
@@ -57,7 +62,7 @@ Note: some of the new features are only available with
certain drivers.
h2Changes/h2
ul
-tbd
+liRemoved d3d1x state tracker (unused, unmaintained and broken)/li
/ul
/div
--
1.7.10.4
Reviewed-by: Matt Turner matts...@gmail.com
On Wed, Apr 17, 2013 at 6:07 PM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 18/04/13 01:55, Emil Velikov wrote:
On 18/04/13 01:21, Paul Berry wrote:
On 12 April 2013 01:26, Christian König deathsim...@vodafone.de wrote:
From: Christian König christian.koe...@amd.com
Since we now have
It's next to useless, since it just allows you to turn off VDPAU and
XvMC with a single switch. Just check whether Gallium drivers are
enabled instead.
---
configure.ac | 17 +
1 files changed, 1 insertions(+), 16 deletions(-)
diff --git a/configure.ac b/configure.ac
index
\
- $(API_DEFINES) \
$(DEFINES)
noinst_PROGRAMS = gen_matypes
--
1.7.10.4
Series is Reviewed-by: Matt Turner matts...@gmail.com
There's an instance of IN_DRI_DRIVER in a scons file that I didn't see
removed. May want to remove it too.
___
mesa-dev
Probably a copy-n-paste mistake.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 422816d..f1539d5 100644
Listed in the restrictions section of CMP, but not on the work-arounds
page.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index
---
src/glsl/builtins/tools/generate_builtins.py |1 +
src/glsl/glcpp/glcpp-parse.y |3 +++
src/glsl/glsl_parser_extras.cpp |1 +
src/glsl/glsl_parser_extras.h|2 ++
src/glsl/standalone_scaffolding.cpp |1 +
---
src/glsl/builtins/ir/bitCount.ir| 41 ++
src/glsl/builtins/ir/bitfieldExtract.ir | 57
src/glsl/builtins/ir/bitfieldInsert.ir | 65 +++
src/glsl/builtins/ir/bitfieldReverse.ir | 41
---
src/glsl/ir.cpp|8 +++-
src/glsl/ir.h | 21 -
src/glsl/ir_validate.cpp | 26 ++
src/glsl/opt_algebraic.cpp |6 +++---
This series, available at
git://people.freedesktop.org/~mattst88/mesa arb_gpu_shader5
adds support for the bit built-ins for ARB_gpu_shader5 to the GLSL
compiler and the i965 driver.
Interesting parts of the series -
- New IR operations for each built-in, plus two operations that match
i965
---
src/glsl/ir_constant_expression.cpp | 123 +++
1 files changed, 123 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_constant_expression.cpp
b/src/glsl/ir_constant_expression.cpp
index c09e56a..119fe59 100644
--- a/src/glsl/ir_constant_expression.cpp
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.
---
src/glsl/ir.cpp |2 +
src/glsl/ir.h | 18
src/glsl/ir_optimization.h |1 +
src/glsl/ir_validate.cpp| 12
---
src/glsl/ir_optimization.h |1 +
src/glsl/lower_instructions.cpp | 61 +++
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 49b1475..445dc49 100644
---
---
src/glsl/ir_optimization.h |1 +
src/glsl/lower_instructions.cpp | 82 +++
2 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 445dc49..c5405e5 100644
---
---
src/mesa/drivers/dri/i965/brw_structs.h | 31 +++
1 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri/i965/brw_structs.h
index 75365e0..c322edf 100644
---
---
src/mesa/drivers/dri/i965/brw_defines.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 38f0356..a5d9452 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 34 +++---
1 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
Specifically
bfe - for bitfieldExtract()
bfi1 and bfi2 - for bitfieldInsert()
bfrev - for bitfieldReverse()
cbit - for bitCount()
fbh - for findMSB()
fbl - for findLSB()
---
src/mesa/drivers/dri/i965/brw_defines.h |7 +++
src/mesa/drivers/dri/i965/brw_disasm.c |7
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
---
src/mesa/drivers/dri/i965/brw_fs.cpp |7 +++
src/mesa/drivers/dri/i965/brw_fs.h |7 +++
.../dri/i965/brw_fs_channel_expressions.cpp| 37 +++
---
src/mesa/drivers/dri/i965/brw_vec4.h |7 +++
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 29 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 48
3 files changed, 84 insertions(+), 0 deletions(-)
diff --git
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b3bd1b9..15a0440 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++
---
src/mesa/drivers/dri/i965/brw_disasm.c | 26 ++
1 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 0b881b7..556e63a 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
---
Do these comments make sense to anyone else?
src/mesa/drivers/dri/i965/brw_defines.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index ea5d2af..6517f24 100644
---
-body_instructions, callback, data);
- } else if (ir-as_return() || ir-as_call()) {
+ } else if (ir-as_jump() || ir-as_call()) {
callback(leader, ir, data);
leader = NULL;
} else if ((ir_function = ir-as_function())) {
--
1.8.2.1
Series is Reviewed-by: Matt
On Mon, Apr 22, 2013 at 6:33 PM, Chris Forbes chr...@ijw.co.nz wrote:
In the last hunk:
+ case ir_binop_bfm:
+ case ir_triop_bfi:
These look like leftovers?
-- Chris
Yes, good call. I've moved them to later in the series where they're
actually added (glsl: Add a pass to lower
On Tue, Apr 23, 2013 at 2:23 AM, Chris Forbes chr...@ijw.co.nz wrote:
+ /* Save op0 */
+ ir_variable *temp = new(ir) ir_variable(ir-operands[0]-
type, bfi_base,
+ ir_var_temporary);
+ this-base_ir-insert_before(temp);
+
Three-source instructions have a vertical stride overloaded to 4, which
prevents directly using vec4 uniforms as arguments. Instead we need to
insert a MOV instruction to do the replication for the three-source
instruction.
With this in place, we can use three-source instructions in the vertex
Only 13 affected programs in shader-db, but they were all helped.
total instructions in shared programs: 368877 - 368851 (-0.01%)
instructions in affected programs: 1576 - 1550 (-1.65%)
---
src/mesa/drivers/dri/i965/brw_shader.cpp| 3 +--
src/mesa/drivers/dri/i965/brw_vec4.h
On Tue, Apr 23, 2013 at 3:42 AM, Chris Forbes chr...@ijw.co.nz wrote:
Would it make more sense to move this patch just before or after patch
11, so the disassembly is correct from the moment you start emitting
these?
Yes, good idea. I've moved it immediately after patch 11, i965/gen7:
Set
Added in e1364530 but never used.
---
configure.ac |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/configure.ac b/configure.ac
index 50e60f6..55ea13d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1899,7 +1899,6 @@ if test x$enable_gallium_loader = xyes; then
For consistency, since we already have HAVE_PIPE_LOADER_{SW,DRM}.
---
configure.ac |2 +-
.../auxiliary/pipe-loader/pipe_loader_drm.c|4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/configure.ac b/configure.ac
index
---
configure.ac |1 -
src/gallium/targets/gbm/Makefile.am|1 +
src/gallium/targets/opencl/Makefile.am |1 +
src/gallium/tests/trivial/Makefile.am |1 +
4 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/configure.ac b/configure.ac
index
It guarded the function prototype of pipe_loader_sw_probe, whose use (in
pipe_loader.c) and definition (in pipe_loader_sw.c) were not guarded.
Both are built into libpipe_loader.la if HAVE_LOADER_GALLIUM, which is
enable_gallium_loader in configure.ac.
---
configure.ac
---
configure.ac |1 -
src/gallium/targets/gbm/Makefile.am|1 +
src/gallium/targets/opencl/Makefile.am |1 +
src/gallium/tests/trivial/Makefile.am |1 +
4 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/configure.ac b/configure.ac
index
The three users of GALLIUM_PIPE_LOADER_LIBS (OpenCL, gallium-gbm,
gallium tests) don't appear to need libws_xlib.la.
---
Seems weird that this wasn't actually needed, but I tested by adding
-Wl,--no-undefined
to each Makefile.am that uses GALLIUM_PIPE_LOADER_LIBS (opencl, tests,
and
);
--
1.7.10.4
Reviewed-by: Matt Turner matts...@gmail.com
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http://lists.freedesktop.org/mailman/listinfo/mesa-dev
v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch.
---
src/glsl/ir.cpp| 8 +++-
src/glsl/ir.h | 21 -
src/glsl/ir_validate.cpp | 26 ++
v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
---
src/glsl/ir_constant_expression.cpp | 123
1 file changed, 123 insertions(+)
diff --git a/src/glsl/ir_constant_expression.cpp
b/src/glsl/ir_constant_expression.cpp
index c09e56a..66b0a64
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.
v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp.
Remove spurious temporary assignment and dereference.
---
src/glsl/ir.cpp| 2 ++
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
v2: Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7
src/mesa/drivers/dri/i965/brw_fs.h
v2: Rebase on LRP addition.
Use fix_3src_operand() when emitting BFE and BFI2.
Add BFE and BFI2 to is_3src_inst check in
brw_vec4_copy_propagation.cpp.
Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts
---
v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
bitfieldExtract at all) since three-source instructions are now
usable in the vertex shader.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git
---
Does this squashed in seem okay, Eric?
src/glsl/lower_instructions.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 6c70a4a..d32ec80 100644
--- a/src/glsl/lower_instructions.cpp
+++
On Wed, May 1, 2013 at 11:54 AM, Andreas Boll
andreas.boll@gmail.com wrote:
ping
2013/4/19 Andreas Boll andreas.boll@gmail.com
Not used anymore.
---
Note: Untested
src/mesa/SConscript |1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/SConscript
On Wed, May 1, 2013 at 2:10 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
@@ -1063,22 +1176,21 @@ brw_blorp_blit_program::translate_tiling(bool
old_tiled_w, bool new_tiled_w)
* X' = (X ~0b1011) 1 | (Y 0b1) 2 | X 0b1 (4)
* Y' = (Y ~0b1) 1 | (X 0b1000) 2 | (X
On Wed, May 1, 2013 at 8:41 PM, Jordan Justen jljus...@gmail.com wrote:
On Tue, Apr 30, 2013 at 10:01 AM, Jordan Justen jljus...@gmail.com wrote:
On Tue, Apr 30, 2013 at 9:57 AM, Ian Romanick i...@freedesktop.org wrote:
On 04/27/2013 04:32 PM, Jordan Justen wrote:
This GLSL extension requires
On Mon, Apr 29, 2013 at 4:08 AM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
As specified in:
http://www.khronos.org/registry/egl/extensions/EXT/EGL_EXT_image_dma_buf_import.txt
Checking for the valid fourcc values is left for drivers avoiding
dependency to drm header files here.
On Wed, May 1, 2013 at 9:25 PM, Jordan Justen jljus...@gmail.com wrote:
pending resolution meant I'd figure out what the AMD driver is
doing, and follow that.
Indeed, sorry -- reading comprehension fail.
___
mesa-dev mailing list
On Thu, May 2, 2013 at 12:08 AM, Topi Pohjolainen
topi.pohjolai...@intel.com wrote:
Provides definitions for dma buffer import extension.
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
Reviewed-by: Matt Turner matts...@gmail.com
On Wed, May 1, 2013 at 12:17 PM, Lauri Kasanen c...@gmx.com wrote:
Without this, the X lib path was not properly passed for tests/:
/usr/bin/ld: cannot find -lXvMCW
/usr/bin/ld: cannot find -lXvMC
/usr/bin/ld: cannot find -lXv
/usr/bin/ld: cannot find -lX11
collect2: ld returned 1 exit
On Thu, May 2, 2013 at 11:52 AM, Lauri Kasanen c...@gmx.com wrote:
On Thu, 2 May 2013 07:58:30 -0700
Matt Turner matts...@gmail.com wrote:
-TEST_LIBS = -lXvMCW -lXvMC -lXv -lX11
+TEST_LIBS = $(XVMC_LIBS) -lXvMCW -lXvMC -lXv -lX11
Doesn't XVMC_LIBS include all of those other libraries? I
v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
v3: Add ir_triop_bitfield_extract as an exception to the op[0]-type ==
op[1]-type assertion in ir_constant_expression.cpp.
Reviewed-by: Chris Forbes chr...@ijw.co.nz [v2]
---
src/glsl/ir_constant_expression.cpp | 126
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.
v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well.
Assert that src2.type (instead of src0.type) matches dest.type since
it's the primary argument and src0 and src1 might correctly have
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
v2: Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts.
v3: Use op0-clone() in ir_triop_bfi to prevent (var_ref
channel_expressions) from appearing multiple times in
v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
bitfieldExtract at all) since three-source instructions are now
usable in the vertex shader.
v3: Lower bitfield_insert in the same pass with everything else, since
it doesn't produce any instructions to be lowered (the other two
The Haswell Bspec says A SIMD16 instruction is not allowed. (but
16-wide BFI1 works for me so far). Since GLSL's bitfieldInsert()
function takes int parameters BFI1 produces the same results in all
channels, so there's never any reason to emit a 16-wide BFI1.
---
Texture operations have very long (hundreds of cycles) latencies. If a
texture operation is ready to be scheduled, prefer it over other types
of instructions.
Typically this will mean the other instructions execute to completion
during the time it takes the texturing operation to return results,
On Tue, Apr 30, 2013 at 9:15 AM, Eric Anholt e...@anholt.net wrote:
This will free instruction scheduling to make better choices. No
statistically significant performance difference on GLB2.7 (n=93).
---
Series is:
Reviewed-by: Matt Turner matts...@gmail.com
On Fri, May 3, 2013 at 1:48 AM, Lauri Kasanen c...@gmx.com wrote:
v2: Removed extra libs as requested by Matt Turner.
Signed-off-by: Lauri Kasanen c...@gmx.com
---
src/gallium/state_trackers/xvmc/Makefile.am |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src
201 - 300 of 6330 matches
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