platforms:
conformance/textures/texture-size-cube-maps.html
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git
enabled tex coord units need do
CoordReplace (Eric)
v3: move the sprite point validate code at I915InvalidateState (Eric)
v4: sprite point enable bit update based on _NEW_PROGRAM, too
add relative _NEW-state comments to show what state is being used(Eric)
Signed-off-by: Yuanhan Liu yuanhan
On Wed, Mar 28, 2012 at 01:21:18PM -0700, Eric Anholt wrote:
On Sat, 17 Mar 2012 10:58:27 +0800, Liu Aleaxander aleaxan...@gmail.com
wrote:
On Sat, Mar 17, 2012 at 1:57 AM, Eric Anholt e...@anholt.net wrote:
On Mon, 12 Mar 2012 16:04:00 +0800, Yuanhan Liu
yuanhan@linux.intel.com
3ce3f93d3378fd31df6dca24230edb52407cb9d8 Mon Sep 17 00:00:00 2001
From: Yuanhan Liu yuanhan@linux.intel.com
Date: Tue, 27 Mar 2012 15:41:52 +0800
Subject: [PATCH] intel: fix un-blanced map_refcount issue
This is a regression introduced by commit cdcfd5, which forget to
increase the map_refcount for successfully-mapped
Fix 'set but not used' warnings; gl_version, gl_versions_profiles and
glx_extensions variables are used just only HAVE_XCB_GLX_CREATE_CONTEXT
is defined. Thus those warnings are shown when that macro isn't defined.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/glx/clientinfo.c
On Tue, Mar 20, 2012 at 10:36:24AM -0700, Eric Anholt wrote:
On Mon, 19 Mar 2012 09:38:03 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
On Fri, Mar 16, 2012 at 04:26:43PM -0700, Eric Anholt wrote:
---
src/mesa/drivers/dri/intel/intel_screen.c | 23
;
+ }
+
Looks good to me, except the minor indent issue.
Otherwise,
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
if (__glxHashInsert(priv-drawHash, glxDrawable, pdraw)) {
(*pdraw-destroyDrawable) (pdraw);
return NULL;
--
1.7.9.2.315.g25a78
On Fri, Mar 16, 2012 at 11:13:23AM -0700, Eric Anholt wrote:
On Thu, 15 Mar 2012 14:42:53 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
There are two mipmap layout modes: below and right. And we currently just
use _below_ mode. And in some cases, like height is greater than width
3 files changed, 37 insertions(+), 0 deletions(-)
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 7b2bdad..ff721fb 100644
--- a/src/mesa/drivers/dri/intel
On Fri, Mar 16, 2012 at 04:26:43PM -0700, Eric Anholt wrote:
---
src/mesa/drivers/dri/intel/intel_screen.c | 23 ---
1 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
test.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/gallium/drivers/softpipe/sp_limits.h |1 +
src/gallium/drivers/softpipe/sp_screen.c |2 +-
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/softpipe/sp_limits.h
b/src/gallium
On Thu, Mar 15, 2012 at 01:22:10PM +0800, Yuanhan Liu wrote:
On Tue, Mar 13, 2012 at 07:29:02AM -0700, Jakob Bornecrantz wrote:
- Original Message -
On Mon, Mar 12, 2012 at 05:05:08PM -0700, Jakob Bornecrantz wrote:
Hi all
We well over due for a 8.0.1 release, so I
On Thu, Mar 15, 2012 at 08:32:34PM -0700, Jakob Bornecrantz wrote:
- Original Message -
On Thu, Mar 15, 2012 at 01:22:10PM +0800, Yuanhan Liu wrote:
On Tue, Mar 13, 2012 at 07:29:02AM -0700, Jakob Bornecrantz wrote:
- Original Message -
On Mon, Mar 12, 2012 at 05:05
should be inclued in the next
release(aka 8.0.2 here). Should I do cherry-pick myself? (Usually, Ian
will do that for me before).
Thanks,
Yuanhan Liu
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relased for a while, see
http://lists.freedesktop.org/archives/mesa-dev/2012-February/019167.html
Thanks,
Yuanhan Liu
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On Mon, Mar 12, 2012 at 10:14:06AM +0800, Yuanhan Liu wrote:
On Fri, Mar 09, 2012 at 10:35:33AM -0800, Eric Anholt wrote:
On Thu, 8 Mar 2012 19:21:23 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote:
From ddd1a9d8f0d82c2f5fcb78a471608a005a6a077c Mon Sep 17 00:00:00 2001
From
).
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i915/i915_context.h |1 +
src/mesa/drivers/dri/i915/i915_state.c | 13 +---
src/mesa/drivers/dri/i915/intel_tris.c | 52 ++
3 files changed, 54 insertions(+), 12 deletions
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i915/i915_state.c |8 +++-
src/mesa/drivers/dri/i915/i915_vtbl.c |9 +
2 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_state.c
b/src/mesa/drivers
On Mon, Mar 12, 2012 at 12:30:20PM -0700, Eric Anholt wrote:
On Mon, 12 Mar 2012 16:04:01 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
Is there a reason for this change? What test does it fix?
No big reason and it doesn't
On Fri, Mar 09, 2012 at 10:35:33AM -0800, Eric Anholt wrote:
On Thu, 8 Mar 2012 19:21:23 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
From ddd1a9d8f0d82c2f5fcb78a471608a005a6a077c Mon Sep 17 00:00:00 2001
From: Yuanhan Liu yuanhan@linux.intel.com
Date: Thu, 8 Mar 2012 18:48
On Thu, Mar 08, 2012 at 02:30:30PM +0800, Yuanhan Liu wrote:
The current code would use tex coord to implement varying inputs. If
point sprite is enabled(always enabled in chrome and firefox), the tex
coord would be replaced with the value (x, y, 0, 1) where x and y vary
from 0 to 1. Thus you
will try to understand that by reading more, of course).
BTW, any thoughts on handling varying inputs better(I mean, don't use
texture coord)?
You can use the program I attached to reproduce this issue on pineview.
Thanks,
Yuanhan Liu
#include stdio.h
#include stdlib.h
#include GL/glut.h
#include
.
This would _really_ fix the following webglc case on pineview this time:
https://cvs.khronos.org/svn/repos/registry/trunk/public/webgl/conformance-suites/1.0.1/conformance/rendering/point-size.html
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu yuanhan
On Fri, Mar 02, 2012 at 01:52:00PM +0800, Yuanhan Liu wrote:
On Thu, Mar 01, 2012 at 04:04:59PM +0800, Yuanhan Liu wrote:
On Wed, Feb 29, 2012 at 11:44:59AM -0800, Eric Anholt wrote:
On Wed, 29 Feb 2012 15:11:06 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote:
According
On Tue, Mar 06, 2012 at 08:25:10AM -0800, Eric Anholt wrote:
On Mon, 27 Feb 2012 15:46:32 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c
b/src/mesa/drivers/dri/i965/brw_sf.c
index 6e63583..7950c47 100644
--- a/src/mesa/drivers/dri
We have to do fallback when the 'Clipped Drawing Rectangle X/Y Max'
exceed the hardware's limit no matter the drawing rectangle offset
changed or not.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46665
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
On Wed, Feb 29, 2012 at 11:44:59AM -0800, Eric Anholt wrote:
On Wed, 29 Feb 2012 15:11:06 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
According to 3DSTATE_MAP_STATE at page of 104 in Bspec
vol3d 3D Instructions:
[DevGDG and DevAlv]: Must be a power of 2 for cube maps
Well
On Thu, Mar 01, 2012 at 09:54:46AM -0800, Eric Anholt wrote:
On Thu, 23 Feb 2012 14:19:19 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
The current code would ignore the point size specified by gl_PointSize
builtin variable in vertex shader on Pineview. This patch servers
Ping..
Comments?
Thanks,
Yuanhan Liu
On Mon, Feb 27, 2012 at 03:46:32PM +0800, Yuanhan Liu wrote:
This patch add the support of gl_PointCoord gl builtin variable for
platform gen4 and gen5(ILK).
Unlike gen6+, we don't have a hardware support of gl_PointCoord, means
hardware
Hi Brian,
comments?
Thanks,
Yuanhan Liu
On Thu, Feb 23, 2012 at 02:19:18PM +0800, Yuanhan Liu wrote:
We may specify the point size in a glsl vertex shader.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46311
piglit: glsl-vs-point-size
NOTE: This is a candidate for stable release
ping..
comments?
Thanks,
Yuanhan Liu
On Thu, Feb 23, 2012 at 02:19:19PM +0800, Yuanhan Liu wrote:
The current code would ignore the point size specified by gl_PointSize
builtin variable in vertex shader on Pineview. This patch servers as
fixing that.
This patch fixes the following
On Thu, Feb 23, 2012 at 02:37:06PM +0800, Yuanhan Liu wrote:
On Tue, Feb 21, 2012 at 11:59:17AM -0800, Eric Anholt wrote:
On Sun, 19 Feb 2012 13:31:33 +0800, Liu Aleaxander aleaxan...@gmail.com
wrote:
On Sun, Feb 19, 2012 at 8:54 AM, Eric Anholt e...@anholt.net wrote:
On Sat, 18 Feb
=45975
Piglit: glsl-fs-pointcoord and fbo-gl_pointcoord
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |6 ++
src/mesa/drivers/dri/i965/brw_fs.cpp|9 +
src/mesa
to emit
_TNL_ATTRIB_PSZ with S4_VFMT_POINT_WIDTH in i915ValidateFragmentProgram
just before COLOR0.
I tried it and it worked. This is so *cool*!
Thanks for the nice tip. Will make a patch for that.
Thanks,
Yuanhan Liu
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We may specify the point size in a glsl vertex shader.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46311
piglit: glsl-vs-point-size
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/tnl/t_context.c |3
/rendering/point-size.html
piglit: glsl-vs-point-size
NOTE: This is a candidate for stable release branches.
v2: pick Eric's nice tip for fixing this issue in hardware rendering.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i915/i915_fragprog.c |4
1
(),
but it does work when set to 4. I may not quite understand the urb
layout now; and I'm trying to figure it out.
Thanks,
Yuanhan Liu
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: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 27 +
src/mesa/drivers/dri/i965/brw_fs.h |1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |2 +
src/mesa
)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ glTexSubImage%d(integer/non-integer format mismatch),
^
I guess you missed one 'D' here. Other than that,
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
+ dimensions
On Thu, Jan 19, 2012 at 09:51:32AM -0800, Eric Anholt wrote:
On Thu, 19 Jan 2012 10:30:53 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
When rendering to FBO, rendering is inverted. At the same time, we would
also make sure the point sprite origin is inverted. Or, we will get
On Thu, Jan 19, 2012 at 10:32:30AM -0700, Brian Paul wrote:
On 01/19/2012 10:17 AM, Ian Romanick wrote:
On 01/18/2012 06:30 PM, Yuanhan Liu wrote:
When rendering to FBO, rendering is inverted. At the same time, we
would
also make sure the point sprite origin is inverted. Or, we will get
: This is a candidate for stable release branches.
v2: add the simliar logic to ivb, too (comments from Ian)
simplify the logic operation (comments from Brian)
v3: pick a better comment from Eric
use != for the logic instead of ^ (comments from Ian)
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/gen6_sf_state.c | 19 +--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965
On Wed, Jan 18, 2012 at 06:23:52PM +0800, Yuanhan Liu wrote:
When rendering to FBO, rendering is inverted. At the same time, we would
also make sure the point sprite origin is inverted. Or, we will get an
inverted result correspoinding to rendering to the default winsys FBO.
Bugzilla: https
On Wed, Jan 18, 2012 at 12:13:28PM -0800, Ian Romanick wrote:
On 01/18/2012 02:21 AM, Yuanhan Liu wrote:
On Wed, Jan 18, 2012 at 06:23:52PM +0800, Yuanhan Liu wrote:
When rendering to FBO, rendering is inverted. At the same time, we would
also make sure the point sprite origin is inverted
On Wed, Jan 18, 2012 at 11:53:20AM -0800, Ian Romanick wrote:
On 01/18/2012 02:23 AM, Yuanhan Liu wrote:
When rendering to FBO, rendering is inverted. At the same time, we would
also make sure the point sprite origin is inverted. Or, we will get an
inverted result correspoinding to rendering
: This is a candidate for stable release branches.
v2: add the simliar logic to ivb, too (comments from Ian)
simplify the logic operation (comments from Brian)
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965
On Tue, Jan 10, 2012 at 08:43:18PM -0700, Brian Paul wrote:
On Tue, Jan 3, 2012 at 8:59 PM, Yuanhan Liu yuanhan@linux.intel.com
wrote:
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
Ah index scanning
On Wed, Jan 04, 2012 at 07:23:24PM +0100, Roland Scheidegger wrote:
Am 04.01.2012 04:59, schrieb Yuanhan Liu:
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
Ah index scanning...
I don't like
On Wed, Jan 04, 2012 at 02:55:44PM -0700, Brian Paul wrote:
We were wastefully mapping the whole source/dest buffers before.
---
src/mesa/main/bufferobj.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Looks good to me.
Reviewed-by: Yuanhan Liu yuanhan
to reduce some
map/unmap.
actually map the ib, you lose anyway). Hopefully won't hit that
performance hog often...
A comment inline.
Am 31.12.2011 07:32, schrieb Yuanhan Liu:
[snip]...
+ for (i = 0; i nr_prims; i++) {
+ tmp_ib.ptr = ib-ptr + prims[i].start * vbo_sizeof_ib_type
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
Ah index scanning...
I don't like that this will map/unmap the ib once for each prim,
Me either :)
though
I don't really see a nice way to avoid that (I
On Thu, Dec 29, 2011 at 09:10:03AM +0100, Michel Dänzer wrote:
On Don, 2011-12-29 at 10:03 +0800, Yuanhan Liu wrote:
On Wed, Dec 28, 2011 at 12:07:08PM -0800, Eric Anholt wrote:
On Wed, 28 Dec 2011 13:54:43 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote:
The current code would
.
As when nr_prims = 1, we can pass 1 to paramter nr_prims, thus I made
vbo_get_minmax_index() static.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c |2 +-
src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c |3 +-
src/mesa/main/api_validate.c
On Wed, Dec 28, 2011 at 12:07:08PM -0800, Eric Anholt wrote:
On Wed, 28 Dec 2011 13:54:43 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
The current code would just calculate min/max_index for the first prim
unconditionally, which is wrong if nr_prims 1.
This would some cases
introduce vbo_sizeof_ib_type() function to return the index data type
size. I see some place use switch(ib-type) to get the index data type,
which is sort of duplicate.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/state_tracker/st_draw.c | 15 +
src/mesa
-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 621195d..3d0cc7c 100644
--- a/src
On Tue, Dec 27, 2011 at 11:15:42AM -0800, Eric Anholt wrote:
On Sun, 25 Dec 2011 12:26:25 +0800, Liu Aleaxander aleaxan...@gmail.com
wrote:
On Sun, Dec 25, 2011 at 8:03 AM, Eric Anholt e...@anholt.net wrote:
On Thu, 22 Dec 2011 18:55:50 +0800, Yuanhan Liu
yuanhan@linux.intel.com
For the case that index data is stored in element array buffer object,
and user called glMultiDrawElements, count the min/max_index before
calling vbo-draw_prims. vbo_get_minmax_index() isn't friendly to this
case. So do it while building the prim info.
Signed-off-by: Yuanhan Liu yuanhan
On Thu, Dec 22, 2011 at 02:37:58PM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
Hi, this is a new series of patches for dynamic eu instruction store
size. The first 4 is from Eric. I just grabed it to make it rebase to
current repo. The last 4 patch is from mine
On Thu, Dec 22, 2011 at 02:33:03PM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant
On Thu, Dec 22, 2011 at 11:09:12AM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
[snip]
+ int emit_endif = 1;
Please use bool and true/false rather than int.
Yes, right. Will fix it.
/* In single program flow mode, we can express IF and ELSE
On Thu, Dec 22, 2011 at 07:51:46PM -0800, Kenneth Graunke wrote:
On 12/22/2011 07:04 PM, Yuanhan Liu wrote:
On Thu, Dec 22, 2011 at 02:33:03PM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
[snip]
-#define BRW_EU_MAX_INSN_STACK 5
-#define BRW_EU_MAX_INSN 1
oglc test cases, and found
no regression. (Sandybridge only).
Thanks,
Yuanhan Liu
--
Eric Anholt (4):
i965: Drop unused do_insn argument from gen6_CONT().
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT
From: Eric Anholt e...@anholt.net
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |3 +--
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965
From: Eric Anholt e...@anholt.net
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_clip_line.c |5 +--
src/mesa/drivers/dri/i965/brw_clip_tri.c | 15
From: Eric Anholt e...@anholt.net
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 36 +-
src/mesa/drivers/dri/i965
From: Eric Anholt e...@anholt.net
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |1 +
src/mesa/drivers/dri/i965/brw_eu.h | 10 --
src
address.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 19 insertions(+), 10 deletions
-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |8 +---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 17 -
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
4 files changed, 15 insertions
On Wed, Dec 21, 2011 at 05:57:35AM -0800, Eric Anholt wrote:
On Wed, 21 Dec 2011 17:33:41 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
If dynamic instruction store size is enabled, while after the brw_JMPI()
and before the brw_land_fwd_jump() function, the eu instruction store
brw_DO/JMPI, to let them return the instruction
index.
--
Yuanhan Liu (5):
i965: Add a help function brw_insn_index to get the instruction index
i965: prepare work for dynamic instruction store size on
IF/ELSE/ENDIF
i965: prepare work for dynamic instruction store size on DO/WHILE
i965
The reason to add a help function instead of just use 'insn - p-store'
instead is that this help function includes an assert.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git
the instruction memory address.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 16
3 files changed, 12 insertions(+), 11 deletions
the loop_stack to
store the instruction index instead.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_clip_line.c |2 +-
src/mesa/drivers/dri/i965/brw_clip_tri.c |6 ++--
src/mesa/drivers/dri/i965/brw_clip_unfilled.c |4 +-
src/mesa/drivers/dri
-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |8 +---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 17 -
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
4 files changed, 15 insertions
it to 1'.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |7 ---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 30 insertions(+), 6 deletions
On Fri, Dec 02, 2011 at 11:25:55AM -0800, Eric Anholt wrote:
On Thu, 1 Dec 2011 18:26:50 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Actually the first 5 patches are all prepare work for patch 6.
I checked those patches will all intel oglc testcases, and found
Actually the first 5 patches are all prepare work for patch 6.
I checked those patches will all intel oglc testcases, and found no regressions.
What's better, it fixed something.
Yuanhan Liu (6):
i965: let all the brw_OPCODE functions return an instruction index
instead
i965: remove
Let all the brw_OPCODE functions return an instruction index instead,
and use brw_insn_of(p, index) macro to reference the instruction stored
at p-store[].
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |2 +-
src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +-
src/mesa/drivers
Let all the while loop stack just store the instruction index. This is
somehow more flexible than store the instruction memory address.
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |3 +--
src/mesa/drivers/dri/i965/brw_eu_emit.c |4 ++--
src/mesa/drivers/dri/i965
Here is the final patch to increase the brw eu instruction store size
dynamically instead of just allocating it statically with a constant
limit. This would fix something like 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB
was 16384 while the driver would limit it to 1'.
Signed-off-by: Yuanhan Liu yuanhan
Silence the compile warning
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/glx/drisw_glx.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index a150c61..7ba491b 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
This patch is mainly for the next patch.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa
Increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 1'.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
On Tue, Nov 29, 2011 at 10:35:42AM -0800, Eric Anholt wrote:
On Tue, 29 Nov 2011 16:08:38 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
I'd be more
On Tue, Nov 29, 2011 at 10:40:46AM -0800, Eric Anholt wrote:
On Tue, 29 Nov 2011 16:08:39 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
On Sat, Nov 26, 2011 at 09:01:51AM -0700, Brian Paul wrote:
On 11/23/2011 06:15 PM, Yuanhan Liu wrote:
On Wed, Nov 23, 2011 at 08:25:59AM -0700, Brian Paul wrote:
On 11/23/2011 02:26 AM, Yuanhan Liu wrote:
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515
On Thu, Nov 24, 2011 at 11:25:23AM -0800, Eric Anholt wrote:
On Wed, 23 Nov 2011 12:24:37 -0700, Brian Paul bri...@vmware.com wrote:
On 11/23/2011 12:12 PM, Eric Anholt wrote:
On Wed, 23 Nov 2011 17:34:30 +0800, Yuanhan
Liuyuanhan@linux.intel.com wrote:
From
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/api_arrayelt.c |2 +-
src/mesa/main/api_validate.c | 14 ++--
src/mesa/main/arrayobj.c |4 +++
src/mesa/main/attrib.c|7 ++---
src/mesa/main/bufferobj.c |9 ++-
src/mesa/main
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515: the element buffer object is listed in vertex array object.
Add a testcase to test that.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
tests/all.tests |1 +
tests/general
On Wed, Nov 23, 2011 at 05:27:32PM +0800, Yuanhan Liu wrote:
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515: the element buffer object is listed in vertex array object.
Add a testcase to test that.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
On Wed, Nov 23, 2011 at 11:12:19AM -0800, Eric Anholt wrote:
On Wed, 23 Nov 2011 17:34:30 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
From 9a1da8748f0faa23f34398213ff7ee45fda6bf36 Mon Sep 17 00:00:00 2001
From: Yuanhan Liu yuanhan@linux.intel.com
Date: Wed, 23 Nov 2011 17:37
On Wed, Nov 23, 2011 at 08:33:00AM -0700, Brian Paul wrote:
On 11/23/2011 02:34 AM, Yuanhan Liu wrote:
+GLuint element;
+GLfloat vertics[] = {
minor nit: s/vertics/vertices/
+-1, -1, 0,
+ 1, -1, 0,
+ 1, 1, 0,
+-1, 1, 0
the Elelemnt array buffer to vao.
This would fix most of(3 left) intel oglc vao test fail
[0]: http://www.opengl.org/registry/specs/ARB/vertex_array_object.txt
[1]: http://www.opengl.org/wiki/Vertex_Array_Object
Cc: i...@freedesktop.org
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src
Add a draw-pixel-with-texture testcase to check if texture
sampling is happened while drawing pixels by glDrawPixels.
v2: use piglit_probe_rect_rgba instead of just sampling a
set of pixels(comments from Eric)
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
tests/all.tests
The two patches tries to fix an issue that happened while calling glDrawPixels
with texture enabled.
Here I attached a piglit testcase for this issue.
Yuanhan Liu (2):
swrast: simplify the prototype of function texture_combine
swrast: fix unmatched span-array-ChanType
src/mesa/swrast
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