Re: [Mesa-dev] [PATCH v2 0/6] NVIDIA Tegra support

On 2018-02-23 03:26, Thierry Reding wrote: > From: Thierry Reding > > This series of patches implements initial support for Tegra. The first > two patches import DRM UAPI from v4.16-rc1 that provide framebuffer > modifiers that can be used to specify buffers shared between Nouveau > and the Tegra

[Mesa-dev] [Bug 105105] Suffixless KHR_robustness functions aren't exposed in ES 3.2

https://bugs.freedesktop.org/show_bug.cgi?id=105105 --- Comment #3 from Tapani Pälli --- (In reply to Tapani Pälli from comment #2) > (In reply to Tapani Pälli from comment #1) > > It seems compiler/linker should realize that they are written to shared > > values so we should not optimize those a

Re: [Mesa-dev] [PATCH v2 0/9] anv: Enable fast-clears for multisampled images

Patches 1, 3-9 are: Reviewed-by: Samuel Iglesias Gonsálvez Sam On 24/02/18 07:22, Jason Ekstrand wrote: > We've had multisample compression support for some time and we've had > single-sampled fast-clears but multisampled fast clears haven't been all > that high on anyone's priority list. I d

[Mesa-dev] [PATCH] anv: fix maxResourceSize for pre-gen9

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_formats.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c index 9c52ad5acbd..324797b7f10 100644 --- a/src/intel/vulkan/anv_formats.c +++ b/src

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: Avoid unnecessary transitions before fast clears

HI Jason, -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Jason Ekstrand Gesendet: Montag, 26. Februar 2018 03:33 An: mesa-dev@lists.freedesktop.org Cc: Jason Ekstrand Betreff: [Mesa-dev] [PATCH] anv/cmd_buffer: Avoid unnecessary tra

[Mesa-dev] [PATCH v2] ac: fix f2b and i2b for doubles

Without this llvm was asserting in debug builds. V2: use LLVMConstNull() --- src/amd/common/ac_nir_to_llvm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f37f19404e..789928761b 100644 --- a/src/am

Re: [Mesa-dev] [PATCH 1/2] ac: create ac_get_zero_for_type() helper

On 26/02/18 17:15, Connor Abbott wrote: Why not just use LLVMConstNull()? Because I didn't know it existed :P v2 of patch 2 sent. Thanks! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-de

[Mesa-dev] [PATCH] radeonsi/nir: set TGSI_PROPERTY_NEXT_SHADER

--- src/compiler/shader_info.h | 5 + src/gallium/drivers/radeonsi/si_shader_nir.c | 9 + src/mesa/state_tracker/st_glsl_to_nir.cpp| 12 3 files changed, 26 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index e7

Re: [Mesa-dev] [PATCH 1/8] radeonsi: mask out high VM address bits in registers where needed

I guess this fixes something since it's nominated for stable? Could have a commit message with that. Regards //Ernst 2018-02-25 2:02 GMT+01:00 Marek Olšák : > From: Marek Olšák > > Cc: 17.3 18.0 > --- > src/gallium/drivers/radeonsi/si_compute.c | 4 ++-- > src/gallium/drivers/radeonsi/s

Re: [Mesa-dev] [PATCH] radeonsi/nir: set TGSI_PROPERTY_NEXT_SHADER

Please ignore. This is something that's been sitting in my branch for a while, on second look the logic is wrong. On 26/02/18 20:25, Timothy Arceri wrote: --- src/compiler/shader_info.h | 5 + src/gallium/drivers/radeonsi/si_shader_nir.c | 9 + src/mesa/state

Re: [Mesa-dev] [PATCH] radv: merge tess rings into a single bo

On 02/26/2018 12:28 AM, Dave Airlie wrote: From: Dave Airlie Inspired by a passing commit to radeonsi. --- src/amd/vulkan/radv_device.c | 93 ++- src/amd/vulkan/radv_private.h | 3 +- 2 files changed, 40 insertions(+), 56 deletions(-) diff --git

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 Fabio Pedretti changed: What|Removed |Added CC||pedretti.fa...@gmail.com -- You are r

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 --- Comment #1 from Fabio Pedretti --- I get a slightly different error, Ubuntu 16.04, newer Ubuntu compile fine. Full build log: https://launchpadlibrarian.net/358638969/buildlog_ubuntu-xenial-amd64.mesa_18.1~git1802260730.0cc5be~oibaf~x_BUILD

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/1] ac/nir: use ordered float comparisons except for not equal

On 02/24/2018 02:43 PM, Marek Olšák wrote: On Feb 24, 2018 5:52 AM, "Timothy Arceri" > wrote: Using this on its own I believe will cause CTS regressions, which is what the other patches were about. Feel free to take on the feedback and come up with

[Mesa-dev] [PATCH 2/2] radeonsi/nir: set TGSI_PROPERTY_NEXT_SHADER

--- src/gallium/drivers/radeonsi/si_shader_nir.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index d410a6c2d6..57f8dc6f03 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/sr

[Mesa-dev] [PATCH 1/2] st/glsl_to_nir: gather next_stage in shader_info

--- src/compiler/shader_info.h| 5 + src/mesa/state_tracker/st_glsl_to_nir.cpp | 13 + 2 files changed, 18 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index e7fd7dbe62..11a59ff6ac 100644 --- a/src/compiler/shader_info.h +++ b

[Mesa-dev] [PATCH] radeonsi: set some context vars for nir path

--- src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c index 8707be504e..4a027d8659 100644 --- a/src/gal

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 --- Comment #2 from Gert Wollny --- > I get a slightly different error, Ubuntu 16.04, newer Ubuntu compile fine. Newer Ubuntus use >= gcc-6, and there compiler -std=c++14 is the default, hence the error is alleviated because: > note: unrestri

Re: [Mesa-dev] [PATCH 5/7] ac/radeonsi: pass bindless bool to load_sampler_desc()

Patches 3 and 5 are : Reviewed-by: Samuel Pitoiset Not sure about 4 to be honest. On 02/20/2018 04:42 AM, Timothy Arceri wrote: We also fix the base_index for bindless by using the driver location. --- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/common/ac_shad

Re: [Mesa-dev] [PATCH v2] ac: fix f2b and i2b for doubles

Reviewed-by: Samuel Pitoiset On 02/26/2018 10:14 AM, Timothy Arceri wrote: Without this llvm was asserting in debug builds. V2: use LLVMConstNull() --- src/amd/common/ac_nir_to_llvm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b

Re: [Mesa-dev] [PATCH 00/13] RadeonSI: Reduce user SGPR usage

Nothing wrong with them, really. All the LLVM stuff has caused me to fall behind on going through Mesa patches, sorry for that. 9-13 are finally Reviewed-by: Nicolai Hähnle On 25.02.2018 02:04, Marek Olšák wrote: So what is wrong with patches 9-13? We can do cleanups after those. Marek On

Re: [Mesa-dev] [PATCH 01/14] ac: migrate unique index info shader info

On 02/21/2018 02:35 AM, Dave Airlie wrote: From: Dave Airlie This just moves this function to an inline so the shader_info pass can use it. Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 22 -- src/amd/common/ac_shader_info.h | 25 +++

Re: [Mesa-dev] [PATCH 06/14] radv: drop tcs_out_offsets

On 02/21/2018 02:35 AM, Dave Airlie wrote: From: Dave Airlie Move all calculations to shader generation. Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 39 +++ src/amd/vulkan/radv_pipeline.c | 11 +++ 2 files changed, 30 ins

[Mesa-dev] [PATCH] i965/sbe: fix number of inputs for active components

In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry. Unf

[Mesa-dev] [Bug 105211] build failure after zwp_dmabuf commit if wayland-protocols is not installed

https://bugs.freedesktop.org/show_bug.cgi?id=105211 Daniel Stone changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

Re: [Mesa-dev] [PATCH 02/14] ac/shader_info: start gathering tess output info

On 02/21/2018 02:35 AM, Dave Airlie wrote: From: Dave Airlie This gathers the ls outputs written by the vertex shader, and the tcs outputs, these are needed to calculate certain tcs parameters. These have to be separate for combined gfx9 shaders. Signed-off-by: Dave Airlie --- src/amd/co

Re: [Mesa-dev] [PATCH v2 2/2] nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

On 02/24/2018 11:36 AM, Karol Herbst wrote: currently while insterting barriers, writes and reads to FILE_FLAGS aren't considered. This can lead to WaR hazards in some situations. With the previous commit fixes shaders with intstructions like this: mad u32 $r2 $r4 $r11 $r2 mad u32 { $r5

Re: [Mesa-dev] [PATCH v2 1/2] nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUse

Looks good to me. Reviewed-by: Samuel Pitoiset But please, do a full piglit/CTS runs before pushing it to be sure it doesn't regress anything. On 02/24/2018 11:36 AM, Karol Herbst wrote: In the sched data calculator we have to track first use of defs by iterating over all defs of an instruc

Re: [Mesa-dev] [PATCH 1/8] radeonsi: mask out high VM address bits in registers where needed

On 02/26/2018 10:28 AM, Ernst Sjöstrand wrote: I guess this fixes something since it's nominated for stable? Could have a commit message with that. Yeah, would be nice to know why this is needed, thanks! Regards //Ernst 2018-02-25 2:02 GMT+01:00 Marek Olšák : From: Marek Olšák Cc: 17.3

Re: [Mesa-dev] [PATCH v2 2/2] nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

On Mon, Feb 26, 2018 at 11:52 AM, Samuel Pitoiset wrote: > > > On 02/24/2018 11:36 AM, Karol Herbst wrote: >> >> currently while insterting barriers, writes and reads to FILE_FLAGS aren't >> considered. This can lead to WaR hazards in some situations. >> >> With the previous commit fixes shaders w

Re: [Mesa-dev] [PATCH 1/8] radeonsi: mask out high VM address bits in registers where needed

I don't know if it fixes anything, but better safe than sorry. Marek On Mon, Feb 26, 2018 at 11:55 AM, Samuel Pitoiset wrote: > > > On 02/26/2018 10:28 AM, Ernst Sjöstrand wrote: >> >> I guess this fixes something since it's nominated for stable? >> Could have a commit message with that. > > > Y

Re: [Mesa-dev] [PATCH v2 2/2] nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

On 02/26/2018 12:01 PM, Karol Herbst wrote: On Mon, Feb 26, 2018 at 11:52 AM, Samuel Pitoiset wrote: On 02/24/2018 11:36 AM, Karol Herbst wrote: currently while insterting barriers, writes and reads to FILE_FLAGS aren't considered. This can lead to WaR hazards in some situations. With th

[Mesa-dev] [PATCH] ac/shader: move scanning some info about input PS declarations

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 6 -- src/amd/common/ac_nir_to_llvm.h | 3 --- src/amd/common/ac_shader_info.c | 15 +++ src/amd/common/ac_shader_info.h | 3 +++ src/amd/vulkan/radv_pipeline.c | 14 -- 5 files changed, 26 insert

[Mesa-dev] [PATCH 1/2] radeonsi: create get_base_vertex() helper

--- src/gallium/drivers/radeonsi/si_shader.c | 34 +++- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 7af0bdb99c..adcb03f23f 100644 --- a/src/gallium/drivers/rad

[Mesa-dev] [PATCH 2/2] ac/radeonsi: add load_base_vertex() to the abi

Fixes the following piglit tests: ./bin/arb_shader_draw_parameters-basevertex basevertex -auto -fbo ./bin/arb_shader_draw_parameters-basevertex basevertex-baseinstance -auto -fbo --- src/amd/common/ac_nir_to_llvm.c | 8 +++- src/amd/common/ac_shader_abi.h | 2 ++ src/galliu

Re: [Mesa-dev] [PATCH] glsl: Fix memory leak with known glsl_type instances

ping .. On 02/15/2018 11:12 AM, Tapani Pälli wrote: From: Simon Hausmann When looking up known glsl_type instances in the various hash tables, we end up leaking the key instances used for the lookup, as the glsl_type constructor allocates memory on the global mem_ctx. This patch changes glsl_t

Re: [Mesa-dev] [RFC] opencl: mega-cl

Hi guys, Having attempted a similar thing in the past, I think there are two things at play here. As such I'd recommend trying to keep them separate. 1) Having a single and/or modular - state-tracker <> pipe-driver setup 2) "Hilarities" when having NIR code multiple times per process On 26 Febru

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 1:10 PM, Emil Velikov wrote: > Hi guys, > > Having attempted a similar thing in the past, I think there are two > things at play here. > As such I'd recommend trying to keep them separate. > > 1) Having a single and/or modular - state-tracker <> pipe-driver setup > 2) "Hila

Re: [Mesa-dev] [PATCH] Vulkan: Android.mk: Android build fix

On 02/20/2018 10:10 AM, Harish Krupo wrote: Signed-off-by: Harish Krupo --- src/intel/Android.vulkan.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 6fe736d397..444278613d 100644 --- a/src/intel/Android

Re: [Mesa-dev] [PATCH 12/14] intel/blorp: Add indirect clear color support to mcs_partial_resolve

On 24/02/18 05:58, Jason Ekstrand wrote: Won't this need some swizzling somewhere? Either when storing the color in the fast clear colors (behind the aux surface) or here in the shader? Good question...  I'll have to think on it more but we probably do. No, we do

[Mesa-dev] [AppVeyor] mesa master #7021 failed

Build mesa 7021 failed Commit 6451b0703f by Mauro Rossi on 2/4/2018 9:57 PM: android: vulkan/util: add dependency on libnativewindow for O and later\n\nSimilar to 90dd6e5 ("Android: egl: add dependency on libnativewindow")\n\nFixes the following building error:

[Mesa-dev] [PATCH] radv/gfx9: add a workaround for viewing a slice of 3D as a 2D image

Ported from RadeonSI. That doesn't fix anything known but I think we need it. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 45 + 1 file changed, 37 insertions(+), 8 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/a

[Mesa-dev] [PATCH v2] ac/nir: clean up a hack about rounding 2nd coord component

It's basically just the opposite, and it only makes sense to round the layer for 2D texture arrays. v2: - add SUBPASS Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 7:10 AM, Emil Velikov wrote: > Hi guys, > > Having attempted a similar thing in the past, I think there are two > things at play here. > As such I'd recommend trying to keep them separate. > > 1) Having a single and/or modular - state-tracker <> pipe-driver setup > 2) "Hila

[Mesa-dev] [Bug 104905] SpvOpFOrdEqual doesn't return correct results for NaNs

https://bugs.freedesktop.org/show_bug.cgi?id=104905 --- Comment #2 from Samuel Pitoiset --- This should fix the issue https://cgit.freedesktop.org/mesa/mesa/commit/?id=e05507a427b79e481eb8e45d7aa3c9b4b78376bf Can you confirm and close the bug, please? Thanks! -- You are receiving this mail

[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #6 from Samuel Pitoiset --- This fixes the "cutscene" issue https://cgit.freedesktop.org/mesa/mesa/commit/?id=e05507a427b79e481eb8e45d7aa3c9b4b78376bf -- You are receiving this mail because: You are the assignee for the bug. You ar

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 8:06 AM, Rob Clark wrote: > On Mon, Feb 26, 2018 at 7:10 AM, Emil Velikov > wrote: >> Hi guys, >> >> Having attempted a similar thing in the past, I think there are two >> things at play here. >> As such I'd recommend trying to keep them separate. >> >> 1) Having a single

[Mesa-dev] [PATCH] winsys/amdgpu: request high addresses

We now have hopefully fixed all bugs regarding high addresses on Vega10 and Raven. Start to use the high range to make room for SVM in the low range. Signed-off-by: Christian König --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 16 1 file changed, 12 insertions(+), 4 deletions(

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 7:15 AM, Karol Herbst wrote: > On Mon, Feb 26, 2018 at 1:10 PM, Emil Velikov > wrote: >> Hi guys, >> >> Having attempted a similar thing in the past, I think there are two >> things at play here. >> As such I'd recommend trying to keep them separate. >> >> 1) Having a sin

Re: [Mesa-dev] [PATCH v2 2/9] intel/blorp: Add indirect clear color support to mcs_partial_resolve

On Fri, Feb 23, 2018 at 10:22:57PM -0800, Jason Ekstrand wrote: > This is a bit complicated because we have to get the indirect clear > color in there somehow. In order to not do any more work in the shader > than needed, we set it up as it's own vertex binding which points > directly at the clear

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 2:28 PM, Rob Clark wrote: > On Mon, Feb 26, 2018 at 7:15 AM, Karol Herbst wrote: >> On Mon, Feb 26, 2018 at 1:10 PM, Emil Velikov >> wrote: >>> Hi guys, >>> >>> Having attempted a similar thing in the past, I think there are two >>> things at play here. >>> As such I'd r

[Mesa-dev] [PATCH mesa] vulkan/wsi: clean up cleanup path

Cc: Keith Packard Signed-off-by: Eric Engestrom --- This will make Keith's addition much cleaner as well :) --- src/vulkan/wsi/wsi_common.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/vulkan/wsi/wsi_common.c b/src/vulkan/wsi/wsi_common.c index edba13a13

Re: [Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned

El 23/02/18 a las 22:36, Jason Ekstrand escribió: > Assuming the CTS is still happy with it after those changes, CTS was happy, but piglit has complained a lot. > > Reviewed-by: Jason Ekstrand > > > On Fri, Feb 23, 2018 at 1:16 PM, Chema Casanova

[Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned (v2)

The introduction of 16-bit types with VK_KHR_16bit_storages implies that push constant offsets could be multiple of 2-bytes. Some assertions are updated so offsets should be just multiple of size of the base type but in some cases we can not assume it as doubles aren't aligned to 8 bytes in some ca

Re: [Mesa-dev] [PATCH v2] ac/nir: clean up a hack about rounding 2nd coord component

Reviewed-by: Bas Nieuwenhuizen On Mon, Feb 26, 2018 at 2:05 PM, Samuel Pitoiset wrote: > It's basically just the opposite, and it only makes sense to > round the layer for 2D texture arrays. > > v2: - add SUBPASS > > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_nir_to_llvm.c | 8 +

Re: [Mesa-dev] [PATCH 1/7] anv/spirv: SSBO/UBO buffers needs padding size is not multiple of 32-bits

El 23/02/18 a las 22:31, Jason Ekstrand escribió: > On Fri, Feb 23, 2018 at 12:28 PM, Chema Casanova > wrote: > > > > El 23/02/18 a las 17:26, Jason Ekstrand escribió: > > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > > mailto:jmcasan...

[Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

The surfaces that backup the GPU buffers have a boundary check that considers that access to partial dwords are considered out-of-bounds. For example, buffers with 1/3 16-bit elemnts has size 2 or 6 and the last two bytes would always be read as 0 or its writting ignored. The introduction of 16-bi

Re: [Mesa-dev] [PATCH 05/29] intel/isl: Add a helper for inverting swizzles

On Fri, Jan 26, 2018 at 05:59:34PM -0800, Jason Ekstrand wrote: > --- > src/intel/isl/isl.c | 30 ++ > src/intel/isl/isl.h | 2 ++ > 2 files changed, 32 insertions(+) > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c > index a2d3ae6..420d387 100644 > --- a/sr

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On Mon, Feb 26, 2018 at 9:14 AM, Jose Maria Casanova Crespo wrote: > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-bounds. > For example, buffers with 1/3 16-bit elemnts has size 2 or 6 and the > last two bytes w

[Mesa-dev] [Bug 104905] SpvOpFOrdEqual doesn't return correct results for NaNs

https://bugs.freedesktop.org/show_bug.cgi?id=104905 Józef Kucia changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [Bug 105255] Waiting for fences without waitAll is not implemented

https://bugs.freedesktop.org/show_bug.cgi?id=105255 Bug ID: 105255 Summary: Waiting for fences without waitAll is not implemented Product: Mesa Version: git Hardware: All OS: Linux (All) Status: NEW Severi

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

Hi, On 25.02.2018 22:12, Francisco Jerez wrote: Roland Scheidegger writes: Am 25.02.2018 um 03:35 schrieb Francisco Jerez: Roland Scheidegger writes: This seems to have broken compilation with some gcc versions (with scons build): In file included from src/compiler/glsl/ast_array_index.c

[Mesa-dev] [Bug 105255] Waiting for fences without waitAll is not implemented

https://bugs.freedesktop.org/show_bug.cgi?id=105255 Alex Smith changed: What|Removed |Added CC||asm...@feralinteractive.com -- You are re

Re: [Mesa-dev] [PATCH v2 2/9] intel/blorp: Add indirect clear color support to mcs_partial_resolve

On February 26, 2018 05:33:15 "Pohjolainen, Topi" wrote: On Fri, Feb 23, 2018 at 10:22:57PM -0800, Jason Ekstrand wrote: This is a bit complicated because we have to get the indirect clear color in there somehow. In order to not do any more work in the shader than needed, we set it up as it'

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On Mon, Feb 26, 2018 at 6:14 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-bounds. > For example, buffers with 1/3 16-bit elemnts has size 2 or 6 a

Re: [Mesa-dev] [PATCH 1/7] anv/spirv: SSBO/UBO buffers needs padding size is not multiple of 32-bits

On Mon, Feb 26, 2018 at 6:10 AM, Chema Casanova wrote: > El 23/02/18 a las 22:31, Jason Ekstrand escribió: > > On Fri, Feb 23, 2018 at 12:28 PM, Chema Casanova > > wrote: > > > > > > > > El 23/02/18 a las 17:26, Jason Ekstrand escribió: > > > On Fri, Feb 23,

Re: [Mesa-dev] Killing broken configure toggles and fixing autotools gl.pc

On Friday, 2018-02-23 19:31:59 +, Emil Velikov wrote: > Hi all, > > While fixing a gl.pc + glvnd bug (well sort of), I noticed the > following: > > With GLVND, we started abusing GL_LIB a lot more. Currently autotools > can do a) custom libGL name, b) mangled GL and > c) GLVND. > > Turns

Re: [Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned (v2)

On Mon, Feb 26, 2018 at 6:01 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > The introduction of 16-bit types with VK_KHR_16bit_storages implies that > push constant offsets could be multiple of 2-bytes. Some assertions are > updated so offsets should be just multiple of size of t

Re: [Mesa-dev] [PATCH] anv: fix maxResourceSize for pre-gen9

On Mon, Feb 26, 2018 at 12:58 AM, Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > Signed-off-by: Samuel Iglesias Gonsálvez > --- > src/intel/vulkan/anv_formats.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vu

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: Avoid unnecessary transitions before fast clears

On Sun, Feb 25, 2018 at 9:57 PM, Michael Schellenberger Costa < mschellenbergerco...@googlemail.com> wrote: > HI Jason, > > -Ursprüngliche Nachricht- > Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag > von Jason Ekstrand > Gesendet: Montag, 26. Februar 2018 03:33 >

Re: [Mesa-dev] [PATCH] swr/rast: Fix macOS macro.

On Saturday, 2018-02-24 23:55:21 +, Vinson Lee wrote: > Fixes: a25093de7188 ("swr/rast: Implement JIT shader caching to disk") > Signed-off-by: Vinson Lee Reviewed-by: Eric Engestrom > --- > src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp | 4 ++-- > 1 file changed, 2 insertions(+

Re: [Mesa-dev] [PATCH] winsys/amdgpu: request high addresses

Reviewed-by: Marek Olšák Marek On Mon, Feb 26, 2018 at 2:17 PM, Christian König wrote: > We now have hopefully fixed all bugs regarding high addresses on Vega10 and > Raven. Start to use the high range to make room for SVM in the low > range. > > Signed-off-by: Christian König > --- > src/gal

Re: [Mesa-dev] [PATCH 05/29] intel/isl: Add a helper for inverting swizzles

On Mon, Feb 26, 2018 at 6:19 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Fri, Jan 26, 2018 at 05:59:34PM -0800, Jason Ekstrand wrote: > > --- > > src/intel/isl/isl.c | 30 ++ > > src/intel/isl/isl.h | 2 ++ > > 2 files changed, 32 insertions(+) > >

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On 26/02/18 15:40, Ilia Mirkin wrote: > On Mon, Feb 26, 2018 at 9:14 AM, Jose Maria Casanova Crespo > wrote: >> The surfaces that backup the GPU buffers have a boundary check that >> considers that access to partial dwords are considered out-of-bounds. >> For example, buffers with 1/3 16-bit elemn

[Mesa-dev] [PATCH] meson: fix building without GL

libgl will be undefined if with_glx == 'disabled', so move that check inside the `if with_glx == 'disabled'` block immediately after that check. Fixes: 5c460337fd9c109 ("meson: Fix GL and EGL pkg-config files with glvnd") Reported-by: Jason Ekstrand Signed-off-by: Dylan Baker CC: Daniel Stone C

Re: [Mesa-dev] [PATCH] meson: fix building without GL

Acked-by: Jason Ekstrand Untested-by: Jason Ekstrand On Mon, Feb 26, 2018 at 8:46 AM, Dylan Baker wrote: > libgl will be undefined if with_glx == 'disabled', so move that check > inside the `if with_glx == 'disabled'` block immediately after that > check. > > Fixes: 5c460337fd9c109 ("meson: Fi

Re: [Mesa-dev] [PATCH] meson: fix building without GL

On Monday, 2018-02-26 08:46:54 -0800, Dylan Baker wrote: > libgl will be undefined if with_glx == 'disabled', so move that check > inside the `if with_glx == 'disabled'` block immediately after that typo: s/==/!=/^^ Acked-by: Eric Engestrom > check. > > Fixes: 5c460337fd9c109 ("meso

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On 26/02/18 16:54, Jason Ekstrand wrote: > On Mon, Feb 26, 2018 at 6:14 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial dwords are considered out-of-bounds. >

Re: [Mesa-dev] [PATCH] meson: fix building without GL

On 26 February 2018 at 16:46, Dylan Baker wrote: > libgl will be undefined if with_glx == 'disabled', so move that check > inside the `if with_glx == 'disabled'` block immediately after that > check. > There's some of repetition, making this hard to read. Perhaps: "libgl will be undefined glx is

Re: [Mesa-dev] [PATCH] meson: fix building without GL

On Monday, 2018-02-26 16:56:46 +, Eric Engestrom wrote: > On Monday, 2018-02-26 08:46:54 -0800, Dylan Baker wrote: > > libgl will be undefined if with_glx == 'disabled', so move that check > > inside the `if with_glx == 'disabled'` block immediately after that > typo: s/==/!=/^^ >

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

I've lost track of what's reviewed and what's not. Could you either just send a status list or do a resend once all the current comments are handled? --Jason On February 26, 2018 09:08:01 Chema Casanova wrote: On 26/02/18 16:54, Jason Ekstrand wrote: On Mon, Feb 26, 2018 at 6:14 AM, Jose

Re: [Mesa-dev] [PATCH] meson: fix building without GL

Quoting Eric Engestrom (2018-02-26 09:13:47) > On Monday, 2018-02-26 16:56:46 +, Eric Engestrom wrote: > > On Monday, 2018-02-26 08:46:54 -0800, Dylan Baker wrote: > > > libgl will be undefined if with_glx == 'disabled', so move that check > > > inside the `if with_glx == 'disabled'` block imme

Re: [Mesa-dev] [PATCH] meson: fix building without GL

Quoting Emil Velikov (2018-02-26 09:11:35) > On 26 February 2018 at 16:46, Dylan Baker wrote: > > libgl will be undefined if with_glx == 'disabled', so move that check > > inside the `if with_glx == 'disabled'` block immediately after that > > check. > > > There's some of repetition, making this h

Re: [Mesa-dev] [PATCH 3/7] i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layout

On 23/02/18 21:23, Jason Ekstrand wrote: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > mailto:jmcasan...@igalia.com>> wrote: > > Restrict the use of untyped_surface_write with 16-bit pairs in > ssbo to the cases where we can guarantee that offset is multiple > of 4. >

Re: [Mesa-dev] Mesa (master): glsl: Switch ast_type_qualifier to a 128-bit bitset.

Hello Francisco, This change breaks my ubuntu 16.04 build with gcc 5.4.0. Here’t where it breaks: CXX glsl/glsl_lexer.lo In file included from ../../../src/compiler/glsl/glsl_lexer.ll:27:0: ../../../src/compiler/glsl/ast.h:643:16: error: member ‘ast_type_qualifier::bitset_t ast_type_qua

Re: [Mesa-dev] [PATCH] glsl: Fix memory leak with known glsl_type instances

On 15 February 2018 at 09:12, Tapani Pälli wrote: > From: Simon Hausmann > > When looking up known glsl_type instances in the various hash tables, we > end up leaking the key instances used for the lookup, as the glsl_type > constructor allocates memory on the global mem_ctx. This patch changes >

Re: [Mesa-dev] Mesa (master): glsl: Switch ast_type_qualifier to a 128-bit bitset.

Am 26.02.2018 um 18:52 schrieb Kyriazis, George: > Hello Francisco, > > This change breaks my ubuntu 16.04 build with gcc 5.4.0. Here’t where it > breaks: > > CXX glsl/glsl_lexer.lo > In file included from ../../../src/compiler/glsl/glsl_lexer.ll:27:0: > ../../../src/compiler/glsl/ast.h:

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On 26/02/18 18:20, Jason Ekstrand wrote: > I've lost track of what's reviewed and what's not.  Could you either > just send a status list or do a resend once all the current comments are > handled? Reviewed-by and all feedback addressed -- [1/7] anv/spirv: SSBO/

Re: [Mesa-dev] [PATCH 3/3] build: Move wayland-scanner check into platform

On 23 February 2018 at 11:22, Daniel Stone wrote: > Also only check for wayland-scanner if building for the Wayland > platform. > > Signed-off-by: Daniel Stone > Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf") > Cc: Emil Velikov > Reported-by: Dieter Nützel > Bugzilla: ht

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding wrote: > From: Thierry Reding > > The disk cache implementation uses 64-bit atomic operations. For some > architectures, such as 32-bit ARM, GCC will not be able to translate > these operations into lock-free instructions and will instead rely on H

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On Mon, Feb 26, 2018 at 10:09 AM, Chema Casanova wrote: > On 26/02/18 18:20, Jason Ekstrand wrote: > > I've lost track of what's reviewed and what's not. Could you either > > just send a status list or do a resend once all the current comments are > > handled? > > Reviewed-by and all feedback ad

Re: [Mesa-dev] [PATCH 11/17] intel/compiler/fs: Simplify ddx/ddy code generation

On Fri, Feb 23, 2018 at 4:37 PM, Kenneth Graunke wrote: > On Tuesday, February 20, 2018 9:15:18 PM PST Matt Turner wrote: >> The brw_reg() constructor just obfuscates things here, in my opinion. >> --- >> src/intel/compiler/brw_fs_generator.cpp | 77 >> +++-- >> 1 fil

Re: [Mesa-dev] [PATCH 12/17] intel/compiler/fs: Implement ddy without using align16 for Gen11+

On Fri, Feb 23, 2018 at 4:42 PM, Kenneth Graunke wrote: > On Tuesday, February 20, 2018 9:15:19 PM PST Matt Turner wrote: >> Align16 is no more. We previously generated an align16 ADD instruction >> to calculate DDY: >> >>add(8) g11<1>F -g10<4>.xyxyF g10<4>.zwzwF { align16 1Q }; >> >> Witho

Re: [Mesa-dev] [PATCH v3 01/13] anv/image: Do not override lower bits of dword.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > The lower bits seem to have extra fields in every platform but gen8 > (even though we don't use them in gen9). So just go ahead and avoid > using them for the address. > > Signed-off-by: Rafael Antognolli >

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

It also fixes the errors that I was getting with gcc 5.4.0 with configure build on ubuntu 16.04. Tested-By: George Kyriazis mailto:george.kyria...@intel.com>> On Feb 25, 2018, at 6:52 PM, Roland Scheidegger mailto:srol...@vmware.com>> wrote: Am 25.02.2018 um 21:12 schrieb Francisco Jerez: Rol

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

Quoting Thierry Reding (2018-02-23 05:18:28) > From: Thierry Reding > > The disk cache implementation uses 64-bit atomic operations. For some > architectures, such as 32-bit ARM, GCC will not be able to translate > these operations into lock-free instructions and will instead rely on > the extern

Re: [Mesa-dev] Patch submit question

Thanks Jordan, Since I won’t be checking this in to mesa master, what do I need to do to actually push it to the stable branch, after I get a review on mesa-dev? George > On Feb 23, 2018, at 5:43 PM, Justen, Jordan L > wrote: > > On 2018-02-23 13:20:21, Kyriazis, George wrote: >> Hello mesa-

[Mesa-dev] [PATCH v2] swr/rast: Fix index buffer overfetch issue for non-indexed draws

Populate pLastIndex, even for the non-indexed case. A zero pLastIndex can cause the index offsets inside the fetcher to have non-sensical values that can be either very large positive or very large negative numbers. v2 remove cc mesa-stable, since the stable patch needs to be different from this

Re: [Mesa-dev] [PATCH] i965/sbe: fix number of inputs for active components

Please add the Fixes: tag, so this patch gets applied to the appropriate stable branches. Iago Toral Quiroga writes: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead of going through the bitfie

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On 2018-02-21 13:45:14, Rafael Antognolli wrote: > The size of the clear color struct (expected by the hardware) is 8 > dwords (isl_dev.ss.clear_value_state_size here). But we still need to > track the size of the clear color, used when memcopying it to/from the > state buffer. For that we keep isl

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