Hi,
I generated this patch for linux 2.6.24-rc5 and test it on AT91SAM9263
with iperf.
From: Gregory CLEMENT [EMAIL PROTECTED]
Date: Wed, 12 Dec 2007 18:10:14 +0100
Subject: [PATCH] MACB: clear transmit buffers properly on TX Underrun
Initially transmit buffer pointers were only reset
Haavard Skinnemoen a écrit :
On Thu, 13 Dec 2007 08:51:57 +0100
Gregory CLEMENT [EMAIL PROTECTED] wrote:
Hi,
I generated this patch for linux 2.6.24-rc5 and test it on AT91SAM9263
with iperf.
From: Gregory CLEMENT [EMAIL PROTECTED]
Date: Wed, 12 Dec 2007 18:10:14 +0100
Subject: [PATCH
On 17/06/2015 17:12, Gregory CLEMENT wrote:
Hi Simon,
On 17/06/2015 15:19, Simon Guinot wrote:
The mvneta driver supports the Ethernet IP found in the Armada 370, XP,
380 and 385 SoCs. Since at least one more hardware feature is available
for the Armada XP SoCs then a way to identify them
},
{ }
};
MODULE_DEVICE_TABLE(of, mvneta_match);
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
--
To unsubscribe from this list: send the line unsubscribe netdev in
the body of a message
compatible string marvell,armada-xp-neta.
Signed-off-by: Simon Guinot simon.gui...@sequanux.org
Cc: sta...@vger.kernel.org # v3.8+
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Thanks,
Gregory
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 2 +-
drivers
CLEMENT wrote:
On 17/06/2015 17:12, Gregory CLEMENT wrote:
On 17/06/2015 15:19, Simon Guinot wrote:
The mvneta driver supports the Ethernet IP found in the Armada 370, XP,
380 and 385 SoCs. Since at least one more hardware feature is available
for the Armada XP SoCs then a way to identify them
Hi Simon,
This patch updates the Ethernet DT nodes for Armada XP SoCs with the
compatible string marvell,armada-xp-neta.
Signed-off-by: Simon Guinot simon.gui...@sequanux.org
Cc: sta...@vger.kernel.org # v3.8+
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Thanks,
Gregory
me situation but it doesn't seem to be
the good default behavior. That's why I was looking for a way to let the
use configure it according to his needs.
Please correct me if I am wrong somewhere, because currently I don't
find a good solution for it.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
K
static.
I really would like to have some feedback before going further and
then going in the wring direction.
Thanks,
Gregory CLEMENT (2):
net: mvneta: Associate RX queues with each CPU
net: mvneta: Add naive RSS support
drivers/net/ethernet/marvell/mvneta.c | 264 +++
.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 150 ++
1 file changed, 115 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mv
This patch add the support for the RSS related ethtool
function. Currently it only use one entry in the indirection table which
allows associating an mveneta interface to a given CPU.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mv
eta_pcpu_port *pcpu_port =
>> + per_cpu_ptr(pp->ports, cpu);
>> +
>> + napi_enable(_port->napi);
>> + }
>> +
>
> rxq_def changed, but txq vs CPU mapping remained as in the beginning -
> is it intentional?
txq vs CPU mapping is c
? The two issues look very similar.
Actually there was a bug with this commit, but a fix had been submitted
and accepted yesterday, you can find him here:
https://patchwork.ozlabs.org/patch/518111/.
Thanks,
Gregory
>
> Regards
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and em
Hi,
As stated in the first version: "this patchset reworks the Marvell
neta driver in order to really support its per-CPU interrupts, instead
of faking them as SPI, and allow the use of any RX queue instead of
the hardcoded RX queue 0 that we have currently."
Following the review which has been
pard <maxime.rip...@free-electrons.com>
Cc: <sta...@vger.kernel.org> # v3.8+
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvel
m>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
kernel/irq/manage.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index ad1b064f94fe..dc8a80ecfc4a 100644
--- a/kernel/irq/manage.c
+++ b/k
m>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 143 +-
1 file changed, 142 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marv
using that structure.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 91 ---
1 file changed, 62 insertions(+), 29 deletions(-)
diff -
number of assumption and takes a number of shortcuts in order to just use
that RX queue.
Remove these limitations in order to be able to specify any available
queue.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@fre
ported-by: Willy Tarreau <w...@1wt.eu>
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
kernel/irq/manage.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/kernel/irq/manage.c b/kernel/irq/man
number to determine whether a given interrupt is per-cpu
or not.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/irqchip/
reg = <0x7 0x4000>;
> interrupts-extended = < 8>;
> clocks = < 4>;
> + tx-csum-limit = <9800>;
> status = "disabled";
>
Hi,
On mer., déc. 02 2015, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
>>
>> So far the issue may have been not noticed, because in every IO driver
>> using mvebu_mbus_dram_info for configuring MBUS windows, there's
>> following substraction:
ring boot related to the BM. However I did not
>> manage to use an ethernet interface. The udhcpc never managed to get an
>> IP and if I set the IP manually I could not ping.
>>
>> But on Armada 388 GP I didn't have any issue.
>>
>> Do you have some idea abou
Hi David,
On mer., déc. 02 2015, David Miller <da...@davemloft.net> wrote:
> From: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Date: Wed, 02 Dec 2015 09:16:06 +0100
>
>> Hi David,
>>
>> On mer., déc. 02 2015, David Miller <da...@davemlo
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
drivers/net/ethernet/cadence/macb.c| 26 ++
drivers/net/ethernet/cadence/macb.h| 1 +
3 files changed, 30 insertion
With this patch each CPU is associated with its own set of TX queues.
It also setup the XPS with an initial configuration which set the
affinity matching the hardware configuration.
Suggested-by: Arnd Bergmann <a...@arndb.de>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-elec
es because the mapping is
static.
Thanks,
Gregory
Gregory CLEMENT (4):
net: mvneta: Make the default queue related for each port
net: mvneta: Associate RX queues with each CPU
net: mvneta: Add naive RSS support
net: mvneta: Spread out the TX queues management on all CPUs
drivers/net/ethern
This patch adds the support for the RSS related ethtool
function. Currently it only uses one entry in the indirection table which
allows associating an mvneta interface to a given CPU.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@sem
.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 150 ++
1 file changed, 115 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mv
!), whereas with this patch it was around
0.7ms (and sometime it went to 1.2ms).
Suggested-by: Arnd Bergmann <a...@arndb.de>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 48 ++-
1 file changed, 3
Instead of using the same default queue for all the port. Move it in the
port struct. It will allow have a different default queue for each port.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.
468] orion-ehci f1051000.usb: new USB bus registered, assigned
>>> bus number 2
>>> [1.650111] orion-ehci f1051000.usb: irq 28, io mem 0xf1051000
>>> [1.672467] orion-ehci f1051000.usb: USB 2.0 started, EHCI 1.00
>>> [1.678908] hub 2-0:1.0: USB hu
le conflicts between the branches as suggested by
>> Gregory Clement.
>
> Series applied, thanks.
Could you confirm that you don't apply the last patch?
I would prefer applying it on my tree to avoid merge conflict during the
merge windows.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
the kernel creating a PHY device.
The patch introduces a new optional property "phy-reset-gpios" inspired
from the one use for the FEC.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Since the v1, I used the gpiod functions. It allows to simplify the
code and
Hi Sascha,
On ven., déc. 11 2015, Sascha Hauer <s.ha...@pengutronix.de> wrote:
> On Thu, Dec 10, 2015 at 04:08:08PM +0100, Gregory CLEMENT wrote:
>> Hi Sascha,
>>
>> On jeu., déc. 10 2015, Sascha Hauer <s.ha...@pengutronix.de> wrote:
>>
>> >
creating a PHY device.
The patch introduces a new optional property "reset-gpios" at PHY level.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Hi,
I agree with Sasha to start with a good binding and indeed the reset
is more related to the PHY than
Hi Richard,
On mer., déc. 16 2015, Richard Cochran <richardcoch...@gmail.com> wrote:
> On Wed, Dec 16, 2015 at 07:31:30PM +0100, Gregory CLEMENT wrote:
>> +Optional properties for PHY child node:
>> +- reset-gpios : Should specify the gpio for phy reset
>
> reset
Hi Arnd,
On mer., déc. 16 2015, Arnd Bergmann <a...@arndb.de> wrote:
> On Wednesday 16 December 2015 19:31:30 Gregory CLEMENT wrote:
>> diff --git a/drivers/net/ethernet/cadence/macb.c
>> b/drivers/net/ethernet/cadence/macb.c
>> index 88c1e1a..35661aa 100644
&g
-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/net/macb.txt | 8 ++--
drivers/net/ethernet/cadence/macb.c| 15 ---
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindin
nsg too:
http://marc.info/?l=linux-netdev=145034590619620=2
Thanks,
Gregory
>
> Fixes: 5833e0526820 ("net/macb: add support for resetting PHY using GPIO")
> Cc: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Signed-off-by: Sudip Mukherjee <su...@vector
Hi Sascha,
On jeu., déc. 10 2015, Sascha Hauer <s.ha...@pengutronix.de> wrote:
> Hi Gregory,
>
> On Wed, Dec 09, 2015 at 06:49:43PM +0100, Gregory CLEMENT wrote:
>> With device tree it is no more possible to reset the PHY at board
>> level. Furthermore, doing in the
Instead of using the same default queue for all the port. Move it in the
port struct. It will allow have a different default queue for each port.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.
This patch adds the support for the RSS related ethtool
function. Currently it only uses one entry in the indirection table which
allows associating an mvneta interface to a given CPU.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@sem
.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 150 ++
1 file changed, 115 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mv
,
Gregory
Gregory CLEMENT (4):
net: mvneta: Make the default queue related for each port
net: mvneta: Associate RX queues with each CPU
net: mvneta: Add naive RSS support
net: mvneta: Configure XPS support
drivers/net/ethernet/marvell/mvneta.c | 328 +-
1 fi
Hi Thomas,
On mer., nov. 25 2015, Thomas Petazzoni <thomas.petazz...@free-electrons.com>
wrote:
> Gregory,
>
> On Wed, 25 Nov 2015 15:54:03 +0100, Gregory CLEMENT wrote:
>
>> pp->rxq_def = rxq_def;
>>
>> +pp->indir[0] = rxq_def;
>
>
mvneta support. Because
> of that the register contents were inherited from the bootloader.
It looks OK for me and at least after applying the driver continues
working :)
I guess you find it when you tested suspend to ram.
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Thank
Hi Marcin,
On dim., nov. 22 2015, Marcin Wojtas <m...@semihalf.com> wrote:
> MVNETA_RXQ_HW_BUF_ALLOC bit which controls enabling hardware buffer
> allocation was mistakenly set as BIT(1). This commit fixes the
> assignment.
I confirm it from the datasheet I got:
Reviewed-by:
*/
> +
> static const struct of_device_id mvneta_match[] = {
> { .compatible = "marvell,armada-370-neta" },
> { .compatible = "marvell,armada-xp-neta" },
> @@ -3452,6 +3518,10 @@ MODULE_DEVICE_TABLE(of, mvneta_match);
> static struct platform_driver mvneta_
This patch add the support for the RSS related ethtool
function. Currently it only use one entry in the indirection table which
allows associating an mveneta interface to a given CPU.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mv
Instead of using the same default queue for all the port. Move it in the
port struct. It will allow have a different default queue for each port.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.
.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 150 ++
1 file changed, 115 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mv
The last patch introduces a first level of RSS support through the
ethtool functions. As explained in the introduction there is only one
entry in the RSS lookup table which permits at the end to associate an
mvneta port to a CPU through the RX queues because the mapping is
static.
Thanks,
Gregory
gt; include/linux/mbus.h | 3 +
> 17 files changed, 1677 insertions(+), 64 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/marvell-neta-bm.txt
> create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.c
> create mode 100644
; comment with capital letter?:)
If I got other review, then I can fix it in the next version. But if you
have a look on the otehr commet not all of them start by capital letter.
Thanks,
Greogry
>
> Best regards,
> Marcin
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time a
clock to 2001-01-20 07:57:42
UTC (979977462)
[1.918901] ALSA device list:
[1.921878] No soundcards found.
[2.222505] ata2: SATA link down (SStatus 0 SControl F300)
[2.230484] Freeing unused kernel memory: 4460K (c06fd000 - c0b58000)
--
Gregory Clement, Free Electrons
Kernel, dri
the CPUs and the queues could be wrong. During this loop the
interrupt mask is also updating for each CPUs, It should not be changed
in the same time by other part of the driver.
This patch adds spinlock to create the needed critical sections.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
itten]."
That means that each time we want to manipulate these bits we had to do
it on each cpu and not only on the current cpu.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 100 --
1
cf75e2793c ("net: mvneta: Associate RX queues with each CPU")
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/marve
Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
each CPU") all the percpu irq are used and disabled at initialization, so
there is no point to disable them first.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/
ensures
that all the calls will be done all at once.
Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
Reported-by: Stefan Roese <stefan.ro...@gmail.com>
Suggested-by: Jisheng Zhang <jszh...@marvell.com>
Suggested-by: Russell King <rmk+ker...@arm.linux.org.u
istake in the comments. Pointed by Sergei Shtylyov
- Add a new patch fixing the CPU choice in mvneta_percpu_elect
- Use lock in last patch to prevent remaining race condition. Pointed
by Jisheng
Gregory CLEMENT (7):
net: mvneta: Fix for_each_present_cpu usage
net: mvneta: Fix the CPU
ed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 4c2d12423750..f496f97
the port is stopping. It also uses the spinlock introduces
previously. To avoid the deadlock, the lock has been moved outside the
mvneta_percpu_elect function.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.
>> /* Refill processing */
>> - err = mvneta_rx_refill(pp, rx_desc);
>> + err = bm_in_use ? mvneta_bm_pool_refill(pp->bm_priv,
>> bm_pool) :
>> + mvneta_rx_refill(pp, rx_desc);
>>
itten]."
That means that each time we want to manipulate these bits we had to do
it on each cpu and not only on the current cpu.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 100 --
1
the port is stopping.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 3358c9
ensures
that all the calls will be done all at once.
Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
Reported-by: Stefan Roese <stefan.ro...@gmail.com>
Suggested-by: Jisheng Zhang <jszh...@marvell.com>
Suggested-by: Russell King <rmk+ker...@arm.linux.org.u
the CPUs and the queues could be wrong. During this loop the
interrupt mask is also updating for each CPUs, It should not be changed
in the same time by other part of the driver.
This patch adds spinlock to create the needed critical sections.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
, the other fix potential issues in the
driver.
Thanks,
Gregory
Gregory CLEMENT (6):
net: mvneta: Fix for_each_present_cpu usage
net: mvneta: Use on_each_cpu when possible
net: mvneta: Remove unused code
net: mvneta: Modify the queue related fields from each cpu
net: mvneta
Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
each CPU") all the percpu irq are used and unmask at initialization, so
there is no point to unmask them first.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marv
ed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 90ff5c7e19ea..3d6e313
Hi David,
On sam., janv. 30 2016, David Miller <da...@davemloft.net> wrote:
> From: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Date: Fri, 29 Jan 2016 17:26:06 +0100
>
>> @@ -370,6 +370,8 @@ struct mvneta_port {
>> struct net_device *d
itten]."
That means that each time we want to manipulate these bits we had to do
it on each cpu and not only on the current cpu.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 100 --
1
, the other fix potential issues in the
driver.
Thanks,
Gregory
Changelog:
v1 -> v2
Fix spinlock comment. Pointed by David Miller
Gregory CLEMENT (6):
net: mvneta: Fix for_each_present_cpu usage
net: mvneta: Use on_each_cpu when possible
net: mvneta: Remove unused code
net: mvneta: Mod
ensures
that all the calls will be done all at once.
Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
Reported-by: Stefan Roese <stefan.ro...@gmail.com>
Suggested-by: Jisheng Zhang <jszh...@marvell.com>
Suggested-by: Russell King <rmk+ker...@arm.linux.org.u
ed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 90ff5c7e19ea..3d6e313
Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
each CPU") all the percpu irq are used and unmask at initialization, so
there is no point to unmask them first.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marv
the CPUs and the queues could be wrong. During this loop the
interrupt mask is also updating for each CPUs, It should not be changed
in the same time by other part of the driver.
This patch adds spinlock to create the needed critical sections.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
Hi Sergei,
On lun., févr. 01 2016, Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
wrote:
> Hello.
>
> On 2/1/2016 4:07 PM, Gregory CLEMENT wrote:
>
>> Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
>> each CPU"
the port is stopping.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 4d40d2
Hi Florian,
thanks for your review!
On mer., janv. 27 2016, Florian Fainelli <f.faine...@gmail.com> wrote:
> On 12/01/16 11:10, Gregory CLEMENT wrote:
>> This basic implementation allows to share code between driver using
>> hardware buffer management. As the code
ency it is better if
you merge it in the same time as the 3 other ones.
Thanks,
Gregory
Gregory CLEMENT (2):
net: add a hardware buffer management helper API
net: mvneta: Use the new hwbm framework
Marcin Wojtas (6):
ARM: dts: armada-38x: add buffer manager nodes
ARM: dts: armada-38x: enable buffer
om: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++-
arch/arm/boot/dts/armada-388-clearfog.dts
rating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <grego
Now that the hardware buffer management framework had been introduced,
let's use it.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 45 +++---
drivers/net/ethernet/m
This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
Buffer Manager and
PnC configuration.
[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang <xsw...@marvell.com>
Signed-off-by: Gregory CLE
s used for indirect access to buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@fre
s used for indirect access to buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@fre
number of possible pools, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-o
Hi David,
On jeu., janv. 14 2016, David Laight <david.lai...@aculab.com> wrote:
> From: Gregory CLEMENT
>> Sent: 12 January 2016 19:11
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>> drivers/bus/mvebu-mbus.c | 2 +
Hi Willy,
On mer., févr. 17 2016, Willy Tarreau <w...@1wt.eu> wrote:
> Hi Gregory,
>
> On Tue, Feb 16, 2016 at 04:33:35PM +0100, Gregory CLEMENT wrote:
>> Hello,
>>
>> A few weeks ago I sent a proposal for a API set for HW Buffer
>> management,
ig
> @@ -58,6 +58,7 @@ CONFIG_MTD_M25P80=y
> CONFIG_MTD_NAND=y
> CONFIG_MTD_NAND_PXA3xx=y
> CONFIG_MTD_SPI_NOR=y
> +CONFIG_SRAM=y
> CONFIG_EEPROM_AT24=y
> CONFIG_BLK_DEV_SD=y
> CONFIG_ATA=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-
s used for indirect access to buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@fre
number of possible pools, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-o
uot;
- Removed the patch "ARM: mvebu: enable SRAM support in
mvebu_v7_defconfig" of this series and already applied it
- Modified the order of the patches.
In order to ease the test the branch mvneta-BM-framework-v5 is
available at g...@github.com:MISL-EBU-System-SW/mainline-publ
Now that the hardware buffer management framework had been introduced,
let's use it.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 18 +++--
drivers/net/ethernet/m
rating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <grego
1 - 100 of 274 matches
Mail list logo
