---
** [tickets:#193] Accessing CORTEX-M0+ via APB**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Jul 13, 2018 05:17 AM UTC by SANDEEP BABU
**Last Updated:** Fri Jul 13, 2018 05:17 AM UTC
**Owner:** nobody
---
Sent from sourceforge.net because openocd-devel@lists.sourceforge.net
---
** [tickets:#194] Accessing CORTEX-M0+ via APB**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Jul 13, 2018 05:25 AM UTC by SANDEEP BABU
**Last Updated:** Fri Jul 13, 2018 05:25 AM UTC
**Owner:** nobody
**Attachments:**
-
[2018-07-09.png](https://sourceforge.net/p/openocd/tickets
---
** [tickets:#195] Accessing CORTEX-M0+ via APB2AHB Bridge**
**Status:** new
**Milestone:** 0.9.0
**Created:** Mon Jul 16, 2018 08:39 AM UTC by SANDEEP BABU
**Last Updated:** Mon Jul 16, 2018 08:39 AM UTC
**Owner:** nobody
Hi,
We are using custom SoC design where the CORTEX M0+ cores are
---
** [tickets:#206] Support for Tensilica Vision P5 DSP Core**
**Status:** new
**Milestone:** 0.9.0
**Created:** Wed Aug 29, 2018 04:50 AM UTC by SANDEEP BABU
**Last Updated:** Wed Aug 29, 2018 04:50 AM UTC
**Owner:** nobody
We are working on a chip with Tensilica Vision P5 DSP. To add su
---
** [tickets:#193] Accessing CORTEX-M0+ via APB**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Jul 13, 2018 05:17 AM UTC by SANDEEP BABU
**Last Updated:** Fri Jul 13, 2018 05:24 AM UTC
**Owner:** nobody
---
Sent from sourceforge.net because openocd-devel@lists.sourceforge.ne
Hi,
We are using custom SoC design where the CORTEX M0+ cores are connected to the
DAPLITE via APB2AHB Bridge. We are able to access ROM tables via APB but we are
unable to access M0+ via APB as the JTAG debuggers (we have an Olimex
ARM-USB-OCD-H) by default search for M0+ in AHB bus only. Kind
Hi, Thank you for the fast response. let me post the details regarding the same
here for more clarity on the issue.
# **olimex-arm-usb-ocd-h.cfg**
interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
ftdi_vid_pid 0x15ba 0x002b
ftdi_layout_init 0x0908 0x0b1b
ftdi_layout_signal nTRS
