W.r.t. testing, please note that Michael Fischer recently
ran through his testsuite and it all passed...
He didn't commit the test results to the testing folder though...
--
Øyvind Harboe
Embedded software and hardware consulting services
http://consulting.zylin.com
I've given some thought on how users can figure out if a part
is supported by OpenOCD.
There are thousands of flash/target types combinations out there.
The user may have the part number or some other string to describe
his flash or target.
There are two things that I'd like to see:
- the
Please scroll down...
Zach Welch
Verzonden: woensdag 22 april 2009 22:28
Aan: Dick Hollenbeck
CC: OpenOCD Development
Onderwerp: Re: [Openocd-development] The problem with testing
target hardware
On Wed, 2009-04-22 at 14:31 -0500, Dick Hollenbeck wrote:
Zach Welch wrote:
On Wed,
In others words: nothing beats testing with a real target and there will
always be new devices that require some patching.
Most of the time the trouble is with bugs and quirks in the target
hardware and not actually bugs in OpenOCD as such
--
Øyvind Harboe
Embedded software and hardware
Øyvind Harboe schrieb:
In others words: nothing beats testing with a real target and there will
always be new devices that require some patching.
Most of the time the trouble is with bugs and quirks in the target
hardware and not actually bugs in OpenOCD as such
You are right.
Hi!
A minor change.
Index: src/target/target/wi-9c.cfg
===
--- src/target/target/wi-9c.cfg (revision 1513)
+++ src/target/target/wi-9c.cfg (working copy)
@@ -31,7 +31,7 @@
}
set _TARGETNAME [format %s.cpu $_CHIPNAME]
-jtag
Hi,
I applied the patches that were recently posted for the SST flashes (my
board has SST39VF1601) and I can say they work! A big thank you!
I'm running SVN 1470M.
I've been able to use my JTAGkey to read/write flash but I flashed a bum
u-boot.bin and now I hosed the board and OpenOCD reports
R.Doss wrote:
now on The
List with numerous bullets beneath it.
Yes, this is an FPGA with a serial port on it?The is
your universal
JTAG TAP emulator, which gives feedback about the path than
an actual
TAP is traversing.
Without a
Øyvind Harboe wrote:
In others words: nothing beats testing with a real target and there will
always be new devices that require some patching.
Most of the time the trouble is with bugs and quirks in the target
hardware and not actually bugs in OpenOCD as such
Funny, even if
Hi,
Anyone got experience with bringing up the AT91SAM9260 based boards
and know what the min init is? Can I use the working u-boot to probe
these registers and figure out the settings that way? The board came
with EasyICE (which is a parallel wiggler) and a software tool to
reflash
The device is really an
easedropping tool but the brains behind it would be back on the PC,
perhaps a separate process which only looks at the serial port, and is
probably written in Python if I were to do it.
This keeps the cost out of the device, and puts the emulation software
on a
Øyvind Harboe wrote:
Ironically, resisting the CMake patch, might the best
way to get people to stand up and report their interst ;-)
I'm starting to be more convinced that having both
committed to svn is not detrimental to OpenOCD,
the crowd is growing and you're getting some good
names on
This is a bit off topic for this list but thought I would ask since
quite a bit of discussion on programming STM32 is here.
This is in regard to in-application programming (IAP) mentioned in
PM0042 Programming manual. Does this mean that your application running
in flash can program flash
Hi,
Has anyone here used Open-OCD for Linux kernel and/or application
debugging?
Regards
Tim Clacy
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Edgar Grimberg schrieb:
Hi,
Anyone got experience with bringing up the AT91SAM9260 based boards
and know what the min init is? Can I use the working u-boot to probe
these registers and figure out the settings that way? The board came
with EasyICE (which is a parallel wiggler) and a
Øyvind Harboe wrote:
I've given some thought on how users can figure out if a part
is supported by OpenOCD.
There are thousands of flash/target types combinations out there.
The user may have the part number or some other string to describe
his flash or target.
There are two things that
Try it with the attached configfile.
If it works, can you post it as a patch, so it will get committed?
Edgar
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Hmm... why not delete the files?
Possibly add a comment to the stm32 config file for each of
the supported targets...
--
Øyvind Harboe
Embedded software and hardware consulting services
http://consulting.zylin.com
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On Thu, 2009-04-23 at 17:41 +0200, R.Doss wrote:
Edgar Grimberg schrieb:
Hi,
Anyone got experience with bringing up the AT91SAM9260 based boards
and know what the min init is? Can I use the working u-boot to probe
these registers and figure out the settings that way? The
On Thu, 2009-04-23 at 09:54 +0200, Nico Coesel wrote:
[snip]
Another item for the list: With some imagination it would be possible to
simulate a UART or an SPI interface using the JTAG dongle. Maybe even
bit I/O using the RST en TRST pins. This would allow extending OpenOCD
into a universal
Hello
On Thu, Apr 23, 2009 at 4:47 PM, Timothy Clacy t...@phaseone.com wrote:
Hi,
Has anyone here used Open-OCD for Linux kernel and/or application
debugging?
I posted my finding here(based on arm11 and arm9).
http://elinux.org/DebuggingTheLinuxKernelUsingGdb
debugging a running kernel or
On Thu, Apr 23, 2009 at 6:31 PM, Philippe Waille
philippe.wai...@imag.fr wrote:
Hi
Compiling openocd on SOLARIS (with gcc) fails on #includestdbool.h
included in target/arm11.h
In the svn version, stdbool.h is included in two files :
+ helper/types.h : has a #ifdef HAVE_STDBOOL_H
Committed.
Thanks!
--
Øyvind Harboe
Embedded software and hardware consulting services
http://consulting.zylin.com
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reset halt for STM32 appears to be broken in SVN HEAD...
I don't know if this is a regression.
reset run, halt, flash probe 0 works.
reset halt, flash probe 0 fails.
Any ideas?
Not aware of any issues - i can check tomorrow.
Cheers
Spen
Hi
jtag_khz ??
do you have code in flash that configures the pll ?
When I test, I get exactly the same behaviour when khz=2000 (FT2232 )
. But it works well for slower speeds.
Once the onboard clock config code has configured the pll (72khz) then I
can use 6000khz without problems.
There are
What config script and target board are you using?
--
Øyvind Harboe
Embedded software and hardware consulting services
http://consulting.zylin.com
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Øyvind Harboe wrote:
What config script and target board are you using?
I have played a little with the standard scrips but the interface is
basic ft2232 usbjtag layout and nonstandard vid/pid and Serialnumber string.
For the target it is the stm32.cfg but the reset config is:
resetting first
the jtag, and this rsets my target also, and then a little later
resetting the Cortex core giving two rests in quick succeion. It works
but I dont like it. For my old LM2S811 reset does not work well, but I
have not had time to really dig in to this, just noticed the dual
On Thu, Apr 23, 2009 at 07:36:59PM +0200, Øyvind Harboe wrote:
Hmm... why not delete the files?
Possibly add a comment to the stm32 config file for each of
the supported targets...
I wouldn't do that. It's a good thing to have one explicit board/* file
for every eval board so that users can
Øyvind Harboe wrote:
resetting first
the jtag, and this rsets my target also, and then a little later
resetting the Cortex core giving two rests in quick succeion. It works
but I dont like it. For my old LM2S811 reset does not work well, but I
have not had time to really dig in to this, just
Gene Smith a écrit :
Spencer Oliver wrote:
This is a bit off topic for this list but thought I would ask
since quite a bit of discussion on programming STM32 is here.
This is in regard to in-application programming (IAP) mentioned in
PM0042 Programming manual. Does this mean that your
Øyvind Harboe a écrit :
resetting first
the jtag, and this rsets my target also, and then a little later
resetting the Cortex core giving two rests in quick succeion. It works
but I dont like it. For my old LM2S811 reset does not work well, but I
have not had time to really dig in to this,
Øyvind Hmm... why not delete the files?
Øyvind Possibly add a comment to the stm32 config file for each of
Øyvind the supported targets...
Uwe I wouldn't do that. It's a good thing to have one explicit board/*
file
Uwe for every eval board so that users can easily use predefined configs.
Update SheevaPlug with actual vid/pid/desc used in shipping units.
diff --git a/src/target/interface/sheevaplug.cfg
b/src/target/interface/sheevaplug.cfg
index 1fdfe7a..7914ba0 100644
--- a/src/target/interface/sheevaplug.cfg
+++ b/src/target/interface/sheevaplug.cfg
@@ -6,7 +6,7 @@
interface
Magnus Lundin wrote:
Hi, here are som thoughts after looking throuh some parts of the jtag
subsystem.
What is a stable state ? A state that is unchanged or a state that is
unchanged and has no sideeffects ? Only RESET and PAUSE ?
A stable state is one that can persist with subsequent
Duane Ellis wrote:
zack [arrays]
Dick [nak arrays, they get out of sync, etc]
??? [use C99 array initializers]
All well and good, but remember their is this big nasty other compiler
that does not support C99... openocd does not build with that compiler.
Correct, and C++ does not support
On Fri, Apr 24, 2009 at 12:21 AM, Magnus Lundin lun...@mlu.mine.nu wrote:
Ųyvind Harboe wrote:
resetting first
the jtag, and this rsets my target also, and then a little later
resetting the Cortex core giving two rests in quick succeion. It works
but I dont like it. For my old LM2S811 reset
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