Re: [Openocd-development] cif_probe failure
jie.zeng wrote: If we want to access a register in the board, we must pass the base address which tell cpu where the register reside and a proper offset(depends on bus-width), right? If the offset is not fix the datasheet, how the cpu can access that reg correctly? In my opinion, the base is 0x1000 in this case. The offset(in fact its on-chip addr) from datasheet(flash) are 0x2aa(word) and 0x555(byte). So CPU write memory should use the address 0x12AA or 0x1555. But now cpu use a wrong address which is 0x1554. The result is that cannot get right ManufacturerID and probe failure. You still have not described (or I missed it) your flash setup: what kind of flash, mode (8/16 bit), bus width of the CPU, and how it is all connected together. Also, what flash bank configuration are you using in your openocd config? Without that information, it is impossible to tell what addresses are needed to access the flash. cu Michael ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] cif_probe failure
Hello, Thank you for your time. You still have not described (or I missed it) your flash setup: what kind of flash, mode (8/16 bit), bus width of the CPU, and how it is all connected together. Also, what flash bank configuration are you using in your openocd config? Without that information, it is impossible to tell what addresses are needed to access the flash. Sorry, I must make some mistakes and confused about some basic concepts now. First let me list what I know. My board used vitesse chip and the core is ARM926ejs. From the pin table, there are 8 bit for data bus and 24 bit for address bus. Q: what kind of flash, mode (8/16 bit)? FLASH is EN29LV640T/B, 64 Megabit (8M x 8-bit / 4M x 16-bit) Flash Memory Boot Sector Flash Memory. The mode is 8-bit I think since it connected DQ0~DQ7 as data channel. Q: bus width of the CPU? You mean address bus width? If so, it's configurable and the value is 8 or 16 bit. All of the addr pin(24) connect with flash. I set this bus width to 16 bit through change a register. Now start to talk the openocd config. flash bank # chip_width(addr width) is 16 bit, bus_width(data width) is 8 bit flash bank cfi 0x1000 0x800 2 1 0 Is it correct? In fact, I am not very sure the meaning of chip_width and bus_width in bank structure from source code. With this config, cfi_probe() failed. I think its addresses' problem( maybe may config's ) and I set the value manually and it succeed. Regards, -- ZJ ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] cif_probe failure
zengjie wrote: My board used vitesse chip and the core is ARM926ejs. From the pin table, there are 8 bit for data bus and 24 bit for address bus. Q: what kind of flash, mode (8/16 bit)? FLASH is EN29LV640T/B, 64 Megabit (8M x 8-bit / 4M x 16-bit) Flash Memory Boot Sector Flash Memory. The mode is 8-bit I think since it connected DQ0~DQ7 as data channel. You are using an 16-bit flash in 8-bit mode, making it effectively an 8-bit flash with shifted address lines. In that case, you need the x16_as_x8 option, which explains why your probe fails. Q: bus width of the CPU? You mean address bus width? If so, it's configurable and the value is 8 or 16 bit. All of the addr pin(24) connect with flash. I set this bus width to 16 bit through change a register. This can not work if the flash is connected with only 8 data lines. If only DQ0-DQ7 is connected, you need to configure the CPU bus to be 8 bits wide when accessing the flash. Now start to talk the openocd config. flash bank # chip_width(addr width) is 16 bit, bus_width(data width) is 8 bit flash bank cfi 0x1000 0x800 2 1 0 Is it correct? In fact, I am not very sure the meaning of chip_width and bus_width in bank structure from source code. chip_width is 1, since 1 byte (8 bits) are connected, and bus_width should be 1, too. Furthermore, you need the x16_as_x8 option to tell openocd that the flash uses shifted address lines. I hope the address lines are connected correctly (with A-1 on the flash connected to A0 on the CPU)? cu Michael ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] cif_probe failure
On Wed, 2009-06-03 at 18:55 +0200, Michael Schwingen wrote: flash bank # chip_width(addr width) is 16 bit, bus_width(data width) is 8 bit flash bank cfi 0x1000 0x800 2 1 0 Is it correct? In fact, I am not very sure the meaning of chip_width and bus_width in bank structure from source code. chip_width is 1, since 1 byte (8 bits) are connected, and bus_width should be 1, too. Furthermore, you need the x16_as_x8 option to tell openocd that the flash uses shifted address lines. I hope the address lines are connected correctly (with A-1 on the flash connected to A0 on the CPU)? You're quite right. After I changed CPU bus to 8 bit wide and follow from your word, the new config is: flash bank cfi 0x1000 0x800 1 1 0 x16_as_x8 It works now. telnet Flash Manufacturer/Device: 0x007f 0x00c9 flash 'cfi' found at 0x1000 So I can do program the flash with cfi I think. Thanks a lot. PS: The lastest openocd manual has no description about x16_as_x8 option??? Regars, -- ZJ ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] cif_probe failure
On Wednesday 03 June 2009, jie.zeng wrote:
PS: The lastest openocd manual has no description about x16_as_x8
option???
Upcoming patch changes that to:
@item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
Good enough?
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Re: [Openocd-development] cif_probe failure
On Wed, 2009-06-03 at 19:51 -0700, David Brownell wrote:
On Wednesday 03 June 2009, jie.zeng wrote:
PS: The lastest openocd manual has no description about x16_as_x8
option???
Upcoming patch changes that to:
@item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
Good enough?
Yeah I think. Its understandable. Thanks.
Regards,
--
ZJ
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Re: [Openocd-development] cif_probe failure
jie.zeng wrote:
Again with line no.
2105 static int cfi_probe(struct flash_bank_s *bank)
2106 {
/* snip */
2140 cfi_command(bank, 0x55, command);
2141 if((retval = target_write_memory(target,
flash_address(bank, 0, unlock2), bank-bus_ 2141 width, 1, command)) !
= ERROR_OK)
2142 {
2143 return retval;
2144 }
/* snip */
The address depends on your layout, depends on the chip and bus width.
I'm not sure. I thought that address must match the flash interface
specification. In this case, from the flash's datasheet where descripted
that. And also some other flash datasheet point the same thing as below:
Autoselect stage (cycle, addr, data)
Manfacturer ID(word) (1st, 555, AA) (2nd, 2AA, 55) (3rd, 555, 90)
Manfacturer ID(byte) (1st, AAA, AA) (2nd, 555, 55) (3rd, AAA, 90)
Notice the address 0x2AA and 0x555, it's not 0x2aa * bus_width, but the
source code it is. Why?
If you have multiple flashs wired up on 1 bus, then the address lines
between CPU and flash are shifted, requiring correction. The addresses
in the datasheet are *flash* addresses, not *CPU* addresses.
In case flash_width == bus_width, they are the same.
cu
Michael
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Re: [Openocd-development] cif_probe failure
On Tue, 2009-06-02 at 08:37 +0200, Michael Schwingen wrote: I'm not sure. I thought that address must match the flash interface specification. In this case, from the flash's datasheet where descripted that. And also some other flash datasheet point the same thing as below: Autoselect stage (cycle, addr, data) Manfacturer ID(word)(1st, 555, AA) (2nd, 2AA, 55) (3rd, 555, 90) Manfacturer ID(byte)(1st, AAA, AA) (2nd, 555, 55) (3rd, AAA, 90) Notice the address 0x2AA and 0x555, it's not 0x2aa * bus_width, but the source code it is. Why? If you have multiple flashs wired up on 1 bus, then the address lines between CPU and flash are shifted, requiring correction. The addresses in the datasheet are *flash* addresses, not *CPU* addresses. In case flash_width == bus_width, they are the same. Maybe I got your word. Lets go on. If we want to access a register in the board, we must pass the base address which tell cpu where the register reside and a proper offset(depends on bus-width), right? If the offset is not fix the datasheet, how the cpu can access that reg correctly? In my opinion, the base is 0x1000 in this case. The offset(in fact its on-chip addr) from datasheet(flash) are 0x2aa(word) and 0x555(byte). So CPU write memory should use the address 0x12AA or 0x1555. But now cpu use a wrong address which is 0x1554. The result is that cannot get right ManufacturerID and probe failure. Regards -- ZJ ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] cif_probe failure
On Tuesday 02 June 2009 10:32:03 jie.zeng wrote: On Tue, 2009-06-02 at 08:37 +0200, Michael Schwingen wrote: I'm not sure. I thought that address must match the flash interface specification. In this case, from the flash's datasheet where descripted that. And also some other flash datasheet point the same thing as below: Autoselect stage (cycle, addr, data) Manfacturer ID(word) (1st, 555, AA) (2nd, 2AA, 55) (3rd, 555, 90) Manfacturer ID(byte) (1st, AAA, AA) (2nd, 555, 55) (3rd, AAA, 90) Notice the address 0x2AA and 0x555, it's not 0x2aa * bus_width, but the source code it is. Why? If you have multiple flashs wired up on 1 bus, then the address lines between CPU and flash are shifted, requiring correction. The addresses in the datasheet are *flash* addresses, not *CPU* addresses. In case flash_width == bus_width, they are the same. Maybe I got your word. Lets go on. If we want to access a register in the board, we must pass the base address which tell cpu where the register reside and a proper offset(depends on bus-width), right? If the offset is not fix the datasheet, how the cpu can access that reg correctly? In my opinion, the base is 0x1000 in this case. The offset(in fact its on-chip addr) from datasheet(flash) are 0x2aa(word) and 0x555(byte). So CPU write memory should use the address 0x12AA or 0x1555. But now cpu use a wrong address which is 0x1554. The result is that cannot get right ManufacturerID and probe failure. Regards As Michael tried to explain, you need to understand how your flash chip address bus is related to the cpu address bus. If you are writing from a 16 bit address bus to a 16bit flash chip the correspondence is 1-1 so address flash base+offset(0x2aa) will keep the same. On the contrary if the chip and cpu address width differs, you need to do a shift but _just_ on offset address. Please see pg 3 of cfi specification [0] for detailed info. 0x554 is also valid for 0x555. The former happens to be 0x2aa left shifted 1 bit. [0] http://www.jedec.org/download/search/jesd68-01.pdf -- Raúl Sánchez Siles Departamento de Montaje INFOGLOBAL, S. A. * C/ Virgilio, 2. Ciudad de la Imagen. 28223 Pozuelo de Alarcón (Madrid), España * T: +34 91 506 40 00 * F: +34 91 506 40 01 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] cif_probe failure
Hello:
On Sunday 31 May 2009 12:58:16 jie.zeng wrote:
Hi list,
I've got a new problem. When I use the command `flash probe 0' after
telnet to the server. It cannot probe the flash.
My core is arm926ejs and flash used CFI interface, so go into the code
and I found something is not normal.
# my flash config
flash bank cfi 0x1000 0x0080 2 2 0
What is the addres at which the flash is located and what is its size?. Do
you use a 16bit bus chip/cpu?
At flash/cfi.c
cfi_probe() {
/* snip */
/* detect manufacturer ID */
unlock2 = 0x2AA;
cfi_command(bank, 0x55, command);
if((retval = write_memory(target, flash_addr(bank, 0, unlock2),
buf-width, 1, command)) != ERROR_OK)
{
return retval;
}
/* snip */
}
I can't find this exact code in the file, could you point the line number?
I found the flash_address is not correct(my fault?), and address is
0x1554.
From cfi flash spec, detect manufacturer ID, the byte addr should be
base + 0x555 I think.
The address depends on your layout, depends on the chip and bus width.
After changed manually, it unlucily... SO, in this function, I adjust
write_memory() to target_write_u8() and it can probe success.
I 've no more idea about that.
What's wrong? Is it a bug?
Regards
--
ZJ
Regards,
--
Raúl Sánchez Siles
Departamento de Montaje
INFOGLOBAL, S. A.
* C/ Virgilio, 2. Ciudad de la Imagen.
28223 Pozuelo de Alarcón (Madrid), España
* T: +34 91 506 40 00
* F: +34 91 506 40 01
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Re: [Openocd-development] cif_probe failure
On Mon, 2009-06-01 at 17:32 +0200, Raúl Sánchez Siles wrote:
Hello:
On Sunday 31 May 2009 12:58:16 jie.zeng wrote:
Hi list,
I've got a new problem. When I use the command `flash probe 0' after
telnet to the server. It cannot probe the flash.
My core is arm926ejs and flash used CFI interface, so go into the code
and I found something is not normal.
# my flash config
flash bank cfi 0x1000 0x0080 2 2 0
What is the addres at which the flash is located and what is its size?. Do
you use a 16bit bus chip/cpu?
The flash's address is 0x1000 from board datasheet and size is 8Mb.
The width is 16bit.
At flash/cfi.c
cfi_probe() {
/* snip */
/* detect manufacturer ID */
unlock2 = 0x2AA;
cfi_command(bank, 0x55, command);
if((retval = write_memory(target, flash_addr(bank, 0, unlock2),
buf-width, 1, command)) != ERROR_OK)
{
return retval;
}
/* snip */
}
I can't find this exact code in the file, could you point the line number?
Again with line no.
2105 static int cfi_probe(struct flash_bank_s *bank)
2106 {
/* snip */
2140 cfi_command(bank, 0x55, command);
2141 if((retval = target_write_memory(target,
flash_address(bank, 0, unlock2), bank-bus_ 2141 width, 1, command)) !
= ERROR_OK)
2142 {
2143 return retval;
2144 }
/* snip */
New question about coding style: why the line's width has no limit?
I found the flash_address is not correct(my fault?), and address is
0x1554.
From cfi flash spec, detect manufacturer ID, the byte addr should be
base + 0x555 I think.
The address depends on your layout, depends on the chip and bus width.
I'm not sure. I thought that address must match the flash interface
specification. In this case, from the flash's datasheet where descripted
that. And also some other flash datasheet point the same thing as below:
Autoselect stage (cycle, addr, data)
Manfacturer ID(word)(1st, 555, AA) (2nd, 2AA, 55) (3rd, 555, 90)
Manfacturer ID(byte)(1st, AAA, AA) (2nd, 555, 55) (3rd, AAA, 90)
Notice the address 0x2AA and 0x555, it's not 0x2aa * bus_width, but the
source code it is. Why?
Last, when I ran ./configure, it reported Cannot build run ...
libftdi and I walk into the configure file, the test part use the
function `ftdi_new()' which my ftdi.h is not containing. I force it
return 0 for error-free.
My dist: debian(etch).
Regards,
--
ZJ
After changed manually, it unlucily... SO, in this function, I adjust
write_memory() to target_write_u8() and it can probe success.
I 've no more idea about that.
What's wrong? Is it a bug?
Regards
--
ZJ
Regards,
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[Openocd-development] cif_probe failure
Hi list,
I've got a new problem. When I use the command `flash probe 0' after
telnet to the server. It cannot probe the flash.
My core is arm926ejs and flash used CFI interface, so go into the code
and I found something is not normal.
# my flash config
flash bank cfi 0x1000 0x0080 2 2 0
At flash/cfi.c
cfi_probe() {
/* snip */
/* detect manufacturer ID */
unlock2 = 0x2AA;
cfi_command(bank, 0x55, command);
if((retval = write_memory(target, flash_addr(bank, 0, unlock2),
buf-width, 1, command)) != ERROR_OK)
{
return retval;
}
/* snip */
}
I found the flash_address is not correct(my fault?), and address is
0x1554.
From cfi flash spec, detect manufacturer ID, the byte addr should be
base + 0x555 I think.
After changed manually, it unlucily... SO, in this function, I adjust
write_memory() to target_write_u8() and it can probe success.
I 've no more idea about that.
What's wrong? Is it a bug?
Regards
--
ZJ
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